arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include "kvm_cache_regs.h"
  35 #include "x86.h"
  36
  37 #include <asm/io.h>
  38 #include <asm/desc.h>
  39 #include <asm/vmx.h>
  40 #include <asm/virtext.h>
  41 #include <asm/mce.h>
  42 #include <asm/i387.h>
  43 #include <asm/xcr.h>
  44 #include <asm/perf_event.h>
  45
  46 #include "trace.h"
  47
  48 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  49 #define __ex_clear(x, reg) \
  50         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  51
  52 MODULE_AUTHOR("Qumranet");
  53 MODULE_LICENSE("GPL");
  54
  55 static const struct x86_cpu_id vmx_cpu_id[] = {
  56         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  57         {}
  58 };
  59 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  60
  61 static bool __read_mostly enable_vpid = 1;
  62 module_param_named(vpid, enable_vpid, bool, 0444);
  63
  64 static bool __read_mostly flexpriority_enabled = 1;
  65 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  66
  67 static bool __read_mostly enable_ept = 1;
  68 module_param_named(ept, enable_ept, bool, S_IRUGO);
  69
  70 static bool __read_mostly enable_unrestricted_guest = 1;
  71 module_param_named(unrestricted_guest,
  72                         enable_unrestricted_guest, bool, S_IRUGO);
  73
  74 static bool __read_mostly enable_ept_ad_bits = 1;
  75 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  76
  77 static bool __read_mostly emulate_invalid_guest_state = true;
  78 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  79
  80 static bool __read_mostly vmm_exclusive = 1;
  81 module_param(vmm_exclusive, bool, S_IRUGO);
  82
  83 static bool __read_mostly fasteoi = 1;
  84 module_param(fasteoi, bool, S_IRUGO);
  85
  86 /*
  87  * If nested=1, nested virtualization is supported, i.e., guests may use
  88  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  89  * use VMX instructions.
  90  */
  91 static bool __read_mostly nested = 0;
  92 module_param(nested, bool, S_IRUGO);
  93
  94 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
  95         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
  96 #define KVM_GUEST_CR0_MASK                                              \
  97         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  98 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
  99         (X86_CR0_WP | X86_CR0_NE)
 100 #define KVM_VM_CR0_ALWAYS_ON                                            \
 101         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 102 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 103         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 104          | X86_CR4_OSXMMEXCPT)
 105
 106 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 107 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 108
 109 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 110
 111 /*
 112  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 113  * ple_gap:    upper bound on the amount of time between two successive
 114  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 115  *             According to test, this time is usually smaller than 128 cycles.
 116  * ple_window: upper bound on the amount of time a guest is allowed to execute
 117  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 118  *             less than 2^12 cycles
 119  * Time is measured based on a counter that runs at the same rate as the TSC,
 120  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 121  */
 122 #define KVM_VMX_DEFAULT_PLE_GAP    128
 123 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 124 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 125 module_param(ple_gap, int, S_IRUGO);
 126
 127 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 128 module_param(ple_window, int, S_IRUGO);
 129
 130 #define NR_AUTOLOAD_MSRS 8
 131 #define VMCS02_POOL_SIZE 1
 132
 133 struct vmcs {
 134         u32 revision_id;
 135         u32 abort;
 136         char data[0];
 137 };
 138
 139 /*
 140  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 141  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 142  * loaded on this CPU (so we can clear them if the CPU goes down).
 143  */
 144 struct loaded_vmcs {
 145         struct vmcs *vmcs;
 146         int cpu;
 147         int launched;
 148         struct list_head loaded_vmcss_on_cpu_link;
 149 };
 150
 151 struct shared_msr_entry {
 152         unsigned index;
 153         u64 data;
 154         u64 mask;
 155 };
 156
 157 /*
 158  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 159  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 160  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 161  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 162  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 163  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 164  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 165  * underlying hardware which will be used to run L2.
 166  * This structure is packed to ensure that its layout is identical across
 167  * machines (necessary for live migration).
 168  * If there are changes in this struct, VMCS12_REVISION must be changed.
 169  */
 170 typedef u64 natural_width;
 171 struct __packed vmcs12 {
 172         /* According to the Intel spec, a VMCS region must start with the
 173          * following two fields. Then follow implementation-specific data.
 174          */
 175         u32 revision_id;
 176         u32 abort;
 177
 178         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 179         u32 padding[7]; /* room for future expansion */
 180
 181         u64 io_bitmap_a;
 182         u64 io_bitmap_b;
 183         u64 msr_bitmap;
 184         u64 vm_exit_msr_store_addr;
 185         u64 vm_exit_msr_load_addr;
 186         u64 vm_entry_msr_load_addr;
 187         u64 tsc_offset;
 188         u64 virtual_apic_page_addr;
 189         u64 apic_access_addr;
 190         u64 ept_pointer;
 191         u64 guest_physical_address;
 192         u64 vmcs_link_pointer;
 193         u64 guest_ia32_debugctl;
 194         u64 guest_ia32_pat;
 195         u64 guest_ia32_efer;
 196         u64 guest_ia32_perf_global_ctrl;
 197         u64 guest_pdptr0;
 198         u64 guest_pdptr1;
 199         u64 guest_pdptr2;
 200         u64 guest_pdptr3;
 201         u64 host_ia32_pat;
 202         u64 host_ia32_efer;
 203         u64 host_ia32_perf_global_ctrl;
 204         u64 padding64[8]; /* room for future expansion */
 205         /*
 206          * To allow migration of L1 (complete with its L2 guests) between
 207          * machines of different natural widths (32 or 64 bit), we cannot have
 208          * unsigned long fields with no explict size. We use u64 (aliased
 209          * natural_width) instead. Luckily, x86 is little-endian.
 210          */
 211         natural_width cr0_guest_host_mask;
 212         natural_width cr4_guest_host_mask;
 213         natural_width cr0_read_shadow;
 214         natural_width cr4_read_shadow;
 215         natural_width cr3_target_value0;
 216         natural_width cr3_target_value1;
 217         natural_width cr3_target_value2;
 218         natural_width cr3_target_value3;
 219         natural_width exit_qualification;
 220         natural_width guest_linear_address;
 221         natural_width guest_cr0;
 222         natural_width guest_cr3;
 223         natural_width guest_cr4;
 224         natural_width guest_es_base;
 225         natural_width guest_cs_base;
 226         natural_width guest_ss_base;
 227         natural_width guest_ds_base;
 228         natural_width guest_fs_base;
 229         natural_width guest_gs_base;
 230         natural_width guest_ldtr_base;
 231         natural_width guest_tr_base;
 232         natural_width guest_gdtr_base;
 233         natural_width guest_idtr_base;
 234         natural_width guest_dr7;
 235         natural_width guest_rsp;
 236         natural_width guest_rip;
 237         natural_width guest_rflags;
 238         natural_width guest_pending_dbg_exceptions;
 239         natural_width guest_sysenter_esp;
 240         natural_width guest_sysenter_eip;
 241         natural_width host_cr0;
 242         natural_width host_cr3;
 243         natural_width host_cr4;
 244         natural_width host_fs_base;
 245         natural_width host_gs_base;
 246         natural_width host_tr_base;
 247         natural_width host_gdtr_base;
 248         natural_width host_idtr_base;
 249         natural_width host_ia32_sysenter_esp;
 250         natural_width host_ia32_sysenter_eip;
 251         natural_width host_rsp;
 252         natural_width host_rip;
 253         natural_width paddingl[8]; /* room for future expansion */
 254         u32 pin_based_vm_exec_control;
 255         u32 cpu_based_vm_exec_control;
 256         u32 exception_bitmap;
 257         u32 page_fault_error_code_mask;
 258         u32 page_fault_error_code_match;
 259         u32 cr3_target_count;
 260         u32 vm_exit_controls;
 261         u32 vm_exit_msr_store_count;
 262         u32 vm_exit_msr_load_count;
 263         u32 vm_entry_controls;
 264         u32 vm_entry_msr_load_count;
 265         u32 vm_entry_intr_info_field;
 266         u32 vm_entry_exception_error_code;
 267         u32 vm_entry_instruction_len;
 268         u32 tpr_threshold;
 269         u32 secondary_vm_exec_control;
 270         u32 vm_instruction_error;
 271         u32 vm_exit_reason;
 272         u32 vm_exit_intr_info;
 273         u32 vm_exit_intr_error_code;
 274         u32 idt_vectoring_info_field;
 275         u32 idt_vectoring_error_code;
 276         u32 vm_exit_instruction_len;
 277         u32 vmx_instruction_info;
 278         u32 guest_es_limit;
 279         u32 guest_cs_limit;
 280         u32 guest_ss_limit;
 281         u32 guest_ds_limit;
 282         u32 guest_fs_limit;
 283         u32 guest_gs_limit;
 284         u32 guest_ldtr_limit;
 285         u32 guest_tr_limit;
 286         u32 guest_gdtr_limit;
 287         u32 guest_idtr_limit;
 288         u32 guest_es_ar_bytes;
 289         u32 guest_cs_ar_bytes;
 290         u32 guest_ss_ar_bytes;
 291         u32 guest_ds_ar_bytes;
 292         u32 guest_fs_ar_bytes;
 293         u32 guest_gs_ar_bytes;
 294         u32 guest_ldtr_ar_bytes;
 295         u32 guest_tr_ar_bytes;
 296         u32 guest_interruptibility_info;
 297         u32 guest_activity_state;
 298         u32 guest_sysenter_cs;
 299         u32 host_ia32_sysenter_cs;
 300         u32 padding32[8]; /* room for future expansion */
 301         u16 virtual_processor_id;
 302         u16 guest_es_selector;
 303         u16 guest_cs_selector;
 304         u16 guest_ss_selector;
 305         u16 guest_ds_selector;
 306         u16 guest_fs_selector;
 307         u16 guest_gs_selector;
 308         u16 guest_ldtr_selector;
 309         u16 guest_tr_selector;
 310         u16 host_es_selector;
 311         u16 host_cs_selector;
 312         u16 host_ss_selector;
 313         u16 host_ds_selector;
 314         u16 host_fs_selector;
 315         u16 host_gs_selector;
 316         u16 host_tr_selector;
 317 };
 318
 319 /*
 320  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 321  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 322  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 323  */
 324 #define VMCS12_REVISION 0x11e57ed0
 325
 326 /*
 327  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 328  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 329  * current implementation, 4K are reserved to avoid future complications.
 330  */
 331 #define VMCS12_SIZE 0x1000
 332
 333 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 334 struct vmcs02_list {
 335         struct list_head list;
 336         gpa_t vmptr;
 337         struct loaded_vmcs vmcs02;
 338 };
 339
 340 /*
 341  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 342  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 343  */
 344 struct nested_vmx {
 345         /* Has the level1 guest done vmxon? */
 346         bool vmxon;
 347
 348         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 349         gpa_t current_vmptr;
 350         /* The host-usable pointer to the above */
 351         struct page *current_vmcs12_page;
 352         struct vmcs12 *current_vmcs12;
 353
 354         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 355         struct list_head vmcs02_pool;
 356         int vmcs02_num;
 357         u64 vmcs01_tsc_offset;
 358         /* L2 must run next, and mustn't decide to exit to L1. */
 359         bool nested_run_pending;
 360         /*
 361          * Guest pages referred to in vmcs02 with host-physical pointers, so
 362          * we must keep them pinned while L2 runs.
 363          */
 364         struct page *apic_access_page;
 365 };
 366
 367 struct vcpu_vmx {
 368         struct kvm_vcpu       vcpu;
 369         unsigned long         host_rsp;
 370         u8                    fail;
 371         u8                    cpl;
 372         bool                  nmi_known_unmasked;
 373         u32                   exit_intr_info;
 374         u32                   idt_vectoring_info;
 375         ulong                 rflags;
 376         struct shared_msr_entry *guest_msrs;
 377         int                   nmsrs;
 378         int                   save_nmsrs;
 379 #ifdef CONFIG_X86_64
 380         u64                   msr_host_kernel_gs_base;
 381         u64                   msr_guest_kernel_gs_base;
 382 #endif
 383         /*
 384          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 385          * non-nested (L1) guest, it always points to vmcs01. For a nested
 386          * guest (L2), it points to a different VMCS.
 387          */
 388         struct loaded_vmcs    vmcs01;
 389         struct loaded_vmcs   *loaded_vmcs;
 390         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 391         struct msr_autoload {
 392                 unsigned nr;
 393                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 394                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 395         } msr_autoload;
 396         struct {
 397                 int           loaded;
 398                 u16           fs_sel, gs_sel, ldt_sel;
 399 #ifdef CONFIG_X86_64
 400                 u16           ds_sel, es_sel;
 401 #endif
 402                 int           gs_ldt_reload_needed;
 403                 int           fs_reload_needed;
 404         } host_state;
 405         struct {
 406                 int vm86_active;
 407                 ulong save_rflags;
 408                 struct kvm_save_segment {
 409                         u16 selector;
 410                         unsigned long base;
 411                         u32 limit;
 412                         u32 ar;
 413                 } tr, es, ds, fs, gs;
 414         } rmode;
 415         struct {
 416                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 417                 struct kvm_save_segment seg[8];
 418         } segment_cache;
 419         int vpid;
 420         bool emulation_required;
 421
 422         /* Support for vnmi-less CPUs */
 423         int soft_vnmi_blocked;
 424         ktime_t entry_time;
 425         s64 vnmi_blocked_time;
 426         u32 exit_reason;
 427
 428         bool rdtscp_enabled;
 429
 430         /* Support for a guest hypervisor (nested VMX) */
 431         struct nested_vmx nested;
 432 };
 433
 434 enum segment_cache_field {
 435         SEG_FIELD_SEL = 0,
 436         SEG_FIELD_BASE = 1,
 437         SEG_FIELD_LIMIT = 2,
 438         SEG_FIELD_AR = 3,
 439
 440         SEG_FIELD_NR = 4
 441 };
 442
 443 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 444 {
 445         return container_of(vcpu, struct vcpu_vmx, vcpu);
 446 }
 447
 448 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 449 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 450 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 451                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 452
 453 static unsigned short vmcs_field_to_offset_table[] = {
 454         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 455         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 456         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 457         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 458         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 459         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 460         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 461         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 462         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 463         FIELD(HOST_ES_SELECTOR, host_es_selector),
 464         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 465         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 466         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 467         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 468         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 469         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 470         FIELD64(IO_BITMAP_A, io_bitmap_a),
 471         FIELD64(IO_BITMAP_B, io_bitmap_b),
 472         FIELD64(MSR_BITMAP, msr_bitmap),
 473         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 474         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 475         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 476         FIELD64(TSC_OFFSET, tsc_offset),
 477         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 478         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 479         FIELD64(EPT_POINTER, ept_pointer),
 480         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 481         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 482         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 483         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 484         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 485         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 486         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 487         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 488         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 489         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 490         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 491         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 492         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 493         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 494         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 495         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 496         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 497         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 498         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 499         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 500         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 501         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 502         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 503         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 504         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 505         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 506         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 507         FIELD(TPR_THRESHOLD, tpr_threshold),
 508         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 509         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 510         FIELD(VM_EXIT_REASON, vm_exit_reason),
 511         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 512         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 513         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 514         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 515         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 516         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 517         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 518         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 519         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 520         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 521         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 522         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 523         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 524         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 525         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 526         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 527         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 528         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 529         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 530         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 531         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 532         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 533         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 534         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 535         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 536         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 537         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 538         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 539         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 540         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 541         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 542         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 543         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 544         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 545         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 546         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 547         FIELD(EXIT_QUALIFICATION, exit_qualification),
 548         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 549         FIELD(GUEST_CR0, guest_cr0),
 550         FIELD(GUEST_CR3, guest_cr3),
 551         FIELD(GUEST_CR4, guest_cr4),
 552         FIELD(GUEST_ES_BASE, guest_es_base),
 553         FIELD(GUEST_CS_BASE, guest_cs_base),
 554         FIELD(GUEST_SS_BASE, guest_ss_base),
 555         FIELD(GUEST_DS_BASE, guest_ds_base),
 556         FIELD(GUEST_FS_BASE, guest_fs_base),
 557         FIELD(GUEST_GS_BASE, guest_gs_base),
 558         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 559         FIELD(GUEST_TR_BASE, guest_tr_base),
 560         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 561         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 562         FIELD(GUEST_DR7, guest_dr7),
 563         FIELD(GUEST_RSP, guest_rsp),
 564         FIELD(GUEST_RIP, guest_rip),
 565         FIELD(GUEST_RFLAGS, guest_rflags),
 566         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 567         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 568         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 569         FIELD(HOST_CR0, host_cr0),
 570         FIELD(HOST_CR3, host_cr3),
 571         FIELD(HOST_CR4, host_cr4),
 572         FIELD(HOST_FS_BASE, host_fs_base),
 573         FIELD(HOST_GS_BASE, host_gs_base),
 574         FIELD(HOST_TR_BASE, host_tr_base),
 575         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 576         FIELD(HOST_IDTR_BASE, host_idtr_base),
 577         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 578         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 579         FIELD(HOST_RSP, host_rsp),
 580         FIELD(HOST_RIP, host_rip),
 581 };
 582 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
 583
 584 static inline short vmcs_field_to_offset(unsigned long field)
 585 {
 586         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
 587                 return -1;
 588         return vmcs_field_to_offset_table[field];
 589 }
 590
 591 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 592 {
 593         return to_vmx(vcpu)->nested.current_vmcs12;
 594 }
 595
 596 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 597 {
 598         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 599         if (is_error_page(page)) {
 600                 kvm_release_page_clean(page);
 601                 return NULL;
 602         }
 603         return page;
 604 }
 605
 606 static void nested_release_page(struct page *page)
 607 {
 608         kvm_release_page_dirty(page);
 609 }
 610
 611 static void nested_release_page_clean(struct page *page)
 612 {
 613         kvm_release_page_clean(page);
 614 }
 615
 616 static u64 construct_eptp(unsigned long root_hpa);
 617 static void kvm_cpu_vmxon(u64 addr);
 618 static void kvm_cpu_vmxoff(void);
 619 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
 620 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 621 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 622                             struct kvm_segment *var, int seg);
 623 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 624                             struct kvm_segment *var, int seg);
 625
 626 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 627 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 628 /*
 629  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 630  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 631  */
 632 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 633 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 634
 635 static unsigned long *vmx_io_bitmap_a;
 636 static unsigned long *vmx_io_bitmap_b;
 637 static unsigned long *vmx_msr_bitmap_legacy;
 638 static unsigned long *vmx_msr_bitmap_longmode;
 639
 640 static bool cpu_has_load_ia32_efer;
 641 static bool cpu_has_load_perf_global_ctrl;
 642
 643 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 644 static DEFINE_SPINLOCK(vmx_vpid_lock);
 645
 646 static struct vmcs_config {
 647         int size;
 648         int order;
 649         u32 revision_id;
 650         u32 pin_based_exec_ctrl;
 651         u32 cpu_based_exec_ctrl;
 652         u32 cpu_based_2nd_exec_ctrl;
 653         u32 vmexit_ctrl;
 654         u32 vmentry_ctrl;
 655 } vmcs_config;
 656
 657 static struct vmx_capability {
 658         u32 ept;
 659         u32 vpid;
 660 } vmx_capability;
 661
 662 #define VMX_SEGMENT_FIELD(seg)                                  \
 663         [VCPU_SREG_##seg] = {                                   \
 664                 .selector = GUEST_##seg##_SELECTOR,             \
 665                 .base = GUEST_##seg##_BASE,                     \
 666                 .limit = GUEST_##seg##_LIMIT,                   \
 667                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 668         }
 669
 670 static struct kvm_vmx_segment_field {
 671         unsigned selector;
 672         unsigned base;
 673         unsigned limit;
 674         unsigned ar_bytes;
 675 } kvm_vmx_segment_fields[] = {
 676         VMX_SEGMENT_FIELD(CS),
 677         VMX_SEGMENT_FIELD(DS),
 678         VMX_SEGMENT_FIELD(ES),
 679         VMX_SEGMENT_FIELD(FS),
 680         VMX_SEGMENT_FIELD(GS),
 681         VMX_SEGMENT_FIELD(SS),
 682         VMX_SEGMENT_FIELD(TR),
 683         VMX_SEGMENT_FIELD(LDTR),
 684 };
 685
 686 static u64 host_efer;
 687
 688 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 689
 690 /*
 691  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 692  * away by decrementing the array size.
 693  */
 694 static const u32 vmx_msr_index[] = {
 695 #ifdef CONFIG_X86_64
 696         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 697 #endif
 698         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 699 };
 700 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 701
 702 static inline bool is_page_fault(u32 intr_info)
 703 {
 704         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 705                              INTR_INFO_VALID_MASK)) ==
 706                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 707 }
 708
 709 static inline bool is_no_device(u32 intr_info)
 710 {
 711         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 712                              INTR_INFO_VALID_MASK)) ==
 713                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 714 }
 715
 716 static inline bool is_invalid_opcode(u32 intr_info)
 717 {
 718         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 719                              INTR_INFO_VALID_MASK)) ==
 720                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 721 }
 722
 723 static inline bool is_external_interrupt(u32 intr_info)
 724 {
 725         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 726                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 727 }
 728
 729 static inline bool is_machine_check(u32 intr_info)
 730 {
 731         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 732                              INTR_INFO_VALID_MASK)) ==
 733                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 734 }
 735
 736 static inline bool cpu_has_vmx_msr_bitmap(void)
 737 {
 738         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 739 }
 740
 741 static inline bool cpu_has_vmx_tpr_shadow(void)
 742 {
 743         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 744 }
 745
 746 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 747 {
 748         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 749 }
 750
 751 static inline bool cpu_has_secondary_exec_ctrls(void)
 752 {
 753         return vmcs_config.cpu_based_exec_ctrl &
 754                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 755 }
 756
 757 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 758 {
 759         return vmcs_config.cpu_based_2nd_exec_ctrl &
 760                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 761 }
 762
 763 static inline bool cpu_has_vmx_flexpriority(void)
 764 {
 765         return cpu_has_vmx_tpr_shadow() &&
 766                 cpu_has_vmx_virtualize_apic_accesses();
 767 }
 768
 769 static inline bool cpu_has_vmx_ept_execute_only(void)
 770 {
 771         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 772 }
 773
 774 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 775 {
 776         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 777 }
 778
 779 static inline bool cpu_has_vmx_eptp_writeback(void)
 780 {
 781         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 782 }
 783
 784 static inline bool cpu_has_vmx_ept_2m_page(void)
 785 {
 786         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 787 }
 788
 789 static inline bool cpu_has_vmx_ept_1g_page(void)
 790 {
 791         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 792 }
 793
 794 static inline bool cpu_has_vmx_ept_4levels(void)
 795 {
 796         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 797 }
 798
 799 static inline bool cpu_has_vmx_ept_ad_bits(void)
 800 {
 801         return vmx_capability.ept & VMX_EPT_AD_BIT;
 802 }
 803
 804 static inline bool cpu_has_vmx_invept_individual_addr(void)
 805 {
 806         return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
 807 }
 808
 809 static inline bool cpu_has_vmx_invept_context(void)
 810 {
 811         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 812 }
 813
 814 static inline bool cpu_has_vmx_invept_global(void)
 815 {
 816         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 817 }
 818
 819 static inline bool cpu_has_vmx_invvpid_single(void)
 820 {
 821         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 822 }
 823
 824 static inline bool cpu_has_vmx_invvpid_global(void)
 825 {
 826         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 827 }
 828
 829 static inline bool cpu_has_vmx_ept(void)
 830 {
 831         return vmcs_config.cpu_based_2nd_exec_ctrl &
 832                 SECONDARY_EXEC_ENABLE_EPT;
 833 }
 834
 835 static inline bool cpu_has_vmx_unrestricted_guest(void)
 836 {
 837         return vmcs_config.cpu_based_2nd_exec_ctrl &
 838                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 839 }
 840
 841 static inline bool cpu_has_vmx_ple(void)
 842 {
 843         return vmcs_config.cpu_based_2nd_exec_ctrl &
 844                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 845 }
 846
 847 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 848 {
 849         return flexpriority_enabled && irqchip_in_kernel(kvm);
 850 }
 851
 852 static inline bool cpu_has_vmx_vpid(void)
 853 {
 854         return vmcs_config.cpu_based_2nd_exec_ctrl &
 855                 SECONDARY_EXEC_ENABLE_VPID;
 856 }
 857
 858 static inline bool cpu_has_vmx_rdtscp(void)
 859 {
 860         return vmcs_config.cpu_based_2nd_exec_ctrl &
 861                 SECONDARY_EXEC_RDTSCP;
 862 }
 863
 864 static inline bool cpu_has_vmx_invpcid(void)
 865 {
 866         return vmcs_config.cpu_based_2nd_exec_ctrl &
 867                 SECONDARY_EXEC_ENABLE_INVPCID;
 868 }
 869
 870 static inline bool cpu_has_virtual_nmis(void)
 871 {
 872         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 873 }
 874
 875 static inline bool cpu_has_vmx_wbinvd_exit(void)
 876 {
 877         return vmcs_config.cpu_based_2nd_exec_ctrl &
 878                 SECONDARY_EXEC_WBINVD_EXITING;
 879 }
 880
 881 static inline bool report_flexpriority(void)
 882 {
 883         return flexpriority_enabled;
 884 }
 885
 886 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
 887 {
 888         return vmcs12->cpu_based_vm_exec_control & bit;
 889 }
 890
 891 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
 892 {
 893         return (vmcs12->cpu_based_vm_exec_control &
 894                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
 895                 (vmcs12->secondary_vm_exec_control & bit);
 896 }
 897
 898 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
 899         struct kvm_vcpu *vcpu)
 900 {
 901         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
 902 }
 903
 904 static inline bool is_exception(u32 intr_info)
 905 {
 906         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 907                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
 908 }
 909
 910 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
 911 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
 912                         struct vmcs12 *vmcs12,
 913                         u32 reason, unsigned long qualification);
 914
 915 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 916 {
 917         int i;
 918
 919         for (i = 0; i < vmx->nmsrs; ++i)
 920                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 921                         return i;
 922         return -1;
 923 }
 924
 925 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 926 {
 927     struct {
 928         u64 vpid : 16;
 929         u64 rsvd : 48;
 930         u64 gva;
 931     } operand = { vpid, 0, gva };
 932
 933     asm volatile (__ex(ASM_VMX_INVVPID)
 934                   /* CF==1 or ZF==1 --> rc = -1 */
 935                   "; ja 1f ; ud2 ; 1:"
 936                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 937 }
 938
 939 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 940 {
 941         struct {
 942                 u64 eptp, gpa;
 943         } operand = {eptp, gpa};
 944
 945         asm volatile (__ex(ASM_VMX_INVEPT)
 946                         /* CF==1 or ZF==1 --> rc = -1 */
 947                         "; ja 1f ; ud2 ; 1:\n"
 948                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 949 }
 950
 951 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 952 {
 953         int i;
 954
 955         i = __find_msr_index(vmx, msr);
 956         if (i >= 0)
 957                 return &vmx->guest_msrs[i];
 958         return NULL;
 959 }
 960
 961 static void vmcs_clear(struct vmcs *vmcs)
 962 {
 963         u64 phys_addr = __pa(vmcs);
 964         u8 error;
 965
 966         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 967                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 968                       : "cc", "memory");
 969         if (error)
 970                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 971                        vmcs, phys_addr);
 972 }
 973
 974 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
 975 {
 976         vmcs_clear(loaded_vmcs->vmcs);
 977         loaded_vmcs->cpu = -1;
 978         loaded_vmcs->launched = 0;
 979 }
 980
 981 static void vmcs_load(struct vmcs *vmcs)
 982 {
 983         u64 phys_addr = __pa(vmcs);
 984         u8 error;
 985
 986         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 987                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 988                         : "cc", "memory");
 989         if (error)
 990                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
 991                        vmcs, phys_addr);
 992 }
 993
 994 static void __loaded_vmcs_clear(void *arg)
 995 {
 996         struct loaded_vmcs *loaded_vmcs = arg;
 997         int cpu = raw_smp_processor_id();
 998
 999         if (loaded_vmcs->cpu != cpu)
1000                 return; /* vcpu migration can race with cpu offline */
1001         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1002                 per_cpu(current_vmcs, cpu) = NULL;
1003         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1004         loaded_vmcs_init(loaded_vmcs);
1005 }
1006
1007 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1008 {
1009         if (loaded_vmcs->cpu != -1)
1010                 smp_call_function_single(
1011                         loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
1012 }
1013
1014 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1015 {
1016         if (vmx->vpid == 0)
1017                 return;
1018
1019         if (cpu_has_vmx_invvpid_single())
1020                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1021 }
1022
1023 static inline void vpid_sync_vcpu_global(void)
1024 {
1025         if (cpu_has_vmx_invvpid_global())
1026                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1027 }
1028
1029 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1030 {
1031         if (cpu_has_vmx_invvpid_single())
1032                 vpid_sync_vcpu_single(vmx);
1033         else
1034                 vpid_sync_vcpu_global();
1035 }
1036
1037 static inline void ept_sync_global(void)
1038 {
1039         if (cpu_has_vmx_invept_global())
1040                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1041 }
1042
1043 static inline void ept_sync_context(u64 eptp)
1044 {
1045         if (enable_ept) {
1046                 if (cpu_has_vmx_invept_context())
1047                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1048                 else
1049                         ept_sync_global();
1050         }
1051 }
1052
1053 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1054 {
1055         if (enable_ept) {
1056                 if (cpu_has_vmx_invept_individual_addr())
1057                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1058                                         eptp, gpa);
1059                 else
1060                         ept_sync_context(eptp);
1061         }
1062 }
1063
1064 static __always_inline unsigned long vmcs_readl(unsigned long field)
1065 {
1066         unsigned long value;
1067
1068         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1069                       : "=a"(value) : "d"(field) : "cc");
1070         return value;
1071 }
1072
1073 static __always_inline u16 vmcs_read16(unsigned long field)
1074 {
1075         return vmcs_readl(field);
1076 }
1077
1078 static __always_inline u32 vmcs_read32(unsigned long field)
1079 {
1080         return vmcs_readl(field);
1081 }
1082
1083 static __always_inline u64 vmcs_read64(unsigned long field)
1084 {
1085 #ifdef CONFIG_X86_64
1086         return vmcs_readl(field);
1087 #else
1088         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1089 #endif
1090 }
1091
1092 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1093 {
1094         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1095                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1096         dump_stack();
1097 }
1098
1099 static void vmcs_writel(unsigned long field, unsigned long value)
1100 {
1101         u8 error;
1102
1103         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1104                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1105         if (unlikely(error))
1106                 vmwrite_error(field, value);
1107 }
1108
1109 static void vmcs_write16(unsigned long field, u16 value)
1110 {
1111         vmcs_writel(field, value);
1112 }
1113
1114 static void vmcs_write32(unsigned long field, u32 value)
1115 {
1116         vmcs_writel(field, value);
1117 }
1118
1119 static void vmcs_write64(unsigned long field, u64 value)
1120 {
1121         vmcs_writel(field, value);
1122 #ifndef CONFIG_X86_64
1123         asm volatile ("");
1124         vmcs_writel(field+1, value >> 32);
1125 #endif
1126 }
1127
1128 static void vmcs_clear_bits(unsigned long field, u32 mask)
1129 {
1130         vmcs_writel(field, vmcs_readl(field) & ~mask);
1131 }
1132
1133 static void vmcs_set_bits(unsigned long field, u32 mask)
1134 {
1135         vmcs_writel(field, vmcs_readl(field) | mask);
1136 }
1137
1138 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1139 {
1140         vmx->segment_cache.bitmask = 0;
1141 }
1142
1143 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1144                                        unsigned field)
1145 {
1146         bool ret;
1147         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1148
1149         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1150                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1151                 vmx->segment_cache.bitmask = 0;
1152         }
1153         ret = vmx->segment_cache.bitmask & mask;
1154         vmx->segment_cache.bitmask |= mask;
1155         return ret;
1156 }
1157
1158 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1159 {
1160         u16 *p = &vmx->segment_cache.seg[seg].selector;
1161
1162         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1163                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1164         return *p;
1165 }
1166
1167 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1168 {
1169         ulong *p = &vmx->segment_cache.seg[seg].base;
1170
1171         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1172                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1173         return *p;
1174 }
1175
1176 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1177 {
1178         u32 *p = &vmx->segment_cache.seg[seg].limit;
1179
1180         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1181                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1182         return *p;
1183 }
1184
1185 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1186 {
1187         u32 *p = &vmx->segment_cache.seg[seg].ar;
1188
1189         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1190                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1191         return *p;
1192 }
1193
1194 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1195 {
1196         u32 eb;
1197
1198         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1199              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1200         if ((vcpu->guest_debug &
1201              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1202             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1203                 eb |= 1u << BP_VECTOR;
1204         if (to_vmx(vcpu)->rmode.vm86_active)
1205                 eb = ~0;
1206         if (enable_ept)
1207                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1208         if (vcpu->fpu_active)
1209                 eb &= ~(1u << NM_VECTOR);
1210
1211         /* When we are running a nested L2 guest and L1 specified for it a
1212          * certain exception bitmap, we must trap the same exceptions and pass
1213          * them to L1. When running L2, we will only handle the exceptions
1214          * specified above if L1 did not want them.
1215          */
1216         if (is_guest_mode(vcpu))
1217                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1218
1219         vmcs_write32(EXCEPTION_BITMAP, eb);
1220 }
1221
1222 static void clear_atomic_switch_msr_special(unsigned long entry,
1223                 unsigned long exit)
1224 {
1225         vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1226         vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1227 }
1228
1229 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1230 {
1231         unsigned i;
1232         struct msr_autoload *m = &vmx->msr_autoload;
1233
1234         switch (msr) {
1235         case MSR_EFER:
1236                 if (cpu_has_load_ia32_efer) {
1237                         clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1238                                         VM_EXIT_LOAD_IA32_EFER);
1239                         return;
1240                 }
1241                 break;
1242         case MSR_CORE_PERF_GLOBAL_CTRL:
1243                 if (cpu_has_load_perf_global_ctrl) {
1244                         clear_atomic_switch_msr_special(
1245                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1246                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1247                         return;
1248                 }
1249                 break;
1250         }
1251
1252         for (i = 0; i < m->nr; ++i)
1253                 if (m->guest[i].index == msr)
1254                         break;
1255
1256         if (i == m->nr)
1257                 return;
1258         --m->nr;
1259         m->guest[i] = m->guest[m->nr];
1260         m->host[i] = m->host[m->nr];
1261         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1262         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1263 }
1264
1265 static void add_atomic_switch_msr_special(unsigned long entry,
1266                 unsigned long exit, unsigned long guest_val_vmcs,
1267                 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1268 {
1269         vmcs_write64(guest_val_vmcs, guest_val);
1270         vmcs_write64(host_val_vmcs, host_val);
1271         vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1272         vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1273 }
1274
1275 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1276                                   u64 guest_val, u64 host_val)
1277 {
1278         unsigned i;
1279         struct msr_autoload *m = &vmx->msr_autoload;
1280
1281         switch (msr) {
1282         case MSR_EFER:
1283                 if (cpu_has_load_ia32_efer) {
1284                         add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1285                                         VM_EXIT_LOAD_IA32_EFER,
1286                                         GUEST_IA32_EFER,
1287                                         HOST_IA32_EFER,
1288                                         guest_val, host_val);
1289                         return;
1290                 }
1291                 break;
1292         case MSR_CORE_PERF_GLOBAL_CTRL:
1293                 if (cpu_has_load_perf_global_ctrl) {
1294                         add_atomic_switch_msr_special(
1295                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1296                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1297                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1298                                         HOST_IA32_PERF_GLOBAL_CTRL,
1299                                         guest_val, host_val);
1300                         return;
1301                 }
1302                 break;
1303         }
1304
1305         for (i = 0; i < m->nr; ++i)
1306                 if (m->guest[i].index == msr)
1307                         break;
1308
1309         if (i == NR_AUTOLOAD_MSRS) {
1310                 printk_once(KERN_WARNING"Not enough mst switch entries. "
1311                                 "Can't add msr %x\n", msr);
1312                 return;
1313         } else if (i == m->nr) {
1314                 ++m->nr;
1315                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1316                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1317         }
1318
1319         m->guest[i].index = msr;
1320         m->guest[i].value = guest_val;
1321         m->host[i].index = msr;
1322         m->host[i].value = host_val;
1323 }
1324
1325 static void reload_tss(void)
1326 {
1327         /*
1328          * VT restores TR but not its size.  Useless.
1329          */
1330         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1331         struct desc_struct *descs;
1332
1333         descs = (void *)gdt->address;
1334         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1335         load_TR_desc();
1336 }
1337
1338 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1339 {
1340         u64 guest_efer;
1341         u64 ignore_bits;
1342
1343         guest_efer = vmx->vcpu.arch.efer;
1344
1345         /*
1346          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1347          * outside long mode
1348          */
1349         ignore_bits = EFER_NX | EFER_SCE;
1350 #ifdef CONFIG_X86_64
1351         ignore_bits |= EFER_LMA | EFER_LME;
1352         /* SCE is meaningful only in long mode on Intel */
1353         if (guest_efer & EFER_LMA)
1354                 ignore_bits &= ~(u64)EFER_SCE;
1355 #endif
1356         guest_efer &= ~ignore_bits;
1357         guest_efer |= host_efer & ignore_bits;
1358         vmx->guest_msrs[efer_offset].data = guest_efer;
1359         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1360
1361         clear_atomic_switch_msr(vmx, MSR_EFER);
1362         /* On ept, can't emulate nx, and must switch nx atomically */
1363         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1364                 guest_efer = vmx->vcpu.arch.efer;
1365                 if (!(guest_efer & EFER_LMA))
1366                         guest_efer &= ~EFER_LME;
1367                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1368                 return false;
1369         }
1370
1371         return true;
1372 }
1373
1374 static unsigned long segment_base(u16 selector)
1375 {
1376         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1377         struct desc_struct *d;
1378         unsigned long table_base;
1379         unsigned long v;
1380
1381         if (!(selector & ~3))
1382                 return 0;
1383
1384         table_base = gdt->address;
1385
1386         if (selector & 4) {           /* from ldt */
1387                 u16 ldt_selector = kvm_read_ldt();
1388
1389                 if (!(ldt_selector & ~3))
1390                         return 0;
1391
1392                 table_base = segment_base(ldt_selector);
1393         }
1394         d = (struct desc_struct *)(table_base + (selector & ~7));
1395         v = get_desc_base(d);
1396 #ifdef CONFIG_X86_64
1397        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1398                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1399 #endif
1400         return v;
1401 }
1402
1403 static inline unsigned long kvm_read_tr_base(void)
1404 {
1405         u16 tr;
1406         asm("str %0" : "=g"(tr));
1407         return segment_base(tr);
1408 }
1409
1410 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1411 {
1412         struct vcpu_vmx *vmx = to_vmx(vcpu);
1413         int i;
1414
1415         if (vmx->host_state.loaded)
1416                 return;
1417
1418         vmx->host_state.loaded = 1;
1419         /*
1420          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1421          * allow segment selectors with cpl > 0 or ti == 1.
1422          */
1423         vmx->host_state.ldt_sel = kvm_read_ldt();
1424         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1425         savesegment(fs, vmx->host_state.fs_sel);
1426         if (!(vmx->host_state.fs_sel & 7)) {
1427                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1428                 vmx->host_state.fs_reload_needed = 0;
1429         } else {
1430                 vmcs_write16(HOST_FS_SELECTOR, 0);
1431                 vmx->host_state.fs_reload_needed = 1;
1432         }
1433         savesegment(gs, vmx->host_state.gs_sel);
1434         if (!(vmx->host_state.gs_sel & 7))
1435                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1436         else {
1437                 vmcs_write16(HOST_GS_SELECTOR, 0);
1438                 vmx->host_state.gs_ldt_reload_needed = 1;
1439         }
1440
1441 #ifdef CONFIG_X86_64
1442         savesegment(ds, vmx->host_state.ds_sel);
1443         savesegment(es, vmx->host_state.es_sel);
1444 #endif
1445
1446 #ifdef CONFIG_X86_64
1447         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1448         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1449 #else
1450         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1451         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1452 #endif
1453
1454 #ifdef CONFIG_X86_64
1455         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1456         if (is_long_mode(&vmx->vcpu))
1457                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1458 #endif
1459         for (i = 0; i < vmx->save_nmsrs; ++i)
1460                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1461                                    vmx->guest_msrs[i].data,
1462                                    vmx->guest_msrs[i].mask);
1463 }
1464
1465 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1466 {
1467         if (!vmx->host_state.loaded)
1468                 return;
1469
1470         ++vmx->vcpu.stat.host_state_reload;
1471         vmx->host_state.loaded = 0;
1472 #ifdef CONFIG_X86_64
1473         if (is_long_mode(&vmx->vcpu))
1474                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1475 #endif
1476         if (vmx->host_state.gs_ldt_reload_needed) {
1477                 kvm_load_ldt(vmx->host_state.ldt_sel);
1478 #ifdef CONFIG_X86_64
1479                 load_gs_index(vmx->host_state.gs_sel);
1480 #else
1481                 loadsegment(gs, vmx->host_state.gs_sel);
1482 #endif
1483         }
1484         if (vmx->host_state.fs_reload_needed)
1485                 loadsegment(fs, vmx->host_state.fs_sel);
1486 #ifdef CONFIG_X86_64
1487         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1488                 loadsegment(ds, vmx->host_state.ds_sel);
1489                 loadsegment(es, vmx->host_state.es_sel);
1490         }
1491 #endif
1492         reload_tss();
1493 #ifdef CONFIG_X86_64
1494         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1495 #endif
1496         /*
1497          * If the FPU is not active (through the host task or
1498          * the guest vcpu), then restore the cr0.TS bit.
1499          */
1500         if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1501                 stts();
1502         load_gdt(&__get_cpu_var(host_gdt));
1503 }
1504
1505 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1506 {
1507         preempt_disable();
1508         __vmx_load_host_state(vmx);
1509         preempt_enable();
1510 }
1511
1512 /*
1513  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1514  * vcpu mutex is already taken.
1515  */
1516 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1517 {
1518         struct vcpu_vmx *vmx = to_vmx(vcpu);
1519         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1520
1521         if (!vmm_exclusive)
1522                 kvm_cpu_vmxon(phys_addr);
1523         else if (vmx->loaded_vmcs->cpu != cpu)
1524                 loaded_vmcs_clear(vmx->loaded_vmcs);
1525
1526         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1527                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1528                 vmcs_load(vmx->loaded_vmcs->vmcs);
1529         }
1530
1531         if (vmx->loaded_vmcs->cpu != cpu) {
1532                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1533                 unsigned long sysenter_esp;
1534
1535                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1536                 local_irq_disable();
1537                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1538                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1539                 local_irq_enable();
1540
1541                 /*
1542                  * Linux uses per-cpu TSS and GDT, so set these when switching
1543                  * processors.
1544                  */
1545                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1546                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1547
1548                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1549                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1550                 vmx->loaded_vmcs->cpu = cpu;
1551         }
1552 }
1553
1554 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1555 {
1556         __vmx_load_host_state(to_vmx(vcpu));
1557         if (!vmm_exclusive) {
1558                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1559                 vcpu->cpu = -1;
1560                 kvm_cpu_vmxoff();
1561         }
1562 }
1563
1564 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1565 {
1566         ulong cr0;
1567
1568         if (vcpu->fpu_active)
1569                 return;
1570         vcpu->fpu_active = 1;
1571         cr0 = vmcs_readl(GUEST_CR0);
1572         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1573         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1574         vmcs_writel(GUEST_CR0, cr0);
1575         update_exception_bitmap(vcpu);
1576         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1577         if (is_guest_mode(vcpu))
1578                 vcpu->arch.cr0_guest_owned_bits &=
1579                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1580         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1581 }
1582
1583 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1584
1585 /*
1586  * Return the cr0 value that a nested guest would read. This is a combination
1587  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1588  * its hypervisor (cr0_read_shadow).
1589  */
1590 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1591 {
1592         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1593                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1594 }
1595 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1596 {
1597         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1598                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1599 }
1600
1601 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1602 {
1603         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1604          * set this *before* calling this function.
1605          */
1606         vmx_decache_cr0_guest_bits(vcpu);
1607         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1608         update_exception_bitmap(vcpu);
1609         vcpu->arch.cr0_guest_owned_bits = 0;
1610         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1611         if (is_guest_mode(vcpu)) {
1612                 /*
1613                  * L1's specified read shadow might not contain the TS bit,
1614                  * so now that we turned on shadowing of this bit, we need to
1615                  * set this bit of the shadow. Like in nested_vmx_run we need
1616                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1617                  * up-to-date here because we just decached cr0.TS (and we'll
1618                  * only update vmcs12->guest_cr0 on nested exit).
1619                  */
1620                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1621                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1622                         (vcpu->arch.cr0 & X86_CR0_TS);
1623                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1624         } else
1625                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1626 }
1627
1628 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1629 {
1630         unsigned long rflags, save_rflags;
1631
1632         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1633                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1634                 rflags = vmcs_readl(GUEST_RFLAGS);
1635                 if (to_vmx(vcpu)->rmode.vm86_active) {
1636                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1637                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1638                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1639                 }
1640                 to_vmx(vcpu)->rflags = rflags;
1641         }
1642         return to_vmx(vcpu)->rflags;
1643 }
1644
1645 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1646 {
1647         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1648         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
1649         to_vmx(vcpu)->rflags = rflags;
1650         if (to_vmx(vcpu)->rmode.vm86_active) {
1651                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1652                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1653         }
1654         vmcs_writel(GUEST_RFLAGS, rflags);
1655 }
1656
1657 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1658 {
1659         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1660         int ret = 0;
1661
1662         if (interruptibility & GUEST_INTR_STATE_STI)
1663                 ret |= KVM_X86_SHADOW_INT_STI;
1664         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1665                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1666
1667         return ret & mask;
1668 }
1669
1670 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1671 {
1672         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1673         u32 interruptibility = interruptibility_old;
1674
1675         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1676
1677         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1678                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1679         else if (mask & KVM_X86_SHADOW_INT_STI)
1680                 interruptibility |= GUEST_INTR_STATE_STI;
1681
1682         if ((interruptibility != interruptibility_old))
1683                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1684 }
1685
1686 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1687 {
1688         unsigned long rip;
1689
1690         rip = kvm_rip_read(vcpu);
1691         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1692         kvm_rip_write(vcpu, rip);
1693
1694         /* skipping an emulated instruction also counts */
1695         vmx_set_interrupt_shadow(vcpu, 0);
1696 }
1697
1698 /*
1699  * KVM wants to inject page-faults which it got to the guest. This function
1700  * checks whether in a nested guest, we need to inject them to L1 or L2.
1701  * This function assumes it is called with the exit reason in vmcs02 being
1702  * a #PF exception (this is the only case in which KVM injects a #PF when L2
1703  * is running).
1704  */
1705 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1706 {
1707         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1708
1709         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1710         if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
1711                 return 0;
1712
1713         nested_vmx_vmexit(vcpu);
1714         return 1;
1715 }
1716
1717 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1718                                 bool has_error_code, u32 error_code,
1719                                 bool reinject)
1720 {
1721         struct vcpu_vmx *vmx = to_vmx(vcpu);
1722         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1723
1724         if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1725                 nested_pf_handled(vcpu))
1726                 return;
1727
1728         if (has_error_code) {
1729                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1730                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1731         }
1732
1733         if (vmx->rmode.vm86_active) {
1734                 int inc_eip = 0;
1735                 if (kvm_exception_is_soft(nr))
1736                         inc_eip = vcpu->arch.event_exit_inst_len;
1737                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1738                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1739                 return;
1740         }
1741
1742         if (kvm_exception_is_soft(nr)) {
1743                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1744                              vmx->vcpu.arch.event_exit_inst_len);
1745                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1746         } else
1747                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1748
1749         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1750 }
1751
1752 static bool vmx_rdtscp_supported(void)
1753 {
1754         return cpu_has_vmx_rdtscp();
1755 }
1756
1757 static bool vmx_invpcid_supported(void)
1758 {
1759         return cpu_has_vmx_invpcid() && enable_ept;
1760 }
1761
1762 /*
1763  * Swap MSR entry in host/guest MSR entry array.
1764  */
1765 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1766 {
1767         struct shared_msr_entry tmp;
1768
1769         tmp = vmx->guest_msrs[to];
1770         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1771         vmx->guest_msrs[from] = tmp;
1772 }
1773
1774 /*
1775  * Set up the vmcs to automatically save and restore system
1776  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1777  * mode, as fiddling with msrs is very expensive.
1778  */
1779 static void setup_msrs(struct vcpu_vmx *vmx)
1780 {
1781         int save_nmsrs, index;
1782         unsigned long *msr_bitmap;
1783
1784         save_nmsrs = 0;
1785 #ifdef CONFIG_X86_64
1786         if (is_long_mode(&vmx->vcpu)) {
1787                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1788                 if (index >= 0)
1789                         move_msr_up(vmx, index, save_nmsrs++);
1790                 index = __find_msr_index(vmx, MSR_LSTAR);
1791                 if (index >= 0)
1792                         move_msr_up(vmx, index, save_nmsrs++);
1793                 index = __find_msr_index(vmx, MSR_CSTAR);
1794                 if (index >= 0)
1795                         move_msr_up(vmx, index, save_nmsrs++);
1796                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1797                 if (index >= 0 && vmx->rdtscp_enabled)
1798                         move_msr_up(vmx, index, save_nmsrs++);
1799                 /*
1800                  * MSR_STAR is only needed on long mode guests, and only
1801                  * if efer.sce is enabled.
1802                  */
1803                 index = __find_msr_index(vmx, MSR_STAR);
1804                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1805                         move_msr_up(vmx, index, save_nmsrs++);
1806         }
1807 #endif
1808         index = __find_msr_index(vmx, MSR_EFER);
1809         if (index >= 0 && update_transition_efer(vmx, index))
1810                 move_msr_up(vmx, index, save_nmsrs++);
1811
1812         vmx->save_nmsrs = save_nmsrs;
1813
1814         if (cpu_has_vmx_msr_bitmap()) {
1815                 if (is_long_mode(&vmx->vcpu))
1816                         msr_bitmap = vmx_msr_bitmap_longmode;
1817                 else
1818                         msr_bitmap = vmx_msr_bitmap_legacy;
1819
1820                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1821         }
1822 }
1823
1824 /*
1825  * reads and returns guest's timestamp counter "register"
1826  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1827  */
1828 static u64 guest_read_tsc(void)
1829 {
1830         u64 host_tsc, tsc_offset;
1831
1832         rdtscll(host_tsc);
1833         tsc_offset = vmcs_read64(TSC_OFFSET);
1834         return host_tsc + tsc_offset;
1835 }
1836
1837 /*
1838  * Like guest_read_tsc, but always returns L1's notion of the timestamp
1839  * counter, even if a nested guest (L2) is currently running.
1840  */
1841 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu)
1842 {
1843         u64 host_tsc, tsc_offset;
1844
1845         rdtscll(host_tsc);
1846         tsc_offset = is_guest_mode(vcpu) ?
1847                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1848                 vmcs_read64(TSC_OFFSET);
1849         return host_tsc + tsc_offset;
1850 }
1851
1852 /*
1853  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
1854  * software catchup for faster rates on slower CPUs.
1855  */
1856 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1857 {
1858         if (!scale)
1859                 return;
1860
1861         if (user_tsc_khz > tsc_khz) {
1862                 vcpu->arch.tsc_catchup = 1;
1863                 vcpu->arch.tsc_always_catchup = 1;
1864         } else
1865                 WARN(1, "user requested TSC rate below hardware speed\n");
1866 }
1867
1868 /*
1869  * writes 'offset' into guest's timestamp counter offset register
1870  */
1871 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1872 {
1873         if (is_guest_mode(vcpu)) {
1874                 /*
1875                  * We're here if L1 chose not to trap WRMSR to TSC. According
1876                  * to the spec, this should set L1's TSC; The offset that L1
1877                  * set for L2 remains unchanged, and still needs to be added
1878                  * to the newly set TSC to get L2's TSC.
1879                  */
1880                 struct vmcs12 *vmcs12;
1881                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1882                 /* recalculate vmcs02.TSC_OFFSET: */
1883                 vmcs12 = get_vmcs12(vcpu);
1884                 vmcs_write64(TSC_OFFSET, offset +
1885                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1886                          vmcs12->tsc_offset : 0));
1887         } else {
1888                 vmcs_write64(TSC_OFFSET, offset);
1889         }
1890 }
1891
1892 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1893 {
1894         u64 offset = vmcs_read64(TSC_OFFSET);
1895         vmcs_write64(TSC_OFFSET, offset + adjustment);
1896         if (is_guest_mode(vcpu)) {
1897                 /* Even when running L2, the adjustment needs to apply to L1 */
1898                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1899         }
1900 }
1901
1902 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1903 {
1904         return target_tsc - native_read_tsc();
1905 }
1906
1907 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1908 {
1909         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1910         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1911 }
1912
1913 /*
1914  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1915  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1916  * all guests if the "nested" module option is off, and can also be disabled
1917  * for a single guest by disabling its VMX cpuid bit.
1918  */
1919 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1920 {
1921         return nested && guest_cpuid_has_vmx(vcpu);
1922 }
1923
1924 /*
1925  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1926  * returned for the various VMX controls MSRs when nested VMX is enabled.
1927  * The same values should also be used to verify that vmcs12 control fields are
1928  * valid during nested entry from L1 to L2.
1929  * Each of these control msrs has a low and high 32-bit half: A low bit is on
1930  * if the corresponding bit in the (32-bit) control field *must* be on, and a
1931  * bit in the high half is on if the corresponding bit in the control field
1932  * may be on. See also vmx_control_verify().
1933  * TODO: allow these variables to be modified (downgraded) by module options
1934  * or other means.
1935  */
1936 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1937 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1938 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1939 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1940 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1941 static __init void nested_vmx_setup_ctls_msrs(void)
1942 {
1943         /*
1944          * Note that as a general rule, the high half of the MSRs (bits in
1945          * the control fields which may be 1) should be initialized by the
1946          * intersection of the underlying hardware's MSR (i.e., features which
1947          * can be supported) and the list of features we want to expose -
1948          * because they are known to be properly supported in our code.
1949          * Also, usually, the low half of the MSRs (bits which must be 1) can
1950          * be set to 0, meaning that L1 may turn off any of these bits. The
1951          * reason is that if one of these bits is necessary, it will appear
1952          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1953          * fields of vmcs01 and vmcs02, will turn these bits off - and
1954          * nested_vmx_exit_handled() will not pass related exits to L1.
1955          * These rules have exceptions below.
1956          */
1957
1958         /* pin-based controls */
1959         /*
1960          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1961          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1962          */
1963         nested_vmx_pinbased_ctls_low = 0x16 ;
1964         nested_vmx_pinbased_ctls_high = 0x16 |
1965                 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1966                 PIN_BASED_VIRTUAL_NMIS;
1967
1968         /* exit controls */
1969         nested_vmx_exit_ctls_low = 0;
1970         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
1971 #ifdef CONFIG_X86_64
1972         nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1973 #else
1974         nested_vmx_exit_ctls_high = 0;
1975 #endif
1976
1977         /* entry controls */
1978         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1979                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1980         nested_vmx_entry_ctls_low = 0;
1981         nested_vmx_entry_ctls_high &=
1982                 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1983
1984         /* cpu-based controls */
1985         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1986                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1987         nested_vmx_procbased_ctls_low = 0;
1988         nested_vmx_procbased_ctls_high &=
1989                 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1990                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1991                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1992                 CPU_BASED_CR3_STORE_EXITING |
1993 #ifdef CONFIG_X86_64
1994                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1995 #endif
1996                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1997                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1998                 CPU_BASED_RDPMC_EXITING |
1999                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2000         /*
2001          * We can allow some features even when not supported by the
2002          * hardware. For example, L1 can specify an MSR bitmap - and we
2003          * can use it to avoid exits to L1 - even when L0 runs L2
2004          * without MSR bitmaps.
2005          */
2006         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2007
2008         /* secondary cpu-based controls */
2009         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2010                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2011         nested_vmx_secondary_ctls_low = 0;
2012         nested_vmx_secondary_ctls_high &=
2013                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2014 }
2015
2016 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2017 {
2018         /*
2019          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2020          */
2021         return ((control & high) | low) == control;
2022 }
2023
2024 static inline u64 vmx_control_msr(u32 low, u32 high)
2025 {
2026         return low | ((u64)high << 32);
2027 }
2028
2029 /*
2030  * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2031  * also let it use VMX-specific MSRs.
2032  * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2033  * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2034  * like all other MSRs).
2035  */
2036 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2037 {
2038         if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2039                      msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2040                 /*
2041                  * According to the spec, processors which do not support VMX
2042                  * should throw a #GP(0) when VMX capability MSRs are read.
2043                  */
2044                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2045                 return 1;
2046         }
2047
2048         switch (msr_index) {
2049         case MSR_IA32_FEATURE_CONTROL:
2050                 *pdata = 0;
2051                 break;
2052         case MSR_IA32_VMX_BASIC:
2053                 /*
2054                  * This MSR reports some information about VMX support. We
2055                  * should return information about the VMX we emulate for the
2056                  * guest, and the VMCS structure we give it - not about the
2057                  * VMX support of the underlying hardware.
2058                  */
2059                 *pdata = VMCS12_REVISION |
2060                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2061                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2062                 break;
2063         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2064         case MSR_IA32_VMX_PINBASED_CTLS:
2065                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2066                                         nested_vmx_pinbased_ctls_high);
2067                 break;
2068         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2069         case MSR_IA32_VMX_PROCBASED_CTLS:
2070                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2071                                         nested_vmx_procbased_ctls_high);
2072                 break;
2073         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2074         case MSR_IA32_VMX_EXIT_CTLS:
2075                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2076                                         nested_vmx_exit_ctls_high);
2077                 break;
2078         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2079         case MSR_IA32_VMX_ENTRY_CTLS:
2080                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2081                                         nested_vmx_entry_ctls_high);
2082                 break;
2083         case MSR_IA32_VMX_MISC:
2084                 *pdata = 0;
2085                 break;
2086         /*
2087          * These MSRs specify bits which the guest must keep fixed (on or off)
2088          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2089          * We picked the standard core2 setting.
2090          */
2091 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2092 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2093         case MSR_IA32_VMX_CR0_FIXED0:
2094                 *pdata = VMXON_CR0_ALWAYSON;
2095                 break;
2096         case MSR_IA32_VMX_CR0_FIXED1:
2097                 *pdata = -1ULL;
2098                 break;
2099         case MSR_IA32_VMX_CR4_FIXED0:
2100                 *pdata = VMXON_CR4_ALWAYSON;
2101                 break;
2102         case MSR_IA32_VMX_CR4_FIXED1:
2103                 *pdata = -1ULL;
2104                 break;
2105         case MSR_IA32_VMX_VMCS_ENUM:
2106                 *pdata = 0x1f;
2107                 break;
2108         case MSR_IA32_VMX_PROCBASED_CTLS2:
2109                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2110                                         nested_vmx_secondary_ctls_high);
2111                 break;
2112         case MSR_IA32_VMX_EPT_VPID_CAP:
2113                 /* Currently, no nested ept or nested vpid */
2114                 *pdata = 0;
2115                 break;
2116         default:
2117                 return 0;
2118         }
2119
2120         return 1;
2121 }
2122
2123 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2124 {
2125         if (!nested_vmx_allowed(vcpu))
2126                 return 0;
2127
2128         if (msr_index == MSR_IA32_FEATURE_CONTROL)
2129                 /* TODO: the right thing. */
2130                 return 1;
2131         /*
2132          * No need to treat VMX capability MSRs specially: If we don't handle
2133          * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2134          */
2135         return 0;
2136 }
2137
2138 /*
2139  * Reads an msr value (of 'msr_index') into 'pdata'.
2140  * Returns 0 on success, non-0 otherwise.
2141  * Assumes vcpu_load() was already called.
2142  */
2143 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2144 {
2145         u64 data;
2146         struct shared_msr_entry *msr;
2147
2148         if (!pdata) {
2149                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2150                 return -EINVAL;
2151         }
2152
2153         switch (msr_index) {
2154 #ifdef CONFIG_X86_64
2155         case MSR_FS_BASE:
2156                 data = vmcs_readl(GUEST_FS_BASE);
2157                 break;
2158         case MSR_GS_BASE:
2159                 data = vmcs_readl(GUEST_GS_BASE);
2160                 break;
2161         case MSR_KERNEL_GS_BASE:
2162                 vmx_load_host_state(to_vmx(vcpu));
2163                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2164                 break;
2165 #endif
2166         case MSR_EFER:
2167                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2168         case MSR_IA32_TSC:
2169                 data = guest_read_tsc();
2170                 break;
2171         case MSR_IA32_SYSENTER_CS:
2172                 data = vmcs_read32(GUEST_SYSENTER_CS);
2173                 break;
2174         case MSR_IA32_SYSENTER_EIP:
2175                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2176                 break;
2177         case MSR_IA32_SYSENTER_ESP:
2178                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2179                 break;
2180         case MSR_TSC_AUX:
2181                 if (!to_vmx(vcpu)->rdtscp_enabled)
2182                         return 1;
2183                 /* Otherwise falls through */
2184         default:
2185                 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2186                         return 0;
2187                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2188                 if (msr) {
2189                         data = msr->data;
2190                         break;
2191                 }
2192                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2193         }
2194
2195         *pdata = data;
2196         return 0;
2197 }
2198
2199 /*
2200  * Writes msr value into into the appropriate "register".
2201  * Returns 0 on success, non-0 otherwise.
2202  * Assumes vcpu_load() was already called.
2203  */
2204 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2205 {
2206         struct vcpu_vmx *vmx = to_vmx(vcpu);
2207         struct shared_msr_entry *msr;
2208         int ret = 0;
2209
2210         switch (msr_index) {
2211         case MSR_EFER:
2212                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2213                 break;
2214 #ifdef CONFIG_X86_64
2215         case MSR_FS_BASE:
2216                 vmx_segment_cache_clear(vmx);
2217                 vmcs_writel(GUEST_FS_BASE, data);
2218                 break;
2219         case MSR_GS_BASE:
2220                 vmx_segment_cache_clear(vmx);
2221                 vmcs_writel(GUEST_GS_BASE, data);
2222                 break;
2223         case MSR_KERNEL_GS_BASE:
2224                 vmx_load_host_state(vmx);
2225                 vmx->msr_guest_kernel_gs_base = data;
2226                 break;
2227 #endif
2228         case MSR_IA32_SYSENTER_CS:
2229                 vmcs_write32(GUEST_SYSENTER_CS, data);
2230                 break;
2231         case MSR_IA32_SYSENTER_EIP:
2232                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2233                 break;
2234         case MSR_IA32_SYSENTER_ESP:
2235                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2236                 break;
2237         case MSR_IA32_TSC:
2238                 kvm_write_tsc(vcpu, data);
2239                 break;
2240         case MSR_IA32_CR_PAT:
2241                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2242                         vmcs_write64(GUEST_IA32_PAT, data);
2243                         vcpu->arch.pat = data;
2244                         break;
2245                 }
2246                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2247                 break;
2248         case MSR_TSC_AUX:
2249                 if (!vmx->rdtscp_enabled)
2250                         return 1;
2251                 /* Check reserved bit, higher 32 bits should be zero */
2252                 if ((data >> 32) != 0)
2253                         return 1;
2254                 /* Otherwise falls through */
2255         default:
2256                 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2257                         break;
2258                 msr = find_msr_entry(vmx, msr_index);
2259                 if (msr) {
2260                         msr->data = data;
2261                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2262                                 preempt_disable();
2263                                 kvm_set_shared_msr(msr->index, msr->data,
2264                                                    msr->mask);
2265                                 preempt_enable();
2266                         }
2267                         break;
2268                 }
2269                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2270         }
2271
2272         return ret;
2273 }
2274
2275 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2276 {
2277         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2278         switch (reg) {
2279         case VCPU_REGS_RSP:
2280                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2281                 break;
2282         case VCPU_REGS_RIP:
2283                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2284                 break;
2285         case VCPU_EXREG_PDPTR:
2286                 if (enable_ept)
2287                         ept_save_pdptrs(vcpu);
2288                 break;
2289         default:
2290                 break;
2291         }
2292 }
2293
2294 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
2295 {
2296         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2297                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2298         else
2299                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2300
2301         update_exception_bitmap(vcpu);
2302 }
2303
2304 static __init int cpu_has_kvm_support(void)
2305 {
2306         return cpu_has_vmx();
2307 }
2308
2309 static __init int vmx_disabled_by_bios(void)
2310 {
2311         u64 msr;
2312
2313         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2314         if (msr & FEATURE_CONTROL_LOCKED) {
2315                 /* launched w/ TXT and VMX disabled */
2316                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2317                         && tboot_enabled())
2318                         return 1;
2319                 /* launched w/o TXT and VMX only enabled w/ TXT */
2320                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2321                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2322                         && !tboot_enabled()) {
2323                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2324                                 "activate TXT before enabling KVM\n");
2325                         return 1;
2326                 }
2327                 /* launched w/o TXT and VMX disabled */
2328                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2329                         && !tboot_enabled())
2330                         return 1;
2331         }
2332
2333         return 0;
2334 }
2335
2336 static void kvm_cpu_vmxon(u64 addr)
2337 {
2338         asm volatile (ASM_VMX_VMXON_RAX
2339                         : : "a"(&addr), "m"(addr)
2340                         : "memory", "cc");
2341 }
2342
2343 static int hardware_enable(void *garbage)
2344 {
2345         int cpu = raw_smp_processor_id();
2346         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2347         u64 old, test_bits;
2348
2349         if (read_cr4() & X86_CR4_VMXE)
2350                 return -EBUSY;
2351
2352         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2353         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2354
2355         test_bits = FEATURE_CONTROL_LOCKED;
2356         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2357         if (tboot_enabled())
2358                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2359
2360         if ((old & test_bits) != test_bits) {
2361                 /* enable and lock */
2362                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2363         }
2364         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2365
2366         if (vmm_exclusive) {
2367                 kvm_cpu_vmxon(phys_addr);
2368                 ept_sync_global();
2369         }
2370
2371         store_gdt(&__get_cpu_var(host_gdt));
2372
2373         return 0;
2374 }
2375
2376 static void vmclear_local_loaded_vmcss(void)
2377 {
2378         int cpu = raw_smp_processor_id();
2379         struct loaded_vmcs *v, *n;
2380
2381         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2382                                  loaded_vmcss_on_cpu_link)
2383                 __loaded_vmcs_clear(v);
2384 }
2385
2386
2387 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2388  * tricks.
2389  */
2390 static void kvm_cpu_vmxoff(void)
2391 {
2392         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2393 }
2394
2395 static void hardware_disable(void *garbage)
2396 {
2397         if (vmm_exclusive) {
2398                 vmclear_local_loaded_vmcss();
2399                 kvm_cpu_vmxoff();
2400         }
2401         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2402 }
2403
2404 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2405                                       u32 msr, u32 *result)
2406 {
2407         u32 vmx_msr_low, vmx_msr_high;
2408         u32 ctl = ctl_min | ctl_opt;
2409
2410         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2411
2412         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2413         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2414
2415         /* Ensure minimum (required) set of control bits are supported. */
2416         if (ctl_min & ~ctl)
2417                 return -EIO;
2418
2419         *result = ctl;
2420         return 0;
2421 }
2422
2423 static __init bool allow_1_setting(u32 msr, u32 ctl)
2424 {
2425         u32 vmx_msr_low, vmx_msr_high;
2426
2427         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2428         return vmx_msr_high & ctl;
2429 }
2430
2431 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2432 {
2433         u32 vmx_msr_low, vmx_msr_high;
2434         u32 min, opt, min2, opt2;
2435         u32 _pin_based_exec_control = 0;
2436         u32 _cpu_based_exec_control = 0;
2437         u32 _cpu_based_2nd_exec_control = 0;
2438         u32 _vmexit_control = 0;
2439         u32 _vmentry_control = 0;
2440
2441         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2442         opt = PIN_BASED_VIRTUAL_NMIS;
2443         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2444                                 &_pin_based_exec_control) < 0)
2445                 return -EIO;
2446
2447         min = CPU_BASED_HLT_EXITING |
2448 #ifdef CONFIG_X86_64
2449               CPU_BASED_CR8_LOAD_EXITING |
2450               CPU_BASED_CR8_STORE_EXITING |
2451 #endif
2452               CPU_BASED_CR3_LOAD_EXITING |
2453               CPU_BASED_CR3_STORE_EXITING |
2454               CPU_BASED_USE_IO_BITMAPS |
2455               CPU_BASED_MOV_DR_EXITING |
2456               CPU_BASED_USE_TSC_OFFSETING |
2457               CPU_BASED_MWAIT_EXITING |
2458               CPU_BASED_MONITOR_EXITING |
2459               CPU_BASED_INVLPG_EXITING |
2460               CPU_BASED_RDPMC_EXITING;
2461
2462         opt = CPU_BASED_TPR_SHADOW |
2463               CPU_BASED_USE_MSR_BITMAPS |
2464               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2465         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2466                                 &_cpu_based_exec_control) < 0)
2467                 return -EIO;
2468 #ifdef CONFIG_X86_64
2469         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2470                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2471                                            ~CPU_BASED_CR8_STORE_EXITING;
2472 #endif
2473         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2474                 min2 = 0;
2475                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2476                         SECONDARY_EXEC_WBINVD_EXITING |
2477                         SECONDARY_EXEC_ENABLE_VPID |
2478                         SECONDARY_EXEC_ENABLE_EPT |
2479                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2480                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2481                         SECONDARY_EXEC_RDTSCP |
2482                         SECONDARY_EXEC_ENABLE_INVPCID;
2483                 if (adjust_vmx_controls(min2, opt2,
2484                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2485                                         &_cpu_based_2nd_exec_control) < 0)
2486                         return -EIO;
2487         }
2488 #ifndef CONFIG_X86_64
2489         if (!(_cpu_based_2nd_exec_control &
2490                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2491                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2492 #endif
2493         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2494                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2495                    enabled */
2496                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2497                                              CPU_BASED_CR3_STORE_EXITING |
2498                                              CPU_BASED_INVLPG_EXITING);
2499                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2500                       vmx_capability.ept, vmx_capability.vpid);
2501         }
2502
2503         min = 0;
2504 #ifdef CONFIG_X86_64
2505         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2506 #endif
2507         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
2508         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2509                                 &_vmexit_control) < 0)
2510                 return -EIO;
2511
2512         min = 0;
2513         opt = VM_ENTRY_LOAD_IA32_PAT;
2514         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2515                                 &_vmentry_control) < 0)
2516                 return -EIO;
2517
2518         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2519
2520         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2521         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2522                 return -EIO;
2523
2524 #ifdef CONFIG_X86_64
2525         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2526         if (vmx_msr_high & (1u<<16))
2527                 return -EIO;
2528 #endif
2529
2530         /* Require Write-Back (WB) memory type for VMCS accesses. */
2531         if (((vmx_msr_high >> 18) & 15) != 6)
2532                 return -EIO;
2533
2534         vmcs_conf->size = vmx_msr_high & 0x1fff;
2535         vmcs_conf->order = get_order(vmcs_config.size);
2536         vmcs_conf->revision_id = vmx_msr_low;
2537
2538         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2539         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2540         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2541         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2542         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2543
2544         cpu_has_load_ia32_efer =
2545                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2546                                 VM_ENTRY_LOAD_IA32_EFER)
2547                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2548                                    VM_EXIT_LOAD_IA32_EFER);
2549
2550         cpu_has_load_perf_global_ctrl =
2551                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2552                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2553                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2554                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2555
2556         /*
2557          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2558          * but due to arrata below it can't be used. Workaround is to use
2559          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2560          *
2561          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2562          *
2563          * AAK155             (model 26)
2564          * AAP115             (model 30)
2565          * AAT100             (model 37)
2566          * BC86,AAY89,BD102   (model 44)
2567          * BA97               (model 46)
2568          *
2569          */
2570         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2571                 switch (boot_cpu_data.x86_model) {
2572                 case 26:
2573                 case 30:
2574                 case 37:
2575                 case 44:
2576                 case 46:
2577                         cpu_has_load_perf_global_ctrl = false;
2578                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2579                                         "does not work properly. Using workaround\n");
2580                         break;
2581                 default:
2582                         break;
2583                 }
2584         }
2585
2586         return 0;
2587 }
2588
2589 static struct vmcs *alloc_vmcs_cpu(int cpu)
2590 {
2591         int node = cpu_to_node(cpu);
2592         struct page *pages;
2593         struct vmcs *vmcs;
2594
2595         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2596         if (!pages)
2597                 return NULL;
2598         vmcs = page_address(pages);
2599         memset(vmcs, 0, vmcs_config.size);
2600         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2601         return vmcs;
2602 }
2603
2604 static struct vmcs *alloc_vmcs(void)
2605 {
2606         return alloc_vmcs_cpu(raw_smp_processor_id());
2607 }
2608
2609 static void free_vmcs(struct vmcs *vmcs)
2610 {
2611         free_pages((unsigned long)vmcs, vmcs_config.order);
2612 }
2613
2614 /*
2615  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2616  */
2617 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2618 {
2619         if (!loaded_vmcs->vmcs)
2620                 return;
2621         loaded_vmcs_clear(loaded_vmcs);
2622         free_vmcs(loaded_vmcs->vmcs);
2623         loaded_vmcs->vmcs = NULL;
2624 }
2625
2626 static void free_kvm_area(void)
2627 {
2628         int cpu;
2629
2630         for_each_possible_cpu(cpu) {
2631                 free_vmcs(per_cpu(vmxarea, cpu));
2632                 per_cpu(vmxarea, cpu) = NULL;
2633         }
2634 }
2635
2636 static __init int alloc_kvm_area(void)
2637 {
2638         int cpu;
2639
2640         for_each_possible_cpu(cpu) {
2641                 struct vmcs *vmcs;
2642
2643                 vmcs = alloc_vmcs_cpu(cpu);
2644                 if (!vmcs) {
2645                         free_kvm_area();
2646                         return -ENOMEM;
2647                 }
2648
2649                 per_cpu(vmxarea, cpu) = vmcs;
2650         }
2651         return 0;
2652 }
2653
2654 static __init int hardware_setup(void)
2655 {
2656         if (setup_vmcs_config(&vmcs_config) < 0)
2657                 return -EIO;
2658
2659         if (boot_cpu_has(X86_FEATURE_NX))
2660                 kvm_enable_efer_bits(EFER_NX);
2661
2662         if (!cpu_has_vmx_vpid())
2663                 enable_vpid = 0;
2664
2665         if (!cpu_has_vmx_ept() ||
2666             !cpu_has_vmx_ept_4levels()) {
2667                 enable_ept = 0;
2668                 enable_unrestricted_guest = 0;
2669                 enable_ept_ad_bits = 0;
2670         }
2671
2672         if (!cpu_has_vmx_ept_ad_bits())
2673                 enable_ept_ad_bits = 0;
2674
2675         if (!cpu_has_vmx_unrestricted_guest())
2676                 enable_unrestricted_guest = 0;
2677
2678         if (!cpu_has_vmx_flexpriority())
2679                 flexpriority_enabled = 0;
2680
2681         if (!cpu_has_vmx_tpr_shadow())
2682                 kvm_x86_ops->update_cr8_intercept = NULL;
2683
2684         if (enable_ept && !cpu_has_vmx_ept_2m_page())
2685                 kvm_disable_largepages();
2686
2687         if (!cpu_has_vmx_ple())
2688                 ple_gap = 0;
2689
2690         if (nested)
2691                 nested_vmx_setup_ctls_msrs();
2692
2693         return alloc_kvm_area();
2694 }
2695
2696 static __exit void hardware_unsetup(void)
2697 {
2698         free_kvm_area();
2699 }
2700
2701 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2702 {
2703         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2704
2705         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
2706                 vmcs_write16(sf->selector, save->selector);
2707                 vmcs_writel(sf->base, save->base);
2708                 vmcs_write32(sf->limit, save->limit);
2709                 vmcs_write32(sf->ar_bytes, save->ar);
2710         } else {
2711                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2712                         << AR_DPL_SHIFT;
2713                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2714         }
2715 }
2716
2717 static void enter_pmode(struct kvm_vcpu *vcpu)
2718 {
2719         unsigned long flags;
2720         struct vcpu_vmx *vmx = to_vmx(vcpu);
2721
2722         vmx->emulation_required = 1;
2723         vmx->rmode.vm86_active = 0;
2724
2725         vmx_segment_cache_clear(vmx);
2726
2727         vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
2728         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2729         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2730         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
2731
2732         flags = vmcs_readl(GUEST_RFLAGS);
2733         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2734         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2735         vmcs_writel(GUEST_RFLAGS, flags);
2736
2737         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2738                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2739
2740         update_exception_bitmap(vcpu);
2741
2742         if (emulate_invalid_guest_state)
2743                 return;
2744
2745         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2746         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2747         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2748         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
2749
2750         vmx_segment_cache_clear(vmx);
2751
2752         vmcs_write16(GUEST_SS_SELECTOR, 0);
2753         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2754
2755         vmcs_write16(GUEST_CS_SELECTOR,
2756                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2757         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2758 }
2759
2760 static gva_t rmode_tss_base(struct kvm *kvm)
2761 {
2762         if (!kvm->arch.tss_addr) {
2763                 struct kvm_memslots *slots;
2764                 struct kvm_memory_slot *slot;
2765                 gfn_t base_gfn;
2766
2767                 slots = kvm_memslots(kvm);
2768                 slot = id_to_memslot(slots, 0);
2769                 base_gfn = slot->base_gfn + slot->npages - 3;
2770
2771                 return base_gfn << PAGE_SHIFT;
2772         }
2773         return kvm->arch.tss_addr;
2774 }
2775
2776 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2777 {
2778         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2779
2780         save->selector = vmcs_read16(sf->selector);
2781         save->base = vmcs_readl(sf->base);
2782         save->limit = vmcs_read32(sf->limit);
2783         save->ar = vmcs_read32(sf->ar_bytes);
2784         vmcs_write16(sf->selector, save->base >> 4);
2785         vmcs_write32(sf->base, save->base & 0xffff0);
2786         vmcs_write32(sf->limit, 0xffff);
2787         vmcs_write32(sf->ar_bytes, 0xf3);
2788         if (save->base & 0xf)
2789                 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2790                             " aligned when entering protected mode (seg=%d)",
2791                             seg);
2792 }
2793
2794 static void enter_rmode(struct kvm_vcpu *vcpu)
2795 {
2796         unsigned long flags;
2797         struct vcpu_vmx *vmx = to_vmx(vcpu);
2798         struct kvm_segment var;
2799
2800         if (enable_unrestricted_guest)
2801                 return;
2802
2803         vmx->emulation_required = 1;
2804         vmx->rmode.vm86_active = 1;
2805
2806         /*
2807          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2808          * vcpu. Call it here with phys address pointing 16M below 4G.
2809          */
2810         if (!vcpu->kvm->arch.tss_addr) {
2811                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2812                              "called before entering vcpu\n");
2813                 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2814                 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2815                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2816         }
2817
2818         vmx_segment_cache_clear(vmx);
2819
2820         vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
2821         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
2822         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2823
2824         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
2825         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2826
2827         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
2828         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2829
2830         flags = vmcs_readl(GUEST_RFLAGS);
2831         vmx->rmode.save_rflags = flags;
2832
2833         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2834
2835         vmcs_writel(GUEST_RFLAGS, flags);
2836         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2837         update_exception_bitmap(vcpu);
2838
2839         if (emulate_invalid_guest_state)
2840                 goto continue_rmode;
2841
2842         vmx_get_segment(vcpu, &var, VCPU_SREG_SS);
2843         vmx_set_segment(vcpu, &var, VCPU_SREG_SS);
2844
2845         vmx_get_segment(vcpu, &var, VCPU_SREG_CS);
2846         vmx_set_segment(vcpu, &var, VCPU_SREG_CS);
2847
2848         vmx_get_segment(vcpu, &var, VCPU_SREG_ES);
2849         vmx_set_segment(vcpu, &var, VCPU_SREG_ES);
2850
2851         vmx_get_segment(vcpu, &var, VCPU_SREG_DS);
2852         vmx_set_segment(vcpu, &var, VCPU_SREG_DS);
2853
2854         vmx_get_segment(vcpu, &var, VCPU_SREG_GS);
2855         vmx_set_segment(vcpu, &var, VCPU_SREG_GS);
2856
2857         vmx_get_segment(vcpu, &var, VCPU_SREG_FS);
2858         vmx_set_segment(vcpu, &var, VCPU_SREG_FS);
2859
2860 continue_rmode:
2861         kvm_mmu_reset_context(vcpu);
2862 }
2863
2864 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2865 {
2866         struct vcpu_vmx *vmx = to_vmx(vcpu);
2867         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2868
2869         if (!msr)
2870                 return;
2871
2872         /*
2873          * Force kernel_gs_base reloading before EFER changes, as control
2874          * of this msr depends on is_long_mode().
2875          */
2876         vmx_load_host_state(to_vmx(vcpu));
2877         vcpu->arch.efer = efer;
2878         if (efer & EFER_LMA) {
2879                 vmcs_write32(VM_ENTRY_CONTROLS,
2880                              vmcs_read32(VM_ENTRY_CONTROLS) |
2881                              VM_ENTRY_IA32E_MODE);
2882                 msr->data = efer;
2883         } else {
2884                 vmcs_write32(VM_ENTRY_CONTROLS,
2885                              vmcs_read32(VM_ENTRY_CONTROLS) &
2886                              ~VM_ENTRY_IA32E_MODE);
2887
2888                 msr->data = efer & ~EFER_LME;
2889         }
2890         setup_msrs(vmx);
2891 }
2892
2893 #ifdef CONFIG_X86_64
2894
2895 static void enter_lmode(struct kvm_vcpu *vcpu)
2896 {
2897         u32 guest_tr_ar;
2898
2899         vmx_segment_cache_clear(to_vmx(vcpu));
2900
2901         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2902         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2903                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2904                                      __func__);
2905                 vmcs_write32(GUEST_TR_AR_BYTES,
2906                              (guest_tr_ar & ~AR_TYPE_MASK)
2907                              | AR_TYPE_BUSY_64_TSS);
2908         }
2909         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2910 }
2911
2912 static void exit_lmode(struct kvm_vcpu *vcpu)
2913 {
2914         vmcs_write32(VM_ENTRY_CONTROLS,
2915                      vmcs_read32(VM_ENTRY_CONTROLS)
2916                      & ~VM_ENTRY_IA32E_MODE);
2917         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2918 }
2919
2920 #endif
2921
2922 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2923 {
2924         vpid_sync_context(to_vmx(vcpu));
2925         if (enable_ept) {
2926                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2927                         return;
2928                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2929         }
2930 }
2931
2932 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2933 {
2934         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2935
2936         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2937         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2938 }
2939
2940 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2941 {
2942         if (enable_ept && is_paging(vcpu))
2943                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2944         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2945 }
2946
2947 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2948 {
2949         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2950
2951         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2952         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2953 }
2954
2955 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2956 {
2957         if (!test_bit(VCPU_EXREG_PDPTR,
2958                       (unsigned long *)&vcpu->arch.regs_dirty))
2959                 return;
2960
2961         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2962                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2963                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2964                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2965                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
2966         }
2967 }
2968
2969 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2970 {
2971         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2972                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2973                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2974                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2975                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2976         }
2977
2978         __set_bit(VCPU_EXREG_PDPTR,
2979                   (unsigned long *)&vcpu->arch.regs_avail);
2980         __set_bit(VCPU_EXREG_PDPTR,
2981                   (unsigned long *)&vcpu->arch.regs_dirty);
2982 }
2983
2984 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
2985
2986 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2987                                         unsigned long cr0,
2988                                         struct kvm_vcpu *vcpu)
2989 {
2990         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2991                 vmx_decache_cr3(vcpu);
2992         if (!(cr0 & X86_CR0_PG)) {
2993                 /* From paging/starting to nonpaging */
2994                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2995                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
2996                              (CPU_BASED_CR3_LOAD_EXITING |
2997                               CPU_BASED_CR3_STORE_EXITING));
2998                 vcpu->arch.cr0 = cr0;
2999                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3000         } else if (!is_paging(vcpu)) {
3001                 /* From nonpaging to paging */
3002                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3003                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3004                              ~(CPU_BASED_CR3_LOAD_EXITING |
3005                                CPU_BASED_CR3_STORE_EXITING));
3006                 vcpu->arch.cr0 = cr0;
3007                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3008         }
3009
3010         if (!(cr0 & X86_CR0_WP))
3011                 *hw_cr0 &= ~X86_CR0_WP;
3012 }
3013
3014 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3015 {
3016         struct vcpu_vmx *vmx = to_vmx(vcpu);
3017         unsigned long hw_cr0;
3018
3019         if (enable_unrestricted_guest)
3020                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
3021                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3022         else
3023                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
3024
3025         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3026                 enter_pmode(vcpu);
3027
3028         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3029                 enter_rmode(vcpu);
3030
3031 #ifdef CONFIG_X86_64
3032         if (vcpu->arch.efer & EFER_LME) {
3033                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3034                         enter_lmode(vcpu);
3035                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3036                         exit_lmode(vcpu);
3037         }
3038 #endif
3039
3040         if (enable_ept)
3041                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3042
3043         if (!vcpu->fpu_active)
3044                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3045
3046         vmcs_writel(CR0_READ_SHADOW, cr0);
3047         vmcs_writel(GUEST_CR0, hw_cr0);
3048         vcpu->arch.cr0 = cr0;
3049         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3050 }
3051
3052 static u64 construct_eptp(unsigned long root_hpa)
3053 {
3054         u64 eptp;
3055
3056         /* TODO write the value reading from MSR */
3057         eptp = VMX_EPT_DEFAULT_MT |
3058                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3059         if (enable_ept_ad_bits)
3060                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3061         eptp |= (root_hpa & PAGE_MASK);
3062
3063         return eptp;
3064 }
3065
3066 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3067 {
3068         unsigned long guest_cr3;
3069         u64 eptp;
3070
3071         guest_cr3 = cr3;
3072         if (enable_ept) {
3073                 eptp = construct_eptp(cr3);
3074                 vmcs_write64(EPT_POINTER, eptp);
3075                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
3076                         vcpu->kvm->arch.ept_identity_map_addr;
3077                 ept_load_pdptrs(vcpu);
3078         }
3079
3080         vmx_flush_tlb(vcpu);
3081         vmcs_writel(GUEST_CR3, guest_cr3);
3082 }
3083
3084 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3085 {
3086         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3087                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3088
3089         if (cr4 & X86_CR4_VMXE) {
3090                 /*
3091                  * To use VMXON (and later other VMX instructions), a guest
3092                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3093                  * So basically the check on whether to allow nested VMX
3094                  * is here.
3095                  */
3096                 if (!nested_vmx_allowed(vcpu))
3097                         return 1;
3098         } else if (to_vmx(vcpu)->nested.vmxon)
3099                 return 1;
3100
3101         vcpu->arch.cr4 = cr4;
3102         if (enable_ept) {
3103                 if (!is_paging(vcpu)) {
3104                         hw_cr4 &= ~X86_CR4_PAE;
3105                         hw_cr4 |= X86_CR4_PSE;
3106                 } else if (!(cr4 & X86_CR4_PAE)) {
3107                         hw_cr4 &= ~X86_CR4_PAE;
3108                 }
3109         }
3110
3111         vmcs_writel(CR4_READ_SHADOW, cr4);
3112         vmcs_writel(GUEST_CR4, hw_cr4);
3113         return 0;
3114 }
3115
3116 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3117                             struct kvm_segment *var, int seg)
3118 {
3119         struct vcpu_vmx *vmx = to_vmx(vcpu);
3120         struct kvm_save_segment *save;
3121         u32 ar;
3122
3123         if (vmx->rmode.vm86_active
3124             && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
3125                 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
3126                 || seg == VCPU_SREG_GS)
3127             && !emulate_invalid_guest_state) {
3128                 switch (seg) {
3129                 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
3130                 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
3131                 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
3132                 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
3133                 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
3134                 default: BUG();
3135                 }
3136                 var->selector = save->selector;
3137                 var->base = save->base;
3138                 var->limit = save->limit;
3139                 ar = save->ar;
3140                 if (seg == VCPU_SREG_TR
3141                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3142                         goto use_saved_rmode_seg;
3143         }
3144         var->base = vmx_read_guest_seg_base(vmx, seg);
3145         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3146         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3147         ar = vmx_read_guest_seg_ar(vmx, seg);
3148 use_saved_rmode_seg:
3149         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
3150                 ar = 0;
3151         var->type = ar & 15;
3152         var->s = (ar >> 4) & 1;
3153         var->dpl = (ar >> 5) & 3;
3154         var->present = (ar >> 7) & 1;
3155         var->avl = (ar >> 12) & 1;
3156         var->l = (ar >> 13) & 1;
3157         var->db = (ar >> 14) & 1;
3158         var->g = (ar >> 15) & 1;
3159         var->unusable = (ar >> 16) & 1;
3160 }
3161
3162 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3163 {
3164         struct kvm_segment s;
3165
3166         if (to_vmx(vcpu)->rmode.vm86_active) {
3167                 vmx_get_segment(vcpu, &s, seg);
3168                 return s.base;
3169         }
3170         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3171 }
3172
3173 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
3174 {
3175         if (!is_protmode(vcpu))
3176                 return 0;
3177
3178         if (!is_long_mode(vcpu)
3179             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3180                 return 3;
3181
3182         return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
3183 }
3184
3185 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3186 {
3187         struct vcpu_vmx *vmx = to_vmx(vcpu);
3188
3189         /*
3190          * If we enter real mode with cs.sel & 3 != 0, the normal CPL calculations
3191          * fail; use the cache instead.
3192          */
3193         if (unlikely(vmx->emulation_required && emulate_invalid_guest_state)) {
3194                 return vmx->cpl;
3195         }
3196
3197         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3198                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3199                 vmx->cpl = __vmx_get_cpl(vcpu);
3200         }
3201
3202         return vmx->cpl;
3203 }
3204
3205
3206 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3207 {
3208         u32 ar;
3209
3210         if (var->unusable || !var->present)
3211                 ar = 1 << 16;
3212         else {
3213                 ar = var->type & 15;
3214                 ar |= (var->s & 1) << 4;
3215                 ar |= (var->dpl & 3) << 5;
3216                 ar |= (var->present & 1) << 7;
3217                 ar |= (var->avl & 1) << 12;
3218                 ar |= (var->l & 1) << 13;
3219                 ar |= (var->db & 1) << 14;
3220                 ar |= (var->g & 1) << 15;
3221         }
3222
3223         return ar;
3224 }
3225
3226 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3227                             struct kvm_segment *var, int seg)
3228 {
3229         struct vcpu_vmx *vmx = to_vmx(vcpu);
3230         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3231         u32 ar;
3232
3233         vmx_segment_cache_clear(vmx);
3234
3235         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
3236                 vmcs_write16(sf->selector, var->selector);
3237                 vmx->rmode.tr.selector = var->selector;
3238                 vmx->rmode.tr.base = var->base;
3239                 vmx->rmode.tr.limit = var->limit;
3240                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
3241                 return;
3242         }
3243         vmcs_writel(sf->base, var->base);
3244         vmcs_write32(sf->limit, var->limit);
3245         vmcs_write16(sf->selector, var->selector);
3246         if (vmx->rmode.vm86_active && var->s) {
3247                 /*
3248                  * Hack real-mode segments into vm86 compatibility.
3249                  */
3250                 if (var->base == 0xffff0000 && var->selector == 0xf000)
3251                         vmcs_writel(sf->base, 0xf0000);
3252                 ar = 0xf3;
3253         } else
3254                 ar = vmx_segment_access_rights(var);
3255
3256         /*
3257          *   Fix the "Accessed" bit in AR field of segment registers for older
3258          * qemu binaries.
3259          *   IA32 arch specifies that at the time of processor reset the
3260          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3261          * is setting it to 0 in the usedland code. This causes invalid guest
3262          * state vmexit when "unrestricted guest" mode is turned on.
3263          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3264          * tree. Newer qemu binaries with that qemu fix would not need this
3265          * kvm hack.
3266          */
3267         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3268                 ar |= 0x1; /* Accessed */
3269
3270         vmcs_write32(sf->ar_bytes, ar);
3271         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3272
3273         /*
3274          * Fix segments for real mode guest in hosts that don't have
3275          * "unrestricted_mode" or it was disabled.
3276          * This is done to allow migration of the guests from hosts with
3277          * unrestricted guest like Westmere to older host that don't have
3278          * unrestricted guest like Nehelem.
3279          */
3280         if (!enable_unrestricted_guest && vmx->rmode.vm86_active) {
3281                 switch (seg) {
3282                 case VCPU_SREG_CS:
3283                         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
3284                         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
3285                         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
3286                                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
3287                         vmcs_write16(GUEST_CS_SELECTOR,
3288                                      vmcs_readl(GUEST_CS_BASE) >> 4);
3289                         break;
3290                 case VCPU_SREG_ES:
3291                         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
3292                         break;
3293                 case VCPU_SREG_DS:
3294                         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
3295                         break;
3296                 case VCPU_SREG_GS:
3297                         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
3298                         break;
3299                 case VCPU_SREG_FS:
3300                         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
3301                         break;
3302                 case VCPU_SREG_SS:
3303                         vmcs_write16(GUEST_SS_SELECTOR,
3304                                      vmcs_readl(GUEST_SS_BASE) >> 4);
3305                         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
3306                         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
3307                         break;
3308                 }
3309         }
3310 }
3311
3312 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3313 {
3314         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3315
3316         *db = (ar >> 14) & 1;
3317         *l = (ar >> 13) & 1;
3318 }
3319
3320 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3321 {
3322         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3323         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3324 }
3325
3326 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3327 {
3328         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3329         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3330 }
3331
3332 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3333 {
3334         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3335         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3336 }
3337
3338 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3339 {
3340         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3341         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3342 }
3343
3344 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3345 {
3346         struct kvm_segment var;
3347         u32 ar;
3348
3349         vmx_get_segment(vcpu, &var, seg);
3350         ar = vmx_segment_access_rights(&var);
3351
3352         if (var.base != (var.selector << 4))
3353                 return false;
3354         if (var.limit != 0xffff)
3355                 return false;
3356         if (ar != 0xf3)
3357                 return false;
3358
3359         return true;
3360 }
3361
3362 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3363 {
3364         struct kvm_segment cs;
3365         unsigned int cs_rpl;
3366
3367         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3368         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3369
3370         if (cs.unusable)
3371                 return false;
3372         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3373                 return false;
3374         if (!cs.s)
3375                 return false;
3376         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3377                 if (cs.dpl > cs_rpl)
3378                         return false;
3379         } else {
3380                 if (cs.dpl != cs_rpl)
3381                         return false;
3382         }
3383         if (!cs.present)
3384                 return false;
3385
3386         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3387         return true;
3388 }
3389
3390 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3391 {
3392         struct kvm_segment ss;
3393         unsigned int ss_rpl;
3394
3395         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3396         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3397
3398         if (ss.unusable)
3399                 return true;
3400         if (ss.type != 3 && ss.type != 7)
3401                 return false;
3402         if (!ss.s)
3403                 return false;
3404         if (ss.dpl != ss_rpl) /* DPL != RPL */
3405                 return false;
3406         if (!ss.present)
3407                 return false;
3408
3409         return true;
3410 }
3411
3412 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3413 {
3414         struct kvm_segment var;
3415         unsigned int rpl;
3416
3417         vmx_get_segment(vcpu, &var, seg);
3418         rpl = var.selector & SELECTOR_RPL_MASK;
3419
3420         if (var.unusable)
3421                 return true;
3422         if (!var.s)
3423                 return false;
3424         if (!var.present)
3425                 return false;
3426         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3427                 if (var.dpl < rpl) /* DPL < RPL */
3428                         return false;
3429         }
3430
3431         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3432          * rights flags
3433          */
3434         return true;
3435 }
3436
3437 static bool tr_valid(struct kvm_vcpu *vcpu)
3438 {
3439         struct kvm_segment tr;
3440
3441         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3442
3443         if (tr.unusable)
3444                 return false;
3445         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3446                 return false;
3447         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3448                 return false;
3449         if (!tr.present)
3450                 return false;
3451
3452         return true;
3453 }
3454
3455 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3456 {
3457         struct kvm_segment ldtr;
3458
3459         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3460
3461         if (ldtr.unusable)
3462                 return true;
3463         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3464                 return false;
3465         if (ldtr.type != 2)
3466                 return false;
3467         if (!ldtr.present)
3468                 return false;
3469
3470         return true;
3471 }
3472
3473 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3474 {
3475         struct kvm_segment cs, ss;
3476
3477         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3478         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3479
3480         return ((cs.selector & SELECTOR_RPL_MASK) ==
3481                  (ss.selector & SELECTOR_RPL_MASK));
3482 }
3483
3484 /*
3485  * Check if guest state is valid. Returns true if valid, false if
3486  * not.
3487  * We assume that registers are always usable
3488  */
3489 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3490 {
3491         /* real mode guest state checks */
3492         if (!is_protmode(vcpu)) {
3493                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3494                         return false;
3495                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3496                         return false;
3497                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3498                         return false;
3499                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3500                         return false;
3501                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3502                         return false;
3503                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3504                         return false;
3505         } else {
3506         /* protected mode guest state checks */
3507                 if (!cs_ss_rpl_check(vcpu))
3508                         return false;
3509                 if (!code_segment_valid(vcpu))
3510                         return false;
3511                 if (!stack_segment_valid(vcpu))
3512                         return false;
3513                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3514                         return false;
3515                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3516                         return false;
3517                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3518                         return false;
3519                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3520                         return false;
3521                 if (!tr_valid(vcpu))
3522                         return false;
3523                 if (!ldtr_valid(vcpu))
3524                         return false;
3525         }
3526         /* TODO:
3527          * - Add checks on RIP
3528          * - Add checks on RFLAGS
3529          */
3530
3531         return true;
3532 }
3533
3534 static int init_rmode_tss(struct kvm *kvm)
3535 {
3536         gfn_t fn;
3537         u16 data = 0;
3538         int r, idx, ret = 0;
3539
3540         idx = srcu_read_lock(&kvm->srcu);
3541         fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
3542         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3543         if (r < 0)
3544                 goto out;
3545         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3546         r = kvm_write_guest_page(kvm, fn++, &data,
3547                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3548         if (r < 0)
3549                 goto out;
3550         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3551         if (r < 0)
3552                 goto out;
3553         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3554         if (r < 0)
3555                 goto out;
3556         data = ~0;
3557         r = kvm_write_guest_page(kvm, fn, &data,
3558                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3559                                  sizeof(u8));
3560         if (r < 0)
3561                 goto out;
3562
3563         ret = 1;
3564 out:
3565         srcu_read_unlock(&kvm->srcu, idx);
3566         return ret;
3567 }
3568
3569 static int init_rmode_identity_map(struct kvm *kvm)
3570 {
3571         int i, idx, r, ret;
3572         pfn_t identity_map_pfn;
3573         u32 tmp;
3574
3575         if (!enable_ept)
3576                 return 1;
3577         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3578                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3579                         "haven't been allocated!\n");
3580                 return 0;
3581         }
3582         if (likely(kvm->arch.ept_identity_pagetable_done))
3583                 return 1;
3584         ret = 0;
3585         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3586         idx = srcu_read_lock(&kvm->srcu);
3587         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3588         if (r < 0)
3589                 goto out;
3590         /* Set up identity-mapping pagetable for EPT in real mode */
3591         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3592                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3593                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3594                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3595                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3596                 if (r < 0)
3597                         goto out;
3598         }
3599         kvm->arch.ept_identity_pagetable_done = true;
3600         ret = 1;
3601 out:
3602         srcu_read_unlock(&kvm->srcu, idx);
3603         return ret;
3604 }
3605
3606 static void seg_setup(int seg)
3607 {
3608         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3609         unsigned int ar;
3610
3611         vmcs_write16(sf->selector, 0);
3612         vmcs_writel(sf->base, 0);
3613         vmcs_write32(sf->limit, 0xffff);
3614         if (enable_unrestricted_guest) {
3615                 ar = 0x93;
3616                 if (seg == VCPU_SREG_CS)
3617                         ar |= 0x08; /* code segment */
3618         } else
3619                 ar = 0xf3;
3620
3621         vmcs_write32(sf->ar_bytes, ar);
3622 }
3623
3624 static int alloc_apic_access_page(struct kvm *kvm)
3625 {
3626         struct page *page;
3627         struct kvm_userspace_memory_region kvm_userspace_mem;
3628         int r = 0;
3629
3630         mutex_lock(&kvm->slots_lock);
3631         if (kvm->arch.apic_access_page)
3632                 goto out;
3633         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3634         kvm_userspace_mem.flags = 0;
3635         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3636         kvm_userspace_mem.memory_size = PAGE_SIZE;
3637         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3638         if (r)
3639                 goto out;
3640
3641         page = gfn_to_page(kvm, 0xfee00);
3642         if (is_error_page(page)) {
3643                 r = -EFAULT;
3644                 goto out;
3645         }
3646
3647         kvm->arch.apic_access_page = page;
3648 out:
3649         mutex_unlock(&kvm->slots_lock);
3650         return r;
3651 }
3652
3653 static int alloc_identity_pagetable(struct kvm *kvm)
3654 {
3655         struct page *page;
3656         struct kvm_userspace_memory_region kvm_userspace_mem;
3657         int r = 0;
3658
3659         mutex_lock(&kvm->slots_lock);
3660         if (kvm->arch.ept_identity_pagetable)
3661                 goto out;
3662         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3663         kvm_userspace_mem.flags = 0;
3664         kvm_userspace_mem.guest_phys_addr =
3665                 kvm->arch.ept_identity_map_addr;
3666         kvm_userspace_mem.memory_size = PAGE_SIZE;
3667         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3668         if (r)
3669                 goto out;
3670
3671         page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3672         if (is_error_page(page)) {
3673                 r = -EFAULT;
3674                 goto out;
3675         }
3676
3677         kvm->arch.ept_identity_pagetable = page;
3678 out:
3679         mutex_unlock(&kvm->slots_lock);
3680         return r;
3681 }
3682
3683 static void allocate_vpid(struct vcpu_vmx *vmx)
3684 {
3685         int vpid;
3686
3687         vmx->vpid = 0;
3688         if (!enable_vpid)
3689                 return;
3690         spin_lock(&vmx_vpid_lock);
3691         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3692         if (vpid < VMX_NR_VPIDS) {
3693                 vmx->vpid = vpid;
3694                 __set_bit(vpid, vmx_vpid_bitmap);
3695         }
3696         spin_unlock(&vmx_vpid_lock);
3697 }
3698
3699 static void free_vpid(struct vcpu_vmx *vmx)
3700 {
3701         if (!enable_vpid)
3702                 return;
3703         spin_lock(&vmx_vpid_lock);
3704         if (vmx->vpid != 0)
3705                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3706         spin_unlock(&vmx_vpid_lock);
3707 }
3708
3709 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
3710 {
3711         int f = sizeof(unsigned long);
3712
3713         if (!cpu_has_vmx_msr_bitmap())
3714                 return;
3715
3716         /*
3717          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3718          * have the write-low and read-high bitmap offsets the wrong way round.
3719          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3720          */
3721         if (msr <= 0x1fff) {
3722                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3723                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
3724         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3725                 msr &= 0x1fff;
3726                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3727                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
3728         }
3729 }
3730
3731 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3732 {
3733         if (!longmode_only)
3734                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3735         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3736 }
3737
3738 /*
3739  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3740  * will not change in the lifetime of the guest.
3741  * Note that host-state that does change is set elsewhere. E.g., host-state
3742  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3743  */
3744 static void vmx_set_constant_host_state(void)
3745 {
3746         u32 low32, high32;
3747         unsigned long tmpl;
3748         struct desc_ptr dt;
3749
3750         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
3751         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
3752         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
3753
3754         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
3755 #ifdef CONFIG_X86_64
3756         /*
3757          * Load null selectors, so we can avoid reloading them in
3758          * __vmx_load_host_state(), in case userspace uses the null selectors
3759          * too (the expected case).
3760          */
3761         vmcs_write16(HOST_DS_SELECTOR, 0);
3762         vmcs_write16(HOST_ES_SELECTOR, 0);
3763 #else
3764         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3765         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3766 #endif
3767         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3768         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
3769
3770         native_store_idt(&dt);
3771         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
3772
3773         asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3774         vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3775
3776         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3777         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3778         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3779         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
3780
3781         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3782                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3783                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3784         }
3785 }
3786
3787 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3788 {
3789         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3790         if (enable_ept)
3791                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3792         if (is_guest_mode(&vmx->vcpu))
3793                 vmx->vcpu.arch.cr4_guest_owned_bits &=
3794                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3795         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3796 }
3797
3798 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3799 {
3800         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3801         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3802                 exec_control &= ~CPU_BASED_TPR_SHADOW;
3803 #ifdef CONFIG_X86_64
3804                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3805                                 CPU_BASED_CR8_LOAD_EXITING;
3806 #endif
3807         }
3808         if (!enable_ept)
3809                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3810                                 CPU_BASED_CR3_LOAD_EXITING  |
3811                                 CPU_BASED_INVLPG_EXITING;
3812         return exec_control;
3813 }
3814
3815 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3816 {
3817         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3818         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3819                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3820         if (vmx->vpid == 0)
3821                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3822         if (!enable_ept) {
3823                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3824                 enable_unrestricted_guest = 0;
3825                 /* Enable INVPCID for non-ept guests may cause performance regression. */
3826                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
3827         }
3828         if (!enable_unrestricted_guest)
3829                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3830         if (!ple_gap)
3831                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3832         return exec_control;
3833 }
3834
3835 static void ept_set_mmio_spte_mask(void)
3836 {
3837         /*
3838          * EPT Misconfigurations can be generated if the value of bits 2:0
3839          * of an EPT paging-structure entry is 110b (write/execute).
3840          * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3841          * spte.
3842          */
3843         kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3844 }
3845
3846 /*
3847  * Sets up the vmcs for emulated real mode.
3848  */
3849 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
3850 {
3851 #ifdef CONFIG_X86_64
3852         unsigned long a;
3853 #endif
3854         int i;
3855
3856         /* I/O */
3857         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3858         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
3859
3860         if (cpu_has_vmx_msr_bitmap())
3861                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
3862
3863         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3864
3865         /* Control */
3866         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3867                 vmcs_config.pin_based_exec_ctrl);
3868
3869         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
3870
3871         if (cpu_has_secondary_exec_ctrls()) {
3872                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3873                                 vmx_secondary_exec_control(vmx));
3874         }
3875
3876         if (ple_gap) {
3877                 vmcs_write32(PLE_GAP, ple_gap);
3878                 vmcs_write32(PLE_WINDOW, ple_window);
3879         }
3880
3881         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3882         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
3883         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
3884
3885         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
3886         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
3887         vmx_set_constant_host_state();
3888 #ifdef CONFIG_X86_64
3889         rdmsrl(MSR_FS_BASE, a);
3890         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3891         rdmsrl(MSR_GS_BASE, a);
3892         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3893 #else
3894         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3895         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3896 #endif
3897
3898         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3899         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
3900         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
3901         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
3902         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
3903
3904         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3905                 u32 msr_low, msr_high;
3906                 u64 host_pat;
3907                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3908                 host_pat = msr_low | ((u64) msr_high << 32);
3909                 /* Write the default value follow host pat */
3910                 vmcs_write64(GUEST_IA32_PAT, host_pat);
3911                 /* Keep arch.pat sync with GUEST_IA32_PAT */
3912                 vmx->vcpu.arch.pat = host_pat;
3913         }
3914
3915         for (i = 0; i < NR_VMX_MSR; ++i) {
3916                 u32 index = vmx_msr_index[i];
3917                 u32 data_low, data_high;
3918                 int j = vmx->nmsrs;
3919
3920                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3921                         continue;
3922                 if (wrmsr_safe(index, data_low, data_high) < 0)
3923                         continue;
3924                 vmx->guest_msrs[j].index = i;
3925                 vmx->guest_msrs[j].data = 0;
3926                 vmx->guest_msrs[j].mask = -1ull;
3927                 ++vmx->nmsrs;
3928         }
3929
3930         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
3931
3932         /* 22.2.1, 20.8.1 */
3933         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3934
3935         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
3936         set_cr4_guest_host_mask(vmx);
3937
3938         kvm_write_tsc(&vmx->vcpu, 0);
3939
3940         return 0;
3941 }
3942
3943 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3944 {
3945         struct vcpu_vmx *vmx = to_vmx(vcpu);
3946         u64 msr;
3947         int ret;
3948
3949         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3950
3951         vmx->rmode.vm86_active = 0;
3952
3953         vmx->soft_vnmi_blocked = 0;
3954
3955         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
3956         kvm_set_cr8(&vmx->vcpu, 0);
3957         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
3958         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3959                 msr |= MSR_IA32_APICBASE_BSP;
3960         kvm_set_apic_base(&vmx->vcpu, msr);
3961
3962         ret = fx_init(&vmx->vcpu);
3963         if (ret != 0)
3964                 goto out;
3965
3966         vmx_segment_cache_clear(vmx);
3967
3968         seg_setup(VCPU_SREG_CS);
3969         /*
3970          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3971          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
3972          */
3973         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
3974                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3975                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3976         } else {
3977                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3978                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
3979         }
3980
3981         seg_setup(VCPU_SREG_DS);
3982         seg_setup(VCPU_SREG_ES);
3983         seg_setup(VCPU_SREG_FS);
3984         seg_setup(VCPU_SREG_GS);
3985         seg_setup(VCPU_SREG_SS);
3986
3987         vmcs_write16(GUEST_TR_SELECTOR, 0);
3988         vmcs_writel(GUEST_TR_BASE, 0);
3989         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3990         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3991
3992         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3993         vmcs_writel(GUEST_LDTR_BASE, 0);
3994         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3995         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3996
3997         vmcs_write32(GUEST_SYSENTER_CS, 0);
3998         vmcs_writel(GUEST_SYSENTER_ESP, 0);
3999         vmcs_writel(GUEST_SYSENTER_EIP, 0);
4000
4001         vmcs_writel(GUEST_RFLAGS, 0x02);
4002         if (kvm_vcpu_is_bsp(&vmx->vcpu))
4003                 kvm_rip_write(vcpu, 0xfff0);
4004         else
4005                 kvm_rip_write(vcpu, 0);
4006         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
4007
4008         vmcs_writel(GUEST_DR7, 0x400);
4009
4010         vmcs_writel(GUEST_GDTR_BASE, 0);
4011         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4012
4013         vmcs_writel(GUEST_IDTR_BASE, 0);
4014         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4015
4016         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4017         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4018         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4019
4020         /* Special registers */
4021         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4022
4023         setup_msrs(vmx);
4024
4025         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4026
4027         if (cpu_has_vmx_tpr_shadow()) {
4028                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4029                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4030                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4031                                      __pa(vmx->vcpu.arch.apic->regs));
4032                 vmcs_write32(TPR_THRESHOLD, 0);
4033         }
4034
4035         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4036                 vmcs_write64(APIC_ACCESS_ADDR,
4037                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
4038
4039         if (vmx->vpid != 0)
4040                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4041
4042         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4043         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
4044         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4045         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
4046         vmx_set_cr4(&vmx->vcpu, 0);
4047         vmx_set_efer(&vmx->vcpu, 0);
4048         vmx_fpu_activate(&vmx->vcpu);
4049         update_exception_bitmap(&vmx->vcpu);
4050
4051         vpid_sync_context(vmx);
4052
4053         ret = 0;
4054
4055         /* HACK: Don't enable emulation on guest boot/reset */
4056         vmx->emulation_required = 0;
4057
4058 out:
4059         return ret;
4060 }
4061
4062 /*
4063  * In nested virtualization, check if L1 asked to exit on external interrupts.
4064  * For most existing hypervisors, this will always return true.
4065  */
4066 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4067 {
4068         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4069                 PIN_BASED_EXT_INTR_MASK;
4070 }
4071
4072 static void enable_irq_window(struct kvm_vcpu *vcpu)
4073 {
4074         u32 cpu_based_vm_exec_control;
4075         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4076                 /*
4077                  * We get here if vmx_interrupt_allowed() said we can't
4078                  * inject to L1 now because L2 must run. Ask L2 to exit
4079                  * right after entry, so we can inject to L1 more promptly.
4080                  */
4081                 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
4082                 return;
4083         }
4084
4085         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4086         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4087         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4088 }
4089
4090 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4091 {
4092         u32 cpu_based_vm_exec_control;
4093
4094         if (!cpu_has_virtual_nmis()) {
4095                 enable_irq_window(vcpu);
4096                 return;
4097         }
4098
4099         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4100                 enable_irq_window(vcpu);
4101                 return;
4102         }
4103         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4104         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4105         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4106 }
4107
4108 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4109 {
4110         struct vcpu_vmx *vmx = to_vmx(vcpu);
4111         uint32_t intr;
4112         int irq = vcpu->arch.interrupt.nr;
4113
4114         trace_kvm_inj_virq(irq);
4115
4116         ++vcpu->stat.irq_injections;
4117         if (vmx->rmode.vm86_active) {
4118                 int inc_eip = 0;
4119                 if (vcpu->arch.interrupt.soft)
4120                         inc_eip = vcpu->arch.event_exit_inst_len;
4121                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4122                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4123                 return;
4124         }
4125         intr = irq | INTR_INFO_VALID_MASK;
4126         if (vcpu->arch.interrupt.soft) {
4127                 intr |= INTR_TYPE_SOFT_INTR;
4128                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4129                              vmx->vcpu.arch.event_exit_inst_len);
4130         } else
4131                 intr |= INTR_TYPE_EXT_INTR;
4132         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4133 }
4134
4135 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4136 {
4137         struct vcpu_vmx *vmx = to_vmx(vcpu);
4138
4139         if (is_guest_mode(vcpu))
4140                 return;
4141
4142         if (!cpu_has_virtual_nmis()) {
4143                 /*
4144                  * Tracking the NMI-blocked state in software is built upon
4145                  * finding the next open IRQ window. This, in turn, depends on
4146                  * well-behaving guests: They have to keep IRQs disabled at
4147                  * least as long as the NMI handler runs. Otherwise we may
4148                  * cause NMI nesting, maybe breaking the guest. But as this is
4149                  * highly unlikely, we can live with the residual risk.
4150                  */
4151                 vmx->soft_vnmi_blocked = 1;
4152                 vmx->vnmi_blocked_time = 0;
4153         }
4154
4155         ++vcpu->stat.nmi_injections;
4156         vmx->nmi_known_unmasked = false;
4157         if (vmx->rmode.vm86_active) {
4158                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4159                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4160                 return;
4161         }
4162         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4163                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4164 }
4165
4166 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4167 {
4168         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4169                 return 0;
4170
4171         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4172                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4173                    | GUEST_INTR_STATE_NMI));
4174 }
4175
4176 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4177 {
4178         if (!cpu_has_virtual_nmis())
4179                 return to_vmx(vcpu)->soft_vnmi_blocked;
4180         if (to_vmx(vcpu)->nmi_known_unmasked)
4181                 return false;
4182         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4183 }
4184
4185 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4186 {
4187         struct vcpu_vmx *vmx = to_vmx(vcpu);
4188
4189         if (!cpu_has_virtual_nmis()) {
4190                 if (vmx->soft_vnmi_blocked != masked) {
4191                         vmx->soft_vnmi_blocked = masked;
4192                         vmx->vnmi_blocked_time = 0;
4193                 }
4194         } else {
4195                 vmx->nmi_known_unmasked = !masked;
4196                 if (masked)
4197                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4198                                       GUEST_INTR_STATE_NMI);
4199                 else
4200                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4201                                         GUEST_INTR_STATE_NMI);
4202         }
4203 }
4204
4205 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4206 {
4207         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4208                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4209                 if (to_vmx(vcpu)->nested.nested_run_pending ||
4210                     (vmcs12->idt_vectoring_info_field &
4211                      VECTORING_INFO_VALID_MASK))
4212                         return 0;
4213                 nested_vmx_vmexit(vcpu);
4214                 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4215                 vmcs12->vm_exit_intr_info = 0;
4216                 /* fall through to normal code, but now in L1, not L2 */
4217         }
4218
4219         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4220                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4221                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4222 }
4223
4224 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4225 {
4226         int ret;
4227         struct kvm_userspace_memory_region tss_mem = {
4228                 .slot = TSS_PRIVATE_MEMSLOT,
4229                 .guest_phys_addr = addr,
4230                 .memory_size = PAGE_SIZE * 3,
4231                 .flags = 0,
4232         };
4233
4234         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
4235         if (ret)
4236                 return ret;
4237         kvm->arch.tss_addr = addr;
4238         if (!init_rmode_tss(kvm))
4239                 return  -ENOMEM;
4240
4241         return 0;
4242 }
4243
4244 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4245                                   int vec, u32 err_code)
4246 {
4247         /*
4248          * Instruction with address size override prefix opcode 0x67
4249          * Cause the #SS fault with 0 error code in VM86 mode.
4250          */
4251         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
4252                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
4253                         return 1;
4254         /*
4255          * Forward all other exceptions that are valid in real mode.
4256          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4257          *        the required debugging infrastructure rework.
4258          */
4259         switch (vec) {
4260         case DB_VECTOR:
4261                 if (vcpu->guest_debug &
4262                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4263                         return 0;
4264                 kvm_queue_exception(vcpu, vec);
4265                 return 1;
4266         case BP_VECTOR:
4267                 /*
4268                  * Update instruction length as we may reinject the exception
4269                  * from user space while in guest debugging mode.
4270                  */
4271                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4272                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4273                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4274                         return 0;
4275                 /* fall through */
4276         case DE_VECTOR:
4277         case OF_VECTOR:
4278         case BR_VECTOR:
4279         case UD_VECTOR:
4280         case DF_VECTOR:
4281         case SS_VECTOR:
4282         case GP_VECTOR:
4283         case MF_VECTOR:
4284                 kvm_queue_exception(vcpu, vec);
4285                 return 1;
4286         }
4287         return 0;
4288 }
4289
4290 /*
4291  * Trigger machine check on the host. We assume all the MSRs are already set up
4292  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4293  * We pass a fake environment to the machine check handler because we want
4294  * the guest to be always treated like user space, no matter what context
4295  * it used internally.
4296  */
4297 static void kvm_machine_check(void)
4298 {
4299 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4300         struct pt_regs regs = {
4301                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4302                 .flags = X86_EFLAGS_IF,
4303         };
4304
4305         do_machine_check(&regs, 0);
4306 #endif
4307 }
4308
4309 static int handle_machine_check(struct kvm_vcpu *vcpu)
4310 {
4311         /* already handled by vcpu_run */
4312         return 1;
4313 }
4314
4315 static int handle_exception(struct kvm_vcpu *vcpu)
4316 {
4317         struct vcpu_vmx *vmx = to_vmx(vcpu);
4318         struct kvm_run *kvm_run = vcpu->run;
4319         u32 intr_info, ex_no, error_code;
4320         unsigned long cr2, rip, dr6;
4321         u32 vect_info;
4322         enum emulation_result er;
4323
4324         vect_info = vmx->idt_vectoring_info;
4325         intr_info = vmx->exit_intr_info;
4326
4327         if (is_machine_check(intr_info))
4328                 return handle_machine_check(vcpu);
4329
4330         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4331             !is_page_fault(intr_info)) {
4332                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4333                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4334                 vcpu->run->internal.ndata = 2;
4335                 vcpu->run->internal.data[0] = vect_info;
4336                 vcpu->run->internal.data[1] = intr_info;
4337                 return 0;
4338         }
4339
4340         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4341                 return 1;  /* already handled by vmx_vcpu_run() */
4342
4343         if (is_no_device(intr_info)) {
4344                 vmx_fpu_activate(vcpu);
4345                 return 1;
4346         }
4347
4348         if (is_invalid_opcode(intr_info)) {
4349                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4350                 if (er != EMULATE_DONE)
4351                         kvm_queue_exception(vcpu, UD_VECTOR);
4352                 return 1;
4353         }
4354
4355         error_code = 0;
4356         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4357                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4358         if (is_page_fault(intr_info)) {
4359                 /* EPT won't cause page fault directly */
4360                 BUG_ON(enable_ept);
4361                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4362                 trace_kvm_page_fault(cr2, error_code);
4363
4364                 if (kvm_event_needs_reinjection(vcpu))
4365                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4366                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4367         }
4368
4369         if (vmx->rmode.vm86_active &&
4370             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
4371                                                                 error_code)) {
4372                 if (vcpu->arch.halt_request) {
4373                         vcpu->arch.halt_request = 0;
4374                         return kvm_emulate_halt(vcpu);
4375                 }
4376                 return 1;
4377         }
4378
4379         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4380         switch (ex_no) {
4381         case DB_VECTOR:
4382                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4383                 if (!(vcpu->guest_debug &
4384                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4385                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4386                         kvm_queue_exception(vcpu, DB_VECTOR);
4387                         return 1;
4388                 }
4389                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4390                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4391                 /* fall through */
4392         case BP_VECTOR:
4393                 /*
4394                  * Update instruction length as we may reinject #BP from
4395                  * user space while in guest debugging mode. Reading it for
4396                  * #DB as well causes no harm, it is not used in that case.
4397                  */
4398                 vmx->vcpu.arch.event_exit_inst_len =
4399                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4400                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4401                 rip = kvm_rip_read(vcpu);
4402                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4403                 kvm_run->debug.arch.exception = ex_no;
4404                 break;
4405         default:
4406                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4407                 kvm_run->ex.exception = ex_no;
4408                 kvm_run->ex.error_code = error_code;
4409                 break;
4410         }
4411         return 0;
4412 }
4413
4414 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4415 {
4416         ++vcpu->stat.irq_exits;
4417         return 1;
4418 }
4419
4420 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4421 {
4422         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4423         return 0;
4424 }
4425
4426 static int handle_io(struct kvm_vcpu *vcpu)
4427 {
4428         unsigned long exit_qualification;
4429         int size, in, string;
4430         unsigned port;
4431
4432         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4433         string = (exit_qualification & 16) != 0;
4434         in = (exit_qualification & 8) != 0;
4435
4436         ++vcpu->stat.io_exits;
4437
4438         if (string || in)
4439                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4440
4441         port = exit_qualification >> 16;
4442         size = (exit_qualification & 7) + 1;
4443         skip_emulated_instruction(vcpu);
4444
4445         return kvm_fast_pio_out(vcpu, size, port);
4446 }
4447
4448 static void
4449 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4450 {
4451         /*
4452          * Patch in the VMCALL instruction:
4453          */
4454         hypercall[0] = 0x0f;
4455         hypercall[1] = 0x01;
4456         hypercall[2] = 0xc1;
4457 }
4458
4459 /* called to set cr0 as approriate for a mov-to-cr0 exit. */
4460 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4461 {
4462         if (to_vmx(vcpu)->nested.vmxon &&
4463             ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4464                 return 1;
4465
4466         if (is_guest_mode(vcpu)) {
4467                 /*
4468                  * We get here when L2 changed cr0 in a way that did not change
4469                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4470                  * but did change L0 shadowed bits. This can currently happen
4471                  * with the TS bit: L0 may want to leave TS on (for lazy fpu
4472                  * loading) while pretending to allow the guest to change it.
4473                  */
4474                 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4475                          (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4476                         return 1;
4477                 vmcs_writel(CR0_READ_SHADOW, val);
4478                 return 0;
4479         } else
4480                 return kvm_set_cr0(vcpu, val);
4481 }
4482
4483 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4484 {
4485         if (is_guest_mode(vcpu)) {
4486                 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4487                          (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4488                         return 1;
4489                 vmcs_writel(CR4_READ_SHADOW, val);
4490                 return 0;
4491         } else
4492                 return kvm_set_cr4(vcpu, val);
4493 }
4494
4495 /* called to set cr0 as approriate for clts instruction exit. */
4496 static void handle_clts(struct kvm_vcpu *vcpu)
4497 {
4498         if (is_guest_mode(vcpu)) {
4499                 /*
4500                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4501                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4502                  * just pretend it's off (also in arch.cr0 for fpu_activate).
4503                  */
4504                 vmcs_writel(CR0_READ_SHADOW,
4505                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4506                 vcpu->arch.cr0 &= ~X86_CR0_TS;
4507         } else
4508                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4509 }
4510
4511 static int handle_cr(struct kvm_vcpu *vcpu)
4512 {
4513         unsigned long exit_qualification, val;
4514         int cr;
4515         int reg;
4516         int err;
4517
4518         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4519         cr = exit_qualification & 15;
4520         reg = (exit_qualification >> 8) & 15;
4521         switch ((exit_qualification >> 4) & 3) {
4522         case 0: /* mov to cr */
4523                 val = kvm_register_read(vcpu, reg);
4524                 trace_kvm_cr_write(cr, val);
4525                 switch (cr) {
4526                 case 0:
4527                         err = handle_set_cr0(vcpu, val);
4528                         kvm_complete_insn_gp(vcpu, err);
4529                         return 1;
4530                 case 3:
4531                         err = kvm_set_cr3(vcpu, val);
4532                         kvm_complete_insn_gp(vcpu, err);
4533                         return 1;
4534                 case 4:
4535                         err = handle_set_cr4(vcpu, val);
4536                         kvm_complete_insn_gp(vcpu, err);
4537                         return 1;
4538                 case 8: {
4539                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4540                                 u8 cr8 = kvm_register_read(vcpu, reg);
4541                                 err = kvm_set_cr8(vcpu, cr8);
4542                                 kvm_complete_insn_gp(vcpu, err);
4543                                 if (irqchip_in_kernel(vcpu->kvm))
4544                                         return 1;
4545                                 if (cr8_prev <= cr8)
4546                                         return 1;
4547                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4548                                 return 0;
4549                         }
4550                 }
4551                 break;
4552         case 2: /* clts */
4553                 handle_clts(vcpu);
4554                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4555                 skip_emulated_instruction(vcpu);
4556                 vmx_fpu_activate(vcpu);
4557                 return 1;
4558         case 1: /*mov from cr*/
4559                 switch (cr) {
4560                 case 3:
4561                         val = kvm_read_cr3(vcpu);
4562                         kvm_register_write(vcpu, reg, val);
4563                         trace_kvm_cr_read(cr, val);
4564                         skip_emulated_instruction(vcpu);
4565                         return 1;
4566                 case 8:
4567                         val = kvm_get_cr8(vcpu);
4568                         kvm_register_write(vcpu, reg, val);
4569                         trace_kvm_cr_read(cr, val);
4570                         skip_emulated_instruction(vcpu);
4571                         return 1;
4572                 }
4573                 break;
4574         case 3: /* lmsw */
4575                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4576                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4577                 kvm_lmsw(vcpu, val);
4578
4579                 skip_emulated_instruction(vcpu);
4580                 return 1;
4581         default:
4582                 break;
4583         }
4584         vcpu->run->exit_reason = 0;
4585         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4586                (int)(exit_qualification >> 4) & 3, cr);
4587         return 0;
4588 }
4589
4590 static int handle_dr(struct kvm_vcpu *vcpu)
4591 {
4592         unsigned long exit_qualification;
4593         int dr, reg;
4594
4595         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4596         if (!kvm_require_cpl(vcpu, 0))
4597                 return 1;
4598         dr = vmcs_readl(GUEST_DR7);
4599         if (dr & DR7_GD) {
4600                 /*
4601                  * As the vm-exit takes precedence over the debug trap, we
4602                  * need to emulate the latter, either for the host or the
4603                  * guest debugging itself.
4604                  */
4605                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4606                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4607                         vcpu->run->debug.arch.dr7 = dr;
4608                         vcpu->run->debug.arch.pc =
4609                                 vmcs_readl(GUEST_CS_BASE) +
4610                                 vmcs_readl(GUEST_RIP);
4611                         vcpu->run->debug.arch.exception = DB_VECTOR;
4612                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4613                         return 0;
4614                 } else {
4615                         vcpu->arch.dr7 &= ~DR7_GD;
4616                         vcpu->arch.dr6 |= DR6_BD;
4617                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4618                         kvm_queue_exception(vcpu, DB_VECTOR);
4619                         return 1;
4620                 }
4621         }
4622
4623         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4624         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4625         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4626         if (exit_qualification & TYPE_MOV_FROM_DR) {
4627                 unsigned long val;
4628                 if (!kvm_get_dr(vcpu, dr, &val))
4629                         kvm_register_write(vcpu, reg, val);
4630         } else
4631                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
4632         skip_emulated_instruction(vcpu);
4633         return 1;
4634 }
4635
4636 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4637 {
4638         vmcs_writel(GUEST_DR7, val);
4639 }
4640
4641 static int handle_cpuid(struct kvm_vcpu *vcpu)
4642 {
4643         kvm_emulate_cpuid(vcpu);
4644         return 1;
4645 }
4646
4647 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4648 {
4649         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4650         u64 data;
4651
4652         if (vmx_get_msr(vcpu, ecx, &data)) {
4653                 trace_kvm_msr_read_ex(ecx);
4654                 kvm_inject_gp(vcpu, 0);
4655                 return 1;
4656         }
4657
4658         trace_kvm_msr_read(ecx, data);
4659
4660         /* FIXME: handling of bits 32:63 of rax, rdx */
4661         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4662         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
4663         skip_emulated_instruction(vcpu);
4664         return 1;
4665 }
4666
4667 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4668 {
4669         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4670         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4671                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
4672
4673         if (vmx_set_msr(vcpu, ecx, data) != 0) {
4674                 trace_kvm_msr_write_ex(ecx, data);
4675                 kvm_inject_gp(vcpu, 0);
4676                 return 1;
4677         }
4678
4679         trace_kvm_msr_write(ecx, data);
4680         skip_emulated_instruction(vcpu);
4681         return 1;
4682 }
4683
4684 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4685 {
4686         kvm_make_request(KVM_REQ_EVENT, vcpu);
4687         return 1;
4688 }
4689
4690 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4691 {
4692         u32 cpu_based_vm_exec_control;
4693
4694         /* clear pending irq */
4695         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4696         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4697         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4698
4699         kvm_make_request(KVM_REQ_EVENT, vcpu);
4700
4701         ++vcpu->stat.irq_window_exits;
4702
4703         /*
4704          * If the user space waits to inject interrupts, exit as soon as
4705          * possible
4706          */
4707         if (!irqchip_in_kernel(vcpu->kvm) &&
4708             vcpu->run->request_interrupt_window &&
4709             !kvm_cpu_has_interrupt(vcpu)) {
4710                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
4711                 return 0;
4712         }
4713         return 1;
4714 }
4715
4716 static int handle_halt(struct kvm_vcpu *vcpu)
4717 {
4718         skip_emulated_instruction(vcpu);
4719         return kvm_emulate_halt(vcpu);
4720 }
4721
4722 static int handle_vmcall(struct kvm_vcpu *vcpu)
4723 {
4724         skip_emulated_instruction(vcpu);
4725         kvm_emulate_hypercall(vcpu);
4726         return 1;
4727 }
4728
4729 static int handle_invd(struct kvm_vcpu *vcpu)
4730 {
4731         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4732 }
4733
4734 static int handle_invlpg(struct kvm_vcpu *vcpu)
4735 {
4736         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4737
4738         kvm_mmu_invlpg(vcpu, exit_qualification);
4739         skip_emulated_instruction(vcpu);
4740         return 1;
4741 }
4742
4743 static int handle_rdpmc(struct kvm_vcpu *vcpu)
4744 {
4745         int err;
4746
4747         err = kvm_rdpmc(vcpu);
4748         kvm_complete_insn_gp(vcpu, err);
4749
4750         return 1;
4751 }
4752
4753 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4754 {
4755         skip_emulated_instruction(vcpu);
4756         kvm_emulate_wbinvd(vcpu);
4757         return 1;
4758 }
4759
4760 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4761 {
4762         u64 new_bv = kvm_read_edx_eax(vcpu);
4763         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4764
4765         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4766                 skip_emulated_instruction(vcpu);
4767         return 1;
4768 }
4769
4770 static int handle_apic_access(struct kvm_vcpu *vcpu)
4771 {
4772         if (likely(fasteoi)) {
4773                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4774                 int access_type, offset;
4775
4776                 access_type = exit_qualification & APIC_ACCESS_TYPE;
4777                 offset = exit_qualification & APIC_ACCESS_OFFSET;
4778                 /*
4779                  * Sane guest uses MOV to write EOI, with written value
4780                  * not cared. So make a short-circuit here by avoiding
4781                  * heavy instruction emulation.
4782                  */
4783                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4784                     (offset == APIC_EOI)) {
4785                         kvm_lapic_set_eoi(vcpu);
4786                         skip_emulated_instruction(vcpu);
4787                         return 1;
4788                 }
4789         }
4790         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4791 }
4792
4793 static int handle_task_switch(struct kvm_vcpu *vcpu)
4794 {
4795         struct vcpu_vmx *vmx = to_vmx(vcpu);
4796         unsigned long exit_qualification;
4797         bool has_error_code = false;
4798         u32 error_code = 0;
4799         u16 tss_selector;
4800         int reason, type, idt_v, idt_index;
4801
4802         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4803         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
4804         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
4805
4806         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4807
4808         reason = (u32)exit_qualification >> 30;
4809         if (reason == TASK_SWITCH_GATE && idt_v) {
4810                 switch (type) {
4811                 case INTR_TYPE_NMI_INTR:
4812                         vcpu->arch.nmi_injected = false;
4813                         vmx_set_nmi_mask(vcpu, true);
4814                         break;
4815                 case INTR_TYPE_EXT_INTR:
4816                 case INTR_TYPE_SOFT_INTR:
4817                         kvm_clear_interrupt_queue(vcpu);
4818                         break;
4819                 case INTR_TYPE_HARD_EXCEPTION:
4820                         if (vmx->idt_vectoring_info &
4821                             VECTORING_INFO_DELIVER_CODE_MASK) {
4822                                 has_error_code = true;
4823                                 error_code =
4824                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
4825                         }
4826                         /* fall through */
4827                 case INTR_TYPE_SOFT_EXCEPTION:
4828                         kvm_clear_exception_queue(vcpu);
4829                         break;
4830                 default:
4831                         break;
4832                 }
4833         }
4834         tss_selector = exit_qualification;
4835
4836         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4837                        type != INTR_TYPE_EXT_INTR &&
4838                        type != INTR_TYPE_NMI_INTR))
4839                 skip_emulated_instruction(vcpu);
4840
4841         if (kvm_task_switch(vcpu, tss_selector,
4842                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
4843                             has_error_code, error_code) == EMULATE_FAIL) {
4844                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4845                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4846                 vcpu->run->internal.ndata = 0;
4847                 return 0;
4848         }
4849
4850         /* clear all local breakpoint enable flags */
4851         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4852
4853         /*
4854          * TODO: What about debug traps on tss switch?
4855          *       Are we supposed to inject them and update dr6?
4856          */
4857
4858         return 1;
4859 }
4860
4861 static int handle_ept_violation(struct kvm_vcpu *vcpu)
4862 {
4863         unsigned long exit_qualification;
4864         gpa_t gpa;
4865         u32 error_code;
4866         int gla_validity;
4867
4868         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4869
4870         if (exit_qualification & (1 << 6)) {
4871                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
4872                 return -EINVAL;
4873         }
4874
4875         gla_validity = (exit_qualification >> 7) & 0x3;
4876         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4877                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4878                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4879                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
4880                         vmcs_readl(GUEST_LINEAR_ADDRESS));
4881                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4882                         (long unsigned int)exit_qualification);
4883                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4884                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
4885                 return 0;
4886         }
4887
4888         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4889         trace_kvm_page_fault(gpa, exit_qualification);
4890
4891         /* It is a write fault? */
4892         error_code = exit_qualification & (1U << 1);
4893         /* ept page table is present? */
4894         error_code |= (exit_qualification >> 3) & 0x1;
4895
4896         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
4897 }
4898
4899 static u64 ept_rsvd_mask(u64 spte, int level)
4900 {
4901         int i;
4902         u64 mask = 0;
4903
4904         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4905                 mask |= (1ULL << i);
4906
4907         if (level > 2)
4908                 /* bits 7:3 reserved */
4909                 mask |= 0xf8;
4910         else if (level == 2) {
4911                 if (spte & (1ULL << 7))
4912                         /* 2MB ref, bits 20:12 reserved */
4913                         mask |= 0x1ff000;
4914                 else
4915                         /* bits 6:3 reserved */
4916                         mask |= 0x78;
4917         }
4918
4919         return mask;
4920 }
4921
4922 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4923                                        int level)
4924 {
4925         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4926
4927         /* 010b (write-only) */
4928         WARN_ON((spte & 0x7) == 0x2);
4929
4930         /* 110b (write/execute) */
4931         WARN_ON((spte & 0x7) == 0x6);
4932
4933         /* 100b (execute-only) and value not supported by logical processor */
4934         if (!cpu_has_vmx_ept_execute_only())
4935                 WARN_ON((spte & 0x7) == 0x4);
4936
4937         /* not 000b */
4938         if ((spte & 0x7)) {
4939                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4940
4941                 if (rsvd_bits != 0) {
4942                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4943                                          __func__, rsvd_bits);
4944                         WARN_ON(1);
4945                 }
4946
4947                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4948                         u64 ept_mem_type = (spte & 0x38) >> 3;
4949
4950                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
4951                             ept_mem_type == 7) {
4952                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4953                                                 __func__, ept_mem_type);
4954                                 WARN_ON(1);
4955                         }
4956                 }
4957         }
4958 }
4959
4960 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
4961 {
4962         u64 sptes[4];
4963         int nr_sptes, i, ret;
4964         gpa_t gpa;
4965
4966         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4967
4968         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4969         if (likely(ret == 1))
4970                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4971                                               EMULATE_DONE;
4972         if (unlikely(!ret))
4973                 return 1;
4974
4975         /* It is the real ept misconfig */
4976         printk(KERN_ERR "EPT: Misconfiguration.\n");
4977         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4978
4979         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4980
4981         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4982                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4983
4984         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4985         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
4986
4987         return 0;
4988 }
4989
4990 static int handle_nmi_window(struct kvm_vcpu *vcpu)
4991 {
4992         u32 cpu_based_vm_exec_control;
4993
4994         /* clear pending NMI */
4995         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4996         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4997         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4998         ++vcpu->stat.nmi_window_exits;
4999         kvm_make_request(KVM_REQ_EVENT, vcpu);
5000
5001         return 1;
5002 }
5003
5004 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5005 {
5006         struct vcpu_vmx *vmx = to_vmx(vcpu);
5007         enum emulation_result err = EMULATE_DONE;
5008         int ret = 1;
5009         u32 cpu_exec_ctrl;
5010         bool intr_window_requested;
5011         unsigned count = 130;
5012
5013         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5014         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5015
5016         while (!guest_state_valid(vcpu) && count-- != 0) {
5017                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5018                         return handle_interrupt_window(&vmx->vcpu);
5019
5020                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5021                         return 1;
5022
5023                 err = emulate_instruction(vcpu, 0);
5024
5025                 if (err == EMULATE_DO_MMIO) {
5026                         ret = 0;
5027                         goto out;
5028                 }
5029
5030                 if (err != EMULATE_DONE) {
5031                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5032                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5033                         vcpu->run->internal.ndata = 0;
5034                         return 0;
5035                 }
5036
5037                 if (signal_pending(current))
5038                         goto out;
5039                 if (need_resched())
5040                         schedule();
5041         }
5042
5043         vmx->emulation_required = !guest_state_valid(vcpu);
5044 out:
5045         return ret;
5046 }
5047
5048 /*
5049  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5050  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5051  */
5052 static int handle_pause(struct kvm_vcpu *vcpu)
5053 {
5054         skip_emulated_instruction(vcpu);
5055         kvm_vcpu_on_spin(vcpu);
5056
5057         return 1;
5058 }
5059
5060 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5061 {
5062         kvm_queue_exception(vcpu, UD_VECTOR);
5063         return 1;
5064 }
5065
5066 /*
5067  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5068  * We could reuse a single VMCS for all the L2 guests, but we also want the
5069  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5070  * allows keeping them loaded on the processor, and in the future will allow
5071  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5072  * every entry if they never change.
5073  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5074  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5075  *
5076  * The following functions allocate and free a vmcs02 in this pool.
5077  */
5078
5079 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5080 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5081 {
5082         struct vmcs02_list *item;
5083         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5084                 if (item->vmptr == vmx->nested.current_vmptr) {
5085                         list_move(&item->list, &vmx->nested.vmcs02_pool);
5086                         return &item->vmcs02;
5087                 }
5088
5089         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5090                 /* Recycle the least recently used VMCS. */
5091                 item = list_entry(vmx->nested.vmcs02_pool.prev,
5092                         struct vmcs02_list, list);
5093                 item->vmptr = vmx->nested.current_vmptr;
5094                 list_move(&item->list, &vmx->nested.vmcs02_pool);
5095                 return &item->vmcs02;
5096         }
5097
5098         /* Create a new VMCS */
5099         item = (struct vmcs02_list *)
5100                 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5101         if (!item)
5102                 return NULL;
5103         item->vmcs02.vmcs = alloc_vmcs();
5104         if (!item->vmcs02.vmcs) {
5105                 kfree(item);
5106                 return NULL;
5107         }
5108         loaded_vmcs_init(&item->vmcs02);
5109         item->vmptr = vmx->nested.current_vmptr;
5110         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5111         vmx->nested.vmcs02_num++;
5112         return &item->vmcs02;
5113 }
5114
5115 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5116 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5117 {
5118         struct vmcs02_list *item;
5119         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5120                 if (item->vmptr == vmptr) {
5121                         free_loaded_vmcs(&item->vmcs02);
5122                         list_del(&item->list);
5123                         kfree(item);
5124                         vmx->nested.vmcs02_num--;
5125                         return;
5126                 }
5127 }
5128
5129 /*
5130  * Free all VMCSs saved for this vcpu, except the one pointed by
5131  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5132  * currently used, if running L2), and vmcs01 when running L2.
5133  */
5134 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5135 {
5136         struct vmcs02_list *item, *n;
5137         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5138                 if (vmx->loaded_vmcs != &item->vmcs02)
5139                         free_loaded_vmcs(&item->vmcs02);
5140                 list_del(&item->list);
5141                 kfree(item);
5142         }
5143         vmx->nested.vmcs02_num = 0;
5144
5145         if (vmx->loaded_vmcs != &vmx->vmcs01)
5146                 free_loaded_vmcs(&vmx->vmcs01);
5147 }
5148
5149 /*
5150  * Emulate the VMXON instruction.
5151  * Currently, we just remember that VMX is active, and do not save or even
5152  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5153  * do not currently need to store anything in that guest-allocated memory
5154  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5155  * argument is different from the VMXON pointer (which the spec says they do).
5156  */
5157 static int handle_vmon(struct kvm_vcpu *vcpu)
5158 {
5159         struct kvm_segment cs;
5160         struct vcpu_vmx *vmx = to_vmx(vcpu);
5161
5162         /* The Intel VMX Instruction Reference lists a bunch of bits that
5163          * are prerequisite to running VMXON, most notably cr4.VMXE must be
5164          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5165          * Otherwise, we should fail with #UD. We test these now:
5166          */
5167         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5168             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5169             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5170                 kvm_queue_exception(vcpu, UD_VECTOR);
5171                 return 1;
5172         }
5173
5174         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5175         if (is_long_mode(vcpu) && !cs.l) {
5176                 kvm_queue_exception(vcpu, UD_VECTOR);
5177                 return 1;
5178         }
5179
5180         if (vmx_get_cpl(vcpu)) {
5181                 kvm_inject_gp(vcpu, 0);
5182                 return 1;
5183         }
5184
5185         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5186         vmx->nested.vmcs02_num = 0;
5187
5188         vmx->nested.vmxon = true;
5189
5190         skip_emulated_instruction(vcpu);
5191         return 1;
5192 }
5193
5194 /*
5195  * Intel's VMX Instruction Reference specifies a common set of prerequisites
5196  * for running VMX instructions (except VMXON, whose prerequisites are
5197  * slightly different). It also specifies what exception to inject otherwise.
5198  */
5199 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5200 {
5201         struct kvm_segment cs;
5202         struct vcpu_vmx *vmx = to_vmx(vcpu);
5203
5204         if (!vmx->nested.vmxon) {
5205                 kvm_queue_exception(vcpu, UD_VECTOR);
5206                 return 0;
5207         }
5208
5209         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5210         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5211             (is_long_mode(vcpu) && !cs.l)) {
5212                 kvm_queue_exception(vcpu, UD_VECTOR);
5213                 return 0;
5214         }
5215
5216         if (vmx_get_cpl(vcpu)) {
5217                 kvm_inject_gp(vcpu, 0);
5218                 return 0;
5219         }
5220
5221         return 1;
5222 }
5223
5224 /*
5225  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5226  * just stops using VMX.
5227  */
5228 static void free_nested(struct vcpu_vmx *vmx)
5229 {
5230         if (!vmx->nested.vmxon)
5231                 return;
5232         vmx->nested.vmxon = false;
5233         if (vmx->nested.current_vmptr != -1ull) {
5234                 kunmap(vmx->nested.current_vmcs12_page);
5235                 nested_release_page(vmx->nested.current_vmcs12_page);
5236                 vmx->nested.current_vmptr = -1ull;
5237                 vmx->nested.current_vmcs12 = NULL;
5238         }
5239         /* Unpin physical memory we referred to in current vmcs02 */
5240         if (vmx->nested.apic_access_page) {
5241                 nested_release_page(vmx->nested.apic_access_page);
5242                 vmx->nested.apic_access_page = 0;
5243         }
5244
5245         nested_free_all_saved_vmcss(vmx);
5246 }
5247
5248 /* Emulate the VMXOFF instruction */
5249 static int handle_vmoff(struct kvm_vcpu *vcpu)
5250 {
5251         if (!nested_vmx_check_permission(vcpu))
5252                 return 1;
5253         free_nested(to_vmx(vcpu));
5254         skip_emulated_instruction(vcpu);
5255         return 1;
5256 }
5257
5258 /*
5259  * Decode the memory-address operand of a vmx instruction, as recorded on an
5260  * exit caused by such an instruction (run by a guest hypervisor).
5261  * On success, returns 0. When the operand is invalid, returns 1 and throws
5262  * #UD or #GP.
5263  */
5264 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5265                                  unsigned long exit_qualification,
5266                                  u32 vmx_instruction_info, gva_t *ret)
5267 {
5268         /*
5269          * According to Vol. 3B, "Information for VM Exits Due to Instruction
5270          * Execution", on an exit, vmx_instruction_info holds most of the
5271          * addressing components of the operand. Only the displacement part
5272          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5273          * For how an actual address is calculated from all these components,
5274          * refer to Vol. 1, "Operand Addressing".
5275          */
5276         int  scaling = vmx_instruction_info & 3;
5277         int  addr_size = (vmx_instruction_info >> 7) & 7;
5278         bool is_reg = vmx_instruction_info & (1u << 10);
5279         int  seg_reg = (vmx_instruction_info >> 15) & 7;
5280         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
5281         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5282         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
5283         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
5284
5285         if (is_reg) {
5286                 kvm_queue_exception(vcpu, UD_VECTOR);
5287                 return 1;
5288         }
5289
5290         /* Addr = segment_base + offset */
5291         /* offset = base + [index * scale] + displacement */
5292         *ret = vmx_get_segment_base(vcpu, seg_reg);
5293         if (base_is_valid)
5294                 *ret += kvm_register_read(vcpu, base_reg);
5295         if (index_is_valid)
5296                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5297         *ret += exit_qualification; /* holds the displacement */
5298
5299         if (addr_size == 1) /* 32 bit */
5300                 *ret &= 0xffffffff;
5301
5302         /*
5303          * TODO: throw #GP (and return 1) in various cases that the VM*
5304          * instructions require it - e.g., offset beyond segment limit,
5305          * unusable or unreadable/unwritable segment, non-canonical 64-bit
5306          * address, and so on. Currently these are not checked.
5307          */
5308         return 0;
5309 }
5310
5311 /*
5312  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5313  * set the success or error code of an emulated VMX instruction, as specified
5314  * by Vol 2B, VMX Instruction Reference, "Conventions".
5315  */
5316 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5317 {
5318         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5319                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5320                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5321 }
5322
5323 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5324 {
5325         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5326                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5327                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5328                         | X86_EFLAGS_CF);
5329 }
5330
5331 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5332                                         u32 vm_instruction_error)
5333 {
5334         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5335                 /*
5336                  * failValid writes the error number to the current VMCS, which
5337                  * can't be done there isn't a current VMCS.
5338                  */
5339                 nested_vmx_failInvalid(vcpu);
5340                 return;
5341         }
5342         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5343                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5344                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5345                         | X86_EFLAGS_ZF);
5346         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5347 }
5348
5349 /* Emulate the VMCLEAR instruction */
5350 static int handle_vmclear(struct kvm_vcpu *vcpu)
5351 {
5352         struct vcpu_vmx *vmx = to_vmx(vcpu);
5353         gva_t gva;
5354         gpa_t vmptr;
5355         struct vmcs12 *vmcs12;
5356         struct page *page;
5357         struct x86_exception e;
5358
5359         if (!nested_vmx_check_permission(vcpu))
5360                 return 1;
5361
5362         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5363                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5364                 return 1;
5365
5366         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5367                                 sizeof(vmptr), &e)) {
5368                 kvm_inject_page_fault(vcpu, &e);
5369                 return 1;
5370         }
5371
5372         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5373                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5374                 skip_emulated_instruction(vcpu);
5375                 return 1;
5376         }
5377
5378         if (vmptr == vmx->nested.current_vmptr) {
5379                 kunmap(vmx->nested.current_vmcs12_page);
5380                 nested_release_page(vmx->nested.current_vmcs12_page);
5381                 vmx->nested.current_vmptr = -1ull;
5382                 vmx->nested.current_vmcs12 = NULL;
5383         }
5384
5385         page = nested_get_page(vcpu, vmptr);
5386         if (page == NULL) {
5387                 /*
5388                  * For accurate processor emulation, VMCLEAR beyond available
5389                  * physical memory should do nothing at all. However, it is
5390                  * possible that a nested vmx bug, not a guest hypervisor bug,
5391                  * resulted in this case, so let's shut down before doing any
5392                  * more damage:
5393                  */
5394                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5395                 return 1;
5396         }
5397         vmcs12 = kmap(page);
5398         vmcs12->launch_state = 0;
5399         kunmap(page);
5400         nested_release_page(page);
5401
5402         nested_free_vmcs02(vmx, vmptr);
5403
5404         skip_emulated_instruction(vcpu);
5405         nested_vmx_succeed(vcpu);
5406         return 1;
5407 }
5408
5409 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5410
5411 /* Emulate the VMLAUNCH instruction */
5412 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5413 {
5414         return nested_vmx_run(vcpu, true);
5415 }
5416
5417 /* Emulate the VMRESUME instruction */
5418 static int handle_vmresume(struct kvm_vcpu *vcpu)
5419 {
5420
5421         return nested_vmx_run(vcpu, false);
5422 }
5423
5424 enum vmcs_field_type {
5425         VMCS_FIELD_TYPE_U16 = 0,
5426         VMCS_FIELD_TYPE_U64 = 1,
5427         VMCS_FIELD_TYPE_U32 = 2,
5428         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5429 };
5430
5431 static inline int vmcs_field_type(unsigned long field)
5432 {
5433         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
5434                 return VMCS_FIELD_TYPE_U32;
5435         return (field >> 13) & 0x3 ;
5436 }
5437
5438 static inline int vmcs_field_readonly(unsigned long field)
5439 {
5440         return (((field >> 10) & 0x3) == 1);
5441 }
5442
5443 /*
5444  * Read a vmcs12 field. Since these can have varying lengths and we return
5445  * one type, we chose the biggest type (u64) and zero-extend the return value
5446  * to that size. Note that the caller, handle_vmread, might need to use only
5447  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5448  * 64-bit fields are to be returned).
5449  */
5450 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5451                                         unsigned long field, u64 *ret)
5452 {
5453         short offset = vmcs_field_to_offset(field);
5454         char *p;
5455
5456         if (offset < 0)
5457                 return 0;
5458
5459         p = ((char *)(get_vmcs12(vcpu))) + offset;
5460
5461         switch (vmcs_field_type(field)) {
5462         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5463                 *ret = *((natural_width *)p);
5464                 return 1;
5465         case VMCS_FIELD_TYPE_U16:
5466                 *ret = *((u16 *)p);
5467                 return 1;
5468         case VMCS_FIELD_TYPE_U32:
5469                 *ret = *((u32 *)p);
5470                 return 1;
5471         case VMCS_FIELD_TYPE_U64:
5472                 *ret = *((u64 *)p);
5473                 return 1;
5474         default:
5475                 return 0; /* can never happen. */
5476         }
5477 }
5478
5479 /*
5480  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5481  * used before) all generate the same failure when it is missing.
5482  */
5483 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5484 {
5485         struct vcpu_vmx *vmx = to_vmx(vcpu);
5486         if (vmx->nested.current_vmptr == -1ull) {
5487                 nested_vmx_failInvalid(vcpu);
5488                 skip_emulated_instruction(vcpu);
5489                 return 0;
5490         }
5491         return 1;
5492 }
5493
5494 static int handle_vmread(struct kvm_vcpu *vcpu)
5495 {
5496         unsigned long field;
5497         u64 field_value;
5498         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5499         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5500         gva_t gva = 0;
5501
5502         if (!nested_vmx_check_permission(vcpu) ||
5503             !nested_vmx_check_vmcs12(vcpu))
5504                 return 1;
5505
5506         /* Decode instruction info and find the field to read */
5507         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5508         /* Read the field, zero-extended to a u64 field_value */
5509         if (!vmcs12_read_any(vcpu, field, &field_value)) {
5510                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5511                 skip_emulated_instruction(vcpu);
5512                 return 1;
5513         }
5514         /*
5515          * Now copy part of this value to register or memory, as requested.
5516          * Note that the number of bits actually copied is 32 or 64 depending
5517          * on the guest's mode (32 or 64 bit), not on the given field's length.
5518          */
5519         if (vmx_instruction_info & (1u << 10)) {
5520                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5521                         field_value);
5522         } else {
5523                 if (get_vmx_mem_address(vcpu, exit_qualification,
5524                                 vmx_instruction_info, &gva))
5525                         return 1;
5526                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5527                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5528                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5529         }
5530
5531         nested_vmx_succeed(vcpu);
5532         skip_emulated_instruction(vcpu);
5533         return 1;
5534 }
5535
5536
5537 static int handle_vmwrite(struct kvm_vcpu *vcpu)
5538 {
5539         unsigned long field;
5540         gva_t gva;
5541         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5542         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5543         char *p;
5544         short offset;
5545         /* The value to write might be 32 or 64 bits, depending on L1's long
5546          * mode, and eventually we need to write that into a field of several
5547          * possible lengths. The code below first zero-extends the value to 64
5548          * bit (field_value), and then copies only the approriate number of
5549          * bits into the vmcs12 field.
5550          */
5551         u64 field_value = 0;
5552         struct x86_exception e;
5553
5554         if (!nested_vmx_check_permission(vcpu) ||
5555             !nested_vmx_check_vmcs12(vcpu))
5556                 return 1;
5557
5558         if (vmx_instruction_info & (1u << 10))
5559                 field_value = kvm_register_read(vcpu,
5560                         (((vmx_instruction_info) >> 3) & 0xf));
5561         else {
5562                 if (get_vmx_mem_address(vcpu, exit_qualification,
5563                                 vmx_instruction_info, &gva))
5564                         return 1;
5565                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5566                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5567                         kvm_inject_page_fault(vcpu, &e);
5568                         return 1;
5569                 }
5570         }
5571
5572
5573         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5574         if (vmcs_field_readonly(field)) {
5575                 nested_vmx_failValid(vcpu,
5576                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5577                 skip_emulated_instruction(vcpu);
5578                 return 1;
5579         }
5580
5581         offset = vmcs_field_to_offset(field);
5582         if (offset < 0) {
5583                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5584                 skip_emulated_instruction(vcpu);
5585                 return 1;
5586         }
5587         p = ((char *) get_vmcs12(vcpu)) + offset;
5588
5589         switch (vmcs_field_type(field)) {
5590         case VMCS_FIELD_TYPE_U16:
5591                 *(u16 *)p = field_value;
5592                 break;
5593         case VMCS_FIELD_TYPE_U32:
5594                 *(u32 *)p = field_value;
5595                 break;
5596         case VMCS_FIELD_TYPE_U64:
5597                 *(u64 *)p = field_value;
5598                 break;
5599         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5600                 *(natural_width *)p = field_value;
5601                 break;
5602         default:
5603                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5604                 skip_emulated_instruction(vcpu);
5605                 return 1;
5606         }
5607
5608         nested_vmx_succeed(vcpu);
5609         skip_emulated_instruction(vcpu);
5610         return 1;
5611 }
5612
5613 /* Emulate the VMPTRLD instruction */
5614 static int handle_vmptrld(struct kvm_vcpu *vcpu)
5615 {
5616         struct vcpu_vmx *vmx = to_vmx(vcpu);
5617         gva_t gva;
5618         gpa_t vmptr;
5619         struct x86_exception e;
5620
5621         if (!nested_vmx_check_permission(vcpu))
5622                 return 1;
5623
5624         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5625                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5626                 return 1;
5627
5628         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5629                                 sizeof(vmptr), &e)) {
5630                 kvm_inject_page_fault(vcpu, &e);
5631                 return 1;
5632         }
5633
5634         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5635                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5636                 skip_emulated_instruction(vcpu);
5637                 return 1;
5638         }
5639
5640         if (vmx->nested.current_vmptr != vmptr) {
5641                 struct vmcs12 *new_vmcs12;
5642                 struct page *page;
5643                 page = nested_get_page(vcpu, vmptr);
5644                 if (page == NULL) {
5645                         nested_vmx_failInvalid(vcpu);
5646                         skip_emulated_instruction(vcpu);
5647                         return 1;
5648                 }
5649                 new_vmcs12 = kmap(page);
5650                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5651                         kunmap(page);
5652                         nested_release_page_clean(page);
5653                         nested_vmx_failValid(vcpu,
5654                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5655                         skip_emulated_instruction(vcpu);
5656                         return 1;
5657                 }
5658                 if (vmx->nested.current_vmptr != -1ull) {
5659                         kunmap(vmx->nested.current_vmcs12_page);
5660                         nested_release_page(vmx->nested.current_vmcs12_page);
5661                 }
5662
5663                 vmx->nested.current_vmptr = vmptr;
5664                 vmx->nested.current_vmcs12 = new_vmcs12;
5665                 vmx->nested.current_vmcs12_page = page;
5666         }
5667
5668         nested_vmx_succeed(vcpu);
5669         skip_emulated_instruction(vcpu);
5670         return 1;
5671 }
5672
5673 /* Emulate the VMPTRST instruction */
5674 static int handle_vmptrst(struct kvm_vcpu *vcpu)
5675 {
5676         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5677         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5678         gva_t vmcs_gva;
5679         struct x86_exception e;
5680
5681         if (!nested_vmx_check_permission(vcpu))
5682                 return 1;
5683
5684         if (get_vmx_mem_address(vcpu, exit_qualification,
5685                         vmx_instruction_info, &vmcs_gva))
5686                 return 1;
5687         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5688         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5689                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
5690                                  sizeof(u64), &e)) {
5691                 kvm_inject_page_fault(vcpu, &e);
5692                 return 1;
5693         }
5694         nested_vmx_succeed(vcpu);
5695         skip_emulated_instruction(vcpu);
5696         return 1;
5697 }
5698
5699 /*
5700  * The exit handlers return 1 if the exit was handled fully and guest execution
5701  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5702  * to be done to userspace and return 0.
5703  */
5704 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5705         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
5706         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5707         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5708         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5709         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5710         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5711         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5712         [EXIT_REASON_CPUID]                   = handle_cpuid,
5713         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
5714         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
5715         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
5716         [EXIT_REASON_HLT]                     = handle_halt,
5717         [EXIT_REASON_INVD]                    = handle_invd,
5718         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5719         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
5720         [EXIT_REASON_VMCALL]                  = handle_vmcall,
5721         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
5722         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
5723         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
5724         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
5725         [EXIT_REASON_VMREAD]                  = handle_vmread,
5726         [EXIT_REASON_VMRESUME]                = handle_vmresume,
5727         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
5728         [EXIT_REASON_VMOFF]                   = handle_vmoff,
5729         [EXIT_REASON_VMON]                    = handle_vmon,
5730         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5731         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5732         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
5733         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
5734         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5735         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5736         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5737         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5738         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5739         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
5740         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
5741 };
5742
5743 static const int kvm_vmx_max_exit_handlers =
5744         ARRAY_SIZE(kvm_vmx_exit_handlers);
5745
5746 /*
5747  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5748  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5749  * disinterest in the current event (read or write a specific MSR) by using an
5750  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5751  */
5752 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5753         struct vmcs12 *vmcs12, u32 exit_reason)
5754 {
5755         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5756         gpa_t bitmap;
5757
5758         if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5759                 return 1;
5760
5761         /*
5762          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5763          * for the four combinations of read/write and low/high MSR numbers.
5764          * First we need to figure out which of the four to use:
5765          */
5766         bitmap = vmcs12->msr_bitmap;
5767         if (exit_reason == EXIT_REASON_MSR_WRITE)
5768                 bitmap += 2048;
5769         if (msr_index >= 0xc0000000) {
5770                 msr_index -= 0xc0000000;
5771                 bitmap += 1024;
5772         }
5773
5774         /* Then read the msr_index'th bit from this bitmap: */
5775         if (msr_index < 1024*8) {
5776                 unsigned char b;
5777                 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5778                 return 1 & (b >> (msr_index & 7));
5779         } else
5780                 return 1; /* let L1 handle the wrong parameter */
5781 }
5782
5783 /*
5784  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5785  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5786  * intercept (via guest_host_mask etc.) the current event.
5787  */
5788 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5789         struct vmcs12 *vmcs12)
5790 {
5791         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5792         int cr = exit_qualification & 15;
5793         int reg = (exit_qualification >> 8) & 15;
5794         unsigned long val = kvm_register_read(vcpu, reg);
5795
5796         switch ((exit_qualification >> 4) & 3) {
5797         case 0: /* mov to cr */
5798                 switch (cr) {
5799                 case 0:
5800                         if (vmcs12->cr0_guest_host_mask &
5801                             (val ^ vmcs12->cr0_read_shadow))
5802                                 return 1;
5803                         break;
5804                 case 3:
5805                         if ((vmcs12->cr3_target_count >= 1 &&
5806                                         vmcs12->cr3_target_value0 == val) ||
5807                                 (vmcs12->cr3_target_count >= 2 &&
5808                                         vmcs12->cr3_target_value1 == val) ||
5809                                 (vmcs12->cr3_target_count >= 3 &&
5810                                         vmcs12->cr3_target_value2 == val) ||
5811                                 (vmcs12->cr3_target_count >= 4 &&
5812                                         vmcs12->cr3_target_value3 == val))
5813                                 return 0;
5814                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5815                                 return 1;
5816                         break;
5817                 case 4:
5818                         if (vmcs12->cr4_guest_host_mask &
5819                             (vmcs12->cr4_read_shadow ^ val))
5820                                 return 1;
5821                         break;
5822                 case 8:
5823                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5824                                 return 1;
5825                         break;
5826                 }
5827                 break;
5828         case 2: /* clts */
5829                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5830                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
5831                         return 1;
5832                 break;
5833         case 1: /* mov from cr */
5834                 switch (cr) {
5835                 case 3:
5836                         if (vmcs12->cpu_based_vm_exec_control &
5837                             CPU_BASED_CR3_STORE_EXITING)
5838                                 return 1;
5839                         break;
5840                 case 8:
5841                         if (vmcs12->cpu_based_vm_exec_control &
5842                             CPU_BASED_CR8_STORE_EXITING)
5843                                 return 1;
5844                         break;
5845                 }
5846                 break;
5847         case 3: /* lmsw */
5848                 /*
5849                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5850                  * cr0. Other attempted changes are ignored, with no exit.
5851                  */
5852                 if (vmcs12->cr0_guest_host_mask & 0xe &
5853                     (val ^ vmcs12->cr0_read_shadow))
5854                         return 1;
5855                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5856                     !(vmcs12->cr0_read_shadow & 0x1) &&
5857                     (val & 0x1))
5858                         return 1;
5859                 break;
5860         }
5861         return 0;
5862 }
5863
5864 /*
5865  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5866  * should handle it ourselves in L0 (and then continue L2). Only call this
5867  * when in is_guest_mode (L2).
5868  */
5869 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5870 {
5871         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5872         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5873         struct vcpu_vmx *vmx = to_vmx(vcpu);
5874         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5875
5876         if (vmx->nested.nested_run_pending)
5877                 return 0;
5878
5879         if (unlikely(vmx->fail)) {
5880                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5881                                     vmcs_read32(VM_INSTRUCTION_ERROR));
5882                 return 1;
5883         }
5884
5885         switch (exit_reason) {
5886         case EXIT_REASON_EXCEPTION_NMI:
5887                 if (!is_exception(intr_info))
5888                         return 0;
5889                 else if (is_page_fault(intr_info))
5890                         return enable_ept;
5891                 return vmcs12->exception_bitmap &
5892                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5893         case EXIT_REASON_EXTERNAL_INTERRUPT:
5894                 return 0;
5895         case EXIT_REASON_TRIPLE_FAULT:
5896                 return 1;
5897         case EXIT_REASON_PENDING_INTERRUPT:
5898         case EXIT_REASON_NMI_WINDOW:
5899                 /*
5900                  * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5901                  * (aka Interrupt Window Exiting) only when L1 turned it on,
5902                  * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5903                  * Same for NMI Window Exiting.
5904                  */
5905                 return 1;
5906         case EXIT_REASON_TASK_SWITCH:
5907                 return 1;
5908         case EXIT_REASON_CPUID:
5909                 return 1;
5910         case EXIT_REASON_HLT:
5911                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5912         case EXIT_REASON_INVD:
5913                 return 1;
5914         case EXIT_REASON_INVLPG:
5915                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5916         case EXIT_REASON_RDPMC:
5917                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5918         case EXIT_REASON_RDTSC:
5919                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5920         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5921         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5922         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5923         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5924         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5925                 /*
5926                  * VMX instructions trap unconditionally. This allows L1 to
5927                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
5928                  */
5929                 return 1;
5930         case EXIT_REASON_CR_ACCESS:
5931                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5932         case EXIT_REASON_DR_ACCESS:
5933                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5934         case EXIT_REASON_IO_INSTRUCTION:
5935                 /* TODO: support IO bitmaps */
5936                 return 1;
5937         case EXIT_REASON_MSR_READ:
5938         case EXIT_REASON_MSR_WRITE:
5939                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5940         case EXIT_REASON_INVALID_STATE:
5941                 return 1;
5942         case EXIT_REASON_MWAIT_INSTRUCTION:
5943                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5944         case EXIT_REASON_MONITOR_INSTRUCTION:
5945                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5946         case EXIT_REASON_PAUSE_INSTRUCTION:
5947                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5948                         nested_cpu_has2(vmcs12,
5949                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5950         case EXIT_REASON_MCE_DURING_VMENTRY:
5951                 return 0;
5952         case EXIT_REASON_TPR_BELOW_THRESHOLD:
5953                 return 1;
5954         case EXIT_REASON_APIC_ACCESS:
5955                 return nested_cpu_has2(vmcs12,
5956                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5957         case EXIT_REASON_EPT_VIOLATION:
5958         case EXIT_REASON_EPT_MISCONFIG:
5959                 return 0;
5960         case EXIT_REASON_WBINVD:
5961                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5962         case EXIT_REASON_XSETBV:
5963                 return 1;
5964         default:
5965                 return 1;
5966         }
5967 }
5968
5969 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5970 {
5971         *info1 = vmcs_readl(EXIT_QUALIFICATION);
5972         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5973 }
5974
5975 /*
5976  * The guest has exited.  See if we can fix it or if we need userspace
5977  * assistance.
5978  */
5979 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5980 {
5981         struct vcpu_vmx *vmx = to_vmx(vcpu);
5982         u32 exit_reason = vmx->exit_reason;
5983         u32 vectoring_info = vmx->idt_vectoring_info;
5984
5985         /* If guest state is invalid, start emulating */
5986         if (vmx->emulation_required && emulate_invalid_guest_state)
5987                 return handle_invalid_guest_state(vcpu);
5988
5989         /*
5990          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5991          * we did not inject a still-pending event to L1 now because of
5992          * nested_run_pending, we need to re-enable this bit.
5993          */
5994         if (vmx->nested.nested_run_pending)
5995                 kvm_make_request(KVM_REQ_EVENT, vcpu);
5996
5997         if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5998             exit_reason == EXIT_REASON_VMRESUME))
5999                 vmx->nested.nested_run_pending = 1;
6000         else
6001                 vmx->nested.nested_run_pending = 0;
6002
6003         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6004                 nested_vmx_vmexit(vcpu);
6005                 return 1;
6006         }
6007
6008         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6009                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6010                 vcpu->run->fail_entry.hardware_entry_failure_reason
6011                         = exit_reason;
6012                 return 0;
6013         }
6014
6015         if (unlikely(vmx->fail)) {
6016                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6017                 vcpu->run->fail_entry.hardware_entry_failure_reason
6018                         = vmcs_read32(VM_INSTRUCTION_ERROR);
6019                 return 0;
6020         }
6021
6022         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
6023                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
6024                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
6025                         exit_reason != EXIT_REASON_TASK_SWITCH))
6026                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
6027                        "(0x%x) and exit reason is 0x%x\n",
6028                        __func__, vectoring_info, exit_reason);
6029
6030         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6031             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6032                                         get_vmcs12(vcpu), vcpu)))) {
6033                 if (vmx_interrupt_allowed(vcpu)) {
6034                         vmx->soft_vnmi_blocked = 0;
6035                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
6036                            vcpu->arch.nmi_pending) {
6037                         /*
6038                          * This CPU don't support us in finding the end of an
6039                          * NMI-blocked window if the guest runs with IRQs
6040                          * disabled. So we pull the trigger after 1 s of
6041                          * futile waiting, but inform the user about this.
6042                          */
6043                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6044                                "state on VCPU %d after 1 s timeout\n",
6045                                __func__, vcpu->vcpu_id);
6046                         vmx->soft_vnmi_blocked = 0;
6047                 }
6048         }
6049
6050         if (exit_reason < kvm_vmx_max_exit_handlers
6051             && kvm_vmx_exit_handlers[exit_reason])
6052                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6053         else {
6054                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6055                 vcpu->run->hw.hardware_exit_reason = exit_reason;
6056         }
6057         return 0;
6058 }
6059
6060 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6061 {
6062         if (irr == -1 || tpr < irr) {
6063                 vmcs_write32(TPR_THRESHOLD, 0);
6064                 return;
6065         }
6066
6067         vmcs_write32(TPR_THRESHOLD, irr);
6068 }
6069
6070 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
6071 {
6072         u32 exit_intr_info;
6073
6074         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6075               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6076                 return;
6077
6078         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6079         exit_intr_info = vmx->exit_intr_info;
6080
6081         /* Handle machine checks before interrupts are enabled */
6082         if (is_machine_check(exit_intr_info))
6083                 kvm_machine_check();
6084
6085         /* We need to handle NMIs before interrupts are enabled */
6086         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
6087             (exit_intr_info & INTR_INFO_VALID_MASK)) {
6088                 kvm_before_handle_nmi(&vmx->vcpu);
6089                 asm("int $2");
6090                 kvm_after_handle_nmi(&vmx->vcpu);
6091         }
6092 }
6093
6094 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6095 {
6096         u32 exit_intr_info;
6097         bool unblock_nmi;
6098         u8 vector;
6099         bool idtv_info_valid;
6100
6101         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6102
6103         if (cpu_has_virtual_nmis()) {
6104                 if (vmx->nmi_known_unmasked)
6105                         return;
6106                 /*
6107                  * Can't use vmx->exit_intr_info since we're not sure what
6108                  * the exit reason is.
6109                  */
6110                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6111                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6112                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6113                 /*
6114                  * SDM 3: 27.7.1.2 (September 2008)
6115                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
6116                  * a guest IRET fault.
6117                  * SDM 3: 23.2.2 (September 2008)
6118                  * Bit 12 is undefined in any of the following cases:
6119                  *  If the VM exit sets the valid bit in the IDT-vectoring
6120                  *   information field.
6121                  *  If the VM exit is due to a double fault.
6122                  */
6123                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6124                     vector != DF_VECTOR && !idtv_info_valid)
6125                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6126                                       GUEST_INTR_STATE_NMI);
6127                 else
6128                         vmx->nmi_known_unmasked =
6129                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6130                                   & GUEST_INTR_STATE_NMI);
6131         } else if (unlikely(vmx->soft_vnmi_blocked))
6132                 vmx->vnmi_blocked_time +=
6133                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
6134 }
6135
6136 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
6137                                       u32 idt_vectoring_info,
6138                                       int instr_len_field,
6139                                       int error_code_field)
6140 {
6141         u8 vector;
6142         int type;
6143         bool idtv_info_valid;
6144
6145         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6146
6147         vmx->vcpu.arch.nmi_injected = false;
6148         kvm_clear_exception_queue(&vmx->vcpu);
6149         kvm_clear_interrupt_queue(&vmx->vcpu);
6150
6151         if (!idtv_info_valid)
6152                 return;
6153
6154         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6155
6156         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6157         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6158
6159         switch (type) {
6160         case INTR_TYPE_NMI_INTR:
6161                 vmx->vcpu.arch.nmi_injected = true;
6162                 /*
6163                  * SDM 3: 27.7.1.2 (September 2008)
6164                  * Clear bit "block by NMI" before VM entry if a NMI
6165                  * delivery faulted.
6166                  */
6167                 vmx_set_nmi_mask(&vmx->vcpu, false);
6168                 break;
6169         case INTR_TYPE_SOFT_EXCEPTION:
6170                 vmx->vcpu.arch.event_exit_inst_len =
6171                         vmcs_read32(instr_len_field);
6172                 /* fall through */
6173         case INTR_TYPE_HARD_EXCEPTION:
6174                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6175                         u32 err = vmcs_read32(error_code_field);
6176                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
6177                 } else
6178                         kvm_queue_exception(&vmx->vcpu, vector);
6179                 break;
6180         case INTR_TYPE_SOFT_INTR:
6181                 vmx->vcpu.arch.event_exit_inst_len =
6182                         vmcs_read32(instr_len_field);
6183                 /* fall through */
6184         case INTR_TYPE_EXT_INTR:
6185                 kvm_queue_interrupt(&vmx->vcpu, vector,
6186                         type == INTR_TYPE_SOFT_INTR);
6187                 break;
6188         default:
6189                 break;
6190         }
6191 }
6192
6193 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6194 {
6195         if (is_guest_mode(&vmx->vcpu))
6196                 return;
6197         __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6198                                   VM_EXIT_INSTRUCTION_LEN,
6199                                   IDT_VECTORING_ERROR_CODE);
6200 }
6201
6202 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6203 {
6204         if (is_guest_mode(vcpu))
6205                 return;
6206         __vmx_complete_interrupts(to_vmx(vcpu),
6207                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6208                                   VM_ENTRY_INSTRUCTION_LEN,
6209                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
6210
6211         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6212 }
6213
6214 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6215 {
6216         int i, nr_msrs;
6217         struct perf_guest_switch_msr *msrs;
6218
6219         msrs = perf_guest_get_msrs(&nr_msrs);
6220
6221         if (!msrs)
6222                 return;
6223
6224         for (i = 0; i < nr_msrs; i++)
6225                 if (msrs[i].host == msrs[i].guest)
6226                         clear_atomic_switch_msr(vmx, msrs[i].msr);
6227                 else
6228                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6229                                         msrs[i].host);
6230 }
6231
6232 #ifdef CONFIG_X86_64
6233 #define R "r"
6234 #define Q "q"
6235 #else
6236 #define R "e"
6237 #define Q "l"
6238 #endif
6239
6240 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6241 {
6242         struct vcpu_vmx *vmx = to_vmx(vcpu);
6243
6244         if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6245                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6246                 if (vmcs12->idt_vectoring_info_field &
6247                                 VECTORING_INFO_VALID_MASK) {
6248                         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6249                                 vmcs12->idt_vectoring_info_field);
6250                         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6251                                 vmcs12->vm_exit_instruction_len);
6252                         if (vmcs12->idt_vectoring_info_field &
6253                                         VECTORING_INFO_DELIVER_CODE_MASK)
6254                                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6255                                         vmcs12->idt_vectoring_error_code);
6256                 }
6257         }
6258
6259         /* Record the guest's net vcpu time for enforced NMI injections. */
6260         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6261                 vmx->entry_time = ktime_get();
6262
6263         /* Don't enter VMX if guest state is invalid, let the exit handler
6264            start emulation until we arrive back to a valid state */
6265         if (vmx->emulation_required && emulate_invalid_guest_state)
6266                 return;
6267
6268         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6269                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6270         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6271                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6272
6273         /* When single-stepping over STI and MOV SS, we must clear the
6274          * corresponding interruptibility bits in the guest state. Otherwise
6275          * vmentry fails as it then expects bit 14 (BS) in pending debug
6276          * exceptions being set, but that's not correct for the guest debugging
6277          * case. */
6278         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6279                 vmx_set_interrupt_shadow(vcpu, 0);
6280
6281         atomic_switch_perf_msrs(vmx);
6282
6283         vmx->__launched = vmx->loaded_vmcs->launched;
6284         asm(
6285                 /* Store host registers */
6286                 "push %%"R"dx; push %%"R"bp;"
6287                 "push %%"R"cx \n\t" /* placeholder for guest rcx */
6288                 "push %%"R"cx \n\t"
6289                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
6290                 "je 1f \n\t"
6291                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
6292                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
6293                 "1: \n\t"
6294                 /* Reload cr2 if changed */
6295                 "mov %c[cr2](%0), %%"R"ax \n\t"
6296                 "mov %%cr2, %%"R"dx \n\t"
6297                 "cmp %%"R"ax, %%"R"dx \n\t"
6298                 "je 2f \n\t"
6299                 "mov %%"R"ax, %%cr2 \n\t"
6300                 "2: \n\t"
6301                 /* Check if vmlaunch of vmresume is needed */
6302                 "cmpl $0, %c[launched](%0) \n\t"
6303                 /* Load guest registers.  Don't clobber flags. */
6304                 "mov %c[rax](%0), %%"R"ax \n\t"
6305                 "mov %c[rbx](%0), %%"R"bx \n\t"
6306                 "mov %c[rdx](%0), %%"R"dx \n\t"
6307                 "mov %c[rsi](%0), %%"R"si \n\t"
6308                 "mov %c[rdi](%0), %%"R"di \n\t"
6309                 "mov %c[rbp](%0), %%"R"bp \n\t"
6310 #ifdef CONFIG_X86_64
6311                 "mov %c[r8](%0),  %%r8  \n\t"
6312                 "mov %c[r9](%0),  %%r9  \n\t"
6313                 "mov %c[r10](%0), %%r10 \n\t"
6314                 "mov %c[r11](%0), %%r11 \n\t"
6315                 "mov %c[r12](%0), %%r12 \n\t"
6316                 "mov %c[r13](%0), %%r13 \n\t"
6317                 "mov %c[r14](%0), %%r14 \n\t"
6318                 "mov %c[r15](%0), %%r15 \n\t"
6319 #endif
6320                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
6321
6322                 /* Enter guest mode */
6323                 "jne .Llaunched \n\t"
6324                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
6325                 "jmp .Lkvm_vmx_return \n\t"
6326                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
6327                 ".Lkvm_vmx_return: "
6328                 /* Save guest registers, load host registers, keep flags */
6329                 "mov %0, %c[wordsize](%%"R"sp) \n\t"
6330                 "pop %0 \n\t"
6331                 "mov %%"R"ax, %c[rax](%0) \n\t"
6332                 "mov %%"R"bx, %c[rbx](%0) \n\t"
6333                 "pop"Q" %c[rcx](%0) \n\t"
6334                 "mov %%"R"dx, %c[rdx](%0) \n\t"
6335                 "mov %%"R"si, %c[rsi](%0) \n\t"
6336                 "mov %%"R"di, %c[rdi](%0) \n\t"
6337                 "mov %%"R"bp, %c[rbp](%0) \n\t"
6338 #ifdef CONFIG_X86_64
6339                 "mov %%r8,  %c[r8](%0) \n\t"
6340                 "mov %%r9,  %c[r9](%0) \n\t"
6341                 "mov %%r10, %c[r10](%0) \n\t"
6342                 "mov %%r11, %c[r11](%0) \n\t"
6343                 "mov %%r12, %c[r12](%0) \n\t"
6344                 "mov %%r13, %c[r13](%0) \n\t"
6345                 "mov %%r14, %c[r14](%0) \n\t"
6346                 "mov %%r15, %c[r15](%0) \n\t"
6347 #endif
6348                 "mov %%cr2, %%"R"ax   \n\t"
6349                 "mov %%"R"ax, %c[cr2](%0) \n\t"
6350
6351                 "pop  %%"R"bp; pop  %%"R"dx \n\t"
6352                 "setbe %c[fail](%0) \n\t"
6353               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
6354                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
6355                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
6356                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
6357                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6358                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6359                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6360                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6361                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6362                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6363                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
6364 #ifdef CONFIG_X86_64
6365                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6366                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6367                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6368                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6369                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6370                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6371                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6372                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6373 #endif
6374                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6375                 [wordsize]"i"(sizeof(ulong))
6376               : "cc", "memory"
6377                 , R"ax", R"bx", R"di", R"si"
6378 #ifdef CONFIG_X86_64
6379                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6380 #endif
6381               );
6382
6383 #ifndef CONFIG_X86_64
6384         /*
6385          * The sysexit path does not restore ds/es, so we must set them to
6386          * a reasonable value ourselves.
6387          *
6388          * We can't defer this to vmx_load_host_state() since that function
6389          * may be executed in interrupt context, which saves and restore segments
6390          * around it, nullifying its effect.
6391          */
6392         loadsegment(ds, __USER_DS);
6393         loadsegment(es, __USER_DS);
6394 #endif
6395
6396         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6397                                   | (1 << VCPU_EXREG_RFLAGS)
6398                                   | (1 << VCPU_EXREG_CPL)
6399                                   | (1 << VCPU_EXREG_PDPTR)
6400                                   | (1 << VCPU_EXREG_SEGMENTS)
6401                                   | (1 << VCPU_EXREG_CR3));
6402         vcpu->arch.regs_dirty = 0;
6403
6404         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6405
6406         if (is_guest_mode(vcpu)) {
6407                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6408                 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6409                 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6410                         vmcs12->idt_vectoring_error_code =
6411                                 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6412                         vmcs12->vm_exit_instruction_len =
6413                                 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6414                 }
6415         }
6416
6417         vmx->loaded_vmcs->launched = 1;
6418
6419         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
6420         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
6421
6422         vmx_complete_atomic_exit(vmx);
6423         vmx_recover_nmi_blocking(vmx);
6424         vmx_complete_interrupts(vmx);
6425 }
6426
6427 #undef R
6428 #undef Q
6429
6430 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6431 {
6432         struct vcpu_vmx *vmx = to_vmx(vcpu);
6433
6434         free_vpid(vmx);
6435         free_nested(vmx);
6436         free_loaded_vmcs(vmx->loaded_vmcs);
6437         kfree(vmx->guest_msrs);
6438         kvm_vcpu_uninit(vcpu);
6439         kmem_cache_free(kvm_vcpu_cache, vmx);
6440 }
6441
6442 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6443 {
6444         int err;
6445         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
6446         int cpu;
6447
6448         if (!vmx)
6449                 return ERR_PTR(-ENOMEM);
6450
6451         allocate_vpid(vmx);
6452
6453         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6454         if (err)
6455                 goto free_vcpu;
6456
6457         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
6458         err = -ENOMEM;
6459         if (!vmx->guest_msrs) {
6460                 goto uninit_vcpu;
6461         }
6462
6463         vmx->loaded_vmcs = &vmx->vmcs01;
6464         vmx->loaded_vmcs->vmcs = alloc_vmcs();
6465         if (!vmx->loaded_vmcs->vmcs)
6466                 goto free_msrs;
6467         if (!vmm_exclusive)
6468                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6469         loaded_vmcs_init(vmx->loaded_vmcs);
6470         if (!vmm_exclusive)
6471                 kvm_cpu_vmxoff();
6472
6473         cpu = get_cpu();
6474         vmx_vcpu_load(&vmx->vcpu, cpu);
6475         vmx->vcpu.cpu = cpu;
6476         err = vmx_vcpu_setup(vmx);
6477         vmx_vcpu_put(&vmx->vcpu);
6478         put_cpu();
6479         if (err)
6480                 goto free_vmcs;
6481         if (vm_need_virtualize_apic_accesses(kvm))
6482                 err = alloc_apic_access_page(kvm);
6483                 if (err)
6484                         goto free_vmcs;
6485
6486         if (enable_ept) {
6487                 if (!kvm->arch.ept_identity_map_addr)
6488                         kvm->arch.ept_identity_map_addr =
6489                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
6490                 err = -ENOMEM;
6491                 if (alloc_identity_pagetable(kvm) != 0)
6492                         goto free_vmcs;
6493                 if (!init_rmode_identity_map(kvm))
6494                         goto free_vmcs;
6495         }
6496
6497         vmx->nested.current_vmptr = -1ull;
6498         vmx->nested.current_vmcs12 = NULL;
6499
6500         return &vmx->vcpu;
6501
6502 free_vmcs:
6503         free_loaded_vmcs(vmx->loaded_vmcs);
6504 free_msrs:
6505         kfree(vmx->guest_msrs);
6506 uninit_vcpu:
6507         kvm_vcpu_uninit(&vmx->vcpu);
6508 free_vcpu:
6509         free_vpid(vmx);
6510         kmem_cache_free(kvm_vcpu_cache, vmx);
6511         return ERR_PTR(err);
6512 }
6513
6514 static void __init vmx_check_processor_compat(void *rtn)
6515 {
6516         struct vmcs_config vmcs_conf;
6517
6518         *(int *)rtn = 0;
6519         if (setup_vmcs_config(&vmcs_conf) < 0)
6520                 *(int *)rtn = -EIO;
6521         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6522                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6523                                 smp_processor_id());
6524                 *(int *)rtn = -EIO;
6525         }
6526 }
6527
6528 static int get_ept_level(void)
6529 {
6530         return VMX_EPT_DEFAULT_GAW + 1;
6531 }
6532
6533 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6534 {
6535         u64 ret;
6536
6537         /* For VT-d and EPT combination
6538          * 1. MMIO: always map as UC
6539          * 2. EPT with VT-d:
6540          *   a. VT-d without snooping control feature: can't guarantee the
6541          *      result, try to trust guest.
6542          *   b. VT-d with snooping control feature: snooping control feature of
6543          *      VT-d engine can guarantee the cache correctness. Just set it
6544          *      to WB to keep consistent with host. So the same as item 3.
6545          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6546          *    consistent with host MTRR
6547          */
6548         if (is_mmio)
6549                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
6550         else if (vcpu->kvm->arch.iommu_domain &&
6551                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6552                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6553                       VMX_EPT_MT_EPTE_SHIFT;
6554         else
6555                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
6556                         | VMX_EPT_IPAT_BIT;
6557
6558         return ret;
6559 }
6560
6561 static int vmx_get_lpage_level(void)
6562 {
6563         if (enable_ept && !cpu_has_vmx_ept_1g_page())
6564                 return PT_DIRECTORY_LEVEL;
6565         else
6566                 /* For shadow and EPT supported 1GB page */
6567                 return PT_PDPE_LEVEL;
6568 }
6569
6570 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6571 {
6572         struct kvm_cpuid_entry2 *best;
6573         struct vcpu_vmx *vmx = to_vmx(vcpu);
6574         u32 exec_control;
6575
6576         vmx->rdtscp_enabled = false;
6577         if (vmx_rdtscp_supported()) {
6578                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6579                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6580                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6581                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6582                                 vmx->rdtscp_enabled = true;
6583                         else {
6584                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6585                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6586                                                 exec_control);
6587                         }
6588                 }
6589         }
6590
6591         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6592         /* Exposing INVPCID only when PCID is exposed */
6593         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6594         if (vmx_invpcid_supported() &&
6595             best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
6596             guest_cpuid_has_pcid(vcpu)) {
6597                 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
6598                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6599                              exec_control);
6600         } else {
6601                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6602                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6603                              exec_control);
6604                 if (best)
6605                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
6606         }
6607 }
6608
6609 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6610 {
6611         if (func == 1 && nested)
6612                 entry->ecx |= bit(X86_FEATURE_VMX);
6613 }
6614
6615 /*
6616  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6617  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6618  * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6619  * guest in a way that will both be appropriate to L1's requests, and our
6620  * needs. In addition to modifying the active vmcs (which is vmcs02), this
6621  * function also has additional necessary side-effects, like setting various
6622  * vcpu->arch fields.
6623  */
6624 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6625 {
6626         struct vcpu_vmx *vmx = to_vmx(vcpu);
6627         u32 exec_control;
6628
6629         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6630         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6631         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6632         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6633         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6634         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6635         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6636         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6637         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6638         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6639         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6640         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6641         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6642         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6643         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6644         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6645         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6646         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6647         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6648         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6649         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6650         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6651         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6652         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6653         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6654         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6655         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6656         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6657         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6658         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6659         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6660         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6661         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6662         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6663         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6664         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6665
6666         vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6667         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6668                 vmcs12->vm_entry_intr_info_field);
6669         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6670                 vmcs12->vm_entry_exception_error_code);
6671         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6672                 vmcs12->vm_entry_instruction_len);
6673         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6674                 vmcs12->guest_interruptibility_info);
6675         vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6676         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6677         vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6678         vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6679         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6680                 vmcs12->guest_pending_dbg_exceptions);
6681         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6682         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6683
6684         vmcs_write64(VMCS_LINK_POINTER, -1ull);
6685
6686         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6687                 (vmcs_config.pin_based_exec_ctrl |
6688                  vmcs12->pin_based_vm_exec_control));
6689
6690         /*
6691          * Whether page-faults are trapped is determined by a combination of
6692          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6693          * If enable_ept, L0 doesn't care about page faults and we should
6694          * set all of these to L1's desires. However, if !enable_ept, L0 does
6695          * care about (at least some) page faults, and because it is not easy
6696          * (if at all possible?) to merge L0 and L1's desires, we simply ask
6697          * to exit on each and every L2 page fault. This is done by setting
6698          * MASK=MATCH=0 and (see below) EB.PF=1.
6699          * Note that below we don't need special code to set EB.PF beyond the
6700          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6701          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6702          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6703          *
6704          * A problem with this approach (when !enable_ept) is that L1 may be
6705          * injected with more page faults than it asked for. This could have
6706          * caused problems, but in practice existing hypervisors don't care.
6707          * To fix this, we will need to emulate the PFEC checking (on the L1
6708          * page tables), using walk_addr(), when injecting PFs to L1.
6709          */
6710         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6711                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6712         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6713                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6714
6715         if (cpu_has_secondary_exec_ctrls()) {
6716                 u32 exec_control = vmx_secondary_exec_control(vmx);
6717                 if (!vmx->rdtscp_enabled)
6718                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
6719                 /* Take the following fields only from vmcs12 */
6720                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6721                 if (nested_cpu_has(vmcs12,
6722                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6723                         exec_control |= vmcs12->secondary_vm_exec_control;
6724
6725                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6726                         /*
6727                          * Translate L1 physical address to host physical
6728                          * address for vmcs02. Keep the page pinned, so this
6729                          * physical address remains valid. We keep a reference
6730                          * to it so we can release it later.
6731                          */
6732                         if (vmx->nested.apic_access_page) /* shouldn't happen */
6733                                 nested_release_page(vmx->nested.apic_access_page);
6734                         vmx->nested.apic_access_page =
6735                                 nested_get_page(vcpu, vmcs12->apic_access_addr);
6736                         /*
6737                          * If translation failed, no matter: This feature asks
6738                          * to exit when accessing the given address, and if it
6739                          * can never be accessed, this feature won't do
6740                          * anything anyway.
6741                          */
6742                         if (!vmx->nested.apic_access_page)
6743                                 exec_control &=
6744                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6745                         else
6746                                 vmcs_write64(APIC_ACCESS_ADDR,
6747                                   page_to_phys(vmx->nested.apic_access_page));
6748                 }
6749
6750                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6751         }
6752
6753
6754         /*
6755          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6756          * Some constant fields are set here by vmx_set_constant_host_state().
6757          * Other fields are different per CPU, and will be set later when
6758          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6759          */
6760         vmx_set_constant_host_state();
6761
6762         /*
6763          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6764          * entry, but only if the current (host) sp changed from the value
6765          * we wrote last (vmx->host_rsp). This cache is no longer relevant
6766          * if we switch vmcs, and rather than hold a separate cache per vmcs,
6767          * here we just force the write to happen on entry.
6768          */
6769         vmx->host_rsp = 0;
6770
6771         exec_control = vmx_exec_control(vmx); /* L0's desires */
6772         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6773         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6774         exec_control &= ~CPU_BASED_TPR_SHADOW;
6775         exec_control |= vmcs12->cpu_based_vm_exec_control;
6776         /*
6777          * Merging of IO and MSR bitmaps not currently supported.
6778          * Rather, exit every time.
6779          */
6780         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6781         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6782         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6783
6784         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6785
6786         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6787          * bitwise-or of what L1 wants to trap for L2, and what we want to
6788          * trap. Note that CR0.TS also needs updating - we do this later.
6789          */
6790         update_exception_bitmap(vcpu);
6791         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6792         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6793
6794         /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6795         vmcs_write32(VM_EXIT_CONTROLS,
6796                 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6797         vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6798                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6799
6800         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6801                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6802         else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6803                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6804
6805
6806         set_cr4_guest_host_mask(vmx);
6807
6808         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
6809                 vmcs_write64(TSC_OFFSET,
6810                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6811         else
6812                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
6813
6814         if (enable_vpid) {
6815                 /*
6816                  * Trivially support vpid by letting L2s share their parent
6817                  * L1's vpid. TODO: move to a more elaborate solution, giving
6818                  * each L2 its own vpid and exposing the vpid feature to L1.
6819                  */
6820                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6821                 vmx_flush_tlb(vcpu);
6822         }
6823
6824         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6825                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6826         if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6827                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6828         else
6829                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6830         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6831         vmx_set_efer(vcpu, vcpu->arch.efer);
6832
6833         /*
6834          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6835          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6836          * The CR0_READ_SHADOW is what L2 should have expected to read given
6837          * the specifications by L1; It's not enough to take
6838          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6839          * have more bits than L1 expected.
6840          */
6841         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6842         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6843
6844         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6845         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6846
6847         /* shadow page tables on either EPT or shadow page tables */
6848         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6849         kvm_mmu_reset_context(vcpu);
6850
6851         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6852         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6853 }
6854
6855 /*
6856  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6857  * for running an L2 nested guest.
6858  */
6859 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6860 {
6861         struct vmcs12 *vmcs12;
6862         struct vcpu_vmx *vmx = to_vmx(vcpu);
6863         int cpu;
6864         struct loaded_vmcs *vmcs02;
6865
6866         if (!nested_vmx_check_permission(vcpu) ||
6867             !nested_vmx_check_vmcs12(vcpu))
6868                 return 1;
6869
6870         skip_emulated_instruction(vcpu);
6871         vmcs12 = get_vmcs12(vcpu);
6872
6873         /*
6874          * The nested entry process starts with enforcing various prerequisites
6875          * on vmcs12 as required by the Intel SDM, and act appropriately when
6876          * they fail: As the SDM explains, some conditions should cause the
6877          * instruction to fail, while others will cause the instruction to seem
6878          * to succeed, but return an EXIT_REASON_INVALID_STATE.
6879          * To speed up the normal (success) code path, we should avoid checking
6880          * for misconfigurations which will anyway be caught by the processor
6881          * when using the merged vmcs02.
6882          */
6883         if (vmcs12->launch_state == launch) {
6884                 nested_vmx_failValid(vcpu,
6885                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6886                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6887                 return 1;
6888         }
6889
6890         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6891                         !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6892                 /*TODO: Also verify bits beyond physical address width are 0*/
6893                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6894                 return 1;
6895         }
6896
6897         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6898                         !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6899                 /*TODO: Also verify bits beyond physical address width are 0*/
6900                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6901                 return 1;
6902         }
6903
6904         if (vmcs12->vm_entry_msr_load_count > 0 ||
6905             vmcs12->vm_exit_msr_load_count > 0 ||
6906             vmcs12->vm_exit_msr_store_count > 0) {
6907                 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6908                                     __func__);
6909                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6910                 return 1;
6911         }
6912
6913         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6914               nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6915             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6916               nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6917             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6918               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6919             !vmx_control_verify(vmcs12->vm_exit_controls,
6920               nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6921             !vmx_control_verify(vmcs12->vm_entry_controls,
6922               nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6923         {
6924                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6925                 return 1;
6926         }
6927
6928         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6929             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6930                 nested_vmx_failValid(vcpu,
6931                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6932                 return 1;
6933         }
6934
6935         if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6936             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6937                 nested_vmx_entry_failure(vcpu, vmcs12,
6938                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6939                 return 1;
6940         }
6941         if (vmcs12->vmcs_link_pointer != -1ull) {
6942                 nested_vmx_entry_failure(vcpu, vmcs12,
6943                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6944                 return 1;
6945         }
6946
6947         /*
6948          * We're finally done with prerequisite checking, and can start with
6949          * the nested entry.
6950          */
6951
6952         vmcs02 = nested_get_current_vmcs02(vmx);
6953         if (!vmcs02)
6954                 return -ENOMEM;
6955
6956         enter_guest_mode(vcpu);
6957
6958         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6959
6960         cpu = get_cpu();
6961         vmx->loaded_vmcs = vmcs02;
6962         vmx_vcpu_put(vcpu);
6963         vmx_vcpu_load(vcpu, cpu);
6964         vcpu->cpu = cpu;
6965         put_cpu();
6966
6967         vmcs12->launch_state = 1;
6968
6969         prepare_vmcs02(vcpu, vmcs12);
6970
6971         /*
6972          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6973          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6974          * returned as far as L1 is concerned. It will only return (and set
6975          * the success flag) when L2 exits (see nested_vmx_vmexit()).
6976          */
6977         return 1;
6978 }
6979
6980 /*
6981  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6982  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6983  * This function returns the new value we should put in vmcs12.guest_cr0.
6984  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6985  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6986  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6987  *     didn't trap the bit, because if L1 did, so would L0).
6988  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6989  *     been modified by L2, and L1 knows it. So just leave the old value of
6990  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6991  *     isn't relevant, because if L0 traps this bit it can set it to anything.
6992  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6993  *     changed these bits, and therefore they need to be updated, but L0
6994  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6995  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6996  */
6997 static inline unsigned long
6998 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6999 {
7000         return
7001         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
7002         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
7003         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
7004                         vcpu->arch.cr0_guest_owned_bits));
7005 }
7006
7007 static inline unsigned long
7008 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7009 {
7010         return
7011         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
7012         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
7013         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
7014                         vcpu->arch.cr4_guest_owned_bits));
7015 }
7016
7017 /*
7018  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
7019  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
7020  * and this function updates it to reflect the changes to the guest state while
7021  * L2 was running (and perhaps made some exits which were handled directly by L0
7022  * without going back to L1), and to reflect the exit reason.
7023  * Note that we do not have to copy here all VMCS fields, just those that
7024  * could have changed by the L2 guest or the exit - i.e., the guest-state and
7025  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7026  * which already writes to vmcs12 directly.
7027  */
7028 void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7029 {
7030         /* update guest state fields: */
7031         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
7032         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
7033
7034         kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
7035         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7036         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
7037         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
7038
7039         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
7040         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
7041         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
7042         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
7043         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
7044         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
7045         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
7046         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
7047         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
7048         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
7049         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
7050         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
7051         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
7052         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
7053         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
7054         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
7055         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
7056         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
7057         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
7058         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
7059         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
7060         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
7061         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
7062         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
7063         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
7064         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
7065         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7066         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7067         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7068         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7069         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7070         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7071         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7072         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7073         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7074         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7075
7076         vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
7077         vmcs12->guest_interruptibility_info =
7078                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7079         vmcs12->guest_pending_dbg_exceptions =
7080                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7081
7082         /* TODO: These cannot have changed unless we have MSR bitmaps and
7083          * the relevant bit asks not to trap the change */
7084         vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
7085         if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
7086                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7087         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7088         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7089         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7090
7091         /* update exit information fields: */
7092
7093         vmcs12->vm_exit_reason  = vmcs_read32(VM_EXIT_REASON);
7094         vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7095
7096         vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7097         vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
7098         vmcs12->idt_vectoring_info_field =
7099                 vmcs_read32(IDT_VECTORING_INFO_FIELD);
7100         vmcs12->idt_vectoring_error_code =
7101                 vmcs_read32(IDT_VECTORING_ERROR_CODE);
7102         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7103         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7104
7105         /* clear vm-entry fields which are to be cleared on exit */
7106         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
7107                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
7108 }
7109
7110 /*
7111  * A part of what we need to when the nested L2 guest exits and we want to
7112  * run its L1 parent, is to reset L1's guest state to the host state specified
7113  * in vmcs12.
7114  * This function is to be called not only on normal nested exit, but also on
7115  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7116  * Failures During or After Loading Guest State").
7117  * This function should be called when the active VMCS is L1's (vmcs01).
7118  */
7119 void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7120 {
7121         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7122                 vcpu->arch.efer = vmcs12->host_ia32_efer;
7123         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
7124                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7125         else
7126                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7127         vmx_set_efer(vcpu, vcpu->arch.efer);
7128
7129         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7130         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
7131         /*
7132          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7133          * actually changed, because it depends on the current state of
7134          * fpu_active (which may have changed).
7135          * Note that vmx_set_cr0 refers to efer set above.
7136          */
7137         kvm_set_cr0(vcpu, vmcs12->host_cr0);
7138         /*
7139          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7140          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7141          * but we also need to update cr0_guest_host_mask and exception_bitmap.
7142          */
7143         update_exception_bitmap(vcpu);
7144         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7145         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7146
7147         /*
7148          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7149          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7150          */
7151         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
7152         kvm_set_cr4(vcpu, vmcs12->host_cr4);
7153
7154         /* shadow page tables on either EPT or shadow page tables */
7155         kvm_set_cr3(vcpu, vmcs12->host_cr3);
7156         kvm_mmu_reset_context(vcpu);
7157
7158         if (enable_vpid) {
7159                 /*
7160                  * Trivially support vpid by letting L2s share their parent
7161                  * L1's vpid. TODO: move to a more elaborate solution, giving
7162                  * each L2 its own vpid and exposing the vpid feature to L1.
7163                  */
7164                 vmx_flush_tlb(vcpu);
7165         }
7166
7167
7168         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7169         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7170         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7171         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7172         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7173         vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7174         vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7175         vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7176         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7177         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7178         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7179         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7180         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7181         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7182         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7183
7184         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7185                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7186         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7187                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7188                         vmcs12->host_ia32_perf_global_ctrl);
7189 }
7190
7191 /*
7192  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7193  * and modify vmcs12 to make it see what it would expect to see there if
7194  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7195  */
7196 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7197 {
7198         struct vcpu_vmx *vmx = to_vmx(vcpu);
7199         int cpu;
7200         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7201
7202         leave_guest_mode(vcpu);
7203         prepare_vmcs12(vcpu, vmcs12);
7204
7205         cpu = get_cpu();
7206         vmx->loaded_vmcs = &vmx->vmcs01;
7207         vmx_vcpu_put(vcpu);
7208         vmx_vcpu_load(vcpu, cpu);
7209         vcpu->cpu = cpu;
7210         put_cpu();
7211
7212         /* if no vmcs02 cache requested, remove the one we used */
7213         if (VMCS02_POOL_SIZE == 0)
7214                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7215
7216         load_vmcs12_host_state(vcpu, vmcs12);
7217
7218         /* Update TSC_OFFSET if TSC was changed while L2 ran */
7219         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7220
7221         /* This is needed for same reason as it was needed in prepare_vmcs02 */
7222         vmx->host_rsp = 0;
7223
7224         /* Unpin physical memory we referred to in vmcs02 */
7225         if (vmx->nested.apic_access_page) {
7226                 nested_release_page(vmx->nested.apic_access_page);
7227                 vmx->nested.apic_access_page = 0;
7228         }
7229
7230         /*
7231          * Exiting from L2 to L1, we're now back to L1 which thinks it just
7232          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7233          * success or failure flag accordingly.
7234          */
7235         if (unlikely(vmx->fail)) {
7236                 vmx->fail = 0;
7237                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7238         } else
7239                 nested_vmx_succeed(vcpu);
7240 }
7241
7242 /*
7243  * L1's failure to enter L2 is a subset of a normal exit, as explained in
7244  * 23.7 "VM-entry failures during or after loading guest state" (this also
7245  * lists the acceptable exit-reason and exit-qualification parameters).
7246  * It should only be called before L2 actually succeeded to run, and when
7247  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7248  */
7249 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7250                         struct vmcs12 *vmcs12,
7251                         u32 reason, unsigned long qualification)
7252 {
7253         load_vmcs12_host_state(vcpu, vmcs12);
7254         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7255         vmcs12->exit_qualification = qualification;
7256         nested_vmx_succeed(vcpu);
7257 }
7258
7259 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7260                                struct x86_instruction_info *info,
7261                                enum x86_intercept_stage stage)
7262 {
7263         return X86EMUL_CONTINUE;
7264 }
7265
7266 static struct kvm_x86_ops vmx_x86_ops = {
7267         .cpu_has_kvm_support = cpu_has_kvm_support,
7268         .disabled_by_bios = vmx_disabled_by_bios,
7269         .hardware_setup = hardware_setup,
7270         .hardware_unsetup = hardware_unsetup,
7271         .check_processor_compatibility = vmx_check_processor_compat,
7272         .hardware_enable = hardware_enable,
7273         .hardware_disable = hardware_disable,
7274         .cpu_has_accelerated_tpr = report_flexpriority,
7275
7276         .vcpu_create = vmx_create_vcpu,
7277         .vcpu_free = vmx_free_vcpu,
7278         .vcpu_reset = vmx_vcpu_reset,
7279
7280         .prepare_guest_switch = vmx_save_host_state,
7281         .vcpu_load = vmx_vcpu_load,
7282         .vcpu_put = vmx_vcpu_put,
7283
7284         .set_guest_debug = set_guest_debug,
7285         .get_msr = vmx_get_msr,
7286         .set_msr = vmx_set_msr,
7287         .get_segment_base = vmx_get_segment_base,
7288         .get_segment = vmx_get_segment,
7289         .set_segment = vmx_set_segment,
7290         .get_cpl = vmx_get_cpl,
7291         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7292         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7293         .decache_cr3 = vmx_decache_cr3,
7294         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7295         .set_cr0 = vmx_set_cr0,
7296         .set_cr3 = vmx_set_cr3,
7297         .set_cr4 = vmx_set_cr4,
7298         .set_efer = vmx_set_efer,
7299         .get_idt = vmx_get_idt,
7300         .set_idt = vmx_set_idt,
7301         .get_gdt = vmx_get_gdt,
7302         .set_gdt = vmx_set_gdt,
7303         .set_dr7 = vmx_set_dr7,
7304         .cache_reg = vmx_cache_reg,
7305         .get_rflags = vmx_get_rflags,
7306         .set_rflags = vmx_set_rflags,
7307         .fpu_activate = vmx_fpu_activate,
7308         .fpu_deactivate = vmx_fpu_deactivate,
7309
7310         .tlb_flush = vmx_flush_tlb,
7311
7312         .run = vmx_vcpu_run,
7313         .handle_exit = vmx_handle_exit,
7314         .skip_emulated_instruction = skip_emulated_instruction,
7315         .set_interrupt_shadow = vmx_set_interrupt_shadow,
7316         .get_interrupt_shadow = vmx_get_interrupt_shadow,
7317         .patch_hypercall = vmx_patch_hypercall,
7318         .set_irq = vmx_inject_irq,
7319         .set_nmi = vmx_inject_nmi,
7320         .queue_exception = vmx_queue_exception,
7321         .cancel_injection = vmx_cancel_injection,
7322         .interrupt_allowed = vmx_interrupt_allowed,
7323         .nmi_allowed = vmx_nmi_allowed,
7324         .get_nmi_mask = vmx_get_nmi_mask,
7325         .set_nmi_mask = vmx_set_nmi_mask,
7326         .enable_nmi_window = enable_nmi_window,
7327         .enable_irq_window = enable_irq_window,
7328         .update_cr8_intercept = update_cr8_intercept,
7329
7330         .set_tss_addr = vmx_set_tss_addr,
7331         .get_tdp_level = get_ept_level,
7332         .get_mt_mask = vmx_get_mt_mask,
7333
7334         .get_exit_info = vmx_get_exit_info,
7335
7336         .get_lpage_level = vmx_get_lpage_level,
7337
7338         .cpuid_update = vmx_cpuid_update,
7339
7340         .rdtscp_supported = vmx_rdtscp_supported,
7341         .invpcid_supported = vmx_invpcid_supported,
7342
7343         .set_supported_cpuid = vmx_set_supported_cpuid,
7344
7345         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7346
7347         .set_tsc_khz = vmx_set_tsc_khz,
7348         .write_tsc_offset = vmx_write_tsc_offset,
7349         .adjust_tsc_offset = vmx_adjust_tsc_offset,
7350         .compute_tsc_offset = vmx_compute_tsc_offset,
7351         .read_l1_tsc = vmx_read_l1_tsc,
7352
7353         .set_tdp_cr3 = vmx_set_cr3,
7354
7355         .check_intercept = vmx_check_intercept,
7356 };
7357
7358 static int __init vmx_init(void)
7359 {
7360         int r, i;
7361
7362         rdmsrl_safe(MSR_EFER, &host_efer);
7363
7364         for (i = 0; i < NR_VMX_MSR; ++i)
7365                 kvm_define_shared_msr(i, vmx_msr_index[i]);
7366
7367         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
7368         if (!vmx_io_bitmap_a)
7369                 return -ENOMEM;
7370
7371         r = -ENOMEM;
7372
7373         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
7374         if (!vmx_io_bitmap_b)
7375                 goto out;
7376
7377         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
7378         if (!vmx_msr_bitmap_legacy)
7379                 goto out1;
7380
7381
7382         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
7383         if (!vmx_msr_bitmap_longmode)
7384                 goto out2;
7385
7386
7387         /*
7388          * Allow direct access to the PC debug port (it is often used for I/O
7389          * delays, but the vmexits simply slow things down).
7390          */
7391         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7392         clear_bit(0x80, vmx_io_bitmap_a);
7393
7394         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
7395
7396         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7397         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
7398
7399         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7400
7401         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7402                      __alignof__(struct vcpu_vmx), THIS_MODULE);
7403         if (r)
7404                 goto out3;
7405
7406         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7407         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7408         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7409         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7410         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7411         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
7412
7413         if (enable_ept) {
7414                 kvm_mmu_set_mask_ptes(0ull,
7415                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
7416                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
7417                         0ull, VMX_EPT_EXECUTABLE_MASK);
7418                 ept_set_mmio_spte_mask();
7419                 kvm_enable_tdp();
7420         } else
7421                 kvm_disable_tdp();
7422
7423         return 0;
7424
7425 out3:
7426         free_page((unsigned long)vmx_msr_bitmap_longmode);
7427 out2:
7428         free_page((unsigned long)vmx_msr_bitmap_legacy);
7429 out1:
7430         free_page((unsigned long)vmx_io_bitmap_b);
7431 out:
7432         free_page((unsigned long)vmx_io_bitmap_a);
7433         return r;
7434 }
7435
7436 static void __exit vmx_exit(void)
7437 {
7438         free_page((unsigned long)vmx_msr_bitmap_legacy);
7439         free_page((unsigned long)vmx_msr_bitmap_longmode);
7440         free_page((unsigned long)vmx_io_bitmap_b);
7441         free_page((unsigned long)vmx_io_bitmap_a);
7442
7443         kvm_exit();
7444 }
7445
7446 module_init(vmx_init)
7447 module_exit(vmx_exit)