arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21
  22 #include <linux/kvm_host.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/mm.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/ftrace_event.h>
  30 #include <linux/slab.h>
  31 #include <linux/tboot.h>
  32 #include "kvm_cache_regs.h"
  33 #include "x86.h"
  34
  35 #include <asm/io.h>
  36 #include <asm/desc.h>
  37 #include <asm/vmx.h>
  38 #include <asm/virtext.h>
  39 #include <asm/mce.h>
  40 #include <asm/i387.h>
  41 #include <asm/xcr.h>
  42
  43 #include "trace.h"
  44
  45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  46
  47 MODULE_AUTHOR("Qumranet");
  48 MODULE_LICENSE("GPL");
  49
  50 static int __read_mostly bypass_guest_pf = 1;
  51 module_param(bypass_guest_pf, bool, S_IRUGO);
  52
  53 static int __read_mostly enable_vpid = 1;
  54 module_param_named(vpid, enable_vpid, bool, 0444);
  55
  56 static int __read_mostly flexpriority_enabled = 1;
  57 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  58
  59 static int __read_mostly enable_ept = 1;
  60 module_param_named(ept, enable_ept, bool, S_IRUGO);
  61
  62 static int __read_mostly enable_unrestricted_guest = 1;
  63 module_param_named(unrestricted_guest,
  64                         enable_unrestricted_guest, bool, S_IRUGO);
  65
  66 static int __read_mostly emulate_invalid_guest_state = 0;
  67 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  68
  69 static int __read_mostly vmm_exclusive = 1;
  70 module_param(vmm_exclusive, bool, S_IRUGO);
  71
  72 static int __read_mostly yield_on_hlt = 1;
  73 module_param(yield_on_hlt, bool, S_IRUGO);
  74
  75 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
  76         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
  77 #define KVM_GUEST_CR0_MASK                                              \
  78         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  79 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
  80         (X86_CR0_WP | X86_CR0_NE)
  81 #define KVM_VM_CR0_ALWAYS_ON                                            \
  82         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  83 #define KVM_CR4_GUEST_OWNED_BITS                                      \
  84         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
  85          | X86_CR4_OSXMMEXCPT)
  86
  87 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
  88 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
  89
  90 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
  91
  92 /*
  93  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
  94  * ple_gap:    upper bound on the amount of time between two successive
  95  *             executions of PAUSE in a loop. Also indicate if ple enabled.
  96  *             According to test, this time is usually smaller than 128 cycles.
  97  * ple_window: upper bound on the amount of time a guest is allowed to execute
  98  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
  99  *             less than 2^12 cycles
 100  * Time is measured based on a counter that runs at the same rate as the TSC,
 101  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 102  */
 103 #define KVM_VMX_DEFAULT_PLE_GAP    128
 104 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 105 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 106 module_param(ple_gap, int, S_IRUGO);
 107
 108 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 109 module_param(ple_window, int, S_IRUGO);
 110
 111 #define NR_AUTOLOAD_MSRS 1
 112
 113 struct vmcs {
 114         u32 revision_id;
 115         u32 abort;
 116         char data[0];
 117 };
 118
 119 struct shared_msr_entry {
 120         unsigned index;
 121         u64 data;
 122         u64 mask;
 123 };
 124
 125 struct vcpu_vmx {
 126         struct kvm_vcpu       vcpu;
 127         struct list_head      local_vcpus_link;
 128         unsigned long         host_rsp;
 129         int                   launched;
 130         u8                    fail;
 131         u8                    cpl;
 132         u32                   exit_intr_info;
 133         u32                   idt_vectoring_info;
 134         ulong                 rflags;
 135         struct shared_msr_entry *guest_msrs;
 136         int                   nmsrs;
 137         int                   save_nmsrs;
 138 #ifdef CONFIG_X86_64
 139         u64                   msr_host_kernel_gs_base;
 140         u64                   msr_guest_kernel_gs_base;
 141 #endif
 142         struct vmcs          *vmcs;
 143         struct msr_autoload {
 144                 unsigned nr;
 145                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 146                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 147         } msr_autoload;
 148         struct {
 149                 int           loaded;
 150                 u16           fs_sel, gs_sel, ldt_sel;
 151                 int           gs_ldt_reload_needed;
 152                 int           fs_reload_needed;
 153         } host_state;
 154         struct {
 155                 int vm86_active;
 156                 ulong save_rflags;
 157                 struct kvm_save_segment {
 158                         u16 selector;
 159                         unsigned long base;
 160                         u32 limit;
 161                         u32 ar;
 162                 } tr, es, ds, fs, gs;
 163         } rmode;
 164         int vpid;
 165         bool emulation_required;
 166
 167         /* Support for vnmi-less CPUs */
 168         int soft_vnmi_blocked;
 169         ktime_t entry_time;
 170         s64 vnmi_blocked_time;
 171         u32 exit_reason;
 172
 173         bool rdtscp_enabled;
 174 };
 175
 176 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 177 {
 178         return container_of(vcpu, struct vcpu_vmx, vcpu);
 179 }
 180
 181 static u64 construct_eptp(unsigned long root_hpa);
 182 static void kvm_cpu_vmxon(u64 addr);
 183 static void kvm_cpu_vmxoff(void);
 184 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
 185 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 186
 187 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 188 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 189 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
 190 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 191
 192 static unsigned long *vmx_io_bitmap_a;
 193 static unsigned long *vmx_io_bitmap_b;
 194 static unsigned long *vmx_msr_bitmap_legacy;
 195 static unsigned long *vmx_msr_bitmap_longmode;
 196
 197 static bool cpu_has_load_ia32_efer;
 198
 199 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 200 static DEFINE_SPINLOCK(vmx_vpid_lock);
 201
 202 static struct vmcs_config {
 203         int size;
 204         int order;
 205         u32 revision_id;
 206         u32 pin_based_exec_ctrl;
 207         u32 cpu_based_exec_ctrl;
 208         u32 cpu_based_2nd_exec_ctrl;
 209         u32 vmexit_ctrl;
 210         u32 vmentry_ctrl;
 211 } vmcs_config;
 212
 213 static struct vmx_capability {
 214         u32 ept;
 215         u32 vpid;
 216 } vmx_capability;
 217
 218 #define VMX_SEGMENT_FIELD(seg)                                  \
 219         [VCPU_SREG_##seg] = {                                   \
 220                 .selector = GUEST_##seg##_SELECTOR,             \
 221                 .base = GUEST_##seg##_BASE,                     \
 222                 .limit = GUEST_##seg##_LIMIT,                   \
 223                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 224         }
 225
 226 static struct kvm_vmx_segment_field {
 227         unsigned selector;
 228         unsigned base;
 229         unsigned limit;
 230         unsigned ar_bytes;
 231 } kvm_vmx_segment_fields[] = {
 232         VMX_SEGMENT_FIELD(CS),
 233         VMX_SEGMENT_FIELD(DS),
 234         VMX_SEGMENT_FIELD(ES),
 235         VMX_SEGMENT_FIELD(FS),
 236         VMX_SEGMENT_FIELD(GS),
 237         VMX_SEGMENT_FIELD(SS),
 238         VMX_SEGMENT_FIELD(TR),
 239         VMX_SEGMENT_FIELD(LDTR),
 240 };
 241
 242 static u64 host_efer;
 243
 244 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 245
 246 /*
 247  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 248  * away by decrementing the array size.
 249  */
 250 static const u32 vmx_msr_index[] = {
 251 #ifdef CONFIG_X86_64
 252         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 253 #endif
 254         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 255 };
 256 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 257
 258 static inline bool is_page_fault(u32 intr_info)
 259 {
 260         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 261                              INTR_INFO_VALID_MASK)) ==
 262                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 263 }
 264
 265 static inline bool is_no_device(u32 intr_info)
 266 {
 267         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 268                              INTR_INFO_VALID_MASK)) ==
 269                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 270 }
 271
 272 static inline bool is_invalid_opcode(u32 intr_info)
 273 {
 274         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 275                              INTR_INFO_VALID_MASK)) ==
 276                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 277 }
 278
 279 static inline bool is_external_interrupt(u32 intr_info)
 280 {
 281         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 282                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 283 }
 284
 285 static inline bool is_machine_check(u32 intr_info)
 286 {
 287         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 288                              INTR_INFO_VALID_MASK)) ==
 289                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 290 }
 291
 292 static inline bool cpu_has_vmx_msr_bitmap(void)
 293 {
 294         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 295 }
 296
 297 static inline bool cpu_has_vmx_tpr_shadow(void)
 298 {
 299         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 300 }
 301
 302 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 303 {
 304         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 305 }
 306
 307 static inline bool cpu_has_secondary_exec_ctrls(void)
 308 {
 309         return vmcs_config.cpu_based_exec_ctrl &
 310                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 311 }
 312
 313 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 314 {
 315         return vmcs_config.cpu_based_2nd_exec_ctrl &
 316                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 317 }
 318
 319 static inline bool cpu_has_vmx_flexpriority(void)
 320 {
 321         return cpu_has_vmx_tpr_shadow() &&
 322                 cpu_has_vmx_virtualize_apic_accesses();
 323 }
 324
 325 static inline bool cpu_has_vmx_ept_execute_only(void)
 326 {
 327         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 328 }
 329
 330 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 331 {
 332         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 333 }
 334
 335 static inline bool cpu_has_vmx_eptp_writeback(void)
 336 {
 337         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 338 }
 339
 340 static inline bool cpu_has_vmx_ept_2m_page(void)
 341 {
 342         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 343 }
 344
 345 static inline bool cpu_has_vmx_ept_1g_page(void)
 346 {
 347         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 348 }
 349
 350 static inline bool cpu_has_vmx_ept_4levels(void)
 351 {
 352         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 353 }
 354
 355 static inline bool cpu_has_vmx_invept_individual_addr(void)
 356 {
 357         return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
 358 }
 359
 360 static inline bool cpu_has_vmx_invept_context(void)
 361 {
 362         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 363 }
 364
 365 static inline bool cpu_has_vmx_invept_global(void)
 366 {
 367         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 368 }
 369
 370 static inline bool cpu_has_vmx_invvpid_single(void)
 371 {
 372         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 373 }
 374
 375 static inline bool cpu_has_vmx_invvpid_global(void)
 376 {
 377         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 378 }
 379
 380 static inline bool cpu_has_vmx_ept(void)
 381 {
 382         return vmcs_config.cpu_based_2nd_exec_ctrl &
 383                 SECONDARY_EXEC_ENABLE_EPT;
 384 }
 385
 386 static inline bool cpu_has_vmx_unrestricted_guest(void)
 387 {
 388         return vmcs_config.cpu_based_2nd_exec_ctrl &
 389                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 390 }
 391
 392 static inline bool cpu_has_vmx_ple(void)
 393 {
 394         return vmcs_config.cpu_based_2nd_exec_ctrl &
 395                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 396 }
 397
 398 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 399 {
 400         return flexpriority_enabled && irqchip_in_kernel(kvm);
 401 }
 402
 403 static inline bool cpu_has_vmx_vpid(void)
 404 {
 405         return vmcs_config.cpu_based_2nd_exec_ctrl &
 406                 SECONDARY_EXEC_ENABLE_VPID;
 407 }
 408
 409 static inline bool cpu_has_vmx_rdtscp(void)
 410 {
 411         return vmcs_config.cpu_based_2nd_exec_ctrl &
 412                 SECONDARY_EXEC_RDTSCP;
 413 }
 414
 415 static inline bool cpu_has_virtual_nmis(void)
 416 {
 417         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 418 }
 419
 420 static inline bool cpu_has_vmx_wbinvd_exit(void)
 421 {
 422         return vmcs_config.cpu_based_2nd_exec_ctrl &
 423                 SECONDARY_EXEC_WBINVD_EXITING;
 424 }
 425
 426 static inline bool report_flexpriority(void)
 427 {
 428         return flexpriority_enabled;
 429 }
 430
 431 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 432 {
 433         int i;
 434
 435         for (i = 0; i < vmx->nmsrs; ++i)
 436                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 437                         return i;
 438         return -1;
 439 }
 440
 441 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 442 {
 443     struct {
 444         u64 vpid : 16;
 445         u64 rsvd : 48;
 446         u64 gva;
 447     } operand = { vpid, 0, gva };
 448
 449     asm volatile (__ex(ASM_VMX_INVVPID)
 450                   /* CF==1 or ZF==1 --> rc = -1 */
 451                   "; ja 1f ; ud2 ; 1:"
 452                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 453 }
 454
 455 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 456 {
 457         struct {
 458                 u64 eptp, gpa;
 459         } operand = {eptp, gpa};
 460
 461         asm volatile (__ex(ASM_VMX_INVEPT)
 462                         /* CF==1 or ZF==1 --> rc = -1 */
 463                         "; ja 1f ; ud2 ; 1:\n"
 464                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 465 }
 466
 467 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 468 {
 469         int i;
 470
 471         i = __find_msr_index(vmx, msr);
 472         if (i >= 0)
 473                 return &vmx->guest_msrs[i];
 474         return NULL;
 475 }
 476
 477 static void vmcs_clear(struct vmcs *vmcs)
 478 {
 479         u64 phys_addr = __pa(vmcs);
 480         u8 error;
 481
 482         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 483                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 484                       : "cc", "memory");
 485         if (error)
 486                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 487                        vmcs, phys_addr);
 488 }
 489
 490 static void vmcs_load(struct vmcs *vmcs)
 491 {
 492         u64 phys_addr = __pa(vmcs);
 493         u8 error;
 494
 495         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 496                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 497                         : "cc", "memory");
 498         if (error)
 499                 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 500                        vmcs, phys_addr);
 501 }
 502
 503 static void __vcpu_clear(void *arg)
 504 {
 505         struct vcpu_vmx *vmx = arg;
 506         int cpu = raw_smp_processor_id();
 507
 508         if (vmx->vcpu.cpu == cpu)
 509                 vmcs_clear(vmx->vmcs);
 510         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 511                 per_cpu(current_vmcs, cpu) = NULL;
 512         list_del(&vmx->local_vcpus_link);
 513         vmx->vcpu.cpu = -1;
 514         vmx->launched = 0;
 515 }
 516
 517 static void vcpu_clear(struct vcpu_vmx *vmx)
 518 {
 519         if (vmx->vcpu.cpu == -1)
 520                 return;
 521         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
 522 }
 523
 524 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
 525 {
 526         if (vmx->vpid == 0)
 527                 return;
 528
 529         if (cpu_has_vmx_invvpid_single())
 530                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 531 }
 532
 533 static inline void vpid_sync_vcpu_global(void)
 534 {
 535         if (cpu_has_vmx_invvpid_global())
 536                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
 537 }
 538
 539 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
 540 {
 541         if (cpu_has_vmx_invvpid_single())
 542                 vpid_sync_vcpu_single(vmx);
 543         else
 544                 vpid_sync_vcpu_global();
 545 }
 546
 547 static inline void ept_sync_global(void)
 548 {
 549         if (cpu_has_vmx_invept_global())
 550                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 551 }
 552
 553 static inline void ept_sync_context(u64 eptp)
 554 {
 555         if (enable_ept) {
 556                 if (cpu_has_vmx_invept_context())
 557                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
 558                 else
 559                         ept_sync_global();
 560         }
 561 }
 562
 563 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
 564 {
 565         if (enable_ept) {
 566                 if (cpu_has_vmx_invept_individual_addr())
 567                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
 568                                         eptp, gpa);
 569                 else
 570                         ept_sync_context(eptp);
 571         }
 572 }
 573
 574 static unsigned long vmcs_readl(unsigned long field)
 575 {
 576         unsigned long value = 0;
 577
 578         asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
 579                       : "+a"(value) : "d"(field) : "cc");
 580         return value;
 581 }
 582
 583 static u16 vmcs_read16(unsigned long field)
 584 {
 585         return vmcs_readl(field);
 586 }
 587
 588 static u32 vmcs_read32(unsigned long field)
 589 {
 590         return vmcs_readl(field);
 591 }
 592
 593 static u64 vmcs_read64(unsigned long field)
 594 {
 595 #ifdef CONFIG_X86_64
 596         return vmcs_readl(field);
 597 #else
 598         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 599 #endif
 600 }
 601
 602 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 603 {
 604         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 605                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 606         dump_stack();
 607 }
 608
 609 static void vmcs_writel(unsigned long field, unsigned long value)
 610 {
 611         u8 error;
 612
 613         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
 614                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 615         if (unlikely(error))
 616                 vmwrite_error(field, value);
 617 }
 618
 619 static void vmcs_write16(unsigned long field, u16 value)
 620 {
 621         vmcs_writel(field, value);
 622 }
 623
 624 static void vmcs_write32(unsigned long field, u32 value)
 625 {
 626         vmcs_writel(field, value);
 627 }
 628
 629 static void vmcs_write64(unsigned long field, u64 value)
 630 {
 631         vmcs_writel(field, value);
 632 #ifndef CONFIG_X86_64
 633         asm volatile ("");
 634         vmcs_writel(field+1, value >> 32);
 635 #endif
 636 }
 637
 638 static void vmcs_clear_bits(unsigned long field, u32 mask)
 639 {
 640         vmcs_writel(field, vmcs_readl(field) & ~mask);
 641 }
 642
 643 static void vmcs_set_bits(unsigned long field, u32 mask)
 644 {
 645         vmcs_writel(field, vmcs_readl(field) | mask);
 646 }
 647
 648 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 649 {
 650         u32 eb;
 651
 652         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
 653              (1u << NM_VECTOR) | (1u << DB_VECTOR);
 654         if ((vcpu->guest_debug &
 655              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
 656             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
 657                 eb |= 1u << BP_VECTOR;
 658         if (to_vmx(vcpu)->rmode.vm86_active)
 659                 eb = ~0;
 660         if (enable_ept)
 661                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 662         if (vcpu->fpu_active)
 663                 eb &= ~(1u << NM_VECTOR);
 664         vmcs_write32(EXCEPTION_BITMAP, eb);
 665 }
 666
 667 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
 668 {
 669         unsigned i;
 670         struct msr_autoload *m = &vmx->msr_autoload;
 671
 672         if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
 673                 vmcs_clear_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
 674                 vmcs_clear_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
 675                 return;
 676         }
 677
 678         for (i = 0; i < m->nr; ++i)
 679                 if (m->guest[i].index == msr)
 680                         break;
 681
 682         if (i == m->nr)
 683                 return;
 684         --m->nr;
 685         m->guest[i] = m->guest[m->nr];
 686         m->host[i] = m->host[m->nr];
 687         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
 688         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
 689 }
 690
 691 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
 692                                   u64 guest_val, u64 host_val)
 693 {
 694         unsigned i;
 695         struct msr_autoload *m = &vmx->msr_autoload;
 696
 697         if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
 698                 vmcs_write64(GUEST_IA32_EFER, guest_val);
 699                 vmcs_write64(HOST_IA32_EFER, host_val);
 700                 vmcs_set_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
 701                 vmcs_set_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
 702                 return;
 703         }
 704
 705         for (i = 0; i < m->nr; ++i)
 706                 if (m->guest[i].index == msr)
 707                         break;
 708
 709         if (i == m->nr) {
 710                 ++m->nr;
 711                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
 712                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
 713         }
 714
 715         m->guest[i].index = msr;
 716         m->guest[i].value = guest_val;
 717         m->host[i].index = msr;
 718         m->host[i].value = host_val;
 719 }
 720
 721 static void reload_tss(void)
 722 {
 723         /*
 724          * VT restores TR but not its size.  Useless.
 725          */
 726         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
 727         struct desc_struct *descs;
 728
 729         descs = (void *)gdt->address;
 730         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 731         load_TR_desc();
 732 }
 733
 734 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
 735 {
 736         u64 guest_efer;
 737         u64 ignore_bits;
 738
 739         guest_efer = vmx->vcpu.arch.efer;
 740
 741         /*
 742          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 743          * outside long mode
 744          */
 745         ignore_bits = EFER_NX | EFER_SCE;
 746 #ifdef CONFIG_X86_64
 747         ignore_bits |= EFER_LMA | EFER_LME;
 748         /* SCE is meaningful only in long mode on Intel */
 749         if (guest_efer & EFER_LMA)
 750                 ignore_bits &= ~(u64)EFER_SCE;
 751 #endif
 752         guest_efer &= ~ignore_bits;
 753         guest_efer |= host_efer & ignore_bits;
 754         vmx->guest_msrs[efer_offset].data = guest_efer;
 755         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
 756
 757         clear_atomic_switch_msr(vmx, MSR_EFER);
 758         /* On ept, can't emulate nx, and must switch nx atomically */
 759         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
 760                 guest_efer = vmx->vcpu.arch.efer;
 761                 if (!(guest_efer & EFER_LMA))
 762                         guest_efer &= ~EFER_LME;
 763                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
 764                 return false;
 765         }
 766
 767         return true;
 768 }
 769
 770 static unsigned long segment_base(u16 selector)
 771 {
 772         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
 773         struct desc_struct *d;
 774         unsigned long table_base;
 775         unsigned long v;
 776
 777         if (!(selector & ~3))
 778                 return 0;
 779
 780         table_base = gdt->address;
 781
 782         if (selector & 4) {           /* from ldt */
 783                 u16 ldt_selector = kvm_read_ldt();
 784
 785                 if (!(ldt_selector & ~3))
 786                         return 0;
 787
 788                 table_base = segment_base(ldt_selector);
 789         }
 790         d = (struct desc_struct *)(table_base + (selector & ~7));
 791         v = get_desc_base(d);
 792 #ifdef CONFIG_X86_64
 793        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
 794                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
 795 #endif
 796         return v;
 797 }
 798
 799 static inline unsigned long kvm_read_tr_base(void)
 800 {
 801         u16 tr;
 802         asm("str %0" : "=g"(tr));
 803         return segment_base(tr);
 804 }
 805
 806 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 807 {
 808         struct vcpu_vmx *vmx = to_vmx(vcpu);
 809         int i;
 810
 811         if (vmx->host_state.loaded)
 812                 return;
 813
 814         vmx->host_state.loaded = 1;
 815         /*
 816          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 817          * allow segment selectors with cpl > 0 or ti == 1.
 818          */
 819         vmx->host_state.ldt_sel = kvm_read_ldt();
 820         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 821         savesegment(fs, vmx->host_state.fs_sel);
 822         if (!(vmx->host_state.fs_sel & 7)) {
 823                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 824                 vmx->host_state.fs_reload_needed = 0;
 825         } else {
 826                 vmcs_write16(HOST_FS_SELECTOR, 0);
 827                 vmx->host_state.fs_reload_needed = 1;
 828         }
 829         savesegment(gs, vmx->host_state.gs_sel);
 830         if (!(vmx->host_state.gs_sel & 7))
 831                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 832         else {
 833                 vmcs_write16(HOST_GS_SELECTOR, 0);
 834                 vmx->host_state.gs_ldt_reload_needed = 1;
 835         }
 836
 837 #ifdef CONFIG_X86_64
 838         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 839         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 840 #else
 841         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 842         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 843 #endif
 844
 845 #ifdef CONFIG_X86_64
 846         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 847         if (is_long_mode(&vmx->vcpu))
 848                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 849 #endif
 850         for (i = 0; i < vmx->save_nmsrs; ++i)
 851                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
 852                                    vmx->guest_msrs[i].data,
 853                                    vmx->guest_msrs[i].mask);
 854 }
 855
 856 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
 857 {
 858         if (!vmx->host_state.loaded)
 859                 return;
 860
 861         ++vmx->vcpu.stat.host_state_reload;
 862         vmx->host_state.loaded = 0;
 863 #ifdef CONFIG_X86_64
 864         if (is_long_mode(&vmx->vcpu))
 865                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 866 #endif
 867         if (vmx->host_state.gs_ldt_reload_needed) {
 868                 kvm_load_ldt(vmx->host_state.ldt_sel);
 869 #ifdef CONFIG_X86_64
 870                 load_gs_index(vmx->host_state.gs_sel);
 871 #else
 872                 loadsegment(gs, vmx->host_state.gs_sel);
 873 #endif
 874         }
 875         if (vmx->host_state.fs_reload_needed)
 876                 loadsegment(fs, vmx->host_state.fs_sel);
 877         reload_tss();
 878 #ifdef CONFIG_X86_64
 879         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 880 #endif
 881         if (current_thread_info()->status & TS_USEDFPU)
 882                 clts();
 883         load_gdt(&__get_cpu_var(host_gdt));
 884 }
 885
 886 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 887 {
 888         preempt_disable();
 889         __vmx_load_host_state(vmx);
 890         preempt_enable();
 891 }
 892
 893 /*
 894  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 895  * vcpu mutex is already taken.
 896  */
 897 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 898 {
 899         struct vcpu_vmx *vmx = to_vmx(vcpu);
 900         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
 901
 902         if (!vmm_exclusive)
 903                 kvm_cpu_vmxon(phys_addr);
 904         else if (vcpu->cpu != cpu)
 905                 vcpu_clear(vmx);
 906
 907         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 908                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 909                 vmcs_load(vmx->vmcs);
 910         }
 911
 912         if (vcpu->cpu != cpu) {
 913                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
 914                 unsigned long sysenter_esp;
 915
 916                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
 917                 local_irq_disable();
 918                 list_add(&vmx->local_vcpus_link,
 919                          &per_cpu(vcpus_on_cpu, cpu));
 920                 local_irq_enable();
 921
 922                 /*
 923                  * Linux uses per-cpu TSS and GDT, so set these when switching
 924                  * processors.
 925                  */
 926                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
 927                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
 928
 929                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 930                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 931         }
 932 }
 933
 934 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 935 {
 936         __vmx_load_host_state(to_vmx(vcpu));
 937         if (!vmm_exclusive) {
 938                 __vcpu_clear(to_vmx(vcpu));
 939                 kvm_cpu_vmxoff();
 940         }
 941 }
 942
 943 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 944 {
 945         ulong cr0;
 946
 947         if (vcpu->fpu_active)
 948                 return;
 949         vcpu->fpu_active = 1;
 950         cr0 = vmcs_readl(GUEST_CR0);
 951         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
 952         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
 953         vmcs_writel(GUEST_CR0, cr0);
 954         update_exception_bitmap(vcpu);
 955         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
 956         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
 957 }
 958
 959 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
 960
 961 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 962 {
 963         vmx_decache_cr0_guest_bits(vcpu);
 964         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
 965         update_exception_bitmap(vcpu);
 966         vcpu->arch.cr0_guest_owned_bits = 0;
 967         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
 968         vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
 969 }
 970
 971 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 972 {
 973         unsigned long rflags, save_rflags;
 974
 975         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
 976                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
 977                 rflags = vmcs_readl(GUEST_RFLAGS);
 978                 if (to_vmx(vcpu)->rmode.vm86_active) {
 979                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
 980                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
 981                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
 982                 }
 983                 to_vmx(vcpu)->rflags = rflags;
 984         }
 985         return to_vmx(vcpu)->rflags;
 986 }
 987
 988 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 989 {
 990         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
 991         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
 992         to_vmx(vcpu)->rflags = rflags;
 993         if (to_vmx(vcpu)->rmode.vm86_active) {
 994                 to_vmx(vcpu)->rmode.save_rflags = rflags;
 995                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 996         }
 997         vmcs_writel(GUEST_RFLAGS, rflags);
 998 }
 999
1000 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1001 {
1002         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1003         int ret = 0;
1004
1005         if (interruptibility & GUEST_INTR_STATE_STI)
1006                 ret |= KVM_X86_SHADOW_INT_STI;
1007         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1008                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1009
1010         return ret & mask;
1011 }
1012
1013 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1014 {
1015         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1016         u32 interruptibility = interruptibility_old;
1017
1018         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1019
1020         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1021                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1022         else if (mask & KVM_X86_SHADOW_INT_STI)
1023                 interruptibility |= GUEST_INTR_STATE_STI;
1024
1025         if ((interruptibility != interruptibility_old))
1026                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1027 }
1028
1029 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1030 {
1031         unsigned long rip;
1032
1033         rip = kvm_rip_read(vcpu);
1034         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1035         kvm_rip_write(vcpu, rip);
1036
1037         /* skipping an emulated instruction also counts */
1038         vmx_set_interrupt_shadow(vcpu, 0);
1039 }
1040
1041 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1042 {
1043         /* Ensure that we clear the HLT state in the VMCS.  We don't need to
1044          * explicitly skip the instruction because if the HLT state is set, then
1045          * the instruction is already executing and RIP has already been
1046          * advanced. */
1047         if (!yield_on_hlt &&
1048             vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1049                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1050 }
1051
1052 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1053                                 bool has_error_code, u32 error_code,
1054                                 bool reinject)
1055 {
1056         struct vcpu_vmx *vmx = to_vmx(vcpu);
1057         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1058
1059         if (has_error_code) {
1060                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1061                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1062         }
1063
1064         if (vmx->rmode.vm86_active) {
1065                 if (kvm_inject_realmode_interrupt(vcpu, nr) != EMULATE_DONE)
1066                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1067                 return;
1068         }
1069
1070         if (kvm_exception_is_soft(nr)) {
1071                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1072                              vmx->vcpu.arch.event_exit_inst_len);
1073                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1074         } else
1075                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1076
1077         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1078         vmx_clear_hlt(vcpu);
1079 }
1080
1081 static bool vmx_rdtscp_supported(void)
1082 {
1083         return cpu_has_vmx_rdtscp();
1084 }
1085
1086 /*
1087  * Swap MSR entry in host/guest MSR entry array.
1088  */
1089 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1090 {
1091         struct shared_msr_entry tmp;
1092
1093         tmp = vmx->guest_msrs[to];
1094         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1095         vmx->guest_msrs[from] = tmp;
1096 }
1097
1098 /*
1099  * Set up the vmcs to automatically save and restore system
1100  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1101  * mode, as fiddling with msrs is very expensive.
1102  */
1103 static void setup_msrs(struct vcpu_vmx *vmx)
1104 {
1105         int save_nmsrs, index;
1106         unsigned long *msr_bitmap;
1107
1108         vmx_load_host_state(vmx);
1109         save_nmsrs = 0;
1110 #ifdef CONFIG_X86_64
1111         if (is_long_mode(&vmx->vcpu)) {
1112                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1113                 if (index >= 0)
1114                         move_msr_up(vmx, index, save_nmsrs++);
1115                 index = __find_msr_index(vmx, MSR_LSTAR);
1116                 if (index >= 0)
1117                         move_msr_up(vmx, index, save_nmsrs++);
1118                 index = __find_msr_index(vmx, MSR_CSTAR);
1119                 if (index >= 0)
1120                         move_msr_up(vmx, index, save_nmsrs++);
1121                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1122                 if (index >= 0 && vmx->rdtscp_enabled)
1123                         move_msr_up(vmx, index, save_nmsrs++);
1124                 /*
1125                  * MSR_STAR is only needed on long mode guests, and only
1126                  * if efer.sce is enabled.
1127                  */
1128                 index = __find_msr_index(vmx, MSR_STAR);
1129                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1130                         move_msr_up(vmx, index, save_nmsrs++);
1131         }
1132 #endif
1133         index = __find_msr_index(vmx, MSR_EFER);
1134         if (index >= 0 && update_transition_efer(vmx, index))
1135                 move_msr_up(vmx, index, save_nmsrs++);
1136
1137         vmx->save_nmsrs = save_nmsrs;
1138
1139         if (cpu_has_vmx_msr_bitmap()) {
1140                 if (is_long_mode(&vmx->vcpu))
1141                         msr_bitmap = vmx_msr_bitmap_longmode;
1142                 else
1143                         msr_bitmap = vmx_msr_bitmap_legacy;
1144
1145                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1146         }
1147 }
1148
1149 /*
1150  * reads and returns guest's timestamp counter "register"
1151  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1152  */
1153 static u64 guest_read_tsc(void)
1154 {
1155         u64 host_tsc, tsc_offset;
1156
1157         rdtscll(host_tsc);
1158         tsc_offset = vmcs_read64(TSC_OFFSET);
1159         return host_tsc + tsc_offset;
1160 }
1161
1162 /*
1163  * writes 'offset' into guest's timestamp counter offset register
1164  */
1165 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1166 {
1167         vmcs_write64(TSC_OFFSET, offset);
1168 }
1169
1170 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1171 {
1172         u64 offset = vmcs_read64(TSC_OFFSET);
1173         vmcs_write64(TSC_OFFSET, offset + adjustment);
1174 }
1175
1176 /*
1177  * Reads an msr value (of 'msr_index') into 'pdata'.
1178  * Returns 0 on success, non-0 otherwise.
1179  * Assumes vcpu_load() was already called.
1180  */
1181 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1182 {
1183         u64 data;
1184         struct shared_msr_entry *msr;
1185
1186         if (!pdata) {
1187                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1188                 return -EINVAL;
1189         }
1190
1191         switch (msr_index) {
1192 #ifdef CONFIG_X86_64
1193         case MSR_FS_BASE:
1194                 data = vmcs_readl(GUEST_FS_BASE);
1195                 break;
1196         case MSR_GS_BASE:
1197                 data = vmcs_readl(GUEST_GS_BASE);
1198                 break;
1199         case MSR_KERNEL_GS_BASE:
1200                 vmx_load_host_state(to_vmx(vcpu));
1201                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1202                 break;
1203 #endif
1204         case MSR_EFER:
1205                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1206         case MSR_IA32_TSC:
1207                 data = guest_read_tsc();
1208                 break;
1209         case MSR_IA32_SYSENTER_CS:
1210                 data = vmcs_read32(GUEST_SYSENTER_CS);
1211                 break;
1212         case MSR_IA32_SYSENTER_EIP:
1213                 data = vmcs_readl(GUEST_SYSENTER_EIP);
1214                 break;
1215         case MSR_IA32_SYSENTER_ESP:
1216                 data = vmcs_readl(GUEST_SYSENTER_ESP);
1217                 break;
1218         case MSR_TSC_AUX:
1219                 if (!to_vmx(vcpu)->rdtscp_enabled)
1220                         return 1;
1221                 /* Otherwise falls through */
1222         default:
1223                 vmx_load_host_state(to_vmx(vcpu));
1224                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1225                 if (msr) {
1226                         vmx_load_host_state(to_vmx(vcpu));
1227                         data = msr->data;
1228                         break;
1229                 }
1230                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1231         }
1232
1233         *pdata = data;
1234         return 0;
1235 }
1236
1237 /*
1238  * Writes msr value into into the appropriate "register".
1239  * Returns 0 on success, non-0 otherwise.
1240  * Assumes vcpu_load() was already called.
1241  */
1242 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1243 {
1244         struct vcpu_vmx *vmx = to_vmx(vcpu);
1245         struct shared_msr_entry *msr;
1246         int ret = 0;
1247
1248         switch (msr_index) {
1249         case MSR_EFER:
1250                 vmx_load_host_state(vmx);
1251                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1252                 break;
1253 #ifdef CONFIG_X86_64
1254         case MSR_FS_BASE:
1255                 vmcs_writel(GUEST_FS_BASE, data);
1256                 break;
1257         case MSR_GS_BASE:
1258                 vmcs_writel(GUEST_GS_BASE, data);
1259                 break;
1260         case MSR_KERNEL_GS_BASE:
1261                 vmx_load_host_state(vmx);
1262                 vmx->msr_guest_kernel_gs_base = data;
1263                 break;
1264 #endif
1265         case MSR_IA32_SYSENTER_CS:
1266                 vmcs_write32(GUEST_SYSENTER_CS, data);
1267                 break;
1268         case MSR_IA32_SYSENTER_EIP:
1269                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1270                 break;
1271         case MSR_IA32_SYSENTER_ESP:
1272                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1273                 break;
1274         case MSR_IA32_TSC:
1275                 kvm_write_tsc(vcpu, data);
1276                 break;
1277         case MSR_IA32_CR_PAT:
1278                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1279                         vmcs_write64(GUEST_IA32_PAT, data);
1280                         vcpu->arch.pat = data;
1281                         break;
1282                 }
1283                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1284                 break;
1285         case MSR_TSC_AUX:
1286                 if (!vmx->rdtscp_enabled)
1287                         return 1;
1288                 /* Check reserved bit, higher 32 bits should be zero */
1289                 if ((data >> 32) != 0)
1290                         return 1;
1291                 /* Otherwise falls through */
1292         default:
1293                 msr = find_msr_entry(vmx, msr_index);
1294                 if (msr) {
1295                         vmx_load_host_state(vmx);
1296                         msr->data = data;
1297                         break;
1298                 }
1299                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1300         }
1301
1302         return ret;
1303 }
1304
1305 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1306 {
1307         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1308         switch (reg) {
1309         case VCPU_REGS_RSP:
1310                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1311                 break;
1312         case VCPU_REGS_RIP:
1313                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1314                 break;
1315         case VCPU_EXREG_PDPTR:
1316                 if (enable_ept)
1317                         ept_save_pdptrs(vcpu);
1318                 break;
1319         default:
1320                 break;
1321         }
1322 }
1323
1324 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1325 {
1326         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1327                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1328         else
1329                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1330
1331         update_exception_bitmap(vcpu);
1332 }
1333
1334 static __init int cpu_has_kvm_support(void)
1335 {
1336         return cpu_has_vmx();
1337 }
1338
1339 static __init int vmx_disabled_by_bios(void)
1340 {
1341         u64 msr;
1342
1343         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1344         if (msr & FEATURE_CONTROL_LOCKED) {
1345                 /* launched w/ TXT and VMX disabled */
1346                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1347                         && tboot_enabled())
1348                         return 1;
1349                 /* launched w/o TXT and VMX only enabled w/ TXT */
1350                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1351                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1352                         && !tboot_enabled()) {
1353                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
1354                                 "activate TXT before enabling KVM\n");
1355                         return 1;
1356                 }
1357                 /* launched w/o TXT and VMX disabled */
1358                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1359                         && !tboot_enabled())
1360                         return 1;
1361         }
1362
1363         return 0;
1364 }
1365
1366 static void kvm_cpu_vmxon(u64 addr)
1367 {
1368         asm volatile (ASM_VMX_VMXON_RAX
1369                         : : "a"(&addr), "m"(addr)
1370                         : "memory", "cc");
1371 }
1372
1373 static int hardware_enable(void *garbage)
1374 {
1375         int cpu = raw_smp_processor_id();
1376         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1377         u64 old, test_bits;
1378
1379         if (read_cr4() & X86_CR4_VMXE)
1380                 return -EBUSY;
1381
1382         INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1383         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1384
1385         test_bits = FEATURE_CONTROL_LOCKED;
1386         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1387         if (tboot_enabled())
1388                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1389
1390         if ((old & test_bits) != test_bits) {
1391                 /* enable and lock */
1392                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1393         }
1394         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1395
1396         if (vmm_exclusive) {
1397                 kvm_cpu_vmxon(phys_addr);
1398                 ept_sync_global();
1399         }
1400
1401         store_gdt(&__get_cpu_var(host_gdt));
1402
1403         return 0;
1404 }
1405
1406 static void vmclear_local_vcpus(void)
1407 {
1408         int cpu = raw_smp_processor_id();
1409         struct vcpu_vmx *vmx, *n;
1410
1411         list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1412                                  local_vcpus_link)
1413                 __vcpu_clear(vmx);
1414 }
1415
1416
1417 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1418  * tricks.
1419  */
1420 static void kvm_cpu_vmxoff(void)
1421 {
1422         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1423 }
1424
1425 static void hardware_disable(void *garbage)
1426 {
1427         if (vmm_exclusive) {
1428                 vmclear_local_vcpus();
1429                 kvm_cpu_vmxoff();
1430         }
1431         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1432 }
1433
1434 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1435                                       u32 msr, u32 *result)
1436 {
1437         u32 vmx_msr_low, vmx_msr_high;
1438         u32 ctl = ctl_min | ctl_opt;
1439
1440         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1441
1442         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1443         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1444
1445         /* Ensure minimum (required) set of control bits are supported. */
1446         if (ctl_min & ~ctl)
1447                 return -EIO;
1448
1449         *result = ctl;
1450         return 0;
1451 }
1452
1453 static __init bool allow_1_setting(u32 msr, u32 ctl)
1454 {
1455         u32 vmx_msr_low, vmx_msr_high;
1456
1457         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1458         return vmx_msr_high & ctl;
1459 }
1460
1461 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1462 {
1463         u32 vmx_msr_low, vmx_msr_high;
1464         u32 min, opt, min2, opt2;
1465         u32 _pin_based_exec_control = 0;
1466         u32 _cpu_based_exec_control = 0;
1467         u32 _cpu_based_2nd_exec_control = 0;
1468         u32 _vmexit_control = 0;
1469         u32 _vmentry_control = 0;
1470
1471         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1472         opt = PIN_BASED_VIRTUAL_NMIS;
1473         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1474                                 &_pin_based_exec_control) < 0)
1475                 return -EIO;
1476
1477         min =
1478 #ifdef CONFIG_X86_64
1479               CPU_BASED_CR8_LOAD_EXITING |
1480               CPU_BASED_CR8_STORE_EXITING |
1481 #endif
1482               CPU_BASED_CR3_LOAD_EXITING |
1483               CPU_BASED_CR3_STORE_EXITING |
1484               CPU_BASED_USE_IO_BITMAPS |
1485               CPU_BASED_MOV_DR_EXITING |
1486               CPU_BASED_USE_TSC_OFFSETING |
1487               CPU_BASED_MWAIT_EXITING |
1488               CPU_BASED_MONITOR_EXITING |
1489               CPU_BASED_INVLPG_EXITING;
1490
1491         if (yield_on_hlt)
1492                 min |= CPU_BASED_HLT_EXITING;
1493
1494         opt = CPU_BASED_TPR_SHADOW |
1495               CPU_BASED_USE_MSR_BITMAPS |
1496               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1497         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1498                                 &_cpu_based_exec_control) < 0)
1499                 return -EIO;
1500 #ifdef CONFIG_X86_64
1501         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1502                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1503                                            ~CPU_BASED_CR8_STORE_EXITING;
1504 #endif
1505         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1506                 min2 = 0;
1507                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1508                         SECONDARY_EXEC_WBINVD_EXITING |
1509                         SECONDARY_EXEC_ENABLE_VPID |
1510                         SECONDARY_EXEC_ENABLE_EPT |
1511                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
1512                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1513                         SECONDARY_EXEC_RDTSCP;
1514                 if (adjust_vmx_controls(min2, opt2,
1515                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1516                                         &_cpu_based_2nd_exec_control) < 0)
1517                         return -EIO;
1518         }
1519 #ifndef CONFIG_X86_64
1520         if (!(_cpu_based_2nd_exec_control &
1521                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1522                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1523 #endif
1524         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1525                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1526                    enabled */
1527                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1528                                              CPU_BASED_CR3_STORE_EXITING |
1529                                              CPU_BASED_INVLPG_EXITING);
1530                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1531                       vmx_capability.ept, vmx_capability.vpid);
1532         }
1533
1534         min = 0;
1535 #ifdef CONFIG_X86_64
1536         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1537 #endif
1538         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1539         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1540                                 &_vmexit_control) < 0)
1541                 return -EIO;
1542
1543         min = 0;
1544         opt = VM_ENTRY_LOAD_IA32_PAT;
1545         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1546                                 &_vmentry_control) < 0)
1547                 return -EIO;
1548
1549         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1550
1551         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1552         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1553                 return -EIO;
1554
1555 #ifdef CONFIG_X86_64
1556         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1557         if (vmx_msr_high & (1u<<16))
1558                 return -EIO;
1559 #endif
1560
1561         /* Require Write-Back (WB) memory type for VMCS accesses. */
1562         if (((vmx_msr_high >> 18) & 15) != 6)
1563                 return -EIO;
1564
1565         vmcs_conf->size = vmx_msr_high & 0x1fff;
1566         vmcs_conf->order = get_order(vmcs_config.size);
1567         vmcs_conf->revision_id = vmx_msr_low;
1568
1569         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1570         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1571         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1572         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1573         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1574
1575         cpu_has_load_ia32_efer =
1576                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
1577                                 VM_ENTRY_LOAD_IA32_EFER)
1578                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
1579                                    VM_EXIT_LOAD_IA32_EFER);
1580
1581         return 0;
1582 }
1583
1584 static struct vmcs *alloc_vmcs_cpu(int cpu)
1585 {
1586         int node = cpu_to_node(cpu);
1587         struct page *pages;
1588         struct vmcs *vmcs;
1589
1590         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1591         if (!pages)
1592                 return NULL;
1593         vmcs = page_address(pages);
1594         memset(vmcs, 0, vmcs_config.size);
1595         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1596         return vmcs;
1597 }
1598
1599 static struct vmcs *alloc_vmcs(void)
1600 {
1601         return alloc_vmcs_cpu(raw_smp_processor_id());
1602 }
1603
1604 static void free_vmcs(struct vmcs *vmcs)
1605 {
1606         free_pages((unsigned long)vmcs, vmcs_config.order);
1607 }
1608
1609 static void free_kvm_area(void)
1610 {
1611         int cpu;
1612
1613         for_each_possible_cpu(cpu) {
1614                 free_vmcs(per_cpu(vmxarea, cpu));
1615                 per_cpu(vmxarea, cpu) = NULL;
1616         }
1617 }
1618
1619 static __init int alloc_kvm_area(void)
1620 {
1621         int cpu;
1622
1623         for_each_possible_cpu(cpu) {
1624                 struct vmcs *vmcs;
1625
1626                 vmcs = alloc_vmcs_cpu(cpu);
1627                 if (!vmcs) {
1628                         free_kvm_area();
1629                         return -ENOMEM;
1630                 }
1631
1632                 per_cpu(vmxarea, cpu) = vmcs;
1633         }
1634         return 0;
1635 }
1636
1637 static __init int hardware_setup(void)
1638 {
1639         if (setup_vmcs_config(&vmcs_config) < 0)
1640                 return -EIO;
1641
1642         if (boot_cpu_has(X86_FEATURE_NX))
1643                 kvm_enable_efer_bits(EFER_NX);
1644
1645         if (!cpu_has_vmx_vpid())
1646                 enable_vpid = 0;
1647
1648         if (!cpu_has_vmx_ept() ||
1649             !cpu_has_vmx_ept_4levels()) {
1650                 enable_ept = 0;
1651                 enable_unrestricted_guest = 0;
1652         }
1653
1654         if (!cpu_has_vmx_unrestricted_guest())
1655                 enable_unrestricted_guest = 0;
1656
1657         if (!cpu_has_vmx_flexpriority())
1658                 flexpriority_enabled = 0;
1659
1660         if (!cpu_has_vmx_tpr_shadow())
1661                 kvm_x86_ops->update_cr8_intercept = NULL;
1662
1663         if (enable_ept && !cpu_has_vmx_ept_2m_page())
1664                 kvm_disable_largepages();
1665
1666         if (!cpu_has_vmx_ple())
1667                 ple_gap = 0;
1668
1669         return alloc_kvm_area();
1670 }
1671
1672 static __exit void hardware_unsetup(void)
1673 {
1674         free_kvm_area();
1675 }
1676
1677 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1678 {
1679         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1680
1681         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1682                 vmcs_write16(sf->selector, save->selector);
1683                 vmcs_writel(sf->base, save->base);
1684                 vmcs_write32(sf->limit, save->limit);
1685                 vmcs_write32(sf->ar_bytes, save->ar);
1686         } else {
1687                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1688                         << AR_DPL_SHIFT;
1689                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1690         }
1691 }
1692
1693 static void enter_pmode(struct kvm_vcpu *vcpu)
1694 {
1695         unsigned long flags;
1696         struct vcpu_vmx *vmx = to_vmx(vcpu);
1697
1698         vmx->emulation_required = 1;
1699         vmx->rmode.vm86_active = 0;
1700
1701         vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
1702         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1703         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1704         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1705
1706         flags = vmcs_readl(GUEST_RFLAGS);
1707         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1708         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1709         vmcs_writel(GUEST_RFLAGS, flags);
1710
1711         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1712                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1713
1714         update_exception_bitmap(vcpu);
1715
1716         if (emulate_invalid_guest_state)
1717                 return;
1718
1719         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1720         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1721         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1722         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1723
1724         vmcs_write16(GUEST_SS_SELECTOR, 0);
1725         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1726
1727         vmcs_write16(GUEST_CS_SELECTOR,
1728                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1729         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1730 }
1731
1732 static gva_t rmode_tss_base(struct kvm *kvm)
1733 {
1734         if (!kvm->arch.tss_addr) {
1735                 struct kvm_memslots *slots;
1736                 gfn_t base_gfn;
1737
1738                 slots = kvm_memslots(kvm);
1739                 base_gfn = slots->memslots[0].base_gfn +
1740                                  kvm->memslots->memslots[0].npages - 3;
1741                 return base_gfn << PAGE_SHIFT;
1742         }
1743         return kvm->arch.tss_addr;
1744 }
1745
1746 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1747 {
1748         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1749
1750         save->selector = vmcs_read16(sf->selector);
1751         save->base = vmcs_readl(sf->base);
1752         save->limit = vmcs_read32(sf->limit);
1753         save->ar = vmcs_read32(sf->ar_bytes);
1754         vmcs_write16(sf->selector, save->base >> 4);
1755         vmcs_write32(sf->base, save->base & 0xffff0);
1756         vmcs_write32(sf->limit, 0xffff);
1757         vmcs_write32(sf->ar_bytes, 0xf3);
1758         if (save->base & 0xf)
1759                 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
1760                             " aligned when entering protected mode (seg=%d)",
1761                             seg);
1762 }
1763
1764 static void enter_rmode(struct kvm_vcpu *vcpu)
1765 {
1766         unsigned long flags;
1767         struct vcpu_vmx *vmx = to_vmx(vcpu);
1768
1769         if (enable_unrestricted_guest)
1770                 return;
1771
1772         vmx->emulation_required = 1;
1773         vmx->rmode.vm86_active = 1;
1774
1775         /*
1776          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
1777          * vcpu. Call it here with phys address pointing 16M below 4G.
1778          */
1779         if (!vcpu->kvm->arch.tss_addr) {
1780                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
1781                              "called before entering vcpu\n");
1782                 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
1783                 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
1784                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
1785         }
1786
1787         vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
1788         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1789         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1790
1791         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1792         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1793
1794         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1795         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1796
1797         flags = vmcs_readl(GUEST_RFLAGS);
1798         vmx->rmode.save_rflags = flags;
1799
1800         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1801
1802         vmcs_writel(GUEST_RFLAGS, flags);
1803         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1804         update_exception_bitmap(vcpu);
1805
1806         if (emulate_invalid_guest_state)
1807                 goto continue_rmode;
1808
1809         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1810         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1811         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1812
1813         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1814         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1815         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1816                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1817         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1818
1819         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1820         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1821         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1822         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1823
1824 continue_rmode:
1825         kvm_mmu_reset_context(vcpu);
1826 }
1827
1828 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1829 {
1830         struct vcpu_vmx *vmx = to_vmx(vcpu);
1831         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1832
1833         if (!msr)
1834                 return;
1835
1836         /*
1837          * Force kernel_gs_base reloading before EFER changes, as control
1838          * of this msr depends on is_long_mode().
1839          */
1840         vmx_load_host_state(to_vmx(vcpu));
1841         vcpu->arch.efer = efer;
1842         if (efer & EFER_LMA) {
1843                 vmcs_write32(VM_ENTRY_CONTROLS,
1844                              vmcs_read32(VM_ENTRY_CONTROLS) |
1845                              VM_ENTRY_IA32E_MODE);
1846                 msr->data = efer;
1847         } else {
1848                 vmcs_write32(VM_ENTRY_CONTROLS,
1849                              vmcs_read32(VM_ENTRY_CONTROLS) &
1850                              ~VM_ENTRY_IA32E_MODE);
1851
1852                 msr->data = efer & ~EFER_LME;
1853         }
1854         setup_msrs(vmx);
1855 }
1856
1857 #ifdef CONFIG_X86_64
1858
1859 static void enter_lmode(struct kvm_vcpu *vcpu)
1860 {
1861         u32 guest_tr_ar;
1862
1863         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1864         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1865                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1866                        __func__);
1867                 vmcs_write32(GUEST_TR_AR_BYTES,
1868                              (guest_tr_ar & ~AR_TYPE_MASK)
1869                              | AR_TYPE_BUSY_64_TSS);
1870         }
1871         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
1872 }
1873
1874 static void exit_lmode(struct kvm_vcpu *vcpu)
1875 {
1876         vmcs_write32(VM_ENTRY_CONTROLS,
1877                      vmcs_read32(VM_ENTRY_CONTROLS)
1878                      & ~VM_ENTRY_IA32E_MODE);
1879         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
1880 }
1881
1882 #endif
1883
1884 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1885 {
1886         vpid_sync_context(to_vmx(vcpu));
1887         if (enable_ept) {
1888                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
1889                         return;
1890                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1891         }
1892 }
1893
1894 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1895 {
1896         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1897
1898         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1899         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1900 }
1901
1902 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
1903 {
1904         if (enable_ept && is_paging(vcpu))
1905                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
1906         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
1907 }
1908
1909 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1910 {
1911         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1912
1913         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1914         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
1915 }
1916
1917 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1918 {
1919         if (!test_bit(VCPU_EXREG_PDPTR,
1920                       (unsigned long *)&vcpu->arch.regs_dirty))
1921                 return;
1922
1923         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1924                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
1925                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
1926                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
1927                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1928         }
1929 }
1930
1931 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1932 {
1933         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1934                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1935                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1936                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1937                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1938         }
1939
1940         __set_bit(VCPU_EXREG_PDPTR,
1941                   (unsigned long *)&vcpu->arch.regs_avail);
1942         __set_bit(VCPU_EXREG_PDPTR,
1943                   (unsigned long *)&vcpu->arch.regs_dirty);
1944 }
1945
1946 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1947
1948 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1949                                         unsigned long cr0,
1950                                         struct kvm_vcpu *vcpu)
1951 {
1952         vmx_decache_cr3(vcpu);
1953         if (!(cr0 & X86_CR0_PG)) {
1954                 /* From paging/starting to nonpaging */
1955                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1956                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1957                              (CPU_BASED_CR3_LOAD_EXITING |
1958                               CPU_BASED_CR3_STORE_EXITING));
1959                 vcpu->arch.cr0 = cr0;
1960                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1961         } else if (!is_paging(vcpu)) {
1962                 /* From nonpaging to paging */
1963                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1964                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1965                              ~(CPU_BASED_CR3_LOAD_EXITING |
1966                                CPU_BASED_CR3_STORE_EXITING));
1967                 vcpu->arch.cr0 = cr0;
1968                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1969         }
1970
1971         if (!(cr0 & X86_CR0_WP))
1972                 *hw_cr0 &= ~X86_CR0_WP;
1973 }
1974
1975 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1976 {
1977         struct vcpu_vmx *vmx = to_vmx(vcpu);
1978         unsigned long hw_cr0;
1979
1980         if (enable_unrestricted_guest)
1981                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1982                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1983         else
1984                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1985
1986         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1987                 enter_pmode(vcpu);
1988
1989         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1990                 enter_rmode(vcpu);
1991
1992 #ifdef CONFIG_X86_64
1993         if (vcpu->arch.efer & EFER_LME) {
1994                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1995                         enter_lmode(vcpu);
1996                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1997                         exit_lmode(vcpu);
1998         }
1999 #endif
2000
2001         if (enable_ept)
2002                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2003
2004         if (!vcpu->fpu_active)
2005                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
2006
2007         vmcs_writel(CR0_READ_SHADOW, cr0);
2008         vmcs_writel(GUEST_CR0, hw_cr0);
2009         vcpu->arch.cr0 = cr0;
2010         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2011 }
2012
2013 static u64 construct_eptp(unsigned long root_hpa)
2014 {
2015         u64 eptp;
2016
2017         /* TODO write the value reading from MSR */
2018         eptp = VMX_EPT_DEFAULT_MT |
2019                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
2020         eptp |= (root_hpa & PAGE_MASK);
2021
2022         return eptp;
2023 }
2024
2025 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2026 {
2027         unsigned long guest_cr3;
2028         u64 eptp;
2029
2030         guest_cr3 = cr3;
2031         if (enable_ept) {
2032                 eptp = construct_eptp(cr3);
2033                 vmcs_write64(EPT_POINTER, eptp);
2034                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
2035                         vcpu->kvm->arch.ept_identity_map_addr;
2036                 ept_load_pdptrs(vcpu);
2037         }
2038
2039         vmx_flush_tlb(vcpu);
2040         vmcs_writel(GUEST_CR3, guest_cr3);
2041 }
2042
2043 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2044 {
2045         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
2046                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
2047
2048         vcpu->arch.cr4 = cr4;
2049         if (enable_ept) {
2050                 if (!is_paging(vcpu)) {
2051                         hw_cr4 &= ~X86_CR4_PAE;
2052                         hw_cr4 |= X86_CR4_PSE;
2053                 } else if (!(cr4 & X86_CR4_PAE)) {
2054                         hw_cr4 &= ~X86_CR4_PAE;
2055                 }
2056         }
2057
2058         vmcs_writel(CR4_READ_SHADOW, cr4);
2059         vmcs_writel(GUEST_CR4, hw_cr4);
2060 }
2061
2062 static void vmx_get_segment(struct kvm_vcpu *vcpu,
2063                             struct kvm_segment *var, int seg)
2064 {
2065         struct vcpu_vmx *vmx = to_vmx(vcpu);
2066         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2067         struct kvm_save_segment *save;
2068         u32 ar;
2069
2070         if (vmx->rmode.vm86_active
2071             && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
2072                 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
2073                 || seg == VCPU_SREG_GS)
2074             && !emulate_invalid_guest_state) {
2075                 switch (seg) {
2076                 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
2077                 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
2078                 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
2079                 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
2080                 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
2081                 default: BUG();
2082                 }
2083                 var->selector = save->selector;
2084                 var->base = save->base;
2085                 var->limit = save->limit;
2086                 ar = save->ar;
2087                 if (seg == VCPU_SREG_TR
2088                     || var->selector == vmcs_read16(sf->selector))
2089                         goto use_saved_rmode_seg;
2090         }
2091         var->base = vmcs_readl(sf->base);
2092         var->limit = vmcs_read32(sf->limit);
2093         var->selector = vmcs_read16(sf->selector);
2094         ar = vmcs_read32(sf->ar_bytes);
2095 use_saved_rmode_seg:
2096         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
2097                 ar = 0;
2098         var->type = ar & 15;
2099         var->s = (ar >> 4) & 1;
2100         var->dpl = (ar >> 5) & 3;
2101         var->present = (ar >> 7) & 1;
2102         var->avl = (ar >> 12) & 1;
2103         var->l = (ar >> 13) & 1;
2104         var->db = (ar >> 14) & 1;
2105         var->g = (ar >> 15) & 1;
2106         var->unusable = (ar >> 16) & 1;
2107 }
2108
2109 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2110 {
2111         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2112         struct kvm_segment s;
2113
2114         if (to_vmx(vcpu)->rmode.vm86_active) {
2115                 vmx_get_segment(vcpu, &s, seg);
2116                 return s.base;
2117         }
2118         return vmcs_readl(sf->base);
2119 }
2120
2121 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
2122 {
2123         if (!is_protmode(vcpu))
2124                 return 0;
2125
2126         if (!is_long_mode(vcpu)
2127             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2128                 return 3;
2129
2130         return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2131 }
2132
2133 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2134 {
2135         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
2136                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2137                 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
2138         }
2139         return to_vmx(vcpu)->cpl;
2140 }
2141
2142
2143 static u32 vmx_segment_access_rights(struct kvm_segment *var)
2144 {
2145         u32 ar;
2146
2147         if (var->unusable)
2148                 ar = 1 << 16;
2149         else {
2150                 ar = var->type & 15;
2151                 ar |= (var->s & 1) << 4;
2152                 ar |= (var->dpl & 3) << 5;
2153                 ar |= (var->present & 1) << 7;
2154                 ar |= (var->avl & 1) << 12;
2155                 ar |= (var->l & 1) << 13;
2156                 ar |= (var->db & 1) << 14;
2157                 ar |= (var->g & 1) << 15;
2158         }
2159         if (ar == 0) /* a 0 value means unusable */
2160                 ar = AR_UNUSABLE_MASK;
2161
2162         return ar;
2163 }
2164
2165 static void vmx_set_segment(struct kvm_vcpu *vcpu,
2166                             struct kvm_segment *var, int seg)
2167 {
2168         struct vcpu_vmx *vmx = to_vmx(vcpu);
2169         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2170         u32 ar;
2171
2172         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2173                 vmcs_write16(sf->selector, var->selector);
2174                 vmx->rmode.tr.selector = var->selector;
2175                 vmx->rmode.tr.base = var->base;
2176                 vmx->rmode.tr.limit = var->limit;
2177                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
2178                 return;
2179         }
2180         vmcs_writel(sf->base, var->base);
2181         vmcs_write32(sf->limit, var->limit);
2182         vmcs_write16(sf->selector, var->selector);
2183         if (vmx->rmode.vm86_active && var->s) {
2184                 /*
2185                  * Hack real-mode segments into vm86 compatibility.
2186                  */
2187                 if (var->base == 0xffff0000 && var->selector == 0xf000)
2188                         vmcs_writel(sf->base, 0xf0000);
2189                 ar = 0xf3;
2190         } else
2191                 ar = vmx_segment_access_rights(var);
2192
2193         /*
2194          *   Fix the "Accessed" bit in AR field of segment registers for older
2195          * qemu binaries.
2196          *   IA32 arch specifies that at the time of processor reset the
2197          * "Accessed" bit in the AR field of segment registers is 1. And qemu
2198          * is setting it to 0 in the usedland code. This causes invalid guest
2199          * state vmexit when "unrestricted guest" mode is turned on.
2200          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
2201          * tree. Newer qemu binaries with that qemu fix would not need this
2202          * kvm hack.
2203          */
2204         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2205                 ar |= 0x1; /* Accessed */
2206
2207         vmcs_write32(sf->ar_bytes, ar);
2208         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2209 }
2210
2211 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2212 {
2213         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2214
2215         *db = (ar >> 14) & 1;
2216         *l = (ar >> 13) & 1;
2217 }
2218
2219 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2220 {
2221         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2222         dt->address = vmcs_readl(GUEST_IDTR_BASE);
2223 }
2224
2225 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2226 {
2227         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2228         vmcs_writel(GUEST_IDTR_BASE, dt->address);
2229 }
2230
2231 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2232 {
2233         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2234         dt->address = vmcs_readl(GUEST_GDTR_BASE);
2235 }
2236
2237 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2238 {
2239         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2240         vmcs_writel(GUEST_GDTR_BASE, dt->address);
2241 }
2242
2243 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2244 {
2245         struct kvm_segment var;
2246         u32 ar;
2247
2248         vmx_get_segment(vcpu, &var, seg);
2249         ar = vmx_segment_access_rights(&var);
2250
2251         if (var.base != (var.selector << 4))
2252                 return false;
2253         if (var.limit != 0xffff)
2254                 return false;
2255         if (ar != 0xf3)
2256                 return false;
2257
2258         return true;
2259 }
2260
2261 static bool code_segment_valid(struct kvm_vcpu *vcpu)
2262 {
2263         struct kvm_segment cs;
2264         unsigned int cs_rpl;
2265
2266         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2267         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2268
2269         if (cs.unusable)
2270                 return false;
2271         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2272                 return false;
2273         if (!cs.s)
2274                 return false;
2275         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
2276                 if (cs.dpl > cs_rpl)
2277                         return false;
2278         } else {
2279                 if (cs.dpl != cs_rpl)
2280                         return false;
2281         }
2282         if (!cs.present)
2283                 return false;
2284
2285         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2286         return true;
2287 }
2288
2289 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2290 {
2291         struct kvm_segment ss;
2292         unsigned int ss_rpl;
2293
2294         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2295         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2296
2297         if (ss.unusable)
2298                 return true;
2299         if (ss.type != 3 && ss.type != 7)
2300                 return false;
2301         if (!ss.s)
2302                 return false;
2303         if (ss.dpl != ss_rpl) /* DPL != RPL */
2304                 return false;
2305         if (!ss.present)
2306                 return false;
2307
2308         return true;
2309 }
2310
2311 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2312 {
2313         struct kvm_segment var;
2314         unsigned int rpl;
2315
2316         vmx_get_segment(vcpu, &var, seg);
2317         rpl = var.selector & SELECTOR_RPL_MASK;
2318
2319         if (var.unusable)
2320                 return true;
2321         if (!var.s)
2322                 return false;
2323         if (!var.present)
2324                 return false;
2325         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2326                 if (var.dpl < rpl) /* DPL < RPL */
2327                         return false;
2328         }
2329
2330         /* TODO: Add other members to kvm_segment_field to allow checking for other access
2331          * rights flags
2332          */
2333         return true;
2334 }
2335
2336 static bool tr_valid(struct kvm_vcpu *vcpu)
2337 {
2338         struct kvm_segment tr;
2339
2340         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2341
2342         if (tr.unusable)
2343                 return false;
2344         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
2345                 return false;
2346         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2347                 return false;
2348         if (!tr.present)
2349                 return false;
2350
2351         return true;
2352 }
2353
2354 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2355 {
2356         struct kvm_segment ldtr;
2357
2358         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2359
2360         if (ldtr.unusable)
2361                 return true;
2362         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
2363                 return false;
2364         if (ldtr.type != 2)
2365                 return false;
2366         if (!ldtr.present)
2367                 return false;
2368
2369         return true;
2370 }
2371
2372 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2373 {
2374         struct kvm_segment cs, ss;
2375
2376         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2377         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2378
2379         return ((cs.selector & SELECTOR_RPL_MASK) ==
2380                  (ss.selector & SELECTOR_RPL_MASK));
2381 }
2382
2383 /*
2384  * Check if guest state is valid. Returns true if valid, false if
2385  * not.
2386  * We assume that registers are always usable
2387  */
2388 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2389 {
2390         /* real mode guest state checks */
2391         if (!is_protmode(vcpu)) {
2392                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2393                         return false;
2394                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2395                         return false;
2396                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2397                         return false;
2398                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2399                         return false;
2400                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2401                         return false;
2402                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2403                         return false;
2404         } else {
2405         /* protected mode guest state checks */
2406                 if (!cs_ss_rpl_check(vcpu))
2407                         return false;
2408                 if (!code_segment_valid(vcpu))
2409                         return false;
2410                 if (!stack_segment_valid(vcpu))
2411                         return false;
2412                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2413                         return false;
2414                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2415                         return false;
2416                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2417                         return false;
2418                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2419                         return false;
2420                 if (!tr_valid(vcpu))
2421                         return false;
2422                 if (!ldtr_valid(vcpu))
2423                         return false;
2424         }
2425         /* TODO:
2426          * - Add checks on RIP
2427          * - Add checks on RFLAGS
2428          */
2429
2430         return true;
2431 }
2432
2433 static int init_rmode_tss(struct kvm *kvm)
2434 {
2435         gfn_t fn;
2436         u16 data = 0;
2437         int r, idx, ret = 0;
2438
2439         idx = srcu_read_lock(&kvm->srcu);
2440         fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2441         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2442         if (r < 0)
2443                 goto out;
2444         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2445         r = kvm_write_guest_page(kvm, fn++, &data,
2446                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
2447         if (r < 0)
2448                 goto out;
2449         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2450         if (r < 0)
2451                 goto out;
2452         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2453         if (r < 0)
2454                 goto out;
2455         data = ~0;
2456         r = kvm_write_guest_page(kvm, fn, &data,
2457                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2458                                  sizeof(u8));
2459         if (r < 0)
2460                 goto out;
2461
2462         ret = 1;
2463 out:
2464         srcu_read_unlock(&kvm->srcu, idx);
2465         return ret;
2466 }
2467
2468 static int init_rmode_identity_map(struct kvm *kvm)
2469 {
2470         int i, idx, r, ret;
2471         pfn_t identity_map_pfn;
2472         u32 tmp;
2473
2474         if (!enable_ept)
2475                 return 1;
2476         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2477                 printk(KERN_ERR "EPT: identity-mapping pagetable "
2478                         "haven't been allocated!\n");
2479                 return 0;
2480         }
2481         if (likely(kvm->arch.ept_identity_pagetable_done))
2482                 return 1;
2483         ret = 0;
2484         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2485         idx = srcu_read_lock(&kvm->srcu);
2486         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2487         if (r < 0)
2488                 goto out;
2489         /* Set up identity-mapping pagetable for EPT in real mode */
2490         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2491                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2492                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2493                 r = kvm_write_guest_page(kvm, identity_map_pfn,
2494                                 &tmp, i * sizeof(tmp), sizeof(tmp));
2495                 if (r < 0)
2496                         goto out;
2497         }
2498         kvm->arch.ept_identity_pagetable_done = true;
2499         ret = 1;
2500 out:
2501         srcu_read_unlock(&kvm->srcu, idx);
2502         return ret;
2503 }
2504
2505 static void seg_setup(int seg)
2506 {
2507         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2508         unsigned int ar;
2509
2510         vmcs_write16(sf->selector, 0);
2511         vmcs_writel(sf->base, 0);
2512         vmcs_write32(sf->limit, 0xffff);
2513         if (enable_unrestricted_guest) {
2514                 ar = 0x93;
2515                 if (seg == VCPU_SREG_CS)
2516                         ar |= 0x08; /* code segment */
2517         } else
2518                 ar = 0xf3;
2519
2520         vmcs_write32(sf->ar_bytes, ar);
2521 }
2522
2523 static int alloc_apic_access_page(struct kvm *kvm)
2524 {
2525         struct kvm_userspace_memory_region kvm_userspace_mem;
2526         int r = 0;
2527
2528         mutex_lock(&kvm->slots_lock);
2529         if (kvm->arch.apic_access_page)
2530                 goto out;
2531         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2532         kvm_userspace_mem.flags = 0;
2533         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2534         kvm_userspace_mem.memory_size = PAGE_SIZE;
2535         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2536         if (r)
2537                 goto out;
2538
2539         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2540 out:
2541         mutex_unlock(&kvm->slots_lock);
2542         return r;
2543 }
2544
2545 static int alloc_identity_pagetable(struct kvm *kvm)
2546 {
2547         struct kvm_userspace_memory_region kvm_userspace_mem;
2548         int r = 0;
2549
2550         mutex_lock(&kvm->slots_lock);
2551         if (kvm->arch.ept_identity_pagetable)
2552                 goto out;
2553         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2554         kvm_userspace_mem.flags = 0;
2555         kvm_userspace_mem.guest_phys_addr =
2556                 kvm->arch.ept_identity_map_addr;
2557         kvm_userspace_mem.memory_size = PAGE_SIZE;
2558         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2559         if (r)
2560                 goto out;
2561
2562         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2563                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2564 out:
2565         mutex_unlock(&kvm->slots_lock);
2566         return r;
2567 }
2568
2569 static void allocate_vpid(struct vcpu_vmx *vmx)
2570 {
2571         int vpid;
2572
2573         vmx->vpid = 0;
2574         if (!enable_vpid)
2575                 return;
2576         spin_lock(&vmx_vpid_lock);
2577         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2578         if (vpid < VMX_NR_VPIDS) {
2579                 vmx->vpid = vpid;
2580                 __set_bit(vpid, vmx_vpid_bitmap);
2581         }
2582         spin_unlock(&vmx_vpid_lock);
2583 }
2584
2585 static void free_vpid(struct vcpu_vmx *vmx)
2586 {
2587         if (!enable_vpid)
2588                 return;
2589         spin_lock(&vmx_vpid_lock);
2590         if (vmx->vpid != 0)
2591                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2592         spin_unlock(&vmx_vpid_lock);
2593 }
2594
2595 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2596 {
2597         int f = sizeof(unsigned long);
2598
2599         if (!cpu_has_vmx_msr_bitmap())
2600                 return;
2601
2602         /*
2603          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2604          * have the write-low and read-high bitmap offsets the wrong way round.
2605          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2606          */
2607         if (msr <= 0x1fff) {
2608                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2609                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2610         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2611                 msr &= 0x1fff;
2612                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2613                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2614         }
2615 }
2616
2617 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2618 {
2619         if (!longmode_only)
2620                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2621         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2622 }
2623
2624 /*
2625  * Sets up the vmcs for emulated real mode.
2626  */
2627 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2628 {
2629         u32 host_sysenter_cs, msr_low, msr_high;
2630         u32 junk;
2631         u64 host_pat;
2632         unsigned long a;
2633         struct desc_ptr dt;
2634         int i;
2635         unsigned long kvm_vmx_return;
2636         u32 exec_control;
2637
2638         /* I/O */
2639         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2640         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2641
2642         if (cpu_has_vmx_msr_bitmap())
2643                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2644
2645         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2646
2647         /* Control */
2648         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2649                 vmcs_config.pin_based_exec_ctrl);
2650
2651         exec_control = vmcs_config.cpu_based_exec_ctrl;
2652         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2653                 exec_control &= ~CPU_BASED_TPR_SHADOW;
2654 #ifdef CONFIG_X86_64
2655                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2656                                 CPU_BASED_CR8_LOAD_EXITING;
2657 #endif
2658         }
2659         if (!enable_ept)
2660                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2661                                 CPU_BASED_CR3_LOAD_EXITING  |
2662                                 CPU_BASED_INVLPG_EXITING;
2663         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2664
2665         if (cpu_has_secondary_exec_ctrls()) {
2666                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2667                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2668                         exec_control &=
2669                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2670                 if (vmx->vpid == 0)
2671                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2672                 if (!enable_ept) {
2673                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2674                         enable_unrestricted_guest = 0;
2675                 }
2676                 if (!enable_unrestricted_guest)
2677                         exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2678                 if (!ple_gap)
2679                         exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2680                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2681         }
2682
2683         if (ple_gap) {
2684                 vmcs_write32(PLE_GAP, ple_gap);
2685                 vmcs_write32(PLE_WINDOW, ple_window);
2686         }
2687
2688         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2689         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2690         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
2691
2692         vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS);  /* 22.2.3 */
2693         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
2694         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
2695
2696         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
2697         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2698         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2699         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
2700         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
2701         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2702 #ifdef CONFIG_X86_64
2703         rdmsrl(MSR_FS_BASE, a);
2704         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2705         rdmsrl(MSR_GS_BASE, a);
2706         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2707 #else
2708         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2709         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2710 #endif
2711
2712         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
2713
2714         native_store_idt(&dt);
2715         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
2716
2717         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2718         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2719         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2720         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2721         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2722         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2723         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
2724
2725         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2726         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2727         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2728         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
2729         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2730         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
2731
2732         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2733                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2734                 host_pat = msr_low | ((u64) msr_high << 32);
2735                 vmcs_write64(HOST_IA32_PAT, host_pat);
2736         }
2737         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2738                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2739                 host_pat = msr_low | ((u64) msr_high << 32);
2740                 /* Write the default value follow host pat */
2741                 vmcs_write64(GUEST_IA32_PAT, host_pat);
2742                 /* Keep arch.pat sync with GUEST_IA32_PAT */
2743                 vmx->vcpu.arch.pat = host_pat;
2744         }
2745
2746         for (i = 0; i < NR_VMX_MSR; ++i) {
2747                 u32 index = vmx_msr_index[i];
2748                 u32 data_low, data_high;
2749                 int j = vmx->nmsrs;
2750
2751                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2752                         continue;
2753                 if (wrmsr_safe(index, data_low, data_high) < 0)
2754                         continue;
2755                 vmx->guest_msrs[j].index = i;
2756                 vmx->guest_msrs[j].data = 0;
2757                 vmx->guest_msrs[j].mask = -1ull;
2758                 ++vmx->nmsrs;
2759         }
2760
2761         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2762
2763         /* 22.2.1, 20.8.1 */
2764         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2765
2766         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2767         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
2768         if (enable_ept)
2769                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
2770         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
2771
2772         kvm_write_tsc(&vmx->vcpu, 0);
2773
2774         return 0;
2775 }
2776
2777 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2778 {
2779         struct vcpu_vmx *vmx = to_vmx(vcpu);
2780         u64 msr;
2781         int ret;
2782
2783         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2784
2785         vmx->rmode.vm86_active = 0;
2786
2787         vmx->soft_vnmi_blocked = 0;
2788
2789         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2790         kvm_set_cr8(&vmx->vcpu, 0);
2791         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2792         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2793                 msr |= MSR_IA32_APICBASE_BSP;
2794         kvm_set_apic_base(&vmx->vcpu, msr);
2795
2796         ret = fx_init(&vmx->vcpu);
2797         if (ret != 0)
2798                 goto out;
2799
2800         seg_setup(VCPU_SREG_CS);
2801         /*
2802          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2803          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
2804          */
2805         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2806                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2807                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2808         } else {
2809                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2810                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2811         }
2812
2813         seg_setup(VCPU_SREG_DS);
2814         seg_setup(VCPU_SREG_ES);
2815         seg_setup(VCPU_SREG_FS);
2816         seg_setup(VCPU_SREG_GS);
2817         seg_setup(VCPU_SREG_SS);
2818
2819         vmcs_write16(GUEST_TR_SELECTOR, 0);
2820         vmcs_writel(GUEST_TR_BASE, 0);
2821         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2822         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2823
2824         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2825         vmcs_writel(GUEST_LDTR_BASE, 0);
2826         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2827         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2828
2829         vmcs_write32(GUEST_SYSENTER_CS, 0);
2830         vmcs_writel(GUEST_SYSENTER_ESP, 0);
2831         vmcs_writel(GUEST_SYSENTER_EIP, 0);
2832
2833         vmcs_writel(GUEST_RFLAGS, 0x02);
2834         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2835                 kvm_rip_write(vcpu, 0xfff0);
2836         else
2837                 kvm_rip_write(vcpu, 0);
2838         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2839
2840         vmcs_writel(GUEST_DR7, 0x400);
2841
2842         vmcs_writel(GUEST_GDTR_BASE, 0);
2843         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2844
2845         vmcs_writel(GUEST_IDTR_BASE, 0);
2846         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2847
2848         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
2849         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2850         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2851
2852         /* Special registers */
2853         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2854
2855         setup_msrs(vmx);
2856
2857         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
2858
2859         if (cpu_has_vmx_tpr_shadow()) {
2860                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2861                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2862                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2863                                      __pa(vmx->vcpu.arch.apic->regs));
2864                 vmcs_write32(TPR_THRESHOLD, 0);
2865         }
2866
2867         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2868                 vmcs_write64(APIC_ACCESS_ADDR,
2869                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2870
2871         if (vmx->vpid != 0)
2872                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2873
2874         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
2875         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
2876         vmx_set_cr4(&vmx->vcpu, 0);
2877         vmx_set_efer(&vmx->vcpu, 0);
2878         vmx_fpu_activate(&vmx->vcpu);
2879         update_exception_bitmap(&vmx->vcpu);
2880
2881         vpid_sync_context(vmx);
2882
2883         ret = 0;
2884
2885         /* HACK: Don't enable emulation on guest boot/reset */
2886         vmx->emulation_required = 0;
2887
2888 out:
2889         return ret;
2890 }
2891
2892 static void enable_irq_window(struct kvm_vcpu *vcpu)
2893 {
2894         u32 cpu_based_vm_exec_control;
2895
2896         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2897         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2898         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2899 }
2900
2901 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2902 {
2903         u32 cpu_based_vm_exec_control;
2904
2905         if (!cpu_has_virtual_nmis()) {
2906                 enable_irq_window(vcpu);
2907                 return;
2908         }
2909
2910         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
2911                 enable_irq_window(vcpu);
2912                 return;
2913         }
2914         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2915         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2916         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2917 }
2918
2919 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2920 {
2921         struct vcpu_vmx *vmx = to_vmx(vcpu);
2922         uint32_t intr;
2923         int irq = vcpu->arch.interrupt.nr;
2924
2925         trace_kvm_inj_virq(irq);
2926
2927         ++vcpu->stat.irq_injections;
2928         if (vmx->rmode.vm86_active) {
2929                 if (kvm_inject_realmode_interrupt(vcpu, irq) != EMULATE_DONE)
2930                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2931                 return;
2932         }
2933         intr = irq | INTR_INFO_VALID_MASK;
2934         if (vcpu->arch.interrupt.soft) {
2935                 intr |= INTR_TYPE_SOFT_INTR;
2936                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2937                              vmx->vcpu.arch.event_exit_inst_len);
2938         } else
2939                 intr |= INTR_TYPE_EXT_INTR;
2940         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2941         vmx_clear_hlt(vcpu);
2942 }
2943
2944 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2945 {
2946         struct vcpu_vmx *vmx = to_vmx(vcpu);
2947
2948         if (!cpu_has_virtual_nmis()) {
2949                 /*
2950                  * Tracking the NMI-blocked state in software is built upon
2951                  * finding the next open IRQ window. This, in turn, depends on
2952                  * well-behaving guests: They have to keep IRQs disabled at
2953                  * least as long as the NMI handler runs. Otherwise we may
2954                  * cause NMI nesting, maybe breaking the guest. But as this is
2955                  * highly unlikely, we can live with the residual risk.
2956                  */
2957                 vmx->soft_vnmi_blocked = 1;
2958                 vmx->vnmi_blocked_time = 0;
2959         }
2960
2961         ++vcpu->stat.nmi_injections;
2962         if (vmx->rmode.vm86_active) {
2963                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR) != EMULATE_DONE)
2964                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2965                 return;
2966         }
2967         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2968                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2969         vmx_clear_hlt(vcpu);
2970 }
2971
2972 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2973 {
2974         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2975                 return 0;
2976
2977         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2978                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
2979                    | GUEST_INTR_STATE_NMI));
2980 }
2981
2982 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2983 {
2984         if (!cpu_has_virtual_nmis())
2985                 return to_vmx(vcpu)->soft_vnmi_blocked;
2986         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
2987 }
2988
2989 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2990 {
2991         struct vcpu_vmx *vmx = to_vmx(vcpu);
2992
2993         if (!cpu_has_virtual_nmis()) {
2994                 if (vmx->soft_vnmi_blocked != masked) {
2995                         vmx->soft_vnmi_blocked = masked;
2996                         vmx->vnmi_blocked_time = 0;
2997                 }
2998         } else {
2999                 if (masked)
3000                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3001                                       GUEST_INTR_STATE_NMI);
3002                 else
3003                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3004                                         GUEST_INTR_STATE_NMI);
3005         }
3006 }
3007
3008 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
3009 {
3010         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
3011                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3012                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
3013 }
3014
3015 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
3016 {
3017         int ret;
3018         struct kvm_userspace_memory_region tss_mem = {
3019                 .slot = TSS_PRIVATE_MEMSLOT,
3020                 .guest_phys_addr = addr,
3021                 .memory_size = PAGE_SIZE * 3,
3022                 .flags = 0,
3023         };
3024
3025         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
3026         if (ret)
3027                 return ret;
3028         kvm->arch.tss_addr = addr;
3029         if (!init_rmode_tss(kvm))
3030                 return  -ENOMEM;
3031
3032         return 0;
3033 }
3034
3035 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
3036                                   int vec, u32 err_code)
3037 {
3038         /*
3039          * Instruction with address size override prefix opcode 0x67
3040          * Cause the #SS fault with 0 error code in VM86 mode.
3041          */
3042         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
3043                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
3044                         return 1;
3045         /*
3046          * Forward all other exceptions that are valid in real mode.
3047          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
3048          *        the required debugging infrastructure rework.
3049          */
3050         switch (vec) {
3051         case DB_VECTOR:
3052                 if (vcpu->guest_debug &
3053                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
3054                         return 0;
3055                 kvm_queue_exception(vcpu, vec);
3056                 return 1;
3057         case BP_VECTOR:
3058                 /*
3059                  * Update instruction length as we may reinject the exception
3060                  * from user space while in guest debugging mode.
3061                  */
3062                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
3063                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3064                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
3065                         return 0;
3066                 /* fall through */
3067         case DE_VECTOR:
3068         case OF_VECTOR:
3069         case BR_VECTOR:
3070         case UD_VECTOR:
3071         case DF_VECTOR:
3072         case SS_VECTOR:
3073         case GP_VECTOR:
3074         case MF_VECTOR:
3075                 kvm_queue_exception(vcpu, vec);
3076                 return 1;
3077         }
3078         return 0;
3079 }
3080
3081 /*
3082  * Trigger machine check on the host. We assume all the MSRs are already set up
3083  * by the CPU and that we still run on the same CPU as the MCE occurred on.
3084  * We pass a fake environment to the machine check handler because we want
3085  * the guest to be always treated like user space, no matter what context
3086  * it used internally.
3087  */
3088 static void kvm_machine_check(void)
3089 {
3090 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
3091         struct pt_regs regs = {
3092                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
3093                 .flags = X86_EFLAGS_IF,
3094         };
3095
3096         do_machine_check(&regs, 0);
3097 #endif
3098 }
3099
3100 static int handle_machine_check(struct kvm_vcpu *vcpu)
3101 {
3102         /* already handled by vcpu_run */
3103         return 1;
3104 }
3105
3106 static int handle_exception(struct kvm_vcpu *vcpu)
3107 {
3108         struct vcpu_vmx *vmx = to_vmx(vcpu);
3109         struct kvm_run *kvm_run = vcpu->run;
3110         u32 intr_info, ex_no, error_code;
3111         unsigned long cr2, rip, dr6;
3112         u32 vect_info;
3113         enum emulation_result er;
3114
3115         vect_info = vmx->idt_vectoring_info;
3116         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3117
3118         if (is_machine_check(intr_info))
3119                 return handle_machine_check(vcpu);
3120
3121         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
3122             !is_page_fault(intr_info)) {
3123                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3124                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3125                 vcpu->run->internal.ndata = 2;
3126                 vcpu->run->internal.data[0] = vect_info;
3127                 vcpu->run->internal.data[1] = intr_info;
3128                 return 0;
3129         }
3130
3131         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
3132                 return 1;  /* already handled by vmx_vcpu_run() */
3133
3134         if (is_no_device(intr_info)) {
3135                 vmx_fpu_activate(vcpu);
3136                 return 1;
3137         }
3138
3139         if (is_invalid_opcode(intr_info)) {
3140                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
3141                 if (er != EMULATE_DONE)
3142                         kvm_queue_exception(vcpu, UD_VECTOR);
3143                 return 1;
3144         }
3145
3146         error_code = 0;
3147         rip = kvm_rip_read(vcpu);
3148         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
3149                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3150         if (is_page_fault(intr_info)) {
3151                 /* EPT won't cause page fault directly */
3152                 if (enable_ept)
3153                         BUG();
3154                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
3155                 trace_kvm_page_fault(cr2, error_code);
3156
3157                 if (kvm_event_needs_reinjection(vcpu))
3158                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
3159                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
3160         }
3161
3162         if (vmx->rmode.vm86_active &&
3163             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
3164                                                                 error_code)) {
3165                 if (vcpu->arch.halt_request) {
3166                         vcpu->arch.halt_request = 0;
3167                         return kvm_emulate_halt(vcpu);
3168                 }
3169                 return 1;
3170         }
3171
3172         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
3173         switch (ex_no) {
3174         case DB_VECTOR:
3175                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3176                 if (!(vcpu->guest_debug &
3177                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3178                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3179                         kvm_queue_exception(vcpu, DB_VECTOR);
3180                         return 1;
3181                 }
3182                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3183                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3184                 /* fall through */
3185         case BP_VECTOR:
3186                 /*
3187                  * Update instruction length as we may reinject #BP from
3188                  * user space while in guest debugging mode. Reading it for
3189                  * #DB as well causes no harm, it is not used in that case.
3190                  */
3191                 vmx->vcpu.arch.event_exit_inst_len =
3192                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3193                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
3194                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3195                 kvm_run->debug.arch.exception = ex_no;
3196                 break;
3197         default:
3198                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3199                 kvm_run->ex.exception = ex_no;
3200                 kvm_run->ex.error_code = error_code;
3201                 break;
3202         }
3203         return 0;
3204 }
3205
3206 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
3207 {
3208         ++vcpu->stat.irq_exits;
3209         return 1;
3210 }
3211
3212 static int handle_triple_fault(struct kvm_vcpu *vcpu)
3213 {
3214         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
3215         return 0;
3216 }
3217
3218 static int handle_io(struct kvm_vcpu *vcpu)
3219 {
3220         unsigned long exit_qualification;
3221         int size, in, string;
3222         unsigned port;
3223
3224         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3225         string = (exit_qualification & 16) != 0;
3226         in = (exit_qualification & 8) != 0;
3227
3228         ++vcpu->stat.io_exits;
3229
3230         if (string || in)
3231                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
3232
3233         port = exit_qualification >> 16;
3234         size = (exit_qualification & 7) + 1;
3235         skip_emulated_instruction(vcpu);
3236
3237         return kvm_fast_pio_out(vcpu, size, port);
3238 }
3239
3240 static void
3241 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3242 {
3243         /*
3244          * Patch in the VMCALL instruction:
3245          */
3246         hypercall[0] = 0x0f;
3247         hypercall[1] = 0x01;
3248         hypercall[2] = 0xc1;
3249 }
3250
3251 static int handle_cr(struct kvm_vcpu *vcpu)
3252 {
3253         unsigned long exit_qualification, val;
3254         int cr;
3255         int reg;
3256         int err;
3257
3258         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3259         cr = exit_qualification & 15;
3260         reg = (exit_qualification >> 8) & 15;
3261         switch ((exit_qualification >> 4) & 3) {
3262         case 0: /* mov to cr */
3263                 val = kvm_register_read(vcpu, reg);
3264                 trace_kvm_cr_write(cr, val);
3265                 switch (cr) {
3266                 case 0:
3267                         err = kvm_set_cr0(vcpu, val);
3268                         kvm_complete_insn_gp(vcpu, err);
3269                         return 1;
3270                 case 3:
3271                         err = kvm_set_cr3(vcpu, val);
3272                         kvm_complete_insn_gp(vcpu, err);
3273                         return 1;
3274                 case 4:
3275                         err = kvm_set_cr4(vcpu, val);
3276                         kvm_complete_insn_gp(vcpu, err);
3277                         return 1;
3278                 case 8: {
3279                                 u8 cr8_prev = kvm_get_cr8(vcpu);
3280                                 u8 cr8 = kvm_register_read(vcpu, reg);
3281                                 err = kvm_set_cr8(vcpu, cr8);
3282                                 kvm_complete_insn_gp(vcpu, err);
3283                                 if (irqchip_in_kernel(vcpu->kvm))
3284                                         return 1;
3285                                 if (cr8_prev <= cr8)
3286                                         return 1;
3287                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
3288                                 return 0;
3289                         }
3290                 };
3291                 break;
3292         case 2: /* clts */
3293                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
3294                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
3295                 skip_emulated_instruction(vcpu);
3296                 vmx_fpu_activate(vcpu);
3297                 return 1;
3298         case 1: /*mov from cr*/
3299                 switch (cr) {
3300                 case 3:
3301                         val = kvm_read_cr3(vcpu);
3302                         kvm_register_write(vcpu, reg, val);
3303                         trace_kvm_cr_read(cr, val);
3304                         skip_emulated_instruction(vcpu);
3305                         return 1;
3306                 case 8:
3307                         val = kvm_get_cr8(vcpu);
3308                         kvm_register_write(vcpu, reg, val);
3309                         trace_kvm_cr_read(cr, val);
3310                         skip_emulated_instruction(vcpu);
3311                         return 1;
3312                 }
3313                 break;
3314         case 3: /* lmsw */
3315                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
3316                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
3317                 kvm_lmsw(vcpu, val);
3318
3319                 skip_emulated_instruction(vcpu);
3320                 return 1;
3321         default:
3322                 break;
3323         }
3324         vcpu->run->exit_reason = 0;
3325         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
3326                (int)(exit_qualification >> 4) & 3, cr);
3327         return 0;
3328 }
3329
3330 static int handle_dr(struct kvm_vcpu *vcpu)
3331 {
3332         unsigned long exit_qualification;
3333         int dr, reg;
3334
3335         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
3336         if (!kvm_require_cpl(vcpu, 0))
3337                 return 1;
3338         dr = vmcs_readl(GUEST_DR7);
3339         if (dr & DR7_GD) {
3340                 /*
3341                  * As the vm-exit takes precedence over the debug trap, we
3342                  * need to emulate the latter, either for the host or the
3343                  * guest debugging itself.
3344                  */
3345                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
3346                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3347                         vcpu->run->debug.arch.dr7 = dr;
3348                         vcpu->run->debug.arch.pc =
3349                                 vmcs_readl(GUEST_CS_BASE) +
3350                                 vmcs_readl(GUEST_RIP);
3351                         vcpu->run->debug.arch.exception = DB_VECTOR;
3352                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3353                         return 0;
3354                 } else {
3355                         vcpu->arch.dr7 &= ~DR7_GD;
3356                         vcpu->arch.dr6 |= DR6_BD;
3357                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3358                         kvm_queue_exception(vcpu, DB_VECTOR);
3359                         return 1;
3360                 }
3361         }
3362
3363         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3364         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3365         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3366         if (exit_qualification & TYPE_MOV_FROM_DR) {
3367                 unsigned long val;
3368                 if (!kvm_get_dr(vcpu, dr, &val))
3369                         kvm_register_write(vcpu, reg, val);
3370         } else
3371                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
3372         skip_emulated_instruction(vcpu);
3373         return 1;
3374 }
3375
3376 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3377 {
3378         vmcs_writel(GUEST_DR7, val);
3379 }
3380
3381 static int handle_cpuid(struct kvm_vcpu *vcpu)
3382 {
3383         kvm_emulate_cpuid(vcpu);
3384         return 1;
3385 }
3386
3387 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3388 {
3389         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3390         u64 data;
3391
3392         if (vmx_get_msr(vcpu, ecx, &data)) {
3393                 trace_kvm_msr_read_ex(ecx);
3394                 kvm_inject_gp(vcpu, 0);
3395                 return 1;
3396         }
3397
3398         trace_kvm_msr_read(ecx, data);
3399
3400         /* FIXME: handling of bits 32:63 of rax, rdx */
3401         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3402         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3403         skip_emulated_instruction(vcpu);
3404         return 1;
3405 }
3406
3407 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3408 {
3409         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3410         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3411                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3412
3413         if (vmx_set_msr(vcpu, ecx, data) != 0) {
3414                 trace_kvm_msr_write_ex(ecx, data);
3415                 kvm_inject_gp(vcpu, 0);
3416                 return 1;
3417         }
3418
3419         trace_kvm_msr_write(ecx, data);
3420         skip_emulated_instruction(vcpu);
3421         return 1;
3422 }
3423
3424 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3425 {
3426         kvm_make_request(KVM_REQ_EVENT, vcpu);
3427         return 1;
3428 }
3429
3430 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3431 {
3432         u32 cpu_based_vm_exec_control;
3433
3434         /* clear pending irq */
3435         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3436         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3437         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3438
3439         kvm_make_request(KVM_REQ_EVENT, vcpu);
3440
3441         ++vcpu->stat.irq_window_exits;
3442
3443         /*
3444          * If the user space waits to inject interrupts, exit as soon as
3445          * possible
3446          */
3447         if (!irqchip_in_kernel(vcpu->kvm) &&
3448             vcpu->run->request_interrupt_window &&
3449             !kvm_cpu_has_interrupt(vcpu)) {
3450                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3451                 return 0;
3452         }
3453         return 1;
3454 }
3455
3456 static int handle_halt(struct kvm_vcpu *vcpu)
3457 {
3458         skip_emulated_instruction(vcpu);
3459         return kvm_emulate_halt(vcpu);
3460 }
3461
3462 static int handle_vmcall(struct kvm_vcpu *vcpu)
3463 {
3464         skip_emulated_instruction(vcpu);
3465         kvm_emulate_hypercall(vcpu);
3466         return 1;
3467 }
3468
3469 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3470 {
3471         kvm_queue_exception(vcpu, UD_VECTOR);
3472         return 1;
3473 }
3474
3475 static int handle_invd(struct kvm_vcpu *vcpu)
3476 {
3477         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
3478 }
3479
3480 static int handle_invlpg(struct kvm_vcpu *vcpu)
3481 {
3482         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3483
3484         kvm_mmu_invlpg(vcpu, exit_qualification);
3485         skip_emulated_instruction(vcpu);
3486         return 1;
3487 }
3488
3489 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3490 {
3491         skip_emulated_instruction(vcpu);
3492         kvm_emulate_wbinvd(vcpu);
3493         return 1;
3494 }
3495
3496 static int handle_xsetbv(struct kvm_vcpu *vcpu)
3497 {
3498         u64 new_bv = kvm_read_edx_eax(vcpu);
3499         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3500
3501         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
3502                 skip_emulated_instruction(vcpu);
3503         return 1;
3504 }
3505
3506 static int handle_apic_access(struct kvm_vcpu *vcpu)
3507 {
3508         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
3509 }
3510
3511 static int handle_task_switch(struct kvm_vcpu *vcpu)
3512 {
3513         struct vcpu_vmx *vmx = to_vmx(vcpu);
3514         unsigned long exit_qualification;
3515         bool has_error_code = false;
3516         u32 error_code = 0;
3517         u16 tss_selector;
3518         int reason, type, idt_v;
3519
3520         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3521         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3522
3523         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3524
3525         reason = (u32)exit_qualification >> 30;
3526         if (reason == TASK_SWITCH_GATE && idt_v) {
3527                 switch (type) {
3528                 case INTR_TYPE_NMI_INTR:
3529                         vcpu->arch.nmi_injected = false;
3530                         if (cpu_has_virtual_nmis())
3531                                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3532                                               GUEST_INTR_STATE_NMI);
3533                         break;
3534                 case INTR_TYPE_EXT_INTR:
3535                 case INTR_TYPE_SOFT_INTR:
3536                         kvm_clear_interrupt_queue(vcpu);
3537                         break;
3538                 case INTR_TYPE_HARD_EXCEPTION:
3539                         if (vmx->idt_vectoring_info &
3540                             VECTORING_INFO_DELIVER_CODE_MASK) {
3541                                 has_error_code = true;
3542                                 error_code =
3543                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
3544                         }
3545                         /* fall through */
3546                 case INTR_TYPE_SOFT_EXCEPTION:
3547                         kvm_clear_exception_queue(vcpu);
3548                         break;
3549                 default:
3550                         break;
3551                 }
3552         }
3553         tss_selector = exit_qualification;
3554
3555         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3556                        type != INTR_TYPE_EXT_INTR &&
3557                        type != INTR_TYPE_NMI_INTR))
3558                 skip_emulated_instruction(vcpu);
3559
3560         if (kvm_task_switch(vcpu, tss_selector, reason,
3561                                 has_error_code, error_code) == EMULATE_FAIL) {
3562                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3563                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3564                 vcpu->run->internal.ndata = 0;
3565                 return 0;
3566         }
3567
3568         /* clear all local breakpoint enable flags */
3569         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3570
3571         /*
3572          * TODO: What about debug traps on tss switch?
3573          *       Are we supposed to inject them and update dr6?
3574          */
3575
3576         return 1;
3577 }
3578
3579 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3580 {
3581         unsigned long exit_qualification;
3582         gpa_t gpa;
3583         int gla_validity;
3584
3585         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3586
3587         if (exit_qualification & (1 << 6)) {
3588                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3589                 return -EINVAL;
3590         }
3591
3592         gla_validity = (exit_qualification >> 7) & 0x3;
3593         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3594                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3595                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3596                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3597                         vmcs_readl(GUEST_LINEAR_ADDRESS));
3598                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3599                         (long unsigned int)exit_qualification);
3600                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3601                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3602                 return 0;
3603         }
3604
3605         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3606         trace_kvm_page_fault(gpa, exit_qualification);
3607         return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
3608 }
3609
3610 static u64 ept_rsvd_mask(u64 spte, int level)
3611 {
3612         int i;
3613         u64 mask = 0;
3614
3615         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3616                 mask |= (1ULL << i);
3617
3618         if (level > 2)
3619                 /* bits 7:3 reserved */
3620                 mask |= 0xf8;
3621         else if (level == 2) {
3622                 if (spte & (1ULL << 7))
3623                         /* 2MB ref, bits 20:12 reserved */
3624                         mask |= 0x1ff000;
3625                 else
3626                         /* bits 6:3 reserved */
3627                         mask |= 0x78;
3628         }
3629
3630         return mask;
3631 }
3632
3633 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3634                                        int level)
3635 {
3636         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3637
3638         /* 010b (write-only) */
3639         WARN_ON((spte & 0x7) == 0x2);
3640
3641         /* 110b (write/execute) */
3642         WARN_ON((spte & 0x7) == 0x6);
3643
3644         /* 100b (execute-only) and value not supported by logical processor */
3645         if (!cpu_has_vmx_ept_execute_only())
3646                 WARN_ON((spte & 0x7) == 0x4);
3647
3648         /* not 000b */
3649         if ((spte & 0x7)) {
3650                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3651
3652                 if (rsvd_bits != 0) {
3653                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3654                                          __func__, rsvd_bits);
3655                         WARN_ON(1);
3656                 }
3657
3658                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3659                         u64 ept_mem_type = (spte & 0x38) >> 3;
3660
3661                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
3662                             ept_mem_type == 7) {
3663                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3664                                                 __func__, ept_mem_type);
3665                                 WARN_ON(1);
3666                         }
3667                 }
3668         }
3669 }
3670
3671 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3672 {
3673         u64 sptes[4];
3674         int nr_sptes, i;
3675         gpa_t gpa;
3676
3677         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3678
3679         printk(KERN_ERR "EPT: Misconfiguration.\n");
3680         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3681
3682         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3683
3684         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3685                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3686
3687         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3688         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3689
3690         return 0;
3691 }
3692
3693 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3694 {
3695         u32 cpu_based_vm_exec_control;
3696
3697         /* clear pending NMI */
3698         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3699         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3700         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3701         ++vcpu->stat.nmi_window_exits;
3702         kvm_make_request(KVM_REQ_EVENT, vcpu);
3703
3704         return 1;
3705 }
3706
3707 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3708 {
3709         struct vcpu_vmx *vmx = to_vmx(vcpu);
3710         enum emulation_result err = EMULATE_DONE;
3711         int ret = 1;
3712         u32 cpu_exec_ctrl;
3713         bool intr_window_requested;
3714
3715         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3716         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
3717
3718         while (!guest_state_valid(vcpu)) {
3719                 if (intr_window_requested
3720                     && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
3721                         return handle_interrupt_window(&vmx->vcpu);
3722
3723                 err = emulate_instruction(vcpu, 0);
3724
3725                 if (err == EMULATE_DO_MMIO) {
3726                         ret = 0;
3727                         goto out;
3728                 }
3729
3730                 if (err != EMULATE_DONE)
3731                         return 0;
3732
3733                 if (signal_pending(current))
3734                         goto out;
3735                 if (need_resched())
3736                         schedule();
3737         }
3738
3739         vmx->emulation_required = 0;
3740 out:
3741         return ret;
3742 }
3743
3744 /*
3745  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3746  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3747  */
3748 static int handle_pause(struct kvm_vcpu *vcpu)
3749 {
3750         skip_emulated_instruction(vcpu);
3751         kvm_vcpu_on_spin(vcpu);
3752
3753         return 1;
3754 }
3755
3756 static int handle_invalid_op(struct kvm_vcpu *vcpu)
3757 {
3758         kvm_queue_exception(vcpu, UD_VECTOR);
3759         return 1;
3760 }
3761
3762 /*
3763  * The exit handlers return 1 if the exit was handled fully and guest execution
3764  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
3765  * to be done to userspace and return 0.
3766  */
3767 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3768         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
3769         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
3770         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
3771         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
3772         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
3773         [EXIT_REASON_CR_ACCESS]               = handle_cr,
3774         [EXIT_REASON_DR_ACCESS]               = handle_dr,
3775         [EXIT_REASON_CPUID]                   = handle_cpuid,
3776         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
3777         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
3778         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
3779         [EXIT_REASON_HLT]                     = handle_halt,
3780         [EXIT_REASON_INVD]                    = handle_invd,
3781         [EXIT_REASON_INVLPG]                  = handle_invlpg,
3782         [EXIT_REASON_VMCALL]                  = handle_vmcall,
3783         [EXIT_REASON_VMCLEAR]                 = handle_vmx_insn,
3784         [EXIT_REASON_VMLAUNCH]                = handle_vmx_insn,
3785         [EXIT_REASON_VMPTRLD]                 = handle_vmx_insn,
3786         [EXIT_REASON_VMPTRST]                 = handle_vmx_insn,
3787         [EXIT_REASON_VMREAD]                  = handle_vmx_insn,
3788         [EXIT_REASON_VMRESUME]                = handle_vmx_insn,
3789         [EXIT_REASON_VMWRITE]                 = handle_vmx_insn,
3790         [EXIT_REASON_VMOFF]                   = handle_vmx_insn,
3791         [EXIT_REASON_VMON]                    = handle_vmx_insn,
3792         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
3793         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
3794         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
3795         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
3796         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
3797         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
3798         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
3799         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
3800         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
3801         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
3802         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
3803 };
3804
3805 static const int kvm_vmx_max_exit_handlers =
3806         ARRAY_SIZE(kvm_vmx_exit_handlers);
3807
3808 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3809 {
3810         *info1 = vmcs_readl(EXIT_QUALIFICATION);
3811         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
3812 }
3813
3814 /*
3815  * The guest has exited.  See if we can fix it or if we need userspace
3816  * assistance.
3817  */
3818 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3819 {
3820         struct vcpu_vmx *vmx = to_vmx(vcpu);
3821         u32 exit_reason = vmx->exit_reason;
3822         u32 vectoring_info = vmx->idt_vectoring_info;
3823
3824         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
3825
3826         /* If guest state is invalid, start emulating */
3827         if (vmx->emulation_required && emulate_invalid_guest_state)
3828                 return handle_invalid_guest_state(vcpu);
3829
3830         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
3831                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3832                 vcpu->run->fail_entry.hardware_entry_failure_reason
3833                         = exit_reason;
3834                 return 0;
3835         }
3836
3837         if (unlikely(vmx->fail)) {
3838                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3839                 vcpu->run->fail_entry.hardware_entry_failure_reason
3840                         = vmcs_read32(VM_INSTRUCTION_ERROR);
3841                 return 0;
3842         }
3843
3844         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3845                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3846                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
3847                         exit_reason != EXIT_REASON_TASK_SWITCH))
3848                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3849                        "(0x%x) and exit reason is 0x%x\n",
3850                        __func__, vectoring_info, exit_reason);
3851
3852         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3853                 if (vmx_interrupt_allowed(vcpu)) {
3854                         vmx->soft_vnmi_blocked = 0;
3855                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3856                            vcpu->arch.nmi_pending) {
3857                         /*
3858                          * This CPU don't support us in finding the end of an
3859                          * NMI-blocked window if the guest runs with IRQs
3860                          * disabled. So we pull the trigger after 1 s of
3861                          * futile waiting, but inform the user about this.
3862                          */
3863                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3864                                "state on VCPU %d after 1 s timeout\n",
3865                                __func__, vcpu->vcpu_id);
3866                         vmx->soft_vnmi_blocked = 0;
3867                 }
3868         }
3869
3870         if (exit_reason < kvm_vmx_max_exit_handlers
3871             && kvm_vmx_exit_handlers[exit_reason])
3872                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3873         else {
3874                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3875                 vcpu->run->hw.hardware_exit_reason = exit_reason;
3876         }
3877         return 0;
3878 }
3879
3880 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3881 {
3882         if (irr == -1 || tpr < irr) {
3883                 vmcs_write32(TPR_THRESHOLD, 0);
3884                 return;
3885         }
3886
3887         vmcs_write32(TPR_THRESHOLD, irr);
3888 }
3889
3890 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
3891 {
3892         u32 exit_intr_info = vmx->exit_intr_info;
3893
3894         /* Handle machine checks before interrupts are enabled */
3895         if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3896             || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3897                 && is_machine_check(exit_intr_info)))
3898                 kvm_machine_check();
3899
3900         /* We need to handle NMIs before interrupts are enabled */
3901         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3902             (exit_intr_info & INTR_INFO_VALID_MASK)) {
3903                 kvm_before_handle_nmi(&vmx->vcpu);
3904                 asm("int $2");
3905                 kvm_after_handle_nmi(&vmx->vcpu);
3906         }
3907 }
3908
3909 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
3910 {
3911         u32 exit_intr_info = vmx->exit_intr_info;
3912         bool unblock_nmi;
3913         u8 vector;
3914         bool idtv_info_valid;
3915
3916         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3917
3918         if (cpu_has_virtual_nmis()) {
3919                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3920                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3921                 /*
3922                  * SDM 3: 27.7.1.2 (September 2008)
3923                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
3924                  * a guest IRET fault.
3925                  * SDM 3: 23.2.2 (September 2008)
3926                  * Bit 12 is undefined in any of the following cases:
3927                  *  If the VM exit sets the valid bit in the IDT-vectoring
3928                  *   information field.
3929                  *  If the VM exit is due to a double fault.
3930                  */
3931                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3932                     vector != DF_VECTOR && !idtv_info_valid)
3933                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3934                                       GUEST_INTR_STATE_NMI);
3935         } else if (unlikely(vmx->soft_vnmi_blocked))
3936                 vmx->vnmi_blocked_time +=
3937                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3938 }
3939
3940 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
3941                                       u32 idt_vectoring_info,
3942                                       int instr_len_field,
3943                                       int error_code_field)
3944 {
3945         u8 vector;
3946         int type;
3947         bool idtv_info_valid;
3948
3949         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3950
3951         vmx->vcpu.arch.nmi_injected = false;
3952         kvm_clear_exception_queue(&vmx->vcpu);
3953         kvm_clear_interrupt_queue(&vmx->vcpu);
3954
3955         if (!idtv_info_valid)
3956                 return;
3957
3958         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
3959
3960         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3961         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3962
3963         switch (type) {
3964         case INTR_TYPE_NMI_INTR:
3965                 vmx->vcpu.arch.nmi_injected = true;
3966                 /*
3967                  * SDM 3: 27.7.1.2 (September 2008)
3968                  * Clear bit "block by NMI" before VM entry if a NMI
3969                  * delivery faulted.
3970                  */
3971                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3972                                 GUEST_INTR_STATE_NMI);
3973                 break;
3974         case INTR_TYPE_SOFT_EXCEPTION:
3975                 vmx->vcpu.arch.event_exit_inst_len =
3976                         vmcs_read32(instr_len_field);
3977                 /* fall through */
3978         case INTR_TYPE_HARD_EXCEPTION:
3979                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3980                         u32 err = vmcs_read32(error_code_field);
3981                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
3982                 } else
3983                         kvm_queue_exception(&vmx->vcpu, vector);
3984                 break;
3985         case INTR_TYPE_SOFT_INTR:
3986                 vmx->vcpu.arch.event_exit_inst_len =
3987                         vmcs_read32(instr_len_field);
3988                 /* fall through */
3989         case INTR_TYPE_EXT_INTR:
3990                 kvm_queue_interrupt(&vmx->vcpu, vector,
3991                         type == INTR_TYPE_SOFT_INTR);
3992                 break;
3993         default:
3994                 break;
3995         }
3996 }
3997
3998 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3999 {
4000         __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
4001                                   VM_EXIT_INSTRUCTION_LEN,
4002                                   IDT_VECTORING_ERROR_CODE);
4003 }
4004
4005 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
4006 {
4007         __vmx_complete_interrupts(to_vmx(vcpu),
4008                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
4009                                   VM_ENTRY_INSTRUCTION_LEN,
4010                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
4011
4012         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
4013 }
4014
4015 #ifdef CONFIG_X86_64
4016 #define R "r"
4017 #define Q "q"
4018 #else
4019 #define R "e"
4020 #define Q "l"
4021 #endif
4022
4023 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
4024 {
4025         struct vcpu_vmx *vmx = to_vmx(vcpu);
4026
4027         /* Record the guest's net vcpu time for enforced NMI injections. */
4028         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
4029                 vmx->entry_time = ktime_get();
4030
4031         /* Don't enter VMX if guest state is invalid, let the exit handler
4032            start emulation until we arrive back to a valid state */
4033         if (vmx->emulation_required && emulate_invalid_guest_state)
4034                 return;
4035
4036         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
4037                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
4038         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
4039                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
4040
4041         /* When single-stepping over STI and MOV SS, we must clear the
4042          * corresponding interruptibility bits in the guest state. Otherwise
4043          * vmentry fails as it then expects bit 14 (BS) in pending debug
4044          * exceptions being set, but that's not correct for the guest debugging
4045          * case. */
4046         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
4047                 vmx_set_interrupt_shadow(vcpu, 0);
4048
4049         asm(
4050                 /* Store host registers */
4051                 "push %%"R"dx; push %%"R"bp;"
4052                 "push %%"R"cx \n\t" /* placeholder for guest rcx */
4053                 "push %%"R"cx \n\t"
4054                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
4055                 "je 1f \n\t"
4056                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4057                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
4058                 "1: \n\t"
4059                 /* Reload cr2 if changed */
4060                 "mov %c[cr2](%0), %%"R"ax \n\t"
4061                 "mov %%cr2, %%"R"dx \n\t"
4062                 "cmp %%"R"ax, %%"R"dx \n\t"
4063                 "je 2f \n\t"
4064                 "mov %%"R"ax, %%cr2 \n\t"
4065                 "2: \n\t"
4066                 /* Check if vmlaunch of vmresume is needed */
4067                 "cmpl $0, %c[launched](%0) \n\t"
4068                 /* Load guest registers.  Don't clobber flags. */
4069                 "mov %c[rax](%0), %%"R"ax \n\t"
4070                 "mov %c[rbx](%0), %%"R"bx \n\t"
4071                 "mov %c[rdx](%0), %%"R"dx \n\t"
4072                 "mov %c[rsi](%0), %%"R"si \n\t"
4073                 "mov %c[rdi](%0), %%"R"di \n\t"
4074                 "mov %c[rbp](%0), %%"R"bp \n\t"
4075 #ifdef CONFIG_X86_64
4076                 "mov %c[r8](%0),  %%r8  \n\t"
4077                 "mov %c[r9](%0),  %%r9  \n\t"
4078                 "mov %c[r10](%0), %%r10 \n\t"
4079                 "mov %c[r11](%0), %%r11 \n\t"
4080                 "mov %c[r12](%0), %%r12 \n\t"
4081                 "mov %c[r13](%0), %%r13 \n\t"
4082                 "mov %c[r14](%0), %%r14 \n\t"
4083                 "mov %c[r15](%0), %%r15 \n\t"
4084 #endif
4085                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
4086
4087                 /* Enter guest mode */
4088                 "jne .Llaunched \n\t"
4089                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
4090                 "jmp .Lkvm_vmx_return \n\t"
4091                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
4092                 ".Lkvm_vmx_return: "
4093                 /* Save guest registers, load host registers, keep flags */
4094                 "mov %0, %c[wordsize](%%"R"sp) \n\t"
4095                 "pop %0 \n\t"
4096                 "mov %%"R"ax, %c[rax](%0) \n\t"
4097                 "mov %%"R"bx, %c[rbx](%0) \n\t"
4098                 "pop"Q" %c[rcx](%0) \n\t"
4099                 "mov %%"R"dx, %c[rdx](%0) \n\t"
4100                 "mov %%"R"si, %c[rsi](%0) \n\t"
4101                 "mov %%"R"di, %c[rdi](%0) \n\t"
4102                 "mov %%"R"bp, %c[rbp](%0) \n\t"
4103 #ifdef CONFIG_X86_64
4104                 "mov %%r8,  %c[r8](%0) \n\t"
4105                 "mov %%r9,  %c[r9](%0) \n\t"
4106                 "mov %%r10, %c[r10](%0) \n\t"
4107                 "mov %%r11, %c[r11](%0) \n\t"
4108                 "mov %%r12, %c[r12](%0) \n\t"
4109                 "mov %%r13, %c[r13](%0) \n\t"
4110                 "mov %%r14, %c[r14](%0) \n\t"
4111                 "mov %%r15, %c[r15](%0) \n\t"
4112 #endif
4113                 "mov %%cr2, %%"R"ax   \n\t"
4114                 "mov %%"R"ax, %c[cr2](%0) \n\t"
4115
4116                 "pop  %%"R"bp; pop  %%"R"dx \n\t"
4117                 "setbe %c[fail](%0) \n\t"
4118               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
4119                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
4120                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
4121                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
4122                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
4123                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
4124                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
4125                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
4126                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
4127                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
4128                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
4129 #ifdef CONFIG_X86_64
4130                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
4131                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
4132                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
4133                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
4134                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
4135                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
4136                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
4137                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
4138 #endif
4139                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
4140                 [wordsize]"i"(sizeof(ulong))
4141               : "cc", "memory"
4142                 , R"ax", R"bx", R"di", R"si"
4143 #ifdef CONFIG_X86_64
4144                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4145 #endif
4146               );
4147
4148         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
4149                                   | (1 << VCPU_EXREG_RFLAGS)
4150                                   | (1 << VCPU_EXREG_CPL)
4151                                   | (1 << VCPU_EXREG_PDPTR)
4152                                   | (1 << VCPU_EXREG_CR3));
4153         vcpu->arch.regs_dirty = 0;
4154
4155         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
4156
4157         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
4158         vmx->launched = 1;
4159
4160         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
4161         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
4162
4163         vmx_complete_atomic_exit(vmx);
4164         vmx_recover_nmi_blocking(vmx);
4165         vmx_complete_interrupts(vmx);
4166 }
4167
4168 #undef R
4169 #undef Q
4170
4171 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
4172 {
4173         struct vcpu_vmx *vmx = to_vmx(vcpu);
4174
4175         if (vmx->vmcs) {
4176                 vcpu_clear(vmx);
4177                 free_vmcs(vmx->vmcs);
4178                 vmx->vmcs = NULL;
4179         }
4180 }
4181
4182 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4183 {
4184         struct vcpu_vmx *vmx = to_vmx(vcpu);
4185
4186         free_vpid(vmx);
4187         vmx_free_vmcs(vcpu);
4188         kfree(vmx->guest_msrs);
4189         kvm_vcpu_uninit(vcpu);
4190         kmem_cache_free(kvm_vcpu_cache, vmx);
4191 }
4192
4193 static inline void vmcs_init(struct vmcs *vmcs)
4194 {
4195         u64 phys_addr = __pa(per_cpu(vmxarea, raw_smp_processor_id()));
4196
4197         if (!vmm_exclusive)
4198                 kvm_cpu_vmxon(phys_addr);
4199
4200         vmcs_clear(vmcs);
4201
4202         if (!vmm_exclusive)
4203                 kvm_cpu_vmxoff();
4204 }
4205
4206 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
4207 {
4208         int err;
4209         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
4210         int cpu;
4211
4212         if (!vmx)
4213                 return ERR_PTR(-ENOMEM);
4214
4215         allocate_vpid(vmx);
4216
4217         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4218         if (err)
4219                 goto free_vcpu;
4220
4221         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
4222         if (!vmx->guest_msrs) {
4223                 err = -ENOMEM;
4224                 goto uninit_vcpu;
4225         }
4226
4227         vmx->vmcs = alloc_vmcs();
4228         if (!vmx->vmcs)
4229                 goto free_msrs;
4230
4231         vmcs_init(vmx->vmcs);
4232
4233         cpu = get_cpu();
4234         vmx_vcpu_load(&vmx->vcpu, cpu);
4235         vmx->vcpu.cpu = cpu;
4236         err = vmx_vcpu_setup(vmx);
4237         vmx_vcpu_put(&vmx->vcpu);
4238         put_cpu();
4239         if (err)
4240                 goto free_vmcs;
4241         if (vm_need_virtualize_apic_accesses(kvm))
4242                 if (alloc_apic_access_page(kvm) != 0)
4243                         goto free_vmcs;
4244
4245         if (enable_ept) {
4246                 if (!kvm->arch.ept_identity_map_addr)
4247                         kvm->arch.ept_identity_map_addr =
4248                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
4249                 err = -ENOMEM;
4250                 if (alloc_identity_pagetable(kvm) != 0)
4251                         goto free_vmcs;
4252                 if (!init_rmode_identity_map(kvm))
4253                         goto free_vmcs;
4254         }
4255
4256         return &vmx->vcpu;
4257
4258 free_vmcs:
4259         free_vmcs(vmx->vmcs);
4260 free_msrs:
4261         kfree(vmx->guest_msrs);
4262 uninit_vcpu:
4263         kvm_vcpu_uninit(&vmx->vcpu);
4264 free_vcpu:
4265         free_vpid(vmx);
4266         kmem_cache_free(kvm_vcpu_cache, vmx);
4267         return ERR_PTR(err);
4268 }
4269
4270 static void __init vmx_check_processor_compat(void *rtn)
4271 {
4272         struct vmcs_config vmcs_conf;
4273
4274         *(int *)rtn = 0;
4275         if (setup_vmcs_config(&vmcs_conf) < 0)
4276                 *(int *)rtn = -EIO;
4277         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4278                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4279                                 smp_processor_id());
4280                 *(int *)rtn = -EIO;
4281         }
4282 }
4283
4284 static int get_ept_level(void)
4285 {
4286         return VMX_EPT_DEFAULT_GAW + 1;
4287 }
4288
4289 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4290 {
4291         u64 ret;
4292
4293         /* For VT-d and EPT combination
4294          * 1. MMIO: always map as UC
4295          * 2. EPT with VT-d:
4296          *   a. VT-d without snooping control feature: can't guarantee the
4297          *      result, try to trust guest.
4298          *   b. VT-d with snooping control feature: snooping control feature of
4299          *      VT-d engine can guarantee the cache correctness. Just set it
4300          *      to WB to keep consistent with host. So the same as item 3.
4301          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
4302          *    consistent with host MTRR
4303          */
4304         if (is_mmio)
4305                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
4306         else if (vcpu->kvm->arch.iommu_domain &&
4307                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4308                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4309                       VMX_EPT_MT_EPTE_SHIFT;
4310         else
4311                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
4312                         | VMX_EPT_IPAT_BIT;
4313
4314         return ret;
4315 }
4316
4317 #define _ER(x) { EXIT_REASON_##x, #x }
4318
4319 static const struct trace_print_flags vmx_exit_reasons_str[] = {
4320         _ER(EXCEPTION_NMI),
4321         _ER(EXTERNAL_INTERRUPT),
4322         _ER(TRIPLE_FAULT),
4323         _ER(PENDING_INTERRUPT),
4324         _ER(NMI_WINDOW),
4325         _ER(TASK_SWITCH),
4326         _ER(CPUID),
4327         _ER(HLT),
4328         _ER(INVLPG),
4329         _ER(RDPMC),
4330         _ER(RDTSC),
4331         _ER(VMCALL),
4332         _ER(VMCLEAR),
4333         _ER(VMLAUNCH),
4334         _ER(VMPTRLD),
4335         _ER(VMPTRST),
4336         _ER(VMREAD),
4337         _ER(VMRESUME),
4338         _ER(VMWRITE),
4339         _ER(VMOFF),
4340         _ER(VMON),
4341         _ER(CR_ACCESS),
4342         _ER(DR_ACCESS),
4343         _ER(IO_INSTRUCTION),
4344         _ER(MSR_READ),
4345         _ER(MSR_WRITE),
4346         _ER(MWAIT_INSTRUCTION),
4347         _ER(MONITOR_INSTRUCTION),
4348         _ER(PAUSE_INSTRUCTION),
4349         _ER(MCE_DURING_VMENTRY),
4350         _ER(TPR_BELOW_THRESHOLD),
4351         _ER(APIC_ACCESS),
4352         _ER(EPT_VIOLATION),
4353         _ER(EPT_MISCONFIG),
4354         _ER(WBINVD),
4355         { -1, NULL }
4356 };
4357
4358 #undef _ER
4359
4360 static int vmx_get_lpage_level(void)
4361 {
4362         if (enable_ept && !cpu_has_vmx_ept_1g_page())
4363                 return PT_DIRECTORY_LEVEL;
4364         else
4365                 /* For shadow and EPT supported 1GB page */
4366                 return PT_PDPE_LEVEL;
4367 }
4368
4369 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4370 {
4371         struct kvm_cpuid_entry2 *best;
4372         struct vcpu_vmx *vmx = to_vmx(vcpu);
4373         u32 exec_control;
4374
4375         vmx->rdtscp_enabled = false;
4376         if (vmx_rdtscp_supported()) {
4377                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4378                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4379                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4380                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4381                                 vmx->rdtscp_enabled = true;
4382                         else {
4383                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4384                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4385                                                 exec_control);
4386                         }
4387                 }
4388         }
4389 }
4390
4391 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4392 {
4393 }
4394
4395 static struct kvm_x86_ops vmx_x86_ops = {
4396         .cpu_has_kvm_support = cpu_has_kvm_support,
4397         .disabled_by_bios = vmx_disabled_by_bios,
4398         .hardware_setup = hardware_setup,
4399         .hardware_unsetup = hardware_unsetup,
4400         .check_processor_compatibility = vmx_check_processor_compat,
4401         .hardware_enable = hardware_enable,
4402         .hardware_disable = hardware_disable,
4403         .cpu_has_accelerated_tpr = report_flexpriority,
4404
4405         .vcpu_create = vmx_create_vcpu,
4406         .vcpu_free = vmx_free_vcpu,
4407         .vcpu_reset = vmx_vcpu_reset,
4408
4409         .prepare_guest_switch = vmx_save_host_state,
4410         .vcpu_load = vmx_vcpu_load,
4411         .vcpu_put = vmx_vcpu_put,
4412
4413         .set_guest_debug = set_guest_debug,
4414         .get_msr = vmx_get_msr,
4415         .set_msr = vmx_set_msr,
4416         .get_segment_base = vmx_get_segment_base,
4417         .get_segment = vmx_get_segment,
4418         .set_segment = vmx_set_segment,
4419         .get_cpl = vmx_get_cpl,
4420         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
4421         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
4422         .decache_cr3 = vmx_decache_cr3,
4423         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
4424         .set_cr0 = vmx_set_cr0,
4425         .set_cr3 = vmx_set_cr3,
4426         .set_cr4 = vmx_set_cr4,
4427         .set_efer = vmx_set_efer,
4428         .get_idt = vmx_get_idt,
4429         .set_idt = vmx_set_idt,
4430         .get_gdt = vmx_get_gdt,
4431         .set_gdt = vmx_set_gdt,
4432         .set_dr7 = vmx_set_dr7,
4433         .cache_reg = vmx_cache_reg,
4434         .get_rflags = vmx_get_rflags,
4435         .set_rflags = vmx_set_rflags,
4436         .fpu_activate = vmx_fpu_activate,
4437         .fpu_deactivate = vmx_fpu_deactivate,
4438
4439         .tlb_flush = vmx_flush_tlb,
4440
4441         .run = vmx_vcpu_run,
4442         .handle_exit = vmx_handle_exit,
4443         .skip_emulated_instruction = skip_emulated_instruction,
4444         .set_interrupt_shadow = vmx_set_interrupt_shadow,
4445         .get_interrupt_shadow = vmx_get_interrupt_shadow,
4446         .patch_hypercall = vmx_patch_hypercall,
4447         .set_irq = vmx_inject_irq,
4448         .set_nmi = vmx_inject_nmi,
4449         .queue_exception = vmx_queue_exception,
4450         .cancel_injection = vmx_cancel_injection,
4451         .interrupt_allowed = vmx_interrupt_allowed,
4452         .nmi_allowed = vmx_nmi_allowed,
4453         .get_nmi_mask = vmx_get_nmi_mask,
4454         .set_nmi_mask = vmx_set_nmi_mask,
4455         .enable_nmi_window = enable_nmi_window,
4456         .enable_irq_window = enable_irq_window,
4457         .update_cr8_intercept = update_cr8_intercept,
4458
4459         .set_tss_addr = vmx_set_tss_addr,
4460         .get_tdp_level = get_ept_level,
4461         .get_mt_mask = vmx_get_mt_mask,
4462
4463         .get_exit_info = vmx_get_exit_info,
4464         .exit_reasons_str = vmx_exit_reasons_str,
4465
4466         .get_lpage_level = vmx_get_lpage_level,
4467
4468         .cpuid_update = vmx_cpuid_update,
4469
4470         .rdtscp_supported = vmx_rdtscp_supported,
4471
4472         .set_supported_cpuid = vmx_set_supported_cpuid,
4473
4474         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
4475
4476         .write_tsc_offset = vmx_write_tsc_offset,
4477         .adjust_tsc_offset = vmx_adjust_tsc_offset,
4478
4479         .set_tdp_cr3 = vmx_set_cr3,
4480 };
4481
4482 static int __init vmx_init(void)
4483 {
4484         int r, i;
4485
4486         rdmsrl_safe(MSR_EFER, &host_efer);
4487
4488         for (i = 0; i < NR_VMX_MSR; ++i)
4489                 kvm_define_shared_msr(i, vmx_msr_index[i]);
4490
4491         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4492         if (!vmx_io_bitmap_a)
4493                 return -ENOMEM;
4494
4495         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4496         if (!vmx_io_bitmap_b) {
4497                 r = -ENOMEM;
4498                 goto out;
4499         }
4500
4501         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4502         if (!vmx_msr_bitmap_legacy) {
4503                 r = -ENOMEM;
4504                 goto out1;
4505         }
4506
4507         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4508         if (!vmx_msr_bitmap_longmode) {
4509                 r = -ENOMEM;
4510                 goto out2;
4511         }
4512
4513         /*
4514          * Allow direct access to the PC debug port (it is often used for I/O
4515          * delays, but the vmexits simply slow things down).
4516          */
4517         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4518         clear_bit(0x80, vmx_io_bitmap_a);
4519
4520         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4521
4522         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4523         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4524
4525         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4526
4527         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4528                      __alignof__(struct vcpu_vmx), THIS_MODULE);
4529         if (r)
4530                 goto out3;
4531
4532         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4533         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4534         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4535         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4536         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4537         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4538
4539         if (enable_ept) {
4540                 bypass_guest_pf = 0;
4541                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4542                                 VMX_EPT_EXECUTABLE_MASK);
4543                 kvm_enable_tdp();
4544         } else
4545                 kvm_disable_tdp();
4546
4547         if (bypass_guest_pf)
4548                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4549
4550         return 0;
4551
4552 out3:
4553         free_page((unsigned long)vmx_msr_bitmap_longmode);
4554 out2:
4555         free_page((unsigned long)vmx_msr_bitmap_legacy);
4556 out1:
4557         free_page((unsigned long)vmx_io_bitmap_b);
4558 out:
4559         free_page((unsigned long)vmx_io_bitmap_a);
4560         return r;
4561 }
4562
4563 static void __exit vmx_exit(void)
4564 {
4565         free_page((unsigned long)vmx_msr_bitmap_legacy);
4566         free_page((unsigned long)vmx_msr_bitmap_longmode);
4567         free_page((unsigned long)vmx_io_bitmap_b);
4568         free_page((unsigned long)vmx_io_bitmap_a);
4569
4570         kvm_exit();
4571 }
4572
4573 module_init(vmx_init)
4574 module_exit(vmx_exit)