arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include <linux/hrtimer.h>
  35 #include "kvm_cache_regs.h"
  36 #include "x86.h"
  37
  38 #include <asm/io.h>
  39 #include <asm/desc.h>
  40 #include <asm/vmx.h>
  41 #include <asm/virtext.h>
  42 #include <asm/mce.h>
  43 #include <asm/i387.h>
  44 #include <asm/xcr.h>
  45 #include <asm/perf_event.h>
  46 #include <asm/debugreg.h>
  47 #include <asm/kexec.h>
  48
  49 #include "trace.h"
  50
  51 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  52 #define __ex_clear(x, reg) \
  53         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  54
  55 MODULE_AUTHOR("Qumranet");
  56 MODULE_LICENSE("GPL");
  57
  58 static const struct x86_cpu_id vmx_cpu_id[] = {
  59         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  60         {}
  61 };
  62 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  63
  64 static bool __read_mostly enable_vpid = 1;
  65 module_param_named(vpid, enable_vpid, bool, 0444);
  66
  67 static bool __read_mostly flexpriority_enabled = 1;
  68 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  69
  70 static bool __read_mostly enable_ept = 1;
  71 module_param_named(ept, enable_ept, bool, S_IRUGO);
  72
  73 static bool __read_mostly enable_unrestricted_guest = 1;
  74 module_param_named(unrestricted_guest,
  75                         enable_unrestricted_guest, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_ept_ad_bits = 1;
  78 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  79
  80 static bool __read_mostly emulate_invalid_guest_state = true;
  81 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  82
  83 static bool __read_mostly vmm_exclusive = 1;
  84 module_param(vmm_exclusive, bool, S_IRUGO);
  85
  86 static bool __read_mostly fasteoi = 1;
  87 module_param(fasteoi, bool, S_IRUGO);
  88
  89 static bool __read_mostly enable_apicv = 1;
  90 module_param(enable_apicv, bool, S_IRUGO);
  91
  92 static bool __read_mostly enable_shadow_vmcs = 1;
  93 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  94 /*
  95  * If nested=1, nested virtualization is supported, i.e., guests may use
  96  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  97  * use VMX instructions.
  98  */
  99 static bool __read_mostly nested = 0;
 100 module_param(nested, bool, S_IRUGO);
 101
 102 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 103 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 104 #define KVM_VM_CR0_ALWAYS_ON                                            \
 105         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 106 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 107         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 108          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 109
 110 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 111 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 112
 113 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 114
 115 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 116
 117 /*
 118  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 119  * ple_gap:    upper bound on the amount of time between two successive
 120  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 121  *             According to test, this time is usually smaller than 128 cycles.
 122  * ple_window: upper bound on the amount of time a guest is allowed to execute
 123  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 124  *             less than 2^12 cycles
 125  * Time is measured based on a counter that runs at the same rate as the TSC,
 126  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 127  */
 128 #define KVM_VMX_DEFAULT_PLE_GAP           128
 129 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 130 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 131 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 132 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 133                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 134
 135 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 136 module_param(ple_gap, int, S_IRUGO);
 137
 138 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 139 module_param(ple_window, int, S_IRUGO);
 140
 141 /* Default doubles per-vcpu window every exit. */
 142 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 143 module_param(ple_window_grow, int, S_IRUGO);
 144
 145 /* Default resets per-vcpu window every exit to ple_window. */
 146 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 147 module_param(ple_window_shrink, int, S_IRUGO);
 148
 149 /* Default is to compute the maximum so we can never overflow. */
 150 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 151 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 152 module_param(ple_window_max, int, S_IRUGO);
 153
 154 extern const ulong vmx_return;
 155
 156 #define NR_AUTOLOAD_MSRS 8
 157 #define VMCS02_POOL_SIZE 1
 158
 159 struct vmcs {
 160         u32 revision_id;
 161         u32 abort;
 162         char data[0];
 163 };
 164
 165 /*
 166  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 167  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 168  * loaded on this CPU (so we can clear them if the CPU goes down).
 169  */
 170 struct loaded_vmcs {
 171         struct vmcs *vmcs;
 172         int cpu;
 173         int launched;
 174         struct list_head loaded_vmcss_on_cpu_link;
 175 };
 176
 177 struct shared_msr_entry {
 178         unsigned index;
 179         u64 data;
 180         u64 mask;
 181 };
 182
 183 /*
 184  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 185  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 186  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 187  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 188  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 189  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 190  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 191  * underlying hardware which will be used to run L2.
 192  * This structure is packed to ensure that its layout is identical across
 193  * machines (necessary for live migration).
 194  * If there are changes in this struct, VMCS12_REVISION must be changed.
 195  */
 196 typedef u64 natural_width;
 197 struct __packed vmcs12 {
 198         /* According to the Intel spec, a VMCS region must start with the
 199          * following two fields. Then follow implementation-specific data.
 200          */
 201         u32 revision_id;
 202         u32 abort;
 203
 204         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 205         u32 padding[7]; /* room for future expansion */
 206
 207         u64 io_bitmap_a;
 208         u64 io_bitmap_b;
 209         u64 msr_bitmap;
 210         u64 vm_exit_msr_store_addr;
 211         u64 vm_exit_msr_load_addr;
 212         u64 vm_entry_msr_load_addr;
 213         u64 tsc_offset;
 214         u64 virtual_apic_page_addr;
 215         u64 apic_access_addr;
 216         u64 ept_pointer;
 217         u64 guest_physical_address;
 218         u64 vmcs_link_pointer;
 219         u64 guest_ia32_debugctl;
 220         u64 guest_ia32_pat;
 221         u64 guest_ia32_efer;
 222         u64 guest_ia32_perf_global_ctrl;
 223         u64 guest_pdptr0;
 224         u64 guest_pdptr1;
 225         u64 guest_pdptr2;
 226         u64 guest_pdptr3;
 227         u64 guest_bndcfgs;
 228         u64 host_ia32_pat;
 229         u64 host_ia32_efer;
 230         u64 host_ia32_perf_global_ctrl;
 231         u64 padding64[8]; /* room for future expansion */
 232         /*
 233          * To allow migration of L1 (complete with its L2 guests) between
 234          * machines of different natural widths (32 or 64 bit), we cannot have
 235          * unsigned long fields with no explict size. We use u64 (aliased
 236          * natural_width) instead. Luckily, x86 is little-endian.
 237          */
 238         natural_width cr0_guest_host_mask;
 239         natural_width cr4_guest_host_mask;
 240         natural_width cr0_read_shadow;
 241         natural_width cr4_read_shadow;
 242         natural_width cr3_target_value0;
 243         natural_width cr3_target_value1;
 244         natural_width cr3_target_value2;
 245         natural_width cr3_target_value3;
 246         natural_width exit_qualification;
 247         natural_width guest_linear_address;
 248         natural_width guest_cr0;
 249         natural_width guest_cr3;
 250         natural_width guest_cr4;
 251         natural_width guest_es_base;
 252         natural_width guest_cs_base;
 253         natural_width guest_ss_base;
 254         natural_width guest_ds_base;
 255         natural_width guest_fs_base;
 256         natural_width guest_gs_base;
 257         natural_width guest_ldtr_base;
 258         natural_width guest_tr_base;
 259         natural_width guest_gdtr_base;
 260         natural_width guest_idtr_base;
 261         natural_width guest_dr7;
 262         natural_width guest_rsp;
 263         natural_width guest_rip;
 264         natural_width guest_rflags;
 265         natural_width guest_pending_dbg_exceptions;
 266         natural_width guest_sysenter_esp;
 267         natural_width guest_sysenter_eip;
 268         natural_width host_cr0;
 269         natural_width host_cr3;
 270         natural_width host_cr4;
 271         natural_width host_fs_base;
 272         natural_width host_gs_base;
 273         natural_width host_tr_base;
 274         natural_width host_gdtr_base;
 275         natural_width host_idtr_base;
 276         natural_width host_ia32_sysenter_esp;
 277         natural_width host_ia32_sysenter_eip;
 278         natural_width host_rsp;
 279         natural_width host_rip;
 280         natural_width paddingl[8]; /* room for future expansion */
 281         u32 pin_based_vm_exec_control;
 282         u32 cpu_based_vm_exec_control;
 283         u32 exception_bitmap;
 284         u32 page_fault_error_code_mask;
 285         u32 page_fault_error_code_match;
 286         u32 cr3_target_count;
 287         u32 vm_exit_controls;
 288         u32 vm_exit_msr_store_count;
 289         u32 vm_exit_msr_load_count;
 290         u32 vm_entry_controls;
 291         u32 vm_entry_msr_load_count;
 292         u32 vm_entry_intr_info_field;
 293         u32 vm_entry_exception_error_code;
 294         u32 vm_entry_instruction_len;
 295         u32 tpr_threshold;
 296         u32 secondary_vm_exec_control;
 297         u32 vm_instruction_error;
 298         u32 vm_exit_reason;
 299         u32 vm_exit_intr_info;
 300         u32 vm_exit_intr_error_code;
 301         u32 idt_vectoring_info_field;
 302         u32 idt_vectoring_error_code;
 303         u32 vm_exit_instruction_len;
 304         u32 vmx_instruction_info;
 305         u32 guest_es_limit;
 306         u32 guest_cs_limit;
 307         u32 guest_ss_limit;
 308         u32 guest_ds_limit;
 309         u32 guest_fs_limit;
 310         u32 guest_gs_limit;
 311         u32 guest_ldtr_limit;
 312         u32 guest_tr_limit;
 313         u32 guest_gdtr_limit;
 314         u32 guest_idtr_limit;
 315         u32 guest_es_ar_bytes;
 316         u32 guest_cs_ar_bytes;
 317         u32 guest_ss_ar_bytes;
 318         u32 guest_ds_ar_bytes;
 319         u32 guest_fs_ar_bytes;
 320         u32 guest_gs_ar_bytes;
 321         u32 guest_ldtr_ar_bytes;
 322         u32 guest_tr_ar_bytes;
 323         u32 guest_interruptibility_info;
 324         u32 guest_activity_state;
 325         u32 guest_sysenter_cs;
 326         u32 host_ia32_sysenter_cs;
 327         u32 vmx_preemption_timer_value;
 328         u32 padding32[7]; /* room for future expansion */
 329         u16 virtual_processor_id;
 330         u16 guest_es_selector;
 331         u16 guest_cs_selector;
 332         u16 guest_ss_selector;
 333         u16 guest_ds_selector;
 334         u16 guest_fs_selector;
 335         u16 guest_gs_selector;
 336         u16 guest_ldtr_selector;
 337         u16 guest_tr_selector;
 338         u16 host_es_selector;
 339         u16 host_cs_selector;
 340         u16 host_ss_selector;
 341         u16 host_ds_selector;
 342         u16 host_fs_selector;
 343         u16 host_gs_selector;
 344         u16 host_tr_selector;
 345 };
 346
 347 /*
 348  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 349  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 350  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 351  */
 352 #define VMCS12_REVISION 0x11e57ed0
 353
 354 /*
 355  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 356  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 357  * current implementation, 4K are reserved to avoid future complications.
 358  */
 359 #define VMCS12_SIZE 0x1000
 360
 361 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 362 struct vmcs02_list {
 363         struct list_head list;
 364         gpa_t vmptr;
 365         struct loaded_vmcs vmcs02;
 366 };
 367
 368 /*
 369  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 370  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 371  */
 372 struct nested_vmx {
 373         /* Has the level1 guest done vmxon? */
 374         bool vmxon;
 375         gpa_t vmxon_ptr;
 376
 377         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 378         gpa_t current_vmptr;
 379         /* The host-usable pointer to the above */
 380         struct page *current_vmcs12_page;
 381         struct vmcs12 *current_vmcs12;
 382         struct vmcs *current_shadow_vmcs;
 383         /*
 384          * Indicates if the shadow vmcs must be updated with the
 385          * data hold by vmcs12
 386          */
 387         bool sync_shadow_vmcs;
 388
 389         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 390         struct list_head vmcs02_pool;
 391         int vmcs02_num;
 392         u64 vmcs01_tsc_offset;
 393         /* L2 must run next, and mustn't decide to exit to L1. */
 394         bool nested_run_pending;
 395         /*
 396          * Guest pages referred to in vmcs02 with host-physical pointers, so
 397          * we must keep them pinned while L2 runs.
 398          */
 399         struct page *apic_access_page;
 400         struct page *virtual_apic_page;
 401         u64 msr_ia32_feature_control;
 402
 403         struct hrtimer preemption_timer;
 404         bool preemption_timer_expired;
 405
 406         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 407         u64 vmcs01_debugctl;
 408 };
 409
 410 #define POSTED_INTR_ON  0
 411 /* Posted-Interrupt Descriptor */
 412 struct pi_desc {
 413         u32 pir[8];     /* Posted interrupt requested */
 414         u32 control;    /* bit 0 of control is outstanding notification bit */
 415         u32 rsvd[7];
 416 } __aligned(64);
 417
 418 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 419 {
 420         return test_and_set_bit(POSTED_INTR_ON,
 421                         (unsigned long *)&pi_desc->control);
 422 }
 423
 424 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 425 {
 426         return test_and_clear_bit(POSTED_INTR_ON,
 427                         (unsigned long *)&pi_desc->control);
 428 }
 429
 430 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 431 {
 432         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 433 }
 434
 435 struct vcpu_vmx {
 436         struct kvm_vcpu       vcpu;
 437         unsigned long         host_rsp;
 438         u8                    fail;
 439         bool                  nmi_known_unmasked;
 440         u32                   exit_intr_info;
 441         u32                   idt_vectoring_info;
 442         ulong                 rflags;
 443         struct shared_msr_entry *guest_msrs;
 444         int                   nmsrs;
 445         int                   save_nmsrs;
 446         unsigned long         host_idt_base;
 447 #ifdef CONFIG_X86_64
 448         u64                   msr_host_kernel_gs_base;
 449         u64                   msr_guest_kernel_gs_base;
 450 #endif
 451         u32 vm_entry_controls_shadow;
 452         u32 vm_exit_controls_shadow;
 453         /*
 454          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 455          * non-nested (L1) guest, it always points to vmcs01. For a nested
 456          * guest (L2), it points to a different VMCS.
 457          */
 458         struct loaded_vmcs    vmcs01;
 459         struct loaded_vmcs   *loaded_vmcs;
 460         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 461         struct msr_autoload {
 462                 unsigned nr;
 463                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 464                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 465         } msr_autoload;
 466         struct {
 467                 int           loaded;
 468                 u16           fs_sel, gs_sel, ldt_sel;
 469 #ifdef CONFIG_X86_64
 470                 u16           ds_sel, es_sel;
 471 #endif
 472                 int           gs_ldt_reload_needed;
 473                 int           fs_reload_needed;
 474                 u64           msr_host_bndcfgs;
 475                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 476         } host_state;
 477         struct {
 478                 int vm86_active;
 479                 ulong save_rflags;
 480                 struct kvm_segment segs[8];
 481         } rmode;
 482         struct {
 483                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 484                 struct kvm_save_segment {
 485                         u16 selector;
 486                         unsigned long base;
 487                         u32 limit;
 488                         u32 ar;
 489                 } seg[8];
 490         } segment_cache;
 491         int vpid;
 492         bool emulation_required;
 493
 494         /* Support for vnmi-less CPUs */
 495         int soft_vnmi_blocked;
 496         ktime_t entry_time;
 497         s64 vnmi_blocked_time;
 498         u32 exit_reason;
 499
 500         bool rdtscp_enabled;
 501
 502         /* Posted interrupt descriptor */
 503         struct pi_desc pi_desc;
 504
 505         /* Support for a guest hypervisor (nested VMX) */
 506         struct nested_vmx nested;
 507
 508         /* Dynamic PLE window. */
 509         int ple_window;
 510         bool ple_window_dirty;
 511 };
 512
 513 enum segment_cache_field {
 514         SEG_FIELD_SEL = 0,
 515         SEG_FIELD_BASE = 1,
 516         SEG_FIELD_LIMIT = 2,
 517         SEG_FIELD_AR = 3,
 518
 519         SEG_FIELD_NR = 4
 520 };
 521
 522 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 523 {
 524         return container_of(vcpu, struct vcpu_vmx, vcpu);
 525 }
 526
 527 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 528 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 529 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 530                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 531
 532
 533 static unsigned long shadow_read_only_fields[] = {
 534         /*
 535          * We do NOT shadow fields that are modified when L0
 536          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 537          * VMXON...) executed by L1.
 538          * For example, VM_INSTRUCTION_ERROR is read
 539          * by L1 if a vmx instruction fails (part of the error path).
 540          * Note the code assumes this logic. If for some reason
 541          * we start shadowing these fields then we need to
 542          * force a shadow sync when L0 emulates vmx instructions
 543          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 544          * by nested_vmx_failValid)
 545          */
 546         VM_EXIT_REASON,
 547         VM_EXIT_INTR_INFO,
 548         VM_EXIT_INSTRUCTION_LEN,
 549         IDT_VECTORING_INFO_FIELD,
 550         IDT_VECTORING_ERROR_CODE,
 551         VM_EXIT_INTR_ERROR_CODE,
 552         EXIT_QUALIFICATION,
 553         GUEST_LINEAR_ADDRESS,
 554         GUEST_PHYSICAL_ADDRESS
 555 };
 556 static int max_shadow_read_only_fields =
 557         ARRAY_SIZE(shadow_read_only_fields);
 558
 559 static unsigned long shadow_read_write_fields[] = {
 560         TPR_THRESHOLD,
 561         GUEST_RIP,
 562         GUEST_RSP,
 563         GUEST_CR0,
 564         GUEST_CR3,
 565         GUEST_CR4,
 566         GUEST_INTERRUPTIBILITY_INFO,
 567         GUEST_RFLAGS,
 568         GUEST_CS_SELECTOR,
 569         GUEST_CS_AR_BYTES,
 570         GUEST_CS_LIMIT,
 571         GUEST_CS_BASE,
 572         GUEST_ES_BASE,
 573         GUEST_BNDCFGS,
 574         CR0_GUEST_HOST_MASK,
 575         CR0_READ_SHADOW,
 576         CR4_READ_SHADOW,
 577         TSC_OFFSET,
 578         EXCEPTION_BITMAP,
 579         CPU_BASED_VM_EXEC_CONTROL,
 580         VM_ENTRY_EXCEPTION_ERROR_CODE,
 581         VM_ENTRY_INTR_INFO_FIELD,
 582         VM_ENTRY_INSTRUCTION_LEN,
 583         VM_ENTRY_EXCEPTION_ERROR_CODE,
 584         HOST_FS_BASE,
 585         HOST_GS_BASE,
 586         HOST_FS_SELECTOR,
 587         HOST_GS_SELECTOR
 588 };
 589 static int max_shadow_read_write_fields =
 590         ARRAY_SIZE(shadow_read_write_fields);
 591
 592 static const unsigned short vmcs_field_to_offset_table[] = {
 593         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 594         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 595         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 596         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 597         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 598         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 599         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 600         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 601         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 602         FIELD(HOST_ES_SELECTOR, host_es_selector),
 603         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 604         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 605         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 606         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 607         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 608         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 609         FIELD64(IO_BITMAP_A, io_bitmap_a),
 610         FIELD64(IO_BITMAP_B, io_bitmap_b),
 611         FIELD64(MSR_BITMAP, msr_bitmap),
 612         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 613         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 614         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 615         FIELD64(TSC_OFFSET, tsc_offset),
 616         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 617         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 618         FIELD64(EPT_POINTER, ept_pointer),
 619         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 620         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 621         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 622         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 623         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 624         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 625         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 626         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 627         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 628         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 629         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 630         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 631         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 632         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 633         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 634         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 635         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 636         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 637         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 638         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 639         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 640         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 641         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 642         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 643         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 644         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 645         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 646         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 647         FIELD(TPR_THRESHOLD, tpr_threshold),
 648         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 649         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 650         FIELD(VM_EXIT_REASON, vm_exit_reason),
 651         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 652         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 653         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 654         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 655         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 656         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 657         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 658         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 659         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 660         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 661         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 662         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 663         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 664         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 665         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 666         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 667         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 668         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 669         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 670         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 671         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 672         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 673         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 674         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 675         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 676         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 677         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 678         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 679         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 680         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 681         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 682         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 683         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 684         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 685         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 686         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 687         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 688         FIELD(EXIT_QUALIFICATION, exit_qualification),
 689         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 690         FIELD(GUEST_CR0, guest_cr0),
 691         FIELD(GUEST_CR3, guest_cr3),
 692         FIELD(GUEST_CR4, guest_cr4),
 693         FIELD(GUEST_ES_BASE, guest_es_base),
 694         FIELD(GUEST_CS_BASE, guest_cs_base),
 695         FIELD(GUEST_SS_BASE, guest_ss_base),
 696         FIELD(GUEST_DS_BASE, guest_ds_base),
 697         FIELD(GUEST_FS_BASE, guest_fs_base),
 698         FIELD(GUEST_GS_BASE, guest_gs_base),
 699         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 700         FIELD(GUEST_TR_BASE, guest_tr_base),
 701         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 702         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 703         FIELD(GUEST_DR7, guest_dr7),
 704         FIELD(GUEST_RSP, guest_rsp),
 705         FIELD(GUEST_RIP, guest_rip),
 706         FIELD(GUEST_RFLAGS, guest_rflags),
 707         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 708         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 709         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 710         FIELD(HOST_CR0, host_cr0),
 711         FIELD(HOST_CR3, host_cr3),
 712         FIELD(HOST_CR4, host_cr4),
 713         FIELD(HOST_FS_BASE, host_fs_base),
 714         FIELD(HOST_GS_BASE, host_gs_base),
 715         FIELD(HOST_TR_BASE, host_tr_base),
 716         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 717         FIELD(HOST_IDTR_BASE, host_idtr_base),
 718         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 719         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 720         FIELD(HOST_RSP, host_rsp),
 721         FIELD(HOST_RIP, host_rip),
 722 };
 723
 724 static inline short vmcs_field_to_offset(unsigned long field)
 725 {
 726         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 727
 728         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 729             vmcs_field_to_offset_table[field] == 0)
 730                 return -ENOENT;
 731
 732         return vmcs_field_to_offset_table[field];
 733 }
 734
 735 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 736 {
 737         return to_vmx(vcpu)->nested.current_vmcs12;
 738 }
 739
 740 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 741 {
 742         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 743         if (is_error_page(page))
 744                 return NULL;
 745
 746         return page;
 747 }
 748
 749 static void nested_release_page(struct page *page)
 750 {
 751         kvm_release_page_dirty(page);
 752 }
 753
 754 static void nested_release_page_clean(struct page *page)
 755 {
 756         kvm_release_page_clean(page);
 757 }
 758
 759 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 760 static u64 construct_eptp(unsigned long root_hpa);
 761 static void kvm_cpu_vmxon(u64 addr);
 762 static void kvm_cpu_vmxoff(void);
 763 static bool vmx_mpx_supported(void);
 764 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 765 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 766                             struct kvm_segment *var, int seg);
 767 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 768                             struct kvm_segment *var, int seg);
 769 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 770 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 771 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
 772 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 773 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 774 static int alloc_identity_pagetable(struct kvm *kvm);
 775
 776 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 777 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 778 /*
 779  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 780  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 781  */
 782 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 783 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 784
 785 static unsigned long *vmx_io_bitmap_a;
 786 static unsigned long *vmx_io_bitmap_b;
 787 static unsigned long *vmx_msr_bitmap_legacy;
 788 static unsigned long *vmx_msr_bitmap_longmode;
 789 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 790 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 791 static unsigned long *vmx_vmread_bitmap;
 792 static unsigned long *vmx_vmwrite_bitmap;
 793
 794 static bool cpu_has_load_ia32_efer;
 795 static bool cpu_has_load_perf_global_ctrl;
 796
 797 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 798 static DEFINE_SPINLOCK(vmx_vpid_lock);
 799
 800 static struct vmcs_config {
 801         int size;
 802         int order;
 803         u32 revision_id;
 804         u32 pin_based_exec_ctrl;
 805         u32 cpu_based_exec_ctrl;
 806         u32 cpu_based_2nd_exec_ctrl;
 807         u32 vmexit_ctrl;
 808         u32 vmentry_ctrl;
 809 } vmcs_config;
 810
 811 static struct vmx_capability {
 812         u32 ept;
 813         u32 vpid;
 814 } vmx_capability;
 815
 816 #define VMX_SEGMENT_FIELD(seg)                                  \
 817         [VCPU_SREG_##seg] = {                                   \
 818                 .selector = GUEST_##seg##_SELECTOR,             \
 819                 .base = GUEST_##seg##_BASE,                     \
 820                 .limit = GUEST_##seg##_LIMIT,                   \
 821                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 822         }
 823
 824 static const struct kvm_vmx_segment_field {
 825         unsigned selector;
 826         unsigned base;
 827         unsigned limit;
 828         unsigned ar_bytes;
 829 } kvm_vmx_segment_fields[] = {
 830         VMX_SEGMENT_FIELD(CS),
 831         VMX_SEGMENT_FIELD(DS),
 832         VMX_SEGMENT_FIELD(ES),
 833         VMX_SEGMENT_FIELD(FS),
 834         VMX_SEGMENT_FIELD(GS),
 835         VMX_SEGMENT_FIELD(SS),
 836         VMX_SEGMENT_FIELD(TR),
 837         VMX_SEGMENT_FIELD(LDTR),
 838 };
 839
 840 static u64 host_efer;
 841
 842 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 843
 844 /*
 845  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 846  * away by decrementing the array size.
 847  */
 848 static const u32 vmx_msr_index[] = {
 849 #ifdef CONFIG_X86_64
 850         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 851 #endif
 852         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 853 };
 854
 855 static inline bool is_page_fault(u32 intr_info)
 856 {
 857         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 858                              INTR_INFO_VALID_MASK)) ==
 859                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 860 }
 861
 862 static inline bool is_no_device(u32 intr_info)
 863 {
 864         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 865                              INTR_INFO_VALID_MASK)) ==
 866                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 867 }
 868
 869 static inline bool is_invalid_opcode(u32 intr_info)
 870 {
 871         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 872                              INTR_INFO_VALID_MASK)) ==
 873                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 874 }
 875
 876 static inline bool is_external_interrupt(u32 intr_info)
 877 {
 878         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 879                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 880 }
 881
 882 static inline bool is_machine_check(u32 intr_info)
 883 {
 884         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 885                              INTR_INFO_VALID_MASK)) ==
 886                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 887 }
 888
 889 static inline bool cpu_has_vmx_msr_bitmap(void)
 890 {
 891         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 892 }
 893
 894 static inline bool cpu_has_vmx_tpr_shadow(void)
 895 {
 896         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 897 }
 898
 899 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 900 {
 901         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 902 }
 903
 904 static inline bool cpu_has_secondary_exec_ctrls(void)
 905 {
 906         return vmcs_config.cpu_based_exec_ctrl &
 907                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 908 }
 909
 910 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 911 {
 912         return vmcs_config.cpu_based_2nd_exec_ctrl &
 913                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 914 }
 915
 916 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
 917 {
 918         return vmcs_config.cpu_based_2nd_exec_ctrl &
 919                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
 920 }
 921
 922 static inline bool cpu_has_vmx_apic_register_virt(void)
 923 {
 924         return vmcs_config.cpu_based_2nd_exec_ctrl &
 925                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
 926 }
 927
 928 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
 929 {
 930         return vmcs_config.cpu_based_2nd_exec_ctrl &
 931                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
 932 }
 933
 934 static inline bool cpu_has_vmx_posted_intr(void)
 935 {
 936         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
 937 }
 938
 939 static inline bool cpu_has_vmx_apicv(void)
 940 {
 941         return cpu_has_vmx_apic_register_virt() &&
 942                 cpu_has_vmx_virtual_intr_delivery() &&
 943                 cpu_has_vmx_posted_intr();
 944 }
 945
 946 static inline bool cpu_has_vmx_flexpriority(void)
 947 {
 948         return cpu_has_vmx_tpr_shadow() &&
 949                 cpu_has_vmx_virtualize_apic_accesses();
 950 }
 951
 952 static inline bool cpu_has_vmx_ept_execute_only(void)
 953 {
 954         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 955 }
 956
 957 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 958 {
 959         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 960 }
 961
 962 static inline bool cpu_has_vmx_eptp_writeback(void)
 963 {
 964         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 965 }
 966
 967 static inline bool cpu_has_vmx_ept_2m_page(void)
 968 {
 969         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 970 }
 971
 972 static inline bool cpu_has_vmx_ept_1g_page(void)
 973 {
 974         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 975 }
 976
 977 static inline bool cpu_has_vmx_ept_4levels(void)
 978 {
 979         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 980 }
 981
 982 static inline bool cpu_has_vmx_ept_ad_bits(void)
 983 {
 984         return vmx_capability.ept & VMX_EPT_AD_BIT;
 985 }
 986
 987 static inline bool cpu_has_vmx_invept_context(void)
 988 {
 989         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 990 }
 991
 992 static inline bool cpu_has_vmx_invept_global(void)
 993 {
 994         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 995 }
 996
 997 static inline bool cpu_has_vmx_invvpid_single(void)
 998 {
 999         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1000 }
1001
1002 static inline bool cpu_has_vmx_invvpid_global(void)
1003 {
1004         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1005 }
1006
1007 static inline bool cpu_has_vmx_ept(void)
1008 {
1009         return vmcs_config.cpu_based_2nd_exec_ctrl &
1010                 SECONDARY_EXEC_ENABLE_EPT;
1011 }
1012
1013 static inline bool cpu_has_vmx_unrestricted_guest(void)
1014 {
1015         return vmcs_config.cpu_based_2nd_exec_ctrl &
1016                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1017 }
1018
1019 static inline bool cpu_has_vmx_ple(void)
1020 {
1021         return vmcs_config.cpu_based_2nd_exec_ctrl &
1022                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1023 }
1024
1025 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
1026 {
1027         return flexpriority_enabled && irqchip_in_kernel(kvm);
1028 }
1029
1030 static inline bool cpu_has_vmx_vpid(void)
1031 {
1032         return vmcs_config.cpu_based_2nd_exec_ctrl &
1033                 SECONDARY_EXEC_ENABLE_VPID;
1034 }
1035
1036 static inline bool cpu_has_vmx_rdtscp(void)
1037 {
1038         return vmcs_config.cpu_based_2nd_exec_ctrl &
1039                 SECONDARY_EXEC_RDTSCP;
1040 }
1041
1042 static inline bool cpu_has_vmx_invpcid(void)
1043 {
1044         return vmcs_config.cpu_based_2nd_exec_ctrl &
1045                 SECONDARY_EXEC_ENABLE_INVPCID;
1046 }
1047
1048 static inline bool cpu_has_virtual_nmis(void)
1049 {
1050         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1051 }
1052
1053 static inline bool cpu_has_vmx_wbinvd_exit(void)
1054 {
1055         return vmcs_config.cpu_based_2nd_exec_ctrl &
1056                 SECONDARY_EXEC_WBINVD_EXITING;
1057 }
1058
1059 static inline bool cpu_has_vmx_shadow_vmcs(void)
1060 {
1061         u64 vmx_msr;
1062         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1063         /* check if the cpu supports writing r/o exit information fields */
1064         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1065                 return false;
1066
1067         return vmcs_config.cpu_based_2nd_exec_ctrl &
1068                 SECONDARY_EXEC_SHADOW_VMCS;
1069 }
1070
1071 static inline bool report_flexpriority(void)
1072 {
1073         return flexpriority_enabled;
1074 }
1075
1076 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1077 {
1078         return vmcs12->cpu_based_vm_exec_control & bit;
1079 }
1080
1081 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1082 {
1083         return (vmcs12->cpu_based_vm_exec_control &
1084                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1085                 (vmcs12->secondary_vm_exec_control & bit);
1086 }
1087
1088 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1089 {
1090         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1091 }
1092
1093 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1094 {
1095         return vmcs12->pin_based_vm_exec_control &
1096                 PIN_BASED_VMX_PREEMPTION_TIMER;
1097 }
1098
1099 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1100 {
1101         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1102 }
1103
1104 static inline bool is_exception(u32 intr_info)
1105 {
1106         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1107                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1108 }
1109
1110 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1111                               u32 exit_intr_info,
1112                               unsigned long exit_qualification);
1113 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1114                         struct vmcs12 *vmcs12,
1115                         u32 reason, unsigned long qualification);
1116
1117 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1118 {
1119         int i;
1120
1121         for (i = 0; i < vmx->nmsrs; ++i)
1122                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1123                         return i;
1124         return -1;
1125 }
1126
1127 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1128 {
1129     struct {
1130         u64 vpid : 16;
1131         u64 rsvd : 48;
1132         u64 gva;
1133     } operand = { vpid, 0, gva };
1134
1135     asm volatile (__ex(ASM_VMX_INVVPID)
1136                   /* CF==1 or ZF==1 --> rc = -1 */
1137                   "; ja 1f ; ud2 ; 1:"
1138                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1139 }
1140
1141 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1142 {
1143         struct {
1144                 u64 eptp, gpa;
1145         } operand = {eptp, gpa};
1146
1147         asm volatile (__ex(ASM_VMX_INVEPT)
1148                         /* CF==1 or ZF==1 --> rc = -1 */
1149                         "; ja 1f ; ud2 ; 1:\n"
1150                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1151 }
1152
1153 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1154 {
1155         int i;
1156
1157         i = __find_msr_index(vmx, msr);
1158         if (i >= 0)
1159                 return &vmx->guest_msrs[i];
1160         return NULL;
1161 }
1162
1163 static void vmcs_clear(struct vmcs *vmcs)
1164 {
1165         u64 phys_addr = __pa(vmcs);
1166         u8 error;
1167
1168         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1169                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1170                       : "cc", "memory");
1171         if (error)
1172                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1173                        vmcs, phys_addr);
1174 }
1175
1176 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1177 {
1178         vmcs_clear(loaded_vmcs->vmcs);
1179         loaded_vmcs->cpu = -1;
1180         loaded_vmcs->launched = 0;
1181 }
1182
1183 static void vmcs_load(struct vmcs *vmcs)
1184 {
1185         u64 phys_addr = __pa(vmcs);
1186         u8 error;
1187
1188         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1189                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1190                         : "cc", "memory");
1191         if (error)
1192                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1193                        vmcs, phys_addr);
1194 }
1195
1196 #ifdef CONFIG_KEXEC
1197 /*
1198  * This bitmap is used to indicate whether the vmclear
1199  * operation is enabled on all cpus. All disabled by
1200  * default.
1201  */
1202 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1203
1204 static inline void crash_enable_local_vmclear(int cpu)
1205 {
1206         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1207 }
1208
1209 static inline void crash_disable_local_vmclear(int cpu)
1210 {
1211         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1212 }
1213
1214 static inline int crash_local_vmclear_enabled(int cpu)
1215 {
1216         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1217 }
1218
1219 static void crash_vmclear_local_loaded_vmcss(void)
1220 {
1221         int cpu = raw_smp_processor_id();
1222         struct loaded_vmcs *v;
1223
1224         if (!crash_local_vmclear_enabled(cpu))
1225                 return;
1226
1227         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1228                             loaded_vmcss_on_cpu_link)
1229                 vmcs_clear(v->vmcs);
1230 }
1231 #else
1232 static inline void crash_enable_local_vmclear(int cpu) { }
1233 static inline void crash_disable_local_vmclear(int cpu) { }
1234 #endif /* CONFIG_KEXEC */
1235
1236 static void __loaded_vmcs_clear(void *arg)
1237 {
1238         struct loaded_vmcs *loaded_vmcs = arg;
1239         int cpu = raw_smp_processor_id();
1240
1241         if (loaded_vmcs->cpu != cpu)
1242                 return; /* vcpu migration can race with cpu offline */
1243         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1244                 per_cpu(current_vmcs, cpu) = NULL;
1245         crash_disable_local_vmclear(cpu);
1246         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1247
1248         /*
1249          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1250          * is before setting loaded_vmcs->vcpu to -1 which is done in
1251          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1252          * then adds the vmcs into percpu list before it is deleted.
1253          */
1254         smp_wmb();
1255
1256         loaded_vmcs_init(loaded_vmcs);
1257         crash_enable_local_vmclear(cpu);
1258 }
1259
1260 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1261 {
1262         int cpu = loaded_vmcs->cpu;
1263
1264         if (cpu != -1)
1265                 smp_call_function_single(cpu,
1266                          __loaded_vmcs_clear, loaded_vmcs, 1);
1267 }
1268
1269 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1270 {
1271         if (vmx->vpid == 0)
1272                 return;
1273
1274         if (cpu_has_vmx_invvpid_single())
1275                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1276 }
1277
1278 static inline void vpid_sync_vcpu_global(void)
1279 {
1280         if (cpu_has_vmx_invvpid_global())
1281                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1282 }
1283
1284 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1285 {
1286         if (cpu_has_vmx_invvpid_single())
1287                 vpid_sync_vcpu_single(vmx);
1288         else
1289                 vpid_sync_vcpu_global();
1290 }
1291
1292 static inline void ept_sync_global(void)
1293 {
1294         if (cpu_has_vmx_invept_global())
1295                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1296 }
1297
1298 static inline void ept_sync_context(u64 eptp)
1299 {
1300         if (enable_ept) {
1301                 if (cpu_has_vmx_invept_context())
1302                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1303                 else
1304                         ept_sync_global();
1305         }
1306 }
1307
1308 static __always_inline unsigned long vmcs_readl(unsigned long field)
1309 {
1310         unsigned long value;
1311
1312         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1313                       : "=a"(value) : "d"(field) : "cc");
1314         return value;
1315 }
1316
1317 static __always_inline u16 vmcs_read16(unsigned long field)
1318 {
1319         return vmcs_readl(field);
1320 }
1321
1322 static __always_inline u32 vmcs_read32(unsigned long field)
1323 {
1324         return vmcs_readl(field);
1325 }
1326
1327 static __always_inline u64 vmcs_read64(unsigned long field)
1328 {
1329 #ifdef CONFIG_X86_64
1330         return vmcs_readl(field);
1331 #else
1332         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1333 #endif
1334 }
1335
1336 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1337 {
1338         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1339                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1340         dump_stack();
1341 }
1342
1343 static void vmcs_writel(unsigned long field, unsigned long value)
1344 {
1345         u8 error;
1346
1347         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1348                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1349         if (unlikely(error))
1350                 vmwrite_error(field, value);
1351 }
1352
1353 static void vmcs_write16(unsigned long field, u16 value)
1354 {
1355         vmcs_writel(field, value);
1356 }
1357
1358 static void vmcs_write32(unsigned long field, u32 value)
1359 {
1360         vmcs_writel(field, value);
1361 }
1362
1363 static void vmcs_write64(unsigned long field, u64 value)
1364 {
1365         vmcs_writel(field, value);
1366 #ifndef CONFIG_X86_64
1367         asm volatile ("");
1368         vmcs_writel(field+1, value >> 32);
1369 #endif
1370 }
1371
1372 static void vmcs_clear_bits(unsigned long field, u32 mask)
1373 {
1374         vmcs_writel(field, vmcs_readl(field) & ~mask);
1375 }
1376
1377 static void vmcs_set_bits(unsigned long field, u32 mask)
1378 {
1379         vmcs_writel(field, vmcs_readl(field) | mask);
1380 }
1381
1382 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1383 {
1384         vmcs_write32(VM_ENTRY_CONTROLS, val);
1385         vmx->vm_entry_controls_shadow = val;
1386 }
1387
1388 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1389 {
1390         if (vmx->vm_entry_controls_shadow != val)
1391                 vm_entry_controls_init(vmx, val);
1392 }
1393
1394 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1395 {
1396         return vmx->vm_entry_controls_shadow;
1397 }
1398
1399
1400 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1401 {
1402         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1403 }
1404
1405 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1406 {
1407         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1408 }
1409
1410 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1411 {
1412         vmcs_write32(VM_EXIT_CONTROLS, val);
1413         vmx->vm_exit_controls_shadow = val;
1414 }
1415
1416 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1417 {
1418         if (vmx->vm_exit_controls_shadow != val)
1419                 vm_exit_controls_init(vmx, val);
1420 }
1421
1422 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1423 {
1424         return vmx->vm_exit_controls_shadow;
1425 }
1426
1427
1428 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1429 {
1430         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1431 }
1432
1433 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1434 {
1435         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1436 }
1437
1438 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1439 {
1440         vmx->segment_cache.bitmask = 0;
1441 }
1442
1443 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1444                                        unsigned field)
1445 {
1446         bool ret;
1447         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1448
1449         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1450                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1451                 vmx->segment_cache.bitmask = 0;
1452         }
1453         ret = vmx->segment_cache.bitmask & mask;
1454         vmx->segment_cache.bitmask |= mask;
1455         return ret;
1456 }
1457
1458 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1459 {
1460         u16 *p = &vmx->segment_cache.seg[seg].selector;
1461
1462         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1463                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1464         return *p;
1465 }
1466
1467 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1468 {
1469         ulong *p = &vmx->segment_cache.seg[seg].base;
1470
1471         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1472                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1473         return *p;
1474 }
1475
1476 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1477 {
1478         u32 *p = &vmx->segment_cache.seg[seg].limit;
1479
1480         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1481                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1482         return *p;
1483 }
1484
1485 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1486 {
1487         u32 *p = &vmx->segment_cache.seg[seg].ar;
1488
1489         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1490                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1491         return *p;
1492 }
1493
1494 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1495 {
1496         u32 eb;
1497
1498         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1499              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1500         if ((vcpu->guest_debug &
1501              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1502             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1503                 eb |= 1u << BP_VECTOR;
1504         if (to_vmx(vcpu)->rmode.vm86_active)
1505                 eb = ~0;
1506         if (enable_ept)
1507                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1508         if (vcpu->fpu_active)
1509                 eb &= ~(1u << NM_VECTOR);
1510
1511         /* When we are running a nested L2 guest and L1 specified for it a
1512          * certain exception bitmap, we must trap the same exceptions and pass
1513          * them to L1. When running L2, we will only handle the exceptions
1514          * specified above if L1 did not want them.
1515          */
1516         if (is_guest_mode(vcpu))
1517                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1518
1519         vmcs_write32(EXCEPTION_BITMAP, eb);
1520 }
1521
1522 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1523                 unsigned long entry, unsigned long exit)
1524 {
1525         vm_entry_controls_clearbit(vmx, entry);
1526         vm_exit_controls_clearbit(vmx, exit);
1527 }
1528
1529 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1530 {
1531         unsigned i;
1532         struct msr_autoload *m = &vmx->msr_autoload;
1533
1534         switch (msr) {
1535         case MSR_EFER:
1536                 if (cpu_has_load_ia32_efer) {
1537                         clear_atomic_switch_msr_special(vmx,
1538                                         VM_ENTRY_LOAD_IA32_EFER,
1539                                         VM_EXIT_LOAD_IA32_EFER);
1540                         return;
1541                 }
1542                 break;
1543         case MSR_CORE_PERF_GLOBAL_CTRL:
1544                 if (cpu_has_load_perf_global_ctrl) {
1545                         clear_atomic_switch_msr_special(vmx,
1546                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1547                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1548                         return;
1549                 }
1550                 break;
1551         }
1552
1553         for (i = 0; i < m->nr; ++i)
1554                 if (m->guest[i].index == msr)
1555                         break;
1556
1557         if (i == m->nr)
1558                 return;
1559         --m->nr;
1560         m->guest[i] = m->guest[m->nr];
1561         m->host[i] = m->host[m->nr];
1562         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1563         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1564 }
1565
1566 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1567                 unsigned long entry, unsigned long exit,
1568                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1569                 u64 guest_val, u64 host_val)
1570 {
1571         vmcs_write64(guest_val_vmcs, guest_val);
1572         vmcs_write64(host_val_vmcs, host_val);
1573         vm_entry_controls_setbit(vmx, entry);
1574         vm_exit_controls_setbit(vmx, exit);
1575 }
1576
1577 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1578                                   u64 guest_val, u64 host_val)
1579 {
1580         unsigned i;
1581         struct msr_autoload *m = &vmx->msr_autoload;
1582
1583         switch (msr) {
1584         case MSR_EFER:
1585                 if (cpu_has_load_ia32_efer) {
1586                         add_atomic_switch_msr_special(vmx,
1587                                         VM_ENTRY_LOAD_IA32_EFER,
1588                                         VM_EXIT_LOAD_IA32_EFER,
1589                                         GUEST_IA32_EFER,
1590                                         HOST_IA32_EFER,
1591                                         guest_val, host_val);
1592                         return;
1593                 }
1594                 break;
1595         case MSR_CORE_PERF_GLOBAL_CTRL:
1596                 if (cpu_has_load_perf_global_ctrl) {
1597                         add_atomic_switch_msr_special(vmx,
1598                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1599                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1600                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1601                                         HOST_IA32_PERF_GLOBAL_CTRL,
1602                                         guest_val, host_val);
1603                         return;
1604                 }
1605                 break;
1606         }
1607
1608         for (i = 0; i < m->nr; ++i)
1609                 if (m->guest[i].index == msr)
1610                         break;
1611
1612         if (i == NR_AUTOLOAD_MSRS) {
1613                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1614                                 "Can't add msr %x\n", msr);
1615                 return;
1616         } else if (i == m->nr) {
1617                 ++m->nr;
1618                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1619                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1620         }
1621
1622         m->guest[i].index = msr;
1623         m->guest[i].value = guest_val;
1624         m->host[i].index = msr;
1625         m->host[i].value = host_val;
1626 }
1627
1628 static void reload_tss(void)
1629 {
1630         /*
1631          * VT restores TR but not its size.  Useless.
1632          */
1633         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1634         struct desc_struct *descs;
1635
1636         descs = (void *)gdt->address;
1637         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1638         load_TR_desc();
1639 }
1640
1641 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1642 {
1643         u64 guest_efer;
1644         u64 ignore_bits;
1645
1646         guest_efer = vmx->vcpu.arch.efer;
1647
1648         /*
1649          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1650          * outside long mode
1651          */
1652         ignore_bits = EFER_NX | EFER_SCE;
1653 #ifdef CONFIG_X86_64
1654         ignore_bits |= EFER_LMA | EFER_LME;
1655         /* SCE is meaningful only in long mode on Intel */
1656         if (guest_efer & EFER_LMA)
1657                 ignore_bits &= ~(u64)EFER_SCE;
1658 #endif
1659         guest_efer &= ~ignore_bits;
1660         guest_efer |= host_efer & ignore_bits;
1661         vmx->guest_msrs[efer_offset].data = guest_efer;
1662         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1663
1664         clear_atomic_switch_msr(vmx, MSR_EFER);
1665
1666         /*
1667          * On EPT, we can't emulate NX, so we must switch EFER atomically.
1668          * On CPUs that support "load IA32_EFER", always switch EFER
1669          * atomically, since it's faster than switching it manually.
1670          */
1671         if (cpu_has_load_ia32_efer ||
1672             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1673                 guest_efer = vmx->vcpu.arch.efer;
1674                 if (!(guest_efer & EFER_LMA))
1675                         guest_efer &= ~EFER_LME;
1676                 if (guest_efer != host_efer)
1677                         add_atomic_switch_msr(vmx, MSR_EFER,
1678                                               guest_efer, host_efer);
1679                 return false;
1680         }
1681
1682         return true;
1683 }
1684
1685 static unsigned long segment_base(u16 selector)
1686 {
1687         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1688         struct desc_struct *d;
1689         unsigned long table_base;
1690         unsigned long v;
1691
1692         if (!(selector & ~3))
1693                 return 0;
1694
1695         table_base = gdt->address;
1696
1697         if (selector & 4) {           /* from ldt */
1698                 u16 ldt_selector = kvm_read_ldt();
1699
1700                 if (!(ldt_selector & ~3))
1701                         return 0;
1702
1703                 table_base = segment_base(ldt_selector);
1704         }
1705         d = (struct desc_struct *)(table_base + (selector & ~7));
1706         v = get_desc_base(d);
1707 #ifdef CONFIG_X86_64
1708        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1709                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1710 #endif
1711         return v;
1712 }
1713
1714 static inline unsigned long kvm_read_tr_base(void)
1715 {
1716         u16 tr;
1717         asm("str %0" : "=g"(tr));
1718         return segment_base(tr);
1719 }
1720
1721 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1722 {
1723         struct vcpu_vmx *vmx = to_vmx(vcpu);
1724         int i;
1725
1726         if (vmx->host_state.loaded)
1727                 return;
1728
1729         vmx->host_state.loaded = 1;
1730         /*
1731          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1732          * allow segment selectors with cpl > 0 or ti == 1.
1733          */
1734         vmx->host_state.ldt_sel = kvm_read_ldt();
1735         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1736         savesegment(fs, vmx->host_state.fs_sel);
1737         if (!(vmx->host_state.fs_sel & 7)) {
1738                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1739                 vmx->host_state.fs_reload_needed = 0;
1740         } else {
1741                 vmcs_write16(HOST_FS_SELECTOR, 0);
1742                 vmx->host_state.fs_reload_needed = 1;
1743         }
1744         savesegment(gs, vmx->host_state.gs_sel);
1745         if (!(vmx->host_state.gs_sel & 7))
1746                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1747         else {
1748                 vmcs_write16(HOST_GS_SELECTOR, 0);
1749                 vmx->host_state.gs_ldt_reload_needed = 1;
1750         }
1751
1752 #ifdef CONFIG_X86_64
1753         savesegment(ds, vmx->host_state.ds_sel);
1754         savesegment(es, vmx->host_state.es_sel);
1755 #endif
1756
1757 #ifdef CONFIG_X86_64
1758         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1759         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1760 #else
1761         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1762         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1763 #endif
1764
1765 #ifdef CONFIG_X86_64
1766         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1767         if (is_long_mode(&vmx->vcpu))
1768                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1769 #endif
1770         if (boot_cpu_has(X86_FEATURE_MPX))
1771                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1772         for (i = 0; i < vmx->save_nmsrs; ++i)
1773                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1774                                    vmx->guest_msrs[i].data,
1775                                    vmx->guest_msrs[i].mask);
1776 }
1777
1778 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1779 {
1780         if (!vmx->host_state.loaded)
1781                 return;
1782
1783         ++vmx->vcpu.stat.host_state_reload;
1784         vmx->host_state.loaded = 0;
1785 #ifdef CONFIG_X86_64
1786         if (is_long_mode(&vmx->vcpu))
1787                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1788 #endif
1789         if (vmx->host_state.gs_ldt_reload_needed) {
1790                 kvm_load_ldt(vmx->host_state.ldt_sel);
1791 #ifdef CONFIG_X86_64
1792                 load_gs_index(vmx->host_state.gs_sel);
1793 #else
1794                 loadsegment(gs, vmx->host_state.gs_sel);
1795 #endif
1796         }
1797         if (vmx->host_state.fs_reload_needed)
1798                 loadsegment(fs, vmx->host_state.fs_sel);
1799 #ifdef CONFIG_X86_64
1800         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1801                 loadsegment(ds, vmx->host_state.ds_sel);
1802                 loadsegment(es, vmx->host_state.es_sel);
1803         }
1804 #endif
1805         reload_tss();
1806 #ifdef CONFIG_X86_64
1807         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1808 #endif
1809         if (vmx->host_state.msr_host_bndcfgs)
1810                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1811         /*
1812          * If the FPU is not active (through the host task or
1813          * the guest vcpu), then restore the cr0.TS bit.
1814          */
1815         if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1816                 stts();
1817         load_gdt(this_cpu_ptr(&host_gdt));
1818 }
1819
1820 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1821 {
1822         preempt_disable();
1823         __vmx_load_host_state(vmx);
1824         preempt_enable();
1825 }
1826
1827 /*
1828  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1829  * vcpu mutex is already taken.
1830  */
1831 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1832 {
1833         struct vcpu_vmx *vmx = to_vmx(vcpu);
1834         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1835
1836         if (!vmm_exclusive)
1837                 kvm_cpu_vmxon(phys_addr);
1838         else if (vmx->loaded_vmcs->cpu != cpu)
1839                 loaded_vmcs_clear(vmx->loaded_vmcs);
1840
1841         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1842                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1843                 vmcs_load(vmx->loaded_vmcs->vmcs);
1844         }
1845
1846         if (vmx->loaded_vmcs->cpu != cpu) {
1847                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1848                 unsigned long sysenter_esp;
1849
1850                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1851                 local_irq_disable();
1852                 crash_disable_local_vmclear(cpu);
1853
1854                 /*
1855                  * Read loaded_vmcs->cpu should be before fetching
1856                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
1857                  * See the comments in __loaded_vmcs_clear().
1858                  */
1859                 smp_rmb();
1860
1861                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1862                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1863                 crash_enable_local_vmclear(cpu);
1864                 local_irq_enable();
1865
1866                 /*
1867                  * Linux uses per-cpu TSS and GDT, so set these when switching
1868                  * processors.
1869                  */
1870                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1871                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1872
1873                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1874                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1875                 vmx->loaded_vmcs->cpu = cpu;
1876         }
1877 }
1878
1879 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1880 {
1881         __vmx_load_host_state(to_vmx(vcpu));
1882         if (!vmm_exclusive) {
1883                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1884                 vcpu->cpu = -1;
1885                 kvm_cpu_vmxoff();
1886         }
1887 }
1888
1889 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1890 {
1891         ulong cr0;
1892
1893         if (vcpu->fpu_active)
1894                 return;
1895         vcpu->fpu_active = 1;
1896         cr0 = vmcs_readl(GUEST_CR0);
1897         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1898         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1899         vmcs_writel(GUEST_CR0, cr0);
1900         update_exception_bitmap(vcpu);
1901         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1902         if (is_guest_mode(vcpu))
1903                 vcpu->arch.cr0_guest_owned_bits &=
1904                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1905         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1906 }
1907
1908 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1909
1910 /*
1911  * Return the cr0 value that a nested guest would read. This is a combination
1912  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1913  * its hypervisor (cr0_read_shadow).
1914  */
1915 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1916 {
1917         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1918                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1919 }
1920 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1921 {
1922         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1923                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1924 }
1925
1926 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1927 {
1928         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1929          * set this *before* calling this function.
1930          */
1931         vmx_decache_cr0_guest_bits(vcpu);
1932         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1933         update_exception_bitmap(vcpu);
1934         vcpu->arch.cr0_guest_owned_bits = 0;
1935         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1936         if (is_guest_mode(vcpu)) {
1937                 /*
1938                  * L1's specified read shadow might not contain the TS bit,
1939                  * so now that we turned on shadowing of this bit, we need to
1940                  * set this bit of the shadow. Like in nested_vmx_run we need
1941                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1942                  * up-to-date here because we just decached cr0.TS (and we'll
1943                  * only update vmcs12->guest_cr0 on nested exit).
1944                  */
1945                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1946                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1947                         (vcpu->arch.cr0 & X86_CR0_TS);
1948                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1949         } else
1950                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1951 }
1952
1953 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1954 {
1955         unsigned long rflags, save_rflags;
1956
1957         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1958                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1959                 rflags = vmcs_readl(GUEST_RFLAGS);
1960                 if (to_vmx(vcpu)->rmode.vm86_active) {
1961                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1962                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1963                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1964                 }
1965                 to_vmx(vcpu)->rflags = rflags;
1966         }
1967         return to_vmx(vcpu)->rflags;
1968 }
1969
1970 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1971 {
1972         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1973         to_vmx(vcpu)->rflags = rflags;
1974         if (to_vmx(vcpu)->rmode.vm86_active) {
1975                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1976                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1977         }
1978         vmcs_writel(GUEST_RFLAGS, rflags);
1979 }
1980
1981 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
1982 {
1983         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1984         int ret = 0;
1985
1986         if (interruptibility & GUEST_INTR_STATE_STI)
1987                 ret |= KVM_X86_SHADOW_INT_STI;
1988         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1989                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1990
1991         return ret;
1992 }
1993
1994 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1995 {
1996         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1997         u32 interruptibility = interruptibility_old;
1998
1999         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2000
2001         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2002                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2003         else if (mask & KVM_X86_SHADOW_INT_STI)
2004                 interruptibility |= GUEST_INTR_STATE_STI;
2005
2006         if ((interruptibility != interruptibility_old))
2007                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2008 }
2009
2010 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2011 {
2012         unsigned long rip;
2013
2014         rip = kvm_rip_read(vcpu);
2015         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2016         kvm_rip_write(vcpu, rip);
2017
2018         /* skipping an emulated instruction also counts */
2019         vmx_set_interrupt_shadow(vcpu, 0);
2020 }
2021
2022 /*
2023  * KVM wants to inject page-faults which it got to the guest. This function
2024  * checks whether in a nested guest, we need to inject them to L1 or L2.
2025  */
2026 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2027 {
2028         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2029
2030         if (!(vmcs12->exception_bitmap & (1u << nr)))
2031                 return 0;
2032
2033         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2034                           vmcs_read32(VM_EXIT_INTR_INFO),
2035                           vmcs_readl(EXIT_QUALIFICATION));
2036         return 1;
2037 }
2038
2039 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2040                                 bool has_error_code, u32 error_code,
2041                                 bool reinject)
2042 {
2043         struct vcpu_vmx *vmx = to_vmx(vcpu);
2044         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2045
2046         if (!reinject && is_guest_mode(vcpu) &&
2047             nested_vmx_check_exception(vcpu, nr))
2048                 return;
2049
2050         if (has_error_code) {
2051                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2052                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2053         }
2054
2055         if (vmx->rmode.vm86_active) {
2056                 int inc_eip = 0;
2057                 if (kvm_exception_is_soft(nr))
2058                         inc_eip = vcpu->arch.event_exit_inst_len;
2059                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2060                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2061                 return;
2062         }
2063
2064         if (kvm_exception_is_soft(nr)) {
2065                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2066                              vmx->vcpu.arch.event_exit_inst_len);
2067                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2068         } else
2069                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2070
2071         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2072 }
2073
2074 static bool vmx_rdtscp_supported(void)
2075 {
2076         return cpu_has_vmx_rdtscp();
2077 }
2078
2079 static bool vmx_invpcid_supported(void)
2080 {
2081         return cpu_has_vmx_invpcid() && enable_ept;
2082 }
2083
2084 /*
2085  * Swap MSR entry in host/guest MSR entry array.
2086  */
2087 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2088 {
2089         struct shared_msr_entry tmp;
2090
2091         tmp = vmx->guest_msrs[to];
2092         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2093         vmx->guest_msrs[from] = tmp;
2094 }
2095
2096 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2097 {
2098         unsigned long *msr_bitmap;
2099
2100         if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2101                 if (is_long_mode(vcpu))
2102                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2103                 else
2104                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2105         } else {
2106                 if (is_long_mode(vcpu))
2107                         msr_bitmap = vmx_msr_bitmap_longmode;
2108                 else
2109                         msr_bitmap = vmx_msr_bitmap_legacy;
2110         }
2111
2112         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2113 }
2114
2115 /*
2116  * Set up the vmcs to automatically save and restore system
2117  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2118  * mode, as fiddling with msrs is very expensive.
2119  */
2120 static void setup_msrs(struct vcpu_vmx *vmx)
2121 {
2122         int save_nmsrs, index;
2123
2124         save_nmsrs = 0;
2125 #ifdef CONFIG_X86_64
2126         if (is_long_mode(&vmx->vcpu)) {
2127                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2128                 if (index >= 0)
2129                         move_msr_up(vmx, index, save_nmsrs++);
2130                 index = __find_msr_index(vmx, MSR_LSTAR);
2131                 if (index >= 0)
2132                         move_msr_up(vmx, index, save_nmsrs++);
2133                 index = __find_msr_index(vmx, MSR_CSTAR);
2134                 if (index >= 0)
2135                         move_msr_up(vmx, index, save_nmsrs++);
2136                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2137                 if (index >= 0 && vmx->rdtscp_enabled)
2138                         move_msr_up(vmx, index, save_nmsrs++);
2139                 /*
2140                  * MSR_STAR is only needed on long mode guests, and only
2141                  * if efer.sce is enabled.
2142                  */
2143                 index = __find_msr_index(vmx, MSR_STAR);
2144                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2145                         move_msr_up(vmx, index, save_nmsrs++);
2146         }
2147 #endif
2148         index = __find_msr_index(vmx, MSR_EFER);
2149         if (index >= 0 && update_transition_efer(vmx, index))
2150                 move_msr_up(vmx, index, save_nmsrs++);
2151
2152         vmx->save_nmsrs = save_nmsrs;
2153
2154         if (cpu_has_vmx_msr_bitmap())
2155                 vmx_set_msr_bitmap(&vmx->vcpu);
2156 }
2157
2158 /*
2159  * reads and returns guest's timestamp counter "register"
2160  * guest_tsc = host_tsc + tsc_offset    -- 21.3
2161  */
2162 static u64 guest_read_tsc(void)
2163 {
2164         u64 host_tsc, tsc_offset;
2165
2166         rdtscll(host_tsc);
2167         tsc_offset = vmcs_read64(TSC_OFFSET);
2168         return host_tsc + tsc_offset;
2169 }
2170
2171 /*
2172  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2173  * counter, even if a nested guest (L2) is currently running.
2174  */
2175 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2176 {
2177         u64 tsc_offset;
2178
2179         tsc_offset = is_guest_mode(vcpu) ?
2180                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2181                 vmcs_read64(TSC_OFFSET);
2182         return host_tsc + tsc_offset;
2183 }
2184
2185 /*
2186  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
2187  * software catchup for faster rates on slower CPUs.
2188  */
2189 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2190 {
2191         if (!scale)
2192                 return;
2193
2194         if (user_tsc_khz > tsc_khz) {
2195                 vcpu->arch.tsc_catchup = 1;
2196                 vcpu->arch.tsc_always_catchup = 1;
2197         } else
2198                 WARN(1, "user requested TSC rate below hardware speed\n");
2199 }
2200
2201 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2202 {
2203         return vmcs_read64(TSC_OFFSET);
2204 }
2205
2206 /*
2207  * writes 'offset' into guest's timestamp counter offset register
2208  */
2209 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2210 {
2211         if (is_guest_mode(vcpu)) {
2212                 /*
2213                  * We're here if L1 chose not to trap WRMSR to TSC. According
2214                  * to the spec, this should set L1's TSC; The offset that L1
2215                  * set for L2 remains unchanged, and still needs to be added
2216                  * to the newly set TSC to get L2's TSC.
2217                  */
2218                 struct vmcs12 *vmcs12;
2219                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2220                 /* recalculate vmcs02.TSC_OFFSET: */
2221                 vmcs12 = get_vmcs12(vcpu);
2222                 vmcs_write64(TSC_OFFSET, offset +
2223                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2224                          vmcs12->tsc_offset : 0));
2225         } else {
2226                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2227                                            vmcs_read64(TSC_OFFSET), offset);
2228                 vmcs_write64(TSC_OFFSET, offset);
2229         }
2230 }
2231
2232 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
2233 {
2234         u64 offset = vmcs_read64(TSC_OFFSET);
2235
2236         vmcs_write64(TSC_OFFSET, offset + adjustment);
2237         if (is_guest_mode(vcpu)) {
2238                 /* Even when running L2, the adjustment needs to apply to L1 */
2239                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2240         } else
2241                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2242                                            offset + adjustment);
2243 }
2244
2245 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2246 {
2247         return target_tsc - native_read_tsc();
2248 }
2249
2250 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2251 {
2252         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2253         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2254 }
2255
2256 /*
2257  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2258  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2259  * all guests if the "nested" module option is off, and can also be disabled
2260  * for a single guest by disabling its VMX cpuid bit.
2261  */
2262 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2263 {
2264         return nested && guest_cpuid_has_vmx(vcpu);
2265 }
2266
2267 /*
2268  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2269  * returned for the various VMX controls MSRs when nested VMX is enabled.
2270  * The same values should also be used to verify that vmcs12 control fields are
2271  * valid during nested entry from L1 to L2.
2272  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2273  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2274  * bit in the high half is on if the corresponding bit in the control field
2275  * may be on. See also vmx_control_verify().
2276  * TODO: allow these variables to be modified (downgraded) by module options
2277  * or other means.
2278  */
2279 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2280 static u32 nested_vmx_true_procbased_ctls_low;
2281 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2282 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2283 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2284 static u32 nested_vmx_true_exit_ctls_low;
2285 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2286 static u32 nested_vmx_true_entry_ctls_low;
2287 static u32 nested_vmx_misc_low, nested_vmx_misc_high;
2288 static u32 nested_vmx_ept_caps;
2289 static __init void nested_vmx_setup_ctls_msrs(void)
2290 {
2291         /*
2292          * Note that as a general rule, the high half of the MSRs (bits in
2293          * the control fields which may be 1) should be initialized by the
2294          * intersection of the underlying hardware's MSR (i.e., features which
2295          * can be supported) and the list of features we want to expose -
2296          * because they are known to be properly supported in our code.
2297          * Also, usually, the low half of the MSRs (bits which must be 1) can
2298          * be set to 0, meaning that L1 may turn off any of these bits. The
2299          * reason is that if one of these bits is necessary, it will appear
2300          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2301          * fields of vmcs01 and vmcs02, will turn these bits off - and
2302          * nested_vmx_exit_handled() will not pass related exits to L1.
2303          * These rules have exceptions below.
2304          */
2305
2306         /* pin-based controls */
2307         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2308               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
2309         nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2310         nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
2311                 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS;
2312         nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2313                 PIN_BASED_VMX_PREEMPTION_TIMER;
2314
2315         /* exit controls */
2316         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2317                 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
2318         nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2319
2320         nested_vmx_exit_ctls_high &=
2321 #ifdef CONFIG_X86_64
2322                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2323 #endif
2324                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2325         nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2326                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2327                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2328
2329         if (vmx_mpx_supported())
2330                 nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2331
2332         /* We support free control of debug control saving. */
2333         nested_vmx_true_exit_ctls_low = nested_vmx_exit_ctls_low &
2334                 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2335
2336         /* entry controls */
2337         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2338                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
2339         nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2340         nested_vmx_entry_ctls_high &=
2341 #ifdef CONFIG_X86_64
2342                 VM_ENTRY_IA32E_MODE |
2343 #endif
2344                 VM_ENTRY_LOAD_IA32_PAT;
2345         nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2346                                        VM_ENTRY_LOAD_IA32_EFER);
2347         if (vmx_mpx_supported())
2348                 nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2349
2350         /* We support free control of debug control loading. */
2351         nested_vmx_true_entry_ctls_low = nested_vmx_entry_ctls_low &
2352                 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2353
2354         /* cpu-based controls */
2355         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2356                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2357         nested_vmx_procbased_ctls_low = CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2358         nested_vmx_procbased_ctls_high &=
2359                 CPU_BASED_VIRTUAL_INTR_PENDING |
2360                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2361                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2362                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2363                 CPU_BASED_CR3_STORE_EXITING |
2364 #ifdef CONFIG_X86_64
2365                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2366 #endif
2367                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2368                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2369                 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2370                 CPU_BASED_PAUSE_EXITING | CPU_BASED_TPR_SHADOW |
2371                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2372         /*
2373          * We can allow some features even when not supported by the
2374          * hardware. For example, L1 can specify an MSR bitmap - and we
2375          * can use it to avoid exits to L1 - even when L0 runs L2
2376          * without MSR bitmaps.
2377          */
2378         nested_vmx_procbased_ctls_high |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2379                 CPU_BASED_USE_MSR_BITMAPS;
2380
2381         /* We support free control of CR3 access interception. */
2382         nested_vmx_true_procbased_ctls_low = nested_vmx_procbased_ctls_low &
2383                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2384
2385         /* secondary cpu-based controls */
2386         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2387                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2388         nested_vmx_secondary_ctls_low = 0;
2389         nested_vmx_secondary_ctls_high &=
2390                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2391                 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2392                 SECONDARY_EXEC_WBINVD_EXITING;
2393
2394         if (enable_ept) {
2395                 /* nested EPT: emulate EPT also to L1 */
2396                 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
2397                 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2398                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2399                          VMX_EPT_INVEPT_BIT;
2400                 nested_vmx_ept_caps &= vmx_capability.ept;
2401                 /*
2402                  * For nested guests, we don't do anything specific
2403                  * for single context invalidation. Hence, only advertise
2404                  * support for global context invalidation.
2405                  */
2406                 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2407         } else
2408                 nested_vmx_ept_caps = 0;
2409
2410         /* miscellaneous data */
2411         rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
2412         nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2413         nested_vmx_misc_low |= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2414                 VMX_MISC_ACTIVITY_HLT;
2415         nested_vmx_misc_high = 0;
2416 }
2417
2418 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2419 {
2420         /*
2421          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2422          */
2423         return ((control & high) | low) == control;
2424 }
2425
2426 static inline u64 vmx_control_msr(u32 low, u32 high)
2427 {
2428         return low | ((u64)high << 32);
2429 }
2430
2431 /* Returns 0 on success, non-0 otherwise. */
2432 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2433 {
2434         switch (msr_index) {
2435         case MSR_IA32_VMX_BASIC:
2436                 /*
2437                  * This MSR reports some information about VMX support. We
2438                  * should return information about the VMX we emulate for the
2439                  * guest, and the VMCS structure we give it - not about the
2440                  * VMX support of the underlying hardware.
2441                  */
2442                 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2443                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2444                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2445                 break;
2446         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2447         case MSR_IA32_VMX_PINBASED_CTLS:
2448                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2449                                         nested_vmx_pinbased_ctls_high);
2450                 break;
2451         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2452                 *pdata = vmx_control_msr(nested_vmx_true_procbased_ctls_low,
2453                                         nested_vmx_procbased_ctls_high);
2454                 break;
2455         case MSR_IA32_VMX_PROCBASED_CTLS:
2456                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2457                                         nested_vmx_procbased_ctls_high);
2458                 break;
2459         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2460                 *pdata = vmx_control_msr(nested_vmx_true_exit_ctls_low,
2461                                         nested_vmx_exit_ctls_high);
2462                 break;
2463         case MSR_IA32_VMX_EXIT_CTLS:
2464                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2465                                         nested_vmx_exit_ctls_high);
2466                 break;
2467         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2468                 *pdata = vmx_control_msr(nested_vmx_true_entry_ctls_low,
2469                                         nested_vmx_entry_ctls_high);
2470                 break;
2471         case MSR_IA32_VMX_ENTRY_CTLS:
2472                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2473                                         nested_vmx_entry_ctls_high);
2474                 break;
2475         case MSR_IA32_VMX_MISC:
2476                 *pdata = vmx_control_msr(nested_vmx_misc_low,
2477                                          nested_vmx_misc_high);
2478                 break;
2479         /*
2480          * These MSRs specify bits which the guest must keep fixed (on or off)
2481          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2482          * We picked the standard core2 setting.
2483          */
2484 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2485 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2486         case MSR_IA32_VMX_CR0_FIXED0:
2487                 *pdata = VMXON_CR0_ALWAYSON;
2488                 break;
2489         case MSR_IA32_VMX_CR0_FIXED1:
2490                 *pdata = -1ULL;
2491                 break;
2492         case MSR_IA32_VMX_CR4_FIXED0:
2493                 *pdata = VMXON_CR4_ALWAYSON;
2494                 break;
2495         case MSR_IA32_VMX_CR4_FIXED1:
2496                 *pdata = -1ULL;
2497                 break;
2498         case MSR_IA32_VMX_VMCS_ENUM:
2499                 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2500                 break;
2501         case MSR_IA32_VMX_PROCBASED_CTLS2:
2502                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2503                                         nested_vmx_secondary_ctls_high);
2504                 break;
2505         case MSR_IA32_VMX_EPT_VPID_CAP:
2506                 /* Currently, no nested vpid support */
2507                 *pdata = nested_vmx_ept_caps;
2508                 break;
2509         default:
2510                 return 1;
2511         }
2512
2513         return 0;
2514 }
2515
2516 /*
2517  * Reads an msr value (of 'msr_index') into 'pdata'.
2518  * Returns 0 on success, non-0 otherwise.
2519  * Assumes vcpu_load() was already called.
2520  */
2521 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2522 {
2523         u64 data;
2524         struct shared_msr_entry *msr;
2525
2526         if (!pdata) {
2527                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2528                 return -EINVAL;
2529         }
2530
2531         switch (msr_index) {
2532 #ifdef CONFIG_X86_64
2533         case MSR_FS_BASE:
2534                 data = vmcs_readl(GUEST_FS_BASE);
2535                 break;
2536         case MSR_GS_BASE:
2537                 data = vmcs_readl(GUEST_GS_BASE);
2538                 break;
2539         case MSR_KERNEL_GS_BASE:
2540                 vmx_load_host_state(to_vmx(vcpu));
2541                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2542                 break;
2543 #endif
2544         case MSR_EFER:
2545                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2546         case MSR_IA32_TSC:
2547                 data = guest_read_tsc();
2548                 break;
2549         case MSR_IA32_SYSENTER_CS:
2550                 data = vmcs_read32(GUEST_SYSENTER_CS);
2551                 break;
2552         case MSR_IA32_SYSENTER_EIP:
2553                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2554                 break;
2555         case MSR_IA32_SYSENTER_ESP:
2556                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2557                 break;
2558         case MSR_IA32_BNDCFGS:
2559                 if (!vmx_mpx_supported())
2560                         return 1;
2561                 data = vmcs_read64(GUEST_BNDCFGS);
2562                 break;
2563         case MSR_IA32_FEATURE_CONTROL:
2564                 if (!nested_vmx_allowed(vcpu))
2565                         return 1;
2566                 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2567                 break;
2568         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2569                 if (!nested_vmx_allowed(vcpu))
2570                         return 1;
2571                 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
2572         case MSR_TSC_AUX:
2573                 if (!to_vmx(vcpu)->rdtscp_enabled)
2574                         return 1;
2575                 /* Otherwise falls through */
2576         default:
2577                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2578                 if (msr) {
2579                         data = msr->data;
2580                         break;
2581                 }
2582                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2583         }
2584
2585         *pdata = data;
2586         return 0;
2587 }
2588
2589 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2590
2591 /*
2592  * Writes msr value into into the appropriate "register".
2593  * Returns 0 on success, non-0 otherwise.
2594  * Assumes vcpu_load() was already called.
2595  */
2596 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2597 {
2598         struct vcpu_vmx *vmx = to_vmx(vcpu);
2599         struct shared_msr_entry *msr;
2600         int ret = 0;
2601         u32 msr_index = msr_info->index;
2602         u64 data = msr_info->data;
2603
2604         switch (msr_index) {
2605         case MSR_EFER:
2606                 ret = kvm_set_msr_common(vcpu, msr_info);
2607                 break;
2608 #ifdef CONFIG_X86_64
2609         case MSR_FS_BASE:
2610                 vmx_segment_cache_clear(vmx);
2611                 vmcs_writel(GUEST_FS_BASE, data);
2612                 break;
2613         case MSR_GS_BASE:
2614                 vmx_segment_cache_clear(vmx);
2615                 vmcs_writel(GUEST_GS_BASE, data);
2616                 break;
2617         case MSR_KERNEL_GS_BASE:
2618                 vmx_load_host_state(vmx);
2619                 vmx->msr_guest_kernel_gs_base = data;
2620                 break;
2621 #endif
2622         case MSR_IA32_SYSENTER_CS:
2623                 vmcs_write32(GUEST_SYSENTER_CS, data);
2624                 break;
2625         case MSR_IA32_SYSENTER_EIP:
2626                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2627                 break;
2628         case MSR_IA32_SYSENTER_ESP:
2629                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2630                 break;
2631         case MSR_IA32_BNDCFGS:
2632                 if (!vmx_mpx_supported())
2633                         return 1;
2634                 vmcs_write64(GUEST_BNDCFGS, data);
2635                 break;
2636         case MSR_IA32_TSC:
2637                 kvm_write_tsc(vcpu, msr_info);
2638                 break;
2639         case MSR_IA32_CR_PAT:
2640                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2641                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2642                                 return 1;
2643                         vmcs_write64(GUEST_IA32_PAT, data);
2644                         vcpu->arch.pat = data;
2645                         break;
2646                 }
2647                 ret = kvm_set_msr_common(vcpu, msr_info);
2648                 break;
2649         case MSR_IA32_TSC_ADJUST:
2650                 ret = kvm_set_msr_common(vcpu, msr_info);
2651                 break;
2652         case MSR_IA32_FEATURE_CONTROL:
2653                 if (!nested_vmx_allowed(vcpu) ||
2654                     (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2655                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2656                         return 1;
2657                 vmx->nested.msr_ia32_feature_control = data;
2658                 if (msr_info->host_initiated && data == 0)
2659                         vmx_leave_nested(vcpu);
2660                 break;
2661         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2662                 return 1; /* they are read-only */
2663         case MSR_TSC_AUX:
2664                 if (!vmx->rdtscp_enabled)
2665                         return 1;
2666                 /* Check reserved bit, higher 32 bits should be zero */
2667                 if ((data >> 32) != 0)
2668                         return 1;
2669                 /* Otherwise falls through */
2670         default:
2671                 msr = find_msr_entry(vmx, msr_index);
2672                 if (msr) {
2673                         u64 old_msr_data = msr->data;
2674                         msr->data = data;
2675                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2676                                 preempt_disable();
2677                                 ret = kvm_set_shared_msr(msr->index, msr->data,
2678                                                          msr->mask);
2679                                 preempt_enable();
2680                                 if (ret)
2681                                         msr->data = old_msr_data;
2682                         }
2683                         break;
2684                 }
2685                 ret = kvm_set_msr_common(vcpu, msr_info);
2686         }
2687
2688         return ret;
2689 }
2690
2691 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2692 {
2693         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2694         switch (reg) {
2695         case VCPU_REGS_RSP:
2696                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2697                 break;
2698         case VCPU_REGS_RIP:
2699                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2700                 break;
2701         case VCPU_EXREG_PDPTR:
2702                 if (enable_ept)
2703                         ept_save_pdptrs(vcpu);
2704                 break;
2705         default:
2706                 break;
2707         }
2708 }
2709
2710 static __init int cpu_has_kvm_support(void)
2711 {
2712         return cpu_has_vmx();
2713 }
2714
2715 static __init int vmx_disabled_by_bios(void)
2716 {
2717         u64 msr;
2718
2719         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2720         if (msr & FEATURE_CONTROL_LOCKED) {
2721                 /* launched w/ TXT and VMX disabled */
2722                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2723                         && tboot_enabled())
2724                         return 1;
2725                 /* launched w/o TXT and VMX only enabled w/ TXT */
2726                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2727                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2728                         && !tboot_enabled()) {
2729                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2730                                 "activate TXT before enabling KVM\n");
2731                         return 1;
2732                 }
2733                 /* launched w/o TXT and VMX disabled */
2734                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2735                         && !tboot_enabled())
2736                         return 1;
2737         }
2738
2739         return 0;
2740 }
2741
2742 static void kvm_cpu_vmxon(u64 addr)
2743 {
2744         asm volatile (ASM_VMX_VMXON_RAX
2745                         : : "a"(&addr), "m"(addr)
2746                         : "memory", "cc");
2747 }
2748
2749 static int hardware_enable(void)
2750 {
2751         int cpu = raw_smp_processor_id();
2752         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2753         u64 old, test_bits;
2754
2755         if (read_cr4() & X86_CR4_VMXE)
2756                 return -EBUSY;
2757
2758         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2759
2760         /*
2761          * Now we can enable the vmclear operation in kdump
2762          * since the loaded_vmcss_on_cpu list on this cpu
2763          * has been initialized.
2764          *
2765          * Though the cpu is not in VMX operation now, there
2766          * is no problem to enable the vmclear operation
2767          * for the loaded_vmcss_on_cpu list is empty!
2768          */
2769         crash_enable_local_vmclear(cpu);
2770
2771         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2772
2773         test_bits = FEATURE_CONTROL_LOCKED;
2774         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2775         if (tboot_enabled())
2776                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2777
2778         if ((old & test_bits) != test_bits) {
2779                 /* enable and lock */
2780                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2781         }
2782         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2783
2784         if (vmm_exclusive) {
2785                 kvm_cpu_vmxon(phys_addr);
2786                 ept_sync_global();
2787         }
2788
2789         native_store_gdt(this_cpu_ptr(&host_gdt));
2790
2791         return 0;
2792 }
2793
2794 static void vmclear_local_loaded_vmcss(void)
2795 {
2796         int cpu = raw_smp_processor_id();
2797         struct loaded_vmcs *v, *n;
2798
2799         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2800                                  loaded_vmcss_on_cpu_link)
2801                 __loaded_vmcs_clear(v);
2802 }
2803
2804
2805 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2806  * tricks.
2807  */
2808 static void kvm_cpu_vmxoff(void)
2809 {
2810         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2811 }
2812
2813 static void hardware_disable(void)
2814 {
2815         if (vmm_exclusive) {
2816                 vmclear_local_loaded_vmcss();
2817                 kvm_cpu_vmxoff();
2818         }
2819         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2820 }
2821
2822 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2823                                       u32 msr, u32 *result)
2824 {
2825         u32 vmx_msr_low, vmx_msr_high;
2826         u32 ctl = ctl_min | ctl_opt;
2827
2828         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2829
2830         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2831         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2832
2833         /* Ensure minimum (required) set of control bits are supported. */
2834         if (ctl_min & ~ctl)
2835                 return -EIO;
2836
2837         *result = ctl;
2838         return 0;
2839 }
2840
2841 static __init bool allow_1_setting(u32 msr, u32 ctl)
2842 {
2843         u32 vmx_msr_low, vmx_msr_high;
2844
2845         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2846         return vmx_msr_high & ctl;
2847 }
2848
2849 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2850 {
2851         u32 vmx_msr_low, vmx_msr_high;
2852         u32 min, opt, min2, opt2;
2853         u32 _pin_based_exec_control = 0;
2854         u32 _cpu_based_exec_control = 0;
2855         u32 _cpu_based_2nd_exec_control = 0;
2856         u32 _vmexit_control = 0;
2857         u32 _vmentry_control = 0;
2858
2859         min = CPU_BASED_HLT_EXITING |
2860 #ifdef CONFIG_X86_64
2861               CPU_BASED_CR8_LOAD_EXITING |
2862               CPU_BASED_CR8_STORE_EXITING |
2863 #endif
2864               CPU_BASED_CR3_LOAD_EXITING |
2865               CPU_BASED_CR3_STORE_EXITING |
2866               CPU_BASED_USE_IO_BITMAPS |
2867               CPU_BASED_MOV_DR_EXITING |
2868               CPU_BASED_USE_TSC_OFFSETING |
2869               CPU_BASED_MWAIT_EXITING |
2870               CPU_BASED_MONITOR_EXITING |
2871               CPU_BASED_INVLPG_EXITING |
2872               CPU_BASED_RDPMC_EXITING;
2873
2874         opt = CPU_BASED_TPR_SHADOW |
2875               CPU_BASED_USE_MSR_BITMAPS |
2876               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2877         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2878                                 &_cpu_based_exec_control) < 0)
2879                 return -EIO;
2880 #ifdef CONFIG_X86_64
2881         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2882                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2883                                            ~CPU_BASED_CR8_STORE_EXITING;
2884 #endif
2885         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2886                 min2 = 0;
2887                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2888                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2889                         SECONDARY_EXEC_WBINVD_EXITING |
2890                         SECONDARY_EXEC_ENABLE_VPID |
2891                         SECONDARY_EXEC_ENABLE_EPT |
2892                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2893                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2894                         SECONDARY_EXEC_RDTSCP |
2895                         SECONDARY_EXEC_ENABLE_INVPCID |
2896                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2897                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2898                         SECONDARY_EXEC_SHADOW_VMCS;
2899                 if (adjust_vmx_controls(min2, opt2,
2900                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2901                                         &_cpu_based_2nd_exec_control) < 0)
2902                         return -EIO;
2903         }
2904 #ifndef CONFIG_X86_64
2905         if (!(_cpu_based_2nd_exec_control &
2906                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2907                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2908 #endif
2909
2910         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2911                 _cpu_based_2nd_exec_control &= ~(
2912                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2913                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2914                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2915
2916         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2917                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2918                    enabled */
2919                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2920                                              CPU_BASED_CR3_STORE_EXITING |
2921                                              CPU_BASED_INVLPG_EXITING);
2922                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2923                       vmx_capability.ept, vmx_capability.vpid);
2924         }
2925
2926         min = VM_EXIT_SAVE_DEBUG_CONTROLS;
2927 #ifdef CONFIG_X86_64
2928         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2929 #endif
2930         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2931                 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
2932         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2933                                 &_vmexit_control) < 0)
2934                 return -EIO;
2935
2936         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2937         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2938         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2939                                 &_pin_based_exec_control) < 0)
2940                 return -EIO;
2941
2942         if (!(_cpu_based_2nd_exec_control &
2943                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2944                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2945                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2946
2947         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2948         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
2949         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2950                                 &_vmentry_control) < 0)
2951                 return -EIO;
2952
2953         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2954
2955         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2956         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2957                 return -EIO;
2958
2959 #ifdef CONFIG_X86_64
2960         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2961         if (vmx_msr_high & (1u<<16))
2962                 return -EIO;
2963 #endif
2964
2965         /* Require Write-Back (WB) memory type for VMCS accesses. */
2966         if (((vmx_msr_high >> 18) & 15) != 6)
2967                 return -EIO;
2968
2969         vmcs_conf->size = vmx_msr_high & 0x1fff;
2970         vmcs_conf->order = get_order(vmcs_config.size);
2971         vmcs_conf->revision_id = vmx_msr_low;
2972
2973         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2974         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2975         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2976         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2977         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2978
2979         cpu_has_load_ia32_efer =
2980                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2981                                 VM_ENTRY_LOAD_IA32_EFER)
2982                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2983                                    VM_EXIT_LOAD_IA32_EFER);
2984
2985         cpu_has_load_perf_global_ctrl =
2986                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2987                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2988                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2989                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2990
2991         /*
2992          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2993          * but due to arrata below it can't be used. Workaround is to use
2994          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2995          *
2996          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2997          *
2998          * AAK155             (model 26)
2999          * AAP115             (model 30)
3000          * AAT100             (model 37)
3001          * BC86,AAY89,BD102   (model 44)
3002          * BA97               (model 46)
3003          *
3004          */
3005         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3006                 switch (boot_cpu_data.x86_model) {
3007                 case 26:
3008                 case 30:
3009                 case 37:
3010                 case 44:
3011                 case 46:
3012                         cpu_has_load_perf_global_ctrl = false;
3013                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3014                                         "does not work properly. Using workaround\n");
3015                         break;
3016                 default:
3017                         break;
3018                 }
3019         }
3020
3021         return 0;
3022 }
3023
3024 static struct vmcs *alloc_vmcs_cpu(int cpu)
3025 {
3026         int node = cpu_to_node(cpu);
3027         struct page *pages;
3028         struct vmcs *vmcs;
3029
3030         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
3031         if (!pages)
3032                 return NULL;
3033         vmcs = page_address(pages);
3034         memset(vmcs, 0, vmcs_config.size);
3035         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3036         return vmcs;
3037 }
3038
3039 static struct vmcs *alloc_vmcs(void)
3040 {
3041         return alloc_vmcs_cpu(raw_smp_processor_id());
3042 }
3043
3044 static void free_vmcs(struct vmcs *vmcs)
3045 {
3046         free_pages((unsigned long)vmcs, vmcs_config.order);
3047 }
3048
3049 /*
3050  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3051  */
3052 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3053 {
3054         if (!loaded_vmcs->vmcs)
3055                 return;
3056         loaded_vmcs_clear(loaded_vmcs);
3057         free_vmcs(loaded_vmcs->vmcs);
3058         loaded_vmcs->vmcs = NULL;
3059 }
3060
3061 static void free_kvm_area(void)
3062 {
3063         int cpu;
3064
3065         for_each_possible_cpu(cpu) {
3066                 free_vmcs(per_cpu(vmxarea, cpu));
3067                 per_cpu(vmxarea, cpu) = NULL;
3068         }
3069 }
3070
3071 static void init_vmcs_shadow_fields(void)
3072 {
3073         int i, j;
3074
3075         /* No checks for read only fields yet */
3076
3077         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3078                 switch (shadow_read_write_fields[i]) {
3079                 case GUEST_BNDCFGS:
3080                         if (!vmx_mpx_supported())
3081                                 continue;
3082                         break;
3083                 default:
3084                         break;
3085                 }
3086
3087                 if (j < i)
3088                         shadow_read_write_fields[j] =
3089                                 shadow_read_write_fields[i];
3090                 j++;
3091         }
3092         max_shadow_read_write_fields = j;
3093
3094         /* shadowed fields guest access without vmexit */
3095         for (i = 0; i < max_shadow_read_write_fields; i++) {
3096                 clear_bit(shadow_read_write_fields[i],
3097                           vmx_vmwrite_bitmap);
3098                 clear_bit(shadow_read_write_fields[i],
3099                           vmx_vmread_bitmap);
3100         }
3101         for (i = 0; i < max_shadow_read_only_fields; i++)
3102                 clear_bit(shadow_read_only_fields[i],
3103                           vmx_vmread_bitmap);
3104 }
3105
3106 static __init int alloc_kvm_area(void)
3107 {
3108         int cpu;
3109
3110         for_each_possible_cpu(cpu) {
3111                 struct vmcs *vmcs;
3112
3113                 vmcs = alloc_vmcs_cpu(cpu);
3114                 if (!vmcs) {
3115                         free_kvm_area();
3116                         return -ENOMEM;
3117                 }
3118
3119                 per_cpu(vmxarea, cpu) = vmcs;
3120         }
3121         return 0;
3122 }
3123
3124 static bool emulation_required(struct kvm_vcpu *vcpu)
3125 {
3126         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3127 }
3128
3129 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3130                 struct kvm_segment *save)
3131 {
3132         if (!emulate_invalid_guest_state) {
3133                 /*
3134                  * CS and SS RPL should be equal during guest entry according
3135                  * to VMX spec, but in reality it is not always so. Since vcpu
3136                  * is in the middle of the transition from real mode to
3137                  * protected mode it is safe to assume that RPL 0 is a good
3138                  * default value.
3139                  */
3140                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3141                         save->selector &= ~SELECTOR_RPL_MASK;
3142                 save->dpl = save->selector & SELECTOR_RPL_MASK;
3143                 save->s = 1;
3144         }
3145         vmx_set_segment(vcpu, save, seg);
3146 }
3147
3148 static void enter_pmode(struct kvm_vcpu *vcpu)
3149 {
3150         unsigned long flags;
3151         struct vcpu_vmx *vmx = to_vmx(vcpu);
3152
3153         /*
3154          * Update real mode segment cache. It may be not up-to-date if sement
3155          * register was written while vcpu was in a guest mode.
3156          */
3157         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3158         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3159         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3160         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3161         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3162         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3163
3164         vmx->rmode.vm86_active = 0;
3165
3166         vmx_segment_cache_clear(vmx);
3167
3168         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3169
3170         flags = vmcs_readl(GUEST_RFLAGS);
3171         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3172         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3173         vmcs_writel(GUEST_RFLAGS, flags);
3174
3175         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3176                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3177
3178         update_exception_bitmap(vcpu);
3179
3180         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3181         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3182         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3183         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3184         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3185         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3186 }
3187
3188 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3189 {
3190         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3191         struct kvm_segment var = *save;
3192
3193         var.dpl = 0x3;
3194         if (seg == VCPU_SREG_CS)
3195                 var.type = 0x3;
3196
3197         if (!emulate_invalid_guest_state) {
3198                 var.selector = var.base >> 4;
3199                 var.base = var.base & 0xffff0;
3200                 var.limit = 0xffff;
3201                 var.g = 0;
3202                 var.db = 0;
3203                 var.present = 1;
3204                 var.s = 1;
3205                 var.l = 0;
3206                 var.unusable = 0;
3207                 var.type = 0x3;
3208                 var.avl = 0;
3209                 if (save->base & 0xf)
3210                         printk_once(KERN_WARNING "kvm: segment base is not "
3211                                         "paragraph aligned when entering "
3212                                         "protected mode (seg=%d)", seg);
3213         }
3214
3215         vmcs_write16(sf->selector, var.selector);
3216         vmcs_write32(sf->base, var.base);
3217         vmcs_write32(sf->limit, var.limit);
3218         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3219 }
3220
3221 static void enter_rmode(struct kvm_vcpu *vcpu)
3222 {
3223         unsigned long flags;
3224         struct vcpu_vmx *vmx = to_vmx(vcpu);
3225
3226         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3227         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3228         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3229         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3230         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3231         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3232         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3233
3234         vmx->rmode.vm86_active = 1;
3235
3236         /*
3237          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3238          * vcpu. Warn the user that an update is overdue.
3239          */
3240         if (!vcpu->kvm->arch.tss_addr)
3241                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3242                              "called before entering vcpu\n");
3243
3244         vmx_segment_cache_clear(vmx);
3245
3246         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3247         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3248         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3249
3250         flags = vmcs_readl(GUEST_RFLAGS);
3251         vmx->rmode.save_rflags = flags;
3252
3253         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3254
3255         vmcs_writel(GUEST_RFLAGS, flags);
3256         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3257         update_exception_bitmap(vcpu);
3258
3259         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3260         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3261         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3262         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3263         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3264         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3265
3266         kvm_mmu_reset_context(vcpu);
3267 }
3268
3269 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3270 {
3271         struct vcpu_vmx *vmx = to_vmx(vcpu);
3272         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3273
3274         if (!msr)
3275                 return;
3276
3277         /*
3278          * Force kernel_gs_base reloading before EFER changes, as control
3279          * of this msr depends on is_long_mode().
3280          */
3281         vmx_load_host_state(to_vmx(vcpu));
3282         vcpu->arch.efer = efer;
3283         if (efer & EFER_LMA) {
3284                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3285                 msr->data = efer;
3286         } else {
3287                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3288
3289                 msr->data = efer & ~EFER_LME;
3290         }
3291         setup_msrs(vmx);
3292 }
3293
3294 #ifdef CONFIG_X86_64
3295
3296 static void enter_lmode(struct kvm_vcpu *vcpu)
3297 {
3298         u32 guest_tr_ar;
3299
3300         vmx_segment_cache_clear(to_vmx(vcpu));
3301
3302         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3303         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3304                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3305                                      __func__);
3306                 vmcs_write32(GUEST_TR_AR_BYTES,
3307                              (guest_tr_ar & ~AR_TYPE_MASK)
3308                              | AR_TYPE_BUSY_64_TSS);
3309         }
3310         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3311 }
3312
3313 static void exit_lmode(struct kvm_vcpu *vcpu)
3314 {
3315         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3316         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3317 }
3318
3319 #endif
3320
3321 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3322 {
3323         vpid_sync_context(to_vmx(vcpu));
3324         if (enable_ept) {
3325                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3326                         return;
3327                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3328         }
3329 }
3330
3331 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3332 {
3333         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3334
3335         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3336         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3337 }
3338
3339 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3340 {
3341         if (enable_ept && is_paging(vcpu))
3342                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3343         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3344 }
3345
3346 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3347 {
3348         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3349
3350         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3351         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3352 }
3353
3354 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3355 {
3356         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3357
3358         if (!test_bit(VCPU_EXREG_PDPTR,
3359                       (unsigned long *)&vcpu->arch.regs_dirty))
3360                 return;
3361
3362         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3363                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3364                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3365                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3366                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3367         }
3368 }
3369
3370 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3371 {
3372         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3373
3374         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3375                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3376                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3377                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3378                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3379         }
3380
3381         __set_bit(VCPU_EXREG_PDPTR,
3382                   (unsigned long *)&vcpu->arch.regs_avail);
3383         __set_bit(VCPU_EXREG_PDPTR,
3384                   (unsigned long *)&vcpu->arch.regs_dirty);
3385 }
3386
3387 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3388
3389 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3390                                         unsigned long cr0,
3391                                         struct kvm_vcpu *vcpu)
3392 {
3393         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3394                 vmx_decache_cr3(vcpu);
3395         if (!(cr0 & X86_CR0_PG)) {
3396                 /* From paging/starting to nonpaging */
3397                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3398                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3399                              (CPU_BASED_CR3_LOAD_EXITING |
3400                               CPU_BASED_CR3_STORE_EXITING));
3401                 vcpu->arch.cr0 = cr0;
3402                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3403         } else if (!is_paging(vcpu)) {
3404                 /* From nonpaging to paging */
3405                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3406                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3407                              ~(CPU_BASED_CR3_LOAD_EXITING |
3408                                CPU_BASED_CR3_STORE_EXITING));
3409                 vcpu->arch.cr0 = cr0;
3410                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3411         }
3412
3413         if (!(cr0 & X86_CR0_WP))
3414                 *hw_cr0 &= ~X86_CR0_WP;
3415 }
3416
3417 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3418 {
3419         struct vcpu_vmx *vmx = to_vmx(vcpu);
3420         unsigned long hw_cr0;
3421
3422         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3423         if (enable_unrestricted_guest)
3424                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3425         else {
3426                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3427
3428                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3429                         enter_pmode(vcpu);
3430
3431                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3432                         enter_rmode(vcpu);
3433         }
3434
3435 #ifdef CONFIG_X86_64
3436         if (vcpu->arch.efer & EFER_LME) {
3437                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3438                         enter_lmode(vcpu);
3439                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3440                         exit_lmode(vcpu);
3441         }
3442 #endif
3443
3444         if (enable_ept)
3445                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3446
3447         if (!vcpu->fpu_active)
3448                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3449
3450         vmcs_writel(CR0_READ_SHADOW, cr0);
3451         vmcs_writel(GUEST_CR0, hw_cr0);
3452         vcpu->arch.cr0 = cr0;
3453
3454         /* depends on vcpu->arch.cr0 to be set to a new value */
3455         vmx->emulation_required = emulation_required(vcpu);
3456 }
3457
3458 static u64 construct_eptp(unsigned long root_hpa)
3459 {
3460         u64 eptp;
3461
3462         /* TODO write the value reading from MSR */
3463         eptp = VMX_EPT_DEFAULT_MT |
3464                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3465         if (enable_ept_ad_bits)
3466                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3467         eptp |= (root_hpa & PAGE_MASK);
3468
3469         return eptp;
3470 }
3471
3472 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3473 {
3474         unsigned long guest_cr3;
3475         u64 eptp;
3476
3477         guest_cr3 = cr3;
3478         if (enable_ept) {
3479                 eptp = construct_eptp(cr3);
3480                 vmcs_write64(EPT_POINTER, eptp);
3481                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3482                         guest_cr3 = kvm_read_cr3(vcpu);
3483                 else
3484                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3485                 ept_load_pdptrs(vcpu);
3486         }
3487
3488         vmx_flush_tlb(vcpu);
3489         vmcs_writel(GUEST_CR3, guest_cr3);
3490 }
3491
3492 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3493 {
3494         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3495                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3496
3497         if (cr4 & X86_CR4_VMXE) {
3498                 /*
3499                  * To use VMXON (and later other VMX instructions), a guest
3500                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3501                  * So basically the check on whether to allow nested VMX
3502                  * is here.
3503                  */
3504                 if (!nested_vmx_allowed(vcpu))
3505                         return 1;
3506         }
3507         if (to_vmx(vcpu)->nested.vmxon &&
3508             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3509                 return 1;
3510
3511         vcpu->arch.cr4 = cr4;
3512         if (enable_ept) {
3513                 if (!is_paging(vcpu)) {
3514                         hw_cr4 &= ~X86_CR4_PAE;
3515                         hw_cr4 |= X86_CR4_PSE;
3516                         /*
3517                          * SMEP/SMAP is disabled if CPU is in non-paging mode
3518                          * in hardware. However KVM always uses paging mode to
3519                          * emulate guest non-paging mode with TDP.
3520                          * To emulate this behavior, SMEP/SMAP needs to be
3521                          * manually disabled when guest switches to non-paging
3522                          * mode.
3523                          */
3524                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
3525                 } else if (!(cr4 & X86_CR4_PAE)) {
3526                         hw_cr4 &= ~X86_CR4_PAE;
3527                 }
3528         }
3529
3530         vmcs_writel(CR4_READ_SHADOW, cr4);
3531         vmcs_writel(GUEST_CR4, hw_cr4);
3532         return 0;
3533 }
3534
3535 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3536                             struct kvm_segment *var, int seg)
3537 {
3538         struct vcpu_vmx *vmx = to_vmx(vcpu);
3539         u32 ar;
3540
3541         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3542                 *var = vmx->rmode.segs[seg];
3543                 if (seg == VCPU_SREG_TR
3544                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3545                         return;
3546                 var->base = vmx_read_guest_seg_base(vmx, seg);
3547                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3548                 return;
3549         }
3550         var->base = vmx_read_guest_seg_base(vmx, seg);
3551         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3552         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3553         ar = vmx_read_guest_seg_ar(vmx, seg);
3554         var->unusable = (ar >> 16) & 1;
3555         var->type = ar & 15;
3556         var->s = (ar >> 4) & 1;
3557         var->dpl = (ar >> 5) & 3;
3558         /*
3559          * Some userspaces do not preserve unusable property. Since usable
3560          * segment has to be present according to VMX spec we can use present
3561          * property to amend userspace bug by making unusable segment always
3562          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3563          * segment as unusable.
3564          */
3565         var->present = !var->unusable;
3566         var->avl = (ar >> 12) & 1;
3567         var->l = (ar >> 13) & 1;
3568         var->db = (ar >> 14) & 1;
3569         var->g = (ar >> 15) & 1;
3570 }
3571
3572 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3573 {
3574         struct kvm_segment s;
3575
3576         if (to_vmx(vcpu)->rmode.vm86_active) {
3577                 vmx_get_segment(vcpu, &s, seg);
3578                 return s.base;
3579         }
3580         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3581 }
3582
3583 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3584 {
3585         struct vcpu_vmx *vmx = to_vmx(vcpu);
3586
3587         if (unlikely(vmx->rmode.vm86_active))
3588                 return 0;
3589         else {
3590                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3591                 return AR_DPL(ar);
3592         }
3593 }
3594
3595 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3596 {
3597         u32 ar;
3598
3599         if (var->unusable || !var->present)
3600                 ar = 1 << 16;
3601         else {
3602                 ar = var->type & 15;
3603                 ar |= (var->s & 1) << 4;
3604                 ar |= (var->dpl & 3) << 5;
3605                 ar |= (var->present & 1) << 7;
3606                 ar |= (var->avl & 1) << 12;
3607                 ar |= (var->l & 1) << 13;
3608                 ar |= (var->db & 1) << 14;
3609                 ar |= (var->g & 1) << 15;
3610         }
3611
3612         return ar;
3613 }
3614
3615 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3616                             struct kvm_segment *var, int seg)
3617 {
3618         struct vcpu_vmx *vmx = to_vmx(vcpu);
3619         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3620
3621         vmx_segment_cache_clear(vmx);
3622
3623         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3624                 vmx->rmode.segs[seg] = *var;
3625                 if (seg == VCPU_SREG_TR)
3626                         vmcs_write16(sf->selector, var->selector);
3627                 else if (var->s)
3628                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3629                 goto out;
3630         }
3631
3632         vmcs_writel(sf->base, var->base);
3633         vmcs_write32(sf->limit, var->limit);
3634         vmcs_write16(sf->selector, var->selector);
3635
3636         /*
3637          *   Fix the "Accessed" bit in AR field of segment registers for older
3638          * qemu binaries.
3639          *   IA32 arch specifies that at the time of processor reset the
3640          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3641          * is setting it to 0 in the userland code. This causes invalid guest
3642          * state vmexit when "unrestricted guest" mode is turned on.
3643          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3644          * tree. Newer qemu binaries with that qemu fix would not need this
3645          * kvm hack.
3646          */
3647         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3648                 var->type |= 0x1; /* Accessed */
3649
3650         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3651
3652 out:
3653         vmx->emulation_required = emulation_required(vcpu);
3654 }
3655
3656 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3657 {
3658         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3659
3660         *db = (ar >> 14) & 1;
3661         *l = (ar >> 13) & 1;
3662 }
3663
3664 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3665 {
3666         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3667         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3668 }
3669
3670 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3671 {
3672         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3673         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3674 }
3675
3676 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3677 {
3678         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3679         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3680 }
3681
3682 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3683 {
3684         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3685         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3686 }
3687
3688 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3689 {
3690         struct kvm_segment var;
3691         u32 ar;
3692
3693         vmx_get_segment(vcpu, &var, seg);
3694         var.dpl = 0x3;
3695         if (seg == VCPU_SREG_CS)
3696                 var.type = 0x3;
3697         ar = vmx_segment_access_rights(&var);
3698
3699         if (var.base != (var.selector << 4))
3700                 return false;
3701         if (var.limit != 0xffff)
3702                 return false;
3703         if (ar != 0xf3)
3704                 return false;
3705
3706         return true;
3707 }
3708
3709 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3710 {
3711         struct kvm_segment cs;
3712         unsigned int cs_rpl;
3713
3714         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3715         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3716
3717         if (cs.unusable)
3718                 return false;
3719         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3720                 return false;
3721         if (!cs.s)
3722                 return false;
3723         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3724                 if (cs.dpl > cs_rpl)
3725                         return false;
3726         } else {
3727                 if (cs.dpl != cs_rpl)
3728                         return false;
3729         }
3730         if (!cs.present)
3731                 return false;
3732
3733         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3734         return true;
3735 }
3736
3737 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3738 {
3739         struct kvm_segment ss;
3740         unsigned int ss_rpl;
3741
3742         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3743         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3744
3745         if (ss.unusable)
3746                 return true;
3747         if (ss.type != 3 && ss.type != 7)
3748                 return false;
3749         if (!ss.s)
3750                 return false;
3751         if (ss.dpl != ss_rpl) /* DPL != RPL */
3752                 return false;
3753         if (!ss.present)
3754                 return false;
3755
3756         return true;
3757 }
3758
3759 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3760 {
3761         struct kvm_segment var;
3762         unsigned int rpl;
3763
3764         vmx_get_segment(vcpu, &var, seg);
3765         rpl = var.selector & SELECTOR_RPL_MASK;
3766
3767         if (var.unusable)
3768                 return true;
3769         if (!var.s)
3770                 return false;
3771         if (!var.present)
3772                 return false;
3773         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3774                 if (var.dpl < rpl) /* DPL < RPL */
3775                         return false;
3776         }
3777
3778         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3779          * rights flags
3780          */
3781         return true;
3782 }
3783
3784 static bool tr_valid(struct kvm_vcpu *vcpu)
3785 {
3786         struct kvm_segment tr;
3787
3788         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3789
3790         if (tr.unusable)
3791                 return false;
3792         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3793                 return false;
3794         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3795                 return false;
3796         if (!tr.present)
3797                 return false;
3798
3799         return true;
3800 }
3801
3802 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3803 {
3804         struct kvm_segment ldtr;
3805
3806         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3807
3808         if (ldtr.unusable)
3809                 return true;
3810         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3811                 return false;
3812         if (ldtr.type != 2)
3813                 return false;
3814         if (!ldtr.present)
3815                 return false;
3816
3817         return true;
3818 }
3819
3820 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3821 {
3822         struct kvm_segment cs, ss;
3823
3824         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3825         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3826
3827         return ((cs.selector & SELECTOR_RPL_MASK) ==
3828                  (ss.selector & SELECTOR_RPL_MASK));
3829 }
3830
3831 /*
3832  * Check if guest state is valid. Returns true if valid, false if
3833  * not.
3834  * We assume that registers are always usable
3835  */
3836 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3837 {
3838         if (enable_unrestricted_guest)
3839                 return true;
3840
3841         /* real mode guest state checks */
3842         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3843                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3844                         return false;
3845                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3846                         return false;
3847                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3848                         return false;
3849                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3850                         return false;
3851                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3852                         return false;
3853                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3854                         return false;
3855         } else {
3856         /* protected mode guest state checks */
3857                 if (!cs_ss_rpl_check(vcpu))
3858                         return false;
3859                 if (!code_segment_valid(vcpu))
3860                         return false;
3861                 if (!stack_segment_valid(vcpu))
3862                         return false;
3863                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3864                         return false;
3865                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3866                         return false;
3867                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3868                         return false;
3869                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3870                         return false;
3871                 if (!tr_valid(vcpu))
3872                         return false;
3873                 if (!ldtr_valid(vcpu))
3874                         return false;
3875         }
3876         /* TODO:
3877          * - Add checks on RIP
3878          * - Add checks on RFLAGS
3879          */
3880
3881         return true;
3882 }
3883
3884 static int init_rmode_tss(struct kvm *kvm)
3885 {
3886         gfn_t fn;
3887         u16 data = 0;
3888         int idx, r;
3889
3890         idx = srcu_read_lock(&kvm->srcu);
3891         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
3892         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3893         if (r < 0)
3894                 goto out;
3895         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3896         r = kvm_write_guest_page(kvm, fn++, &data,
3897                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3898         if (r < 0)
3899                 goto out;
3900         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3901         if (r < 0)
3902                 goto out;
3903         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3904         if (r < 0)
3905                 goto out;
3906         data = ~0;
3907         r = kvm_write_guest_page(kvm, fn, &data,
3908                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3909                                  sizeof(u8));
3910 out:
3911         srcu_read_unlock(&kvm->srcu, idx);
3912         return r;
3913 }
3914
3915 static int init_rmode_identity_map(struct kvm *kvm)
3916 {
3917         int i, idx, r = 0;
3918         pfn_t identity_map_pfn;
3919         u32 tmp;
3920
3921         if (!enable_ept)
3922                 return 0;
3923
3924         /* Protect kvm->arch.ept_identity_pagetable_done. */
3925         mutex_lock(&kvm->slots_lock);
3926
3927         if (likely(kvm->arch.ept_identity_pagetable_done))
3928                 goto out2;
3929
3930         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3931
3932         r = alloc_identity_pagetable(kvm);
3933         if (r < 0)
3934                 goto out2;
3935
3936         idx = srcu_read_lock(&kvm->srcu);
3937         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3938         if (r < 0)
3939                 goto out;
3940         /* Set up identity-mapping pagetable for EPT in real mode */
3941         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3942                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3943                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3944                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3945                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3946                 if (r < 0)
3947                         goto out;
3948         }
3949         kvm->arch.ept_identity_pagetable_done = true;
3950
3951 out:
3952         srcu_read_unlock(&kvm->srcu, idx);
3953
3954 out2:
3955         mutex_unlock(&kvm->slots_lock);
3956         return r;
3957 }
3958
3959 static void seg_setup(int seg)
3960 {
3961         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3962         unsigned int ar;
3963
3964         vmcs_write16(sf->selector, 0);
3965         vmcs_writel(sf->base, 0);
3966         vmcs_write32(sf->limit, 0xffff);
3967         ar = 0x93;
3968         if (seg == VCPU_SREG_CS)
3969                 ar |= 0x08; /* code segment */
3970
3971         vmcs_write32(sf->ar_bytes, ar);
3972 }
3973
3974 static int alloc_apic_access_page(struct kvm *kvm)
3975 {
3976         struct page *page;
3977         struct kvm_userspace_memory_region kvm_userspace_mem;
3978         int r = 0;
3979
3980         mutex_lock(&kvm->slots_lock);
3981         if (kvm->arch.apic_access_page_done)
3982                 goto out;
3983         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3984         kvm_userspace_mem.flags = 0;
3985         kvm_userspace_mem.guest_phys_addr = APIC_DEFAULT_PHYS_BASE;
3986         kvm_userspace_mem.memory_size = PAGE_SIZE;
3987         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
3988         if (r)
3989                 goto out;
3990
3991         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
3992         if (is_error_page(page)) {
3993                 r = -EFAULT;
3994                 goto out;
3995         }
3996
3997         /*
3998          * Do not pin the page in memory, so that memory hot-unplug
3999          * is able to migrate it.
4000          */
4001         put_page(page);
4002         kvm->arch.apic_access_page_done = true;
4003 out:
4004         mutex_unlock(&kvm->slots_lock);
4005         return r;
4006 }
4007
4008 static int alloc_identity_pagetable(struct kvm *kvm)
4009 {
4010         /* Called with kvm->slots_lock held. */
4011
4012         struct kvm_userspace_memory_region kvm_userspace_mem;
4013         int r = 0;
4014
4015         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4016
4017         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4018         kvm_userspace_mem.flags = 0;
4019         kvm_userspace_mem.guest_phys_addr =
4020                 kvm->arch.ept_identity_map_addr;
4021         kvm_userspace_mem.memory_size = PAGE_SIZE;
4022         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
4023
4024         return r;
4025 }
4026
4027 static void allocate_vpid(struct vcpu_vmx *vmx)
4028 {
4029         int vpid;
4030
4031         vmx->vpid = 0;
4032         if (!enable_vpid)
4033                 return;
4034         spin_lock(&vmx_vpid_lock);
4035         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4036         if (vpid < VMX_NR_VPIDS) {
4037                 vmx->vpid = vpid;
4038                 __set_bit(vpid, vmx_vpid_bitmap);
4039         }
4040         spin_unlock(&vmx_vpid_lock);
4041 }
4042
4043 static void free_vpid(struct vcpu_vmx *vmx)
4044 {
4045         if (!enable_vpid)
4046                 return;
4047         spin_lock(&vmx_vpid_lock);
4048         if (vmx->vpid != 0)
4049                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4050         spin_unlock(&vmx_vpid_lock);
4051 }
4052
4053 #define MSR_TYPE_R      1
4054 #define MSR_TYPE_W      2
4055 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4056                                                 u32 msr, int type)
4057 {
4058         int f = sizeof(unsigned long);
4059
4060         if (!cpu_has_vmx_msr_bitmap())
4061                 return;
4062
4063         /*
4064          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4065          * have the write-low and read-high bitmap offsets the wrong way round.
4066          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4067          */
4068         if (msr <= 0x1fff) {
4069                 if (type & MSR_TYPE_R)
4070                         /* read-low */
4071                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4072
4073                 if (type & MSR_TYPE_W)
4074                         /* write-low */
4075                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4076
4077         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4078                 msr &= 0x1fff;
4079                 if (type & MSR_TYPE_R)
4080                         /* read-high */
4081                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4082
4083                 if (type & MSR_TYPE_W)
4084                         /* write-high */
4085                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4086
4087         }
4088 }
4089
4090 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4091                                                 u32 msr, int type)
4092 {
4093         int f = sizeof(unsigned long);
4094
4095         if (!cpu_has_vmx_msr_bitmap())
4096                 return;
4097
4098         /*
4099          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4100          * have the write-low and read-high bitmap offsets the wrong way round.
4101          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4102          */
4103         if (msr <= 0x1fff) {
4104                 if (type & MSR_TYPE_R)
4105                         /* read-low */
4106                         __set_bit(msr, msr_bitmap + 0x000 / f);
4107
4108                 if (type & MSR_TYPE_W)
4109                         /* write-low */
4110                         __set_bit(msr, msr_bitmap + 0x800 / f);
4111
4112         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4113                 msr &= 0x1fff;
4114                 if (type & MSR_TYPE_R)
4115                         /* read-high */
4116                         __set_bit(msr, msr_bitmap + 0x400 / f);
4117
4118                 if (type & MSR_TYPE_W)
4119                         /* write-high */
4120                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4121
4122         }
4123 }
4124
4125 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4126 {
4127         if (!longmode_only)
4128                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4129                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4130         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4131                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4132 }
4133
4134 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4135 {
4136         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4137                         msr, MSR_TYPE_R);
4138         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4139                         msr, MSR_TYPE_R);
4140 }
4141
4142 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4143 {
4144         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4145                         msr, MSR_TYPE_R);
4146         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4147                         msr, MSR_TYPE_R);
4148 }
4149
4150 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4151 {
4152         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4153                         msr, MSR_TYPE_W);
4154         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4155                         msr, MSR_TYPE_W);
4156 }
4157
4158 static int vmx_vm_has_apicv(struct kvm *kvm)
4159 {
4160         return enable_apicv && irqchip_in_kernel(kvm);
4161 }
4162
4163 /*
4164  * Send interrupt to vcpu via posted interrupt way.
4165  * 1. If target vcpu is running(non-root mode), send posted interrupt
4166  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4167  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4168  * interrupt from PIR in next vmentry.
4169  */
4170 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4171 {
4172         struct vcpu_vmx *vmx = to_vmx(vcpu);
4173         int r;
4174
4175         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4176                 return;
4177
4178         r = pi_test_and_set_on(&vmx->pi_desc);
4179         kvm_make_request(KVM_REQ_EVENT, vcpu);
4180 #ifdef CONFIG_SMP
4181         if (!r && (vcpu->mode == IN_GUEST_MODE))
4182                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4183                                 POSTED_INTR_VECTOR);
4184         else
4185 #endif
4186                 kvm_vcpu_kick(vcpu);
4187 }
4188
4189 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4190 {
4191         struct vcpu_vmx *vmx = to_vmx(vcpu);
4192
4193         if (!pi_test_and_clear_on(&vmx->pi_desc))
4194                 return;
4195
4196         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4197 }
4198
4199 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4200 {
4201         return;
4202 }
4203
4204 /*
4205  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4206  * will not change in the lifetime of the guest.
4207  * Note that host-state that does change is set elsewhere. E.g., host-state
4208  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4209  */
4210 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4211 {
4212         u32 low32, high32;
4213         unsigned long tmpl;
4214         struct desc_ptr dt;
4215         unsigned long cr4;
4216
4217         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4218         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4219
4220         /* Save the most likely value for this task's CR4 in the VMCS. */
4221         cr4 = read_cr4();
4222         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4223         vmx->host_state.vmcs_host_cr4 = cr4;
4224
4225         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4226 #ifdef CONFIG_X86_64
4227         /*
4228          * Load null selectors, so we can avoid reloading them in
4229          * __vmx_load_host_state(), in case userspace uses the null selectors
4230          * too (the expected case).
4231          */
4232         vmcs_write16(HOST_DS_SELECTOR, 0);
4233         vmcs_write16(HOST_ES_SELECTOR, 0);
4234 #else
4235         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4236         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4237 #endif
4238         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4239         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4240
4241         native_store_idt(&dt);
4242         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4243         vmx->host_idt_base = dt.address;
4244
4245         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4246
4247         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4248         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4249         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4250         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4251
4252         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4253                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4254                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4255         }
4256 }
4257
4258 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4259 {
4260         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4261         if (enable_ept)
4262                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4263         if (is_guest_mode(&vmx->vcpu))
4264                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4265                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4266         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4267 }
4268
4269 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4270 {
4271         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4272
4273         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4274                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4275         return pin_based_exec_ctrl;
4276 }
4277
4278 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4279 {
4280         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4281
4282         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4283                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4284
4285         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4286                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4287 #ifdef CONFIG_X86_64
4288                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4289                                 CPU_BASED_CR8_LOAD_EXITING;
4290 #endif
4291         }
4292         if (!enable_ept)
4293                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4294                                 CPU_BASED_CR3_LOAD_EXITING  |
4295                                 CPU_BASED_INVLPG_EXITING;
4296         return exec_control;
4297 }
4298
4299 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4300 {
4301         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4302         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4303                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4304         if (vmx->vpid == 0)
4305                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4306         if (!enable_ept) {
4307                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4308                 enable_unrestricted_guest = 0;
4309                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4310                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4311         }
4312         if (!enable_unrestricted_guest)
4313                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4314         if (!ple_gap)
4315                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4316         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4317                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4318                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4319         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4320         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4321            (handle_vmptrld).
4322            We can NOT enable shadow_vmcs here because we don't have yet
4323            a current VMCS12
4324         */
4325         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4326         return exec_control;
4327 }
4328
4329 static void ept_set_mmio_spte_mask(void)
4330 {
4331         /*
4332          * EPT Misconfigurations can be generated if the value of bits 2:0
4333          * of an EPT paging-structure entry is 110b (write/execute).
4334          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4335          * spte.
4336          */
4337         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4338 }
4339
4340 /*
4341  * Sets up the vmcs for emulated real mode.
4342  */
4343 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4344 {
4345 #ifdef CONFIG_X86_64
4346         unsigned long a;
4347 #endif
4348         int i;
4349
4350         /* I/O */
4351         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4352         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4353
4354         if (enable_shadow_vmcs) {
4355                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4356                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4357         }
4358         if (cpu_has_vmx_msr_bitmap())
4359                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4360
4361         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4362
4363         /* Control */
4364         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4365
4366         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4367
4368         if (cpu_has_secondary_exec_ctrls()) {
4369                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4370                                 vmx_secondary_exec_control(vmx));
4371         }
4372
4373         if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
4374                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4375                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4376                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4377                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4378
4379                 vmcs_write16(GUEST_INTR_STATUS, 0);
4380
4381                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4382                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4383         }
4384
4385         if (ple_gap) {
4386                 vmcs_write32(PLE_GAP, ple_gap);
4387                 vmx->ple_window = ple_window;
4388                 vmx->ple_window_dirty = true;
4389         }
4390
4391         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4392         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4393         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4394
4395         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4396         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4397         vmx_set_constant_host_state(vmx);
4398 #ifdef CONFIG_X86_64
4399         rdmsrl(MSR_FS_BASE, a);
4400         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4401         rdmsrl(MSR_GS_BASE, a);
4402         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4403 #else
4404         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4405         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4406 #endif
4407
4408         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4409         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4410         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4411         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4412         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4413
4414         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4415                 u32 msr_low, msr_high;
4416                 u64 host_pat;
4417                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4418                 host_pat = msr_low | ((u64) msr_high << 32);
4419                 /* Write the default value follow host pat */
4420                 vmcs_write64(GUEST_IA32_PAT, host_pat);
4421                 /* Keep arch.pat sync with GUEST_IA32_PAT */
4422                 vmx->vcpu.arch.pat = host_pat;
4423         }
4424
4425         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4426                 u32 index = vmx_msr_index[i];
4427                 u32 data_low, data_high;
4428                 int j = vmx->nmsrs;
4429
4430                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4431                         continue;
4432                 if (wrmsr_safe(index, data_low, data_high) < 0)
4433                         continue;
4434                 vmx->guest_msrs[j].index = i;
4435                 vmx->guest_msrs[j].data = 0;
4436                 vmx->guest_msrs[j].mask = -1ull;
4437                 ++vmx->nmsrs;
4438         }
4439
4440
4441         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4442
4443         /* 22.2.1, 20.8.1 */
4444         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4445
4446         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4447         set_cr4_guest_host_mask(vmx);
4448
4449         return 0;
4450 }
4451
4452 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4453 {
4454         struct vcpu_vmx *vmx = to_vmx(vcpu);
4455         struct msr_data apic_base_msr;
4456
4457         vmx->rmode.vm86_active = 0;
4458
4459         vmx->soft_vnmi_blocked = 0;
4460
4461         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4462         kvm_set_cr8(&vmx->vcpu, 0);
4463         apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE;
4464         if (kvm_vcpu_is_bsp(&vmx->vcpu))
4465                 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4466         apic_base_msr.host_initiated = true;
4467         kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
4468
4469         vmx_segment_cache_clear(vmx);
4470
4471         seg_setup(VCPU_SREG_CS);
4472         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4473         vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4474
4475         seg_setup(VCPU_SREG_DS);
4476         seg_setup(VCPU_SREG_ES);
4477         seg_setup(VCPU_SREG_FS);
4478         seg_setup(VCPU_SREG_GS);
4479         seg_setup(VCPU_SREG_SS);
4480
4481         vmcs_write16(GUEST_TR_SELECTOR, 0);
4482         vmcs_writel(GUEST_TR_BASE, 0);
4483         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4484         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4485
4486         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4487         vmcs_writel(GUEST_LDTR_BASE, 0);
4488         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4489         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4490
4491         vmcs_write32(GUEST_SYSENTER_CS, 0);
4492         vmcs_writel(GUEST_SYSENTER_ESP, 0);
4493         vmcs_writel(GUEST_SYSENTER_EIP, 0);
4494
4495         vmcs_writel(GUEST_RFLAGS, 0x02);
4496         kvm_rip_write(vcpu, 0xfff0);
4497
4498         vmcs_writel(GUEST_GDTR_BASE, 0);
4499         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4500
4501         vmcs_writel(GUEST_IDTR_BASE, 0);
4502         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4503
4504         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4505         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4506         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4507
4508         /* Special registers */
4509         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4510
4511         setup_msrs(vmx);
4512
4513         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4514
4515         if (cpu_has_vmx_tpr_shadow()) {
4516                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4517                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4518                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4519                                      __pa(vmx->vcpu.arch.apic->regs));
4520                 vmcs_write32(TPR_THRESHOLD, 0);
4521         }
4522
4523         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4524
4525         if (vmx_vm_has_apicv(vcpu->kvm))
4526                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4527
4528         if (vmx->vpid != 0)
4529                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4530
4531         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4532         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4533         vmx_set_cr4(&vmx->vcpu, 0);
4534         vmx_set_efer(&vmx->vcpu, 0);
4535         vmx_fpu_activate(&vmx->vcpu);
4536         update_exception_bitmap(&vmx->vcpu);
4537
4538         vpid_sync_context(vmx);
4539 }
4540
4541 /*
4542  * In nested virtualization, check if L1 asked to exit on external interrupts.
4543  * For most existing hypervisors, this will always return true.
4544  */
4545 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4546 {
4547         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4548                 PIN_BASED_EXT_INTR_MASK;
4549 }
4550
4551 /*
4552  * In nested virtualization, check if L1 has set
4553  * VM_EXIT_ACK_INTR_ON_EXIT
4554  */
4555 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4556 {
4557         return get_vmcs12(vcpu)->vm_exit_controls &
4558                 VM_EXIT_ACK_INTR_ON_EXIT;
4559 }
4560
4561 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4562 {
4563         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4564                 PIN_BASED_NMI_EXITING;
4565 }
4566
4567 static void enable_irq_window(struct kvm_vcpu *vcpu)
4568 {
4569         u32 cpu_based_vm_exec_control;
4570
4571         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4572         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4573         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4574 }
4575
4576 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4577 {
4578         u32 cpu_based_vm_exec_control;
4579
4580         if (!cpu_has_virtual_nmis() ||
4581             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4582                 enable_irq_window(vcpu);
4583                 return;
4584         }
4585
4586         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4587         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4588         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4589 }
4590
4591 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4592 {
4593         struct vcpu_vmx *vmx = to_vmx(vcpu);
4594         uint32_t intr;
4595         int irq = vcpu->arch.interrupt.nr;
4596
4597         trace_kvm_inj_virq(irq);
4598
4599         ++vcpu->stat.irq_injections;
4600         if (vmx->rmode.vm86_active) {
4601                 int inc_eip = 0;
4602                 if (vcpu->arch.interrupt.soft)
4603                         inc_eip = vcpu->arch.event_exit_inst_len;
4604                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4605                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4606                 return;
4607         }
4608         intr = irq | INTR_INFO_VALID_MASK;
4609         if (vcpu->arch.interrupt.soft) {
4610                 intr |= INTR_TYPE_SOFT_INTR;
4611                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4612                              vmx->vcpu.arch.event_exit_inst_len);
4613         } else
4614                 intr |= INTR_TYPE_EXT_INTR;
4615         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4616 }
4617
4618 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4619 {
4620         struct vcpu_vmx *vmx = to_vmx(vcpu);
4621
4622         if (is_guest_mode(vcpu))
4623                 return;
4624
4625         if (!cpu_has_virtual_nmis()) {
4626                 /*
4627                  * Tracking the NMI-blocked state in software is built upon
4628                  * finding the next open IRQ window. This, in turn, depends on
4629                  * well-behaving guests: They have to keep IRQs disabled at
4630                  * least as long as the NMI handler runs. Otherwise we may
4631                  * cause NMI nesting, maybe breaking the guest. But as this is
4632                  * highly unlikely, we can live with the residual risk.
4633                  */
4634                 vmx->soft_vnmi_blocked = 1;
4635                 vmx->vnmi_blocked_time = 0;
4636         }
4637
4638         ++vcpu->stat.nmi_injections;
4639         vmx->nmi_known_unmasked = false;
4640         if (vmx->rmode.vm86_active) {
4641                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4642                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4643                 return;
4644         }
4645         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4646                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4647 }
4648
4649 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4650 {
4651         if (!cpu_has_virtual_nmis())
4652                 return to_vmx(vcpu)->soft_vnmi_blocked;
4653         if (to_vmx(vcpu)->nmi_known_unmasked)
4654                 return false;
4655         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4656 }
4657
4658 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4659 {
4660         struct vcpu_vmx *vmx = to_vmx(vcpu);
4661
4662         if (!cpu_has_virtual_nmis()) {
4663                 if (vmx->soft_vnmi_blocked != masked) {
4664                         vmx->soft_vnmi_blocked = masked;
4665                         vmx->vnmi_blocked_time = 0;
4666                 }
4667         } else {
4668                 vmx->nmi_known_unmasked = !masked;
4669                 if (masked)
4670                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4671                                       GUEST_INTR_STATE_NMI);
4672                 else
4673                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4674                                         GUEST_INTR_STATE_NMI);
4675         }
4676 }
4677
4678 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4679 {
4680         if (to_vmx(vcpu)->nested.nested_run_pending)
4681                 return 0;
4682
4683         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4684                 return 0;
4685
4686         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4687                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4688                    | GUEST_INTR_STATE_NMI));
4689 }
4690
4691 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4692 {
4693         return (!to_vmx(vcpu)->nested.nested_run_pending &&
4694                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4695                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4696                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4697 }
4698
4699 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4700 {
4701         int ret;
4702         struct kvm_userspace_memory_region tss_mem = {
4703                 .slot = TSS_PRIVATE_MEMSLOT,
4704                 .guest_phys_addr = addr,
4705                 .memory_size = PAGE_SIZE * 3,
4706                 .flags = 0,
4707         };
4708
4709         ret = kvm_set_memory_region(kvm, &tss_mem);
4710         if (ret)
4711                 return ret;
4712         kvm->arch.tss_addr = addr;
4713         return init_rmode_tss(kvm);
4714 }
4715
4716 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4717 {
4718         switch (vec) {
4719         case BP_VECTOR:
4720                 /*
4721                  * Update instruction length as we may reinject the exception
4722                  * from user space while in guest debugging mode.
4723                  */
4724                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4725                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4726                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4727                         return false;
4728                 /* fall through */
4729         case DB_VECTOR:
4730                 if (vcpu->guest_debug &
4731                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4732                         return false;
4733                 /* fall through */
4734         case DE_VECTOR:
4735         case OF_VECTOR:
4736         case BR_VECTOR:
4737         case UD_VECTOR:
4738         case DF_VECTOR:
4739         case SS_VECTOR:
4740         case GP_VECTOR:
4741         case MF_VECTOR:
4742                 return true;
4743         break;
4744         }
4745         return false;
4746 }
4747
4748 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4749                                   int vec, u32 err_code)
4750 {
4751         /*
4752          * Instruction with address size override prefix opcode 0x67
4753          * Cause the #SS fault with 0 error code in VM86 mode.
4754          */
4755         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4756                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4757                         if (vcpu->arch.halt_request) {
4758                                 vcpu->arch.halt_request = 0;
4759                                 return kvm_emulate_halt(vcpu);
4760                         }
4761                         return 1;
4762                 }
4763                 return 0;
4764         }
4765
4766         /*
4767          * Forward all other exceptions that are valid in real mode.
4768          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4769          *        the required debugging infrastructure rework.
4770          */
4771         kvm_queue_exception(vcpu, vec);
4772         return 1;
4773 }
4774
4775 /*
4776  * Trigger machine check on the host. We assume all the MSRs are already set up
4777  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4778  * We pass a fake environment to the machine check handler because we want
4779  * the guest to be always treated like user space, no matter what context
4780  * it used internally.
4781  */
4782 static void kvm_machine_check(void)
4783 {
4784 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4785         struct pt_regs regs = {
4786                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4787                 .flags = X86_EFLAGS_IF,
4788         };
4789
4790         do_machine_check(&regs, 0);
4791 #endif
4792 }
4793
4794 static int handle_machine_check(struct kvm_vcpu *vcpu)
4795 {
4796         /* already handled by vcpu_run */
4797         return 1;
4798 }
4799
4800 static int handle_exception(struct kvm_vcpu *vcpu)
4801 {
4802         struct vcpu_vmx *vmx = to_vmx(vcpu);
4803         struct kvm_run *kvm_run = vcpu->run;
4804         u32 intr_info, ex_no, error_code;
4805         unsigned long cr2, rip, dr6;
4806         u32 vect_info;
4807         enum emulation_result er;
4808
4809         vect_info = vmx->idt_vectoring_info;
4810         intr_info = vmx->exit_intr_info;
4811
4812         if (is_machine_check(intr_info))
4813                 return handle_machine_check(vcpu);
4814
4815         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4816                 return 1;  /* already handled by vmx_vcpu_run() */
4817
4818         if (is_no_device(intr_info)) {
4819                 vmx_fpu_activate(vcpu);
4820                 return 1;
4821         }
4822
4823         if (is_invalid_opcode(intr_info)) {
4824                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4825                 if (er != EMULATE_DONE)
4826                         kvm_queue_exception(vcpu, UD_VECTOR);
4827                 return 1;
4828         }
4829
4830         error_code = 0;
4831         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4832                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4833
4834         /*
4835          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4836          * MMIO, it is better to report an internal error.
4837          * See the comments in vmx_handle_exit.
4838          */
4839         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4840             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4841                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4842                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4843                 vcpu->run->internal.ndata = 2;
4844                 vcpu->run->internal.data[0] = vect_info;
4845                 vcpu->run->internal.data[1] = intr_info;
4846                 return 0;
4847         }
4848
4849         if (is_page_fault(intr_info)) {
4850                 /* EPT won't cause page fault directly */
4851                 BUG_ON(enable_ept);
4852                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4853                 trace_kvm_page_fault(cr2, error_code);
4854
4855                 if (kvm_event_needs_reinjection(vcpu))
4856                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4857                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4858         }
4859
4860         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4861
4862         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4863                 return handle_rmode_exception(vcpu, ex_no, error_code);
4864
4865         switch (ex_no) {
4866         case DB_VECTOR:
4867                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4868                 if (!(vcpu->guest_debug &
4869                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4870                         vcpu->arch.dr6 &= ~15;
4871                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
4872                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
4873                                 skip_emulated_instruction(vcpu);
4874
4875                         kvm_queue_exception(vcpu, DB_VECTOR);
4876                         return 1;
4877                 }
4878                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4879                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4880                 /* fall through */
4881         case BP_VECTOR:
4882                 /*
4883                  * Update instruction length as we may reinject #BP from
4884                  * user space while in guest debugging mode. Reading it for
4885                  * #DB as well causes no harm, it is not used in that case.
4886                  */
4887                 vmx->vcpu.arch.event_exit_inst_len =
4888                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4889                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4890                 rip = kvm_rip_read(vcpu);
4891                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4892                 kvm_run->debug.arch.exception = ex_no;
4893                 break;
4894         default:
4895                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4896                 kvm_run->ex.exception = ex_no;
4897                 kvm_run->ex.error_code = error_code;
4898                 break;
4899         }
4900         return 0;
4901 }
4902
4903 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4904 {
4905         ++vcpu->stat.irq_exits;
4906         return 1;
4907 }
4908
4909 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4910 {
4911         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4912         return 0;
4913 }
4914
4915 static int handle_io(struct kvm_vcpu *vcpu)
4916 {
4917         unsigned long exit_qualification;
4918         int size, in, string;
4919         unsigned port;
4920
4921         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4922         string = (exit_qualification & 16) != 0;
4923         in = (exit_qualification & 8) != 0;
4924
4925         ++vcpu->stat.io_exits;
4926
4927         if (string || in)
4928                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4929
4930         port = exit_qualification >> 16;
4931         size = (exit_qualification & 7) + 1;
4932         skip_emulated_instruction(vcpu);
4933
4934         return kvm_fast_pio_out(vcpu, size, port);
4935 }
4936
4937 static void
4938 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4939 {
4940         /*
4941          * Patch in the VMCALL instruction:
4942          */
4943         hypercall[0] = 0x0f;
4944         hypercall[1] = 0x01;
4945         hypercall[2] = 0xc1;
4946 }
4947
4948 static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4949 {
4950         unsigned long always_on = VMXON_CR0_ALWAYSON;
4951
4952         if (nested_vmx_secondary_ctls_high &
4953                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4954             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4955                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
4956         return (val & always_on) == always_on;
4957 }
4958
4959 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4960 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4961 {
4962         if (is_guest_mode(vcpu)) {
4963                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4964                 unsigned long orig_val = val;
4965
4966                 /*
4967                  * We get here when L2 changed cr0 in a way that did not change
4968                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4969                  * but did change L0 shadowed bits. So we first calculate the
4970                  * effective cr0 value that L1 would like to write into the
4971                  * hardware. It consists of the L2-owned bits from the new
4972                  * value combined with the L1-owned bits from L1's guest_cr0.
4973                  */
4974                 val = (val & ~vmcs12->cr0_guest_host_mask) |
4975                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4976
4977                 if (!nested_cr0_valid(vmcs12, val))
4978                         return 1;
4979
4980                 if (kvm_set_cr0(vcpu, val))
4981                         return 1;
4982                 vmcs_writel(CR0_READ_SHADOW, orig_val);
4983                 return 0;
4984         } else {
4985                 if (to_vmx(vcpu)->nested.vmxon &&
4986                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4987                         return 1;
4988                 return kvm_set_cr0(vcpu, val);
4989         }
4990 }
4991
4992 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4993 {
4994         if (is_guest_mode(vcpu)) {
4995                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4996                 unsigned long orig_val = val;
4997
4998                 /* analogously to handle_set_cr0 */
4999                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5000                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5001                 if (kvm_set_cr4(vcpu, val))
5002                         return 1;
5003                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5004                 return 0;
5005         } else
5006                 return kvm_set_cr4(vcpu, val);
5007 }
5008
5009 /* called to set cr0 as approriate for clts instruction exit. */
5010 static void handle_clts(struct kvm_vcpu *vcpu)
5011 {
5012         if (is_guest_mode(vcpu)) {
5013                 /*
5014                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5015                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5016                  * just pretend it's off (also in arch.cr0 for fpu_activate).
5017                  */
5018                 vmcs_writel(CR0_READ_SHADOW,
5019                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5020                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5021         } else
5022                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5023 }
5024
5025 static int handle_cr(struct kvm_vcpu *vcpu)
5026 {
5027         unsigned long exit_qualification, val;
5028         int cr;
5029         int reg;
5030         int err;
5031
5032         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5033         cr = exit_qualification & 15;
5034         reg = (exit_qualification >> 8) & 15;
5035         switch ((exit_qualification >> 4) & 3) {
5036         case 0: /* mov to cr */
5037                 val = kvm_register_readl(vcpu, reg);
5038                 trace_kvm_cr_write(cr, val);
5039                 switch (cr) {
5040                 case 0:
5041                         err = handle_set_cr0(vcpu, val);
5042                         kvm_complete_insn_gp(vcpu, err);
5043                         return 1;
5044                 case 3:
5045                         err = kvm_set_cr3(vcpu, val);
5046                         kvm_complete_insn_gp(vcpu, err);
5047                         return 1;
5048                 case 4:
5049                         err = handle_set_cr4(vcpu, val);
5050                         kvm_complete_insn_gp(vcpu, err);
5051                         return 1;
5052                 case 8: {
5053                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5054                                 u8 cr8 = (u8)val;
5055                                 err = kvm_set_cr8(vcpu, cr8);
5056                                 kvm_complete_insn_gp(vcpu, err);
5057                                 if (irqchip_in_kernel(vcpu->kvm))
5058                                         return 1;
5059                                 if (cr8_prev <= cr8)
5060                                         return 1;
5061                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5062                                 return 0;
5063                         }
5064                 }
5065                 break;
5066         case 2: /* clts */
5067                 handle_clts(vcpu);
5068                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5069                 skip_emulated_instruction(vcpu);
5070                 vmx_fpu_activate(vcpu);
5071                 return 1;
5072         case 1: /*mov from cr*/
5073                 switch (cr) {
5074                 case 3:
5075                         val = kvm_read_cr3(vcpu);
5076                         kvm_register_write(vcpu, reg, val);
5077                         trace_kvm_cr_read(cr, val);
5078                         skip_emulated_instruction(vcpu);
5079                         return 1;
5080                 case 8:
5081                         val = kvm_get_cr8(vcpu);
5082                         kvm_register_write(vcpu, reg, val);
5083                         trace_kvm_cr_read(cr, val);
5084                         skip_emulated_instruction(vcpu);
5085                         return 1;
5086                 }
5087                 break;
5088         case 3: /* lmsw */
5089                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5090                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5091                 kvm_lmsw(vcpu, val);
5092
5093                 skip_emulated_instruction(vcpu);
5094                 return 1;
5095         default:
5096                 break;
5097         }
5098         vcpu->run->exit_reason = 0;
5099         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5100                (int)(exit_qualification >> 4) & 3, cr);
5101         return 0;
5102 }
5103
5104 static int handle_dr(struct kvm_vcpu *vcpu)
5105 {
5106         unsigned long exit_qualification;
5107         int dr, dr7, reg;
5108
5109         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5110         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5111
5112         /* First, if DR does not exist, trigger UD */
5113         if (!kvm_require_dr(vcpu, dr))
5114                 return 1;
5115
5116         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5117         if (!kvm_require_cpl(vcpu, 0))
5118                 return 1;
5119         dr7 = vmcs_readl(GUEST_DR7);
5120         if (dr7 & DR7_GD) {
5121                 /*
5122                  * As the vm-exit takes precedence over the debug trap, we
5123                  * need to emulate the latter, either for the host or the
5124                  * guest debugging itself.
5125                  */
5126                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5127                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5128                         vcpu->run->debug.arch.dr7 = dr7;
5129                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5130                         vcpu->run->debug.arch.exception = DB_VECTOR;
5131                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5132                         return 0;
5133                 } else {
5134                         vcpu->arch.dr6 &= ~15;
5135                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5136                         kvm_queue_exception(vcpu, DB_VECTOR);
5137                         return 1;
5138                 }
5139         }
5140
5141         if (vcpu->guest_debug == 0) {
5142                 u32 cpu_based_vm_exec_control;
5143
5144                 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5145                 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5146                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5147
5148                 /*
5149                  * No more DR vmexits; force a reload of the debug registers
5150                  * and reenter on this instruction.  The next vmexit will
5151                  * retrieve the full state of the debug registers.
5152                  */
5153                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5154                 return 1;
5155         }
5156
5157         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5158         if (exit_qualification & TYPE_MOV_FROM_DR) {
5159                 unsigned long val;
5160
5161                 if (kvm_get_dr(vcpu, dr, &val))
5162                         return 1;
5163                 kvm_register_write(vcpu, reg, val);
5164         } else
5165                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5166                         return 1;
5167
5168         skip_emulated_instruction(vcpu);
5169         return 1;
5170 }
5171
5172 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5173 {
5174         return vcpu->arch.dr6;
5175 }
5176
5177 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5178 {
5179 }
5180
5181 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5182 {
5183         u32 cpu_based_vm_exec_control;
5184
5185         get_debugreg(vcpu->arch.db[0], 0);
5186         get_debugreg(vcpu->arch.db[1], 1);
5187         get_debugreg(vcpu->arch.db[2], 2);
5188         get_debugreg(vcpu->arch.db[3], 3);
5189         get_debugreg(vcpu->arch.dr6, 6);
5190         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5191
5192         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5193
5194         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5195         cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5196         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5197 }
5198
5199 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5200 {
5201         vmcs_writel(GUEST_DR7, val);
5202 }
5203
5204 static int handle_cpuid(struct kvm_vcpu *vcpu)
5205 {
5206         kvm_emulate_cpuid(vcpu);
5207         return 1;
5208 }
5209
5210 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5211 {
5212         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5213         u64 data;
5214
5215         if (vmx_get_msr(vcpu, ecx, &data)) {
5216                 trace_kvm_msr_read_ex(ecx);
5217                 kvm_inject_gp(vcpu, 0);
5218                 return 1;
5219         }
5220
5221         trace_kvm_msr_read(ecx, data);
5222
5223         /* FIXME: handling of bits 32:63 of rax, rdx */
5224         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5225         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
5226         skip_emulated_instruction(vcpu);
5227         return 1;
5228 }
5229
5230 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5231 {
5232         struct msr_data msr;
5233         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5234         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5235                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5236
5237         msr.data = data;
5238         msr.index = ecx;
5239         msr.host_initiated = false;
5240         if (kvm_set_msr(vcpu, &msr) != 0) {
5241                 trace_kvm_msr_write_ex(ecx, data);
5242                 kvm_inject_gp(vcpu, 0);
5243                 return 1;
5244         }
5245
5246         trace_kvm_msr_write(ecx, data);
5247         skip_emulated_instruction(vcpu);
5248         return 1;
5249 }
5250
5251 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5252 {
5253         kvm_make_request(KVM_REQ_EVENT, vcpu);
5254         return 1;
5255 }
5256
5257 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5258 {
5259         u32 cpu_based_vm_exec_control;
5260
5261         /* clear pending irq */
5262         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5263         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5264         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5265
5266         kvm_make_request(KVM_REQ_EVENT, vcpu);
5267
5268         ++vcpu->stat.irq_window_exits;
5269
5270         /*
5271          * If the user space waits to inject interrupts, exit as soon as
5272          * possible
5273          */
5274         if (!irqchip_in_kernel(vcpu->kvm) &&
5275             vcpu->run->request_interrupt_window &&
5276             !kvm_cpu_has_interrupt(vcpu)) {
5277                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
5278                 return 0;
5279         }
5280         return 1;
5281 }
5282
5283 static int handle_halt(struct kvm_vcpu *vcpu)
5284 {
5285         skip_emulated_instruction(vcpu);
5286         return kvm_emulate_halt(vcpu);
5287 }
5288
5289 static int handle_vmcall(struct kvm_vcpu *vcpu)
5290 {
5291         skip_emulated_instruction(vcpu);
5292         kvm_emulate_hypercall(vcpu);
5293         return 1;
5294 }
5295
5296 static int handle_invd(struct kvm_vcpu *vcpu)
5297 {
5298         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5299 }
5300
5301 static int handle_invlpg(struct kvm_vcpu *vcpu)
5302 {
5303         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5304
5305         kvm_mmu_invlpg(vcpu, exit_qualification);
5306         skip_emulated_instruction(vcpu);
5307         return 1;
5308 }
5309
5310 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5311 {
5312         int err;
5313
5314         err = kvm_rdpmc(vcpu);
5315         kvm_complete_insn_gp(vcpu, err);
5316
5317         return 1;
5318 }
5319
5320 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5321 {
5322         skip_emulated_instruction(vcpu);
5323         kvm_emulate_wbinvd(vcpu);
5324         return 1;
5325 }
5326
5327 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5328 {
5329         u64 new_bv = kvm_read_edx_eax(vcpu);
5330         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5331
5332         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5333                 skip_emulated_instruction(vcpu);
5334         return 1;
5335 }
5336
5337 static int handle_apic_access(struct kvm_vcpu *vcpu)
5338 {
5339         if (likely(fasteoi)) {
5340                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5341                 int access_type, offset;
5342
5343                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5344                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5345                 /*
5346                  * Sane guest uses MOV to write EOI, with written value
5347                  * not cared. So make a short-circuit here by avoiding
5348                  * heavy instruction emulation.
5349                  */
5350                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5351                     (offset == APIC_EOI)) {
5352                         kvm_lapic_set_eoi(vcpu);
5353                         skip_emulated_instruction(vcpu);
5354                         return 1;
5355                 }
5356         }
5357         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5358 }
5359
5360 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5361 {
5362         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5363         int vector = exit_qualification & 0xff;
5364
5365         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5366         kvm_apic_set_eoi_accelerated(vcpu, vector);
5367         return 1;
5368 }
5369
5370 static int handle_apic_write(struct kvm_vcpu *vcpu)
5371 {
5372         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5373         u32 offset = exit_qualification & 0xfff;
5374
5375         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5376         kvm_apic_write_nodecode(vcpu, offset);
5377         return 1;
5378 }
5379
5380 static int handle_task_switch(struct kvm_vcpu *vcpu)
5381 {
5382         struct vcpu_vmx *vmx = to_vmx(vcpu);
5383         unsigned long exit_qualification;
5384         bool has_error_code = false;
5385         u32 error_code = 0;
5386         u16 tss_selector;
5387         int reason, type, idt_v, idt_index;
5388
5389         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5390         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5391         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5392
5393         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5394
5395         reason = (u32)exit_qualification >> 30;
5396         if (reason == TASK_SWITCH_GATE && idt_v) {
5397                 switch (type) {
5398                 case INTR_TYPE_NMI_INTR:
5399                         vcpu->arch.nmi_injected = false;
5400                         vmx_set_nmi_mask(vcpu, true);
5401                         break;
5402                 case INTR_TYPE_EXT_INTR:
5403                 case INTR_TYPE_SOFT_INTR:
5404                         kvm_clear_interrupt_queue(vcpu);
5405                         break;
5406                 case INTR_TYPE_HARD_EXCEPTION:
5407                         if (vmx->idt_vectoring_info &
5408                             VECTORING_INFO_DELIVER_CODE_MASK) {
5409                                 has_error_code = true;
5410                                 error_code =
5411                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5412                         }
5413                         /* fall through */
5414                 case INTR_TYPE_SOFT_EXCEPTION:
5415                         kvm_clear_exception_queue(vcpu);
5416                         break;
5417                 default:
5418                         break;
5419                 }
5420         }
5421         tss_selector = exit_qualification;
5422
5423         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5424                        type != INTR_TYPE_EXT_INTR &&
5425                        type != INTR_TYPE_NMI_INTR))
5426                 skip_emulated_instruction(vcpu);
5427
5428         if (kvm_task_switch(vcpu, tss_selector,
5429                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5430                             has_error_code, error_code) == EMULATE_FAIL) {
5431                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5432                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5433                 vcpu->run->internal.ndata = 0;
5434                 return 0;
5435         }
5436
5437         /* clear all local breakpoint enable flags */
5438         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~0x155);
5439
5440         /*
5441          * TODO: What about debug traps on tss switch?
5442          *       Are we supposed to inject them and update dr6?
5443          */
5444
5445         return 1;
5446 }
5447
5448 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5449 {
5450         unsigned long exit_qualification;
5451         gpa_t gpa;
5452         u32 error_code;
5453         int gla_validity;
5454
5455         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5456
5457         gla_validity = (exit_qualification >> 7) & 0x3;
5458         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5459                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5460                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5461                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5462                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5463                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5464                         (long unsigned int)exit_qualification);
5465                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5466                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5467                 return 0;
5468         }
5469
5470         /*
5471          * EPT violation happened while executing iret from NMI,
5472          * "blocked by NMI" bit has to be set before next VM entry.
5473          * There are errata that may cause this bit to not be set:
5474          * AAK134, BY25.
5475          */
5476         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5477                         cpu_has_virtual_nmis() &&
5478                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5479                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5480
5481         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5482         trace_kvm_page_fault(gpa, exit_qualification);
5483
5484         /* It is a write fault? */
5485         error_code = exit_qualification & PFERR_WRITE_MASK;
5486         /* It is a fetch fault? */
5487         error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
5488         /* ept page table is present? */
5489         error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
5490
5491         vcpu->arch.exit_qualification = exit_qualification;
5492
5493         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5494 }
5495
5496 static u64 ept_rsvd_mask(u64 spte, int level)
5497 {
5498         int i;
5499         u64 mask = 0;
5500
5501         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5502                 mask |= (1ULL << i);
5503
5504         if (level == 4)
5505                 /* bits 7:3 reserved */
5506                 mask |= 0xf8;
5507         else if (spte & (1ULL << 7))
5508                 /*
5509                  * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively,
5510                  * level == 1 if the hypervisor is using the ignored bit 7.
5511                  */
5512                 mask |= (PAGE_SIZE << ((level - 1) * 9)) - PAGE_SIZE;
5513         else if (level > 1)
5514                 /* bits 6:3 reserved */
5515                 mask |= 0x78;
5516
5517         return mask;
5518 }
5519
5520 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5521                                        int level)
5522 {
5523         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5524
5525         /* 010b (write-only) */
5526         WARN_ON((spte & 0x7) == 0x2);
5527
5528         /* 110b (write/execute) */
5529         WARN_ON((spte & 0x7) == 0x6);
5530
5531         /* 100b (execute-only) and value not supported by logical processor */
5532         if (!cpu_has_vmx_ept_execute_only())
5533                 WARN_ON((spte & 0x7) == 0x4);
5534
5535         /* not 000b */
5536         if ((spte & 0x7)) {
5537                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5538
5539                 if (rsvd_bits != 0) {
5540                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5541                                          __func__, rsvd_bits);
5542                         WARN_ON(1);
5543                 }
5544
5545                 /* bits 5:3 are _not_ reserved for large page or leaf page */
5546                 if ((rsvd_bits & 0x38) == 0) {
5547                         u64 ept_mem_type = (spte & 0x38) >> 3;
5548
5549                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
5550                             ept_mem_type == 7) {
5551                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5552                                                 __func__, ept_mem_type);
5553                                 WARN_ON(1);
5554                         }
5555                 }
5556         }
5557 }
5558
5559 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5560 {
5561         u64 sptes[4];
5562         int nr_sptes, i, ret;
5563         gpa_t gpa;
5564
5565         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5566         if (!kvm_io_bus_write(vcpu->kvm, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5567                 skip_emulated_instruction(vcpu);
5568                 return 1;
5569         }
5570
5571         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5572         if (likely(ret == RET_MMIO_PF_EMULATE))
5573                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5574                                               EMULATE_DONE;
5575
5576         if (unlikely(ret == RET_MMIO_PF_INVALID))
5577                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5578
5579         if (unlikely(ret == RET_MMIO_PF_RETRY))
5580                 return 1;
5581
5582         /* It is the real ept misconfig */
5583         printk(KERN_ERR "EPT: Misconfiguration.\n");
5584         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5585
5586         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5587
5588         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5589                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5590
5591         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5592         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5593
5594         return 0;
5595 }
5596
5597 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5598 {
5599         u32 cpu_based_vm_exec_control;
5600
5601         /* clear pending NMI */
5602         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5603         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5604         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5605         ++vcpu->stat.nmi_window_exits;
5606         kvm_make_request(KVM_REQ_EVENT, vcpu);
5607
5608         return 1;
5609 }
5610
5611 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5612 {
5613         struct vcpu_vmx *vmx = to_vmx(vcpu);
5614         enum emulation_result err = EMULATE_DONE;
5615         int ret = 1;
5616         u32 cpu_exec_ctrl;
5617         bool intr_window_requested;
5618         unsigned count = 130;
5619
5620         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5621         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5622
5623         while (vmx->emulation_required && count-- != 0) {
5624                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5625                         return handle_interrupt_window(&vmx->vcpu);
5626
5627                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5628                         return 1;
5629
5630                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5631
5632                 if (err == EMULATE_USER_EXIT) {
5633                         ++vcpu->stat.mmio_exits;
5634                         ret = 0;
5635                         goto out;
5636                 }
5637
5638                 if (err != EMULATE_DONE) {
5639                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5640                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5641                         vcpu->run->internal.ndata = 0;
5642                         return 0;
5643                 }
5644
5645                 if (vcpu->arch.halt_request) {
5646                         vcpu->arch.halt_request = 0;
5647                         ret = kvm_emulate_halt(vcpu);
5648                         goto out;
5649                 }
5650
5651                 if (signal_pending(current))
5652                         goto out;
5653                 if (need_resched())
5654                         schedule();
5655         }
5656
5657 out:
5658         return ret;
5659 }
5660
5661 static int __grow_ple_window(int val)
5662 {
5663         if (ple_window_grow < 1)
5664                 return ple_window;
5665
5666         val = min(val, ple_window_actual_max);
5667
5668         if (ple_window_grow < ple_window)
5669                 val *= ple_window_grow;
5670         else
5671                 val += ple_window_grow;
5672
5673         return val;
5674 }
5675
5676 static int __shrink_ple_window(int val, int modifier, int minimum)
5677 {
5678         if (modifier < 1)
5679                 return ple_window;
5680
5681         if (modifier < ple_window)
5682                 val /= modifier;
5683         else
5684                 val -= modifier;
5685
5686         return max(val, minimum);
5687 }
5688
5689 static void grow_ple_window(struct kvm_vcpu *vcpu)
5690 {
5691         struct vcpu_vmx *vmx = to_vmx(vcpu);
5692         int old = vmx->ple_window;
5693
5694         vmx->ple_window = __grow_ple_window(old);
5695
5696         if (vmx->ple_window != old)
5697                 vmx->ple_window_dirty = true;
5698
5699         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
5700 }
5701
5702 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5703 {
5704         struct vcpu_vmx *vmx = to_vmx(vcpu);
5705         int old = vmx->ple_window;
5706
5707         vmx->ple_window = __shrink_ple_window(old,
5708                                               ple_window_shrink, ple_window);
5709
5710         if (vmx->ple_window != old)
5711                 vmx->ple_window_dirty = true;
5712
5713         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
5714 }
5715
5716 /*
5717  * ple_window_actual_max is computed to be one grow_ple_window() below
5718  * ple_window_max. (See __grow_ple_window for the reason.)
5719  * This prevents overflows, because ple_window_max is int.
5720  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5721  * this process.
5722  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5723  */
5724 static void update_ple_window_actual_max(void)
5725 {
5726         ple_window_actual_max =
5727                         __shrink_ple_window(max(ple_window_max, ple_window),
5728                                             ple_window_grow, INT_MIN);
5729 }
5730
5731 static __init int hardware_setup(void)
5732 {
5733         int r = -ENOMEM, i, msr;
5734
5735         rdmsrl_safe(MSR_EFER, &host_efer);
5736
5737         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
5738                 kvm_define_shared_msr(i, vmx_msr_index[i]);
5739
5740         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
5741         if (!vmx_io_bitmap_a)
5742                 return r;
5743
5744         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
5745         if (!vmx_io_bitmap_b)
5746                 goto out;
5747
5748         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
5749         if (!vmx_msr_bitmap_legacy)
5750                 goto out1;
5751
5752         vmx_msr_bitmap_legacy_x2apic =
5753                                 (unsigned long *)__get_free_page(GFP_KERNEL);
5754         if (!vmx_msr_bitmap_legacy_x2apic)
5755                 goto out2;
5756
5757         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
5758         if (!vmx_msr_bitmap_longmode)
5759                 goto out3;
5760
5761         vmx_msr_bitmap_longmode_x2apic =
5762                                 (unsigned long *)__get_free_page(GFP_KERNEL);
5763         if (!vmx_msr_bitmap_longmode_x2apic)
5764                 goto out4;
5765         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
5766         if (!vmx_vmread_bitmap)
5767                 goto out5;
5768
5769         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
5770         if (!vmx_vmwrite_bitmap)
5771                 goto out6;
5772
5773         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
5774         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
5775
5776         /*
5777          * Allow direct access to the PC debug port (it is often used for I/O
5778          * delays, but the vmexits simply slow things down).
5779          */
5780         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
5781         clear_bit(0x80, vmx_io_bitmap_a);
5782
5783         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
5784
5785         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
5786         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
5787
5788         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
5789         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
5790         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
5791         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
5792         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
5793         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
5794         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
5795
5796         memcpy(vmx_msr_bitmap_legacy_x2apic,
5797                         vmx_msr_bitmap_legacy, PAGE_SIZE);
5798         memcpy(vmx_msr_bitmap_longmode_x2apic,
5799                         vmx_msr_bitmap_longmode, PAGE_SIZE);
5800
5801         if (enable_apicv) {
5802                 for (msr = 0x800; msr <= 0x8ff; msr++)
5803                         vmx_disable_intercept_msr_read_x2apic(msr);
5804
5805                 /* According SDM, in x2apic mode, the whole id reg is used.
5806                  * But in KVM, it only use the highest eight bits. Need to
5807                  * intercept it */
5808                 vmx_enable_intercept_msr_read_x2apic(0x802);
5809                 /* TMCCT */
5810                 vmx_enable_intercept_msr_read_x2apic(0x839);
5811                 /* TPR */
5812                 vmx_disable_intercept_msr_write_x2apic(0x808);
5813                 /* EOI */
5814                 vmx_disable_intercept_msr_write_x2apic(0x80b);
5815                 /* SELF-IPI */
5816                 vmx_disable_intercept_msr_write_x2apic(0x83f);
5817         }
5818
5819         if (enable_ept) {
5820                 kvm_mmu_set_mask_ptes(0ull,
5821                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
5822                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
5823                         0ull, VMX_EPT_EXECUTABLE_MASK);
5824                 ept_set_mmio_spte_mask();
5825                 kvm_enable_tdp();
5826         } else
5827                 kvm_disable_tdp();
5828
5829         update_ple_window_actual_max();
5830
5831         if (setup_vmcs_config(&vmcs_config) < 0) {
5832                 r = -EIO;
5833                 goto out7;
5834     }
5835
5836         if (boot_cpu_has(X86_FEATURE_NX))
5837                 kvm_enable_efer_bits(EFER_NX);
5838
5839         if (!cpu_has_vmx_vpid())
5840                 enable_vpid = 0;
5841         if (!cpu_has_vmx_shadow_vmcs())
5842                 enable_shadow_vmcs = 0;
5843         if (enable_shadow_vmcs)
5844                 init_vmcs_shadow_fields();
5845
5846         if (!cpu_has_vmx_ept() ||
5847             !cpu_has_vmx_ept_4levels()) {
5848                 enable_ept = 0;
5849                 enable_unrestricted_guest = 0;
5850                 enable_ept_ad_bits = 0;
5851         }
5852
5853         if (!cpu_has_vmx_ept_ad_bits())
5854                 enable_ept_ad_bits = 0;
5855
5856         if (!cpu_has_vmx_unrestricted_guest())
5857                 enable_unrestricted_guest = 0;
5858
5859         if (!cpu_has_vmx_flexpriority()) {
5860                 flexpriority_enabled = 0;
5861
5862                 /*
5863                  * set_apic_access_page_addr() is used to reload apic access
5864                  * page upon invalidation.  No need to do anything if the
5865                  * processor does not have the APIC_ACCESS_ADDR VMCS field.
5866                  */
5867                 kvm_x86_ops->set_apic_access_page_addr = NULL;
5868         }
5869
5870         if (!cpu_has_vmx_tpr_shadow())
5871                 kvm_x86_ops->update_cr8_intercept = NULL;
5872
5873         if (enable_ept && !cpu_has_vmx_ept_2m_page())
5874                 kvm_disable_largepages();
5875
5876         if (!cpu_has_vmx_ple())
5877                 ple_gap = 0;
5878
5879         if (!cpu_has_vmx_apicv())
5880                 enable_apicv = 0;
5881
5882         if (enable_apicv)
5883                 kvm_x86_ops->update_cr8_intercept = NULL;
5884         else {
5885                 kvm_x86_ops->hwapic_irr_update = NULL;
5886                 kvm_x86_ops->deliver_posted_interrupt = NULL;
5887                 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
5888         }
5889
5890         if (nested)
5891                 nested_vmx_setup_ctls_msrs();
5892
5893         return alloc_kvm_area();
5894
5895 out7:
5896         free_page((unsigned long)vmx_vmwrite_bitmap);
5897 out6:
5898         free_page((unsigned long)vmx_vmread_bitmap);
5899 out5:
5900         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5901 out4:
5902         free_page((unsigned long)vmx_msr_bitmap_longmode);
5903 out3:
5904         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
5905 out2:
5906         free_page((unsigned long)vmx_msr_bitmap_legacy);
5907 out1:
5908         free_page((unsigned long)vmx_io_bitmap_b);
5909 out:
5910         free_page((unsigned long)vmx_io_bitmap_a);
5911
5912     return r;
5913 }
5914
5915 static __exit void hardware_unsetup(void)
5916 {
5917         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
5918         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5919         free_page((unsigned long)vmx_msr_bitmap_legacy);
5920         free_page((unsigned long)vmx_msr_bitmap_longmode);
5921         free_page((unsigned long)vmx_io_bitmap_b);
5922         free_page((unsigned long)vmx_io_bitmap_a);
5923         free_page((unsigned long)vmx_vmwrite_bitmap);
5924         free_page((unsigned long)vmx_vmread_bitmap);
5925
5926         free_kvm_area();
5927 }
5928
5929 /*
5930  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5931  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5932  */
5933 static int handle_pause(struct kvm_vcpu *vcpu)
5934 {
5935         if (ple_gap)
5936                 grow_ple_window(vcpu);
5937
5938         skip_emulated_instruction(vcpu);
5939         kvm_vcpu_on_spin(vcpu);
5940
5941         return 1;
5942 }
5943
5944 static int handle_nop(struct kvm_vcpu *vcpu)
5945 {
5946         skip_emulated_instruction(vcpu);
5947         return 1;
5948 }
5949
5950 static int handle_mwait(struct kvm_vcpu *vcpu)
5951 {
5952         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5953         return handle_nop(vcpu);
5954 }
5955
5956 static int handle_monitor(struct kvm_vcpu *vcpu)
5957 {
5958         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5959         return handle_nop(vcpu);
5960 }
5961
5962 /*
5963  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5964  * We could reuse a single VMCS for all the L2 guests, but we also want the
5965  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5966  * allows keeping them loaded on the processor, and in the future will allow
5967  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5968  * every entry if they never change.
5969  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5970  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5971  *
5972  * The following functions allocate and free a vmcs02 in this pool.
5973  */
5974
5975 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5976 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5977 {
5978         struct vmcs02_list *item;
5979         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5980                 if (item->vmptr == vmx->nested.current_vmptr) {
5981                         list_move(&item->list, &vmx->nested.vmcs02_pool);
5982                         return &item->vmcs02;
5983                 }
5984
5985         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5986                 /* Recycle the least recently used VMCS. */
5987                 item = list_entry(vmx->nested.vmcs02_pool.prev,
5988                         struct vmcs02_list, list);
5989                 item->vmptr = vmx->nested.current_vmptr;
5990                 list_move(&item->list, &vmx->nested.vmcs02_pool);
5991                 return &item->vmcs02;
5992         }
5993
5994         /* Create a new VMCS */
5995         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5996         if (!item)
5997                 return NULL;
5998         item->vmcs02.vmcs = alloc_vmcs();
5999         if (!item->vmcs02.vmcs) {
6000                 kfree(item);
6001                 return NULL;
6002         }
6003         loaded_vmcs_init(&item->vmcs02);
6004         item->vmptr = vmx->nested.current_vmptr;
6005         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6006         vmx->nested.vmcs02_num++;
6007         return &item->vmcs02;
6008 }
6009
6010 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6011 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6012 {
6013         struct vmcs02_list *item;
6014         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6015                 if (item->vmptr == vmptr) {
6016                         free_loaded_vmcs(&item->vmcs02);
6017                         list_del(&item->list);
6018                         kfree(item);
6019                         vmx->nested.vmcs02_num--;
6020                         return;
6021                 }
6022 }
6023
6024 /*
6025  * Free all VMCSs saved for this vcpu, except the one pointed by
6026  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6027  * must be &vmx->vmcs01.
6028  */
6029 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6030 {
6031         struct vmcs02_list *item, *n;
6032
6033         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6034         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6035                 /*
6036                  * Something will leak if the above WARN triggers.  Better than
6037                  * a use-after-free.
6038                  */
6039                 if (vmx->loaded_vmcs == &item->vmcs02)
6040                         continue;
6041
6042                 free_loaded_vmcs(&item->vmcs02);
6043                 list_del(&item->list);
6044                 kfree(item);
6045                 vmx->nested.vmcs02_num--;
6046         }
6047 }
6048
6049 /*
6050  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6051  * set the success or error code of an emulated VMX instruction, as specified
6052  * by Vol 2B, VMX Instruction Reference, "Conventions".
6053  */
6054 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6055 {
6056         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6057                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6058                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6059 }
6060
6061 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6062 {
6063         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6064                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6065                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6066                         | X86_EFLAGS_CF);
6067 }
6068
6069 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6070                                         u32 vm_instruction_error)
6071 {
6072         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6073                 /*
6074                  * failValid writes the error number to the current VMCS, which
6075                  * can't be done there isn't a current VMCS.
6076                  */
6077                 nested_vmx_failInvalid(vcpu);
6078                 return;
6079         }
6080         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6081                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6082                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6083                         | X86_EFLAGS_ZF);
6084         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6085         /*
6086          * We don't need to force a shadow sync because
6087          * VM_INSTRUCTION_ERROR is not shadowed
6088          */
6089 }
6090
6091 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6092 {
6093         struct vcpu_vmx *vmx =
6094                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6095
6096         vmx->nested.preemption_timer_expired = true;
6097         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6098         kvm_vcpu_kick(&vmx->vcpu);
6099
6100         return HRTIMER_NORESTART;
6101 }
6102
6103 /*
6104  * Decode the memory-address operand of a vmx instruction, as recorded on an
6105  * exit caused by such an instruction (run by a guest hypervisor).
6106  * On success, returns 0. When the operand is invalid, returns 1 and throws
6107  * #UD or #GP.
6108  */
6109 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6110                                  unsigned long exit_qualification,
6111                                  u32 vmx_instruction_info, gva_t *ret)
6112 {
6113         /*
6114          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6115          * Execution", on an exit, vmx_instruction_info holds most of the
6116          * addressing components of the operand. Only the displacement part
6117          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6118          * For how an actual address is calculated from all these components,
6119          * refer to Vol. 1, "Operand Addressing".
6120          */
6121         int  scaling = vmx_instruction_info & 3;
6122         int  addr_size = (vmx_instruction_info >> 7) & 7;
6123         bool is_reg = vmx_instruction_info & (1u << 10);
6124         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6125         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6126         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6127         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6128         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6129
6130         if (is_reg) {
6131                 kvm_queue_exception(vcpu, UD_VECTOR);
6132                 return 1;
6133         }
6134
6135         /* Addr = segment_base + offset */
6136         /* offset = base + [index * scale] + displacement */
6137         *ret = vmx_get_segment_base(vcpu, seg_reg);
6138         if (base_is_valid)
6139                 *ret += kvm_register_read(vcpu, base_reg);
6140         if (index_is_valid)
6141                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
6142         *ret += exit_qualification; /* holds the displacement */
6143
6144         if (addr_size == 1) /* 32 bit */
6145                 *ret &= 0xffffffff;
6146
6147         /*
6148          * TODO: throw #GP (and return 1) in various cases that the VM*
6149          * instructions require it - e.g., offset beyond segment limit,
6150          * unusable or unreadable/unwritable segment, non-canonical 64-bit
6151          * address, and so on. Currently these are not checked.
6152          */
6153         return 0;
6154 }
6155
6156 /*
6157  * This function performs the various checks including
6158  * - if it's 4KB aligned
6159  * - No bits beyond the physical address width are set
6160  * - Returns 0 on success or else 1
6161  * (Intel SDM Section 30.3)
6162  */
6163 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6164                                   gpa_t *vmpointer)
6165 {
6166         gva_t gva;
6167         gpa_t vmptr;
6168         struct x86_exception e;
6169         struct page *page;
6170         struct vcpu_vmx *vmx = to_vmx(vcpu);
6171         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6172
6173         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6174                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6175                 return 1;
6176
6177         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6178                                 sizeof(vmptr), &e)) {
6179                 kvm_inject_page_fault(vcpu, &e);
6180                 return 1;
6181         }
6182
6183         switch (exit_reason) {
6184         case EXIT_REASON_VMON:
6185                 /*
6186                  * SDM 3: 24.11.5
6187                  * The first 4 bytes of VMXON region contain the supported
6188                  * VMCS revision identifier
6189                  *
6190                  * Note - IA32_VMX_BASIC[48] will never be 1
6191                  * for the nested case;
6192                  * which replaces physical address width with 32
6193                  *
6194                  */
6195                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6196                         nested_vmx_failInvalid(vcpu);
6197                         skip_emulated_instruction(vcpu);
6198                         return 1;
6199                 }
6200
6201                 page = nested_get_page(vcpu, vmptr);
6202                 if (page == NULL ||
6203                     *(u32 *)kmap(page) != VMCS12_REVISION) {
6204                         nested_vmx_failInvalid(vcpu);
6205                         kunmap(page);
6206                         skip_emulated_instruction(vcpu);
6207                         return 1;
6208                 }
6209                 kunmap(page);
6210                 vmx->nested.vmxon_ptr = vmptr;
6211                 break;
6212         case EXIT_REASON_VMCLEAR:
6213                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6214                         nested_vmx_failValid(vcpu,
6215                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
6216                         skip_emulated_instruction(vcpu);
6217                         return 1;
6218                 }
6219
6220                 if (vmptr == vmx->nested.vmxon_ptr) {
6221                         nested_vmx_failValid(vcpu,
6222                                              VMXERR_VMCLEAR_VMXON_POINTER);
6223                         skip_emulated_instruction(vcpu);
6224                         return 1;
6225                 }
6226                 break;
6227         case EXIT_REASON_VMPTRLD:
6228                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6229                         nested_vmx_failValid(vcpu,
6230                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
6231                         skip_emulated_instruction(vcpu);
6232                         return 1;
6233                 }
6234
6235                 if (vmptr == vmx->nested.vmxon_ptr) {
6236                         nested_vmx_failValid(vcpu,
6237                                              VMXERR_VMCLEAR_VMXON_POINTER);
6238                         skip_emulated_instruction(vcpu);
6239                         return 1;
6240                 }
6241                 break;
6242         default:
6243                 return 1; /* shouldn't happen */
6244         }
6245
6246         if (vmpointer)
6247                 *vmpointer = vmptr;
6248         return 0;
6249 }
6250
6251 /*
6252  * Emulate the VMXON instruction.
6253  * Currently, we just remember that VMX is active, and do not save or even
6254  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6255  * do not currently need to store anything in that guest-allocated memory
6256  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6257  * argument is different from the VMXON pointer (which the spec says they do).
6258  */
6259 static int handle_vmon(struct kvm_vcpu *vcpu)
6260 {
6261         struct kvm_segment cs;
6262         struct vcpu_vmx *vmx = to_vmx(vcpu);
6263         struct vmcs *shadow_vmcs;
6264         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6265                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6266
6267         /* The Intel VMX Instruction Reference lists a bunch of bits that
6268          * are prerequisite to running VMXON, most notably cr4.VMXE must be
6269          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6270          * Otherwise, we should fail with #UD. We test these now:
6271          */
6272         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6273             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6274             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6275                 kvm_queue_exception(vcpu, UD_VECTOR);
6276                 return 1;
6277         }
6278
6279         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6280         if (is_long_mode(vcpu) && !cs.l) {
6281                 kvm_queue_exception(vcpu, UD_VECTOR);
6282                 return 1;
6283         }
6284
6285         if (vmx_get_cpl(vcpu)) {
6286                 kvm_inject_gp(vcpu, 0);
6287                 return 1;
6288         }
6289
6290         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6291                 return 1;
6292
6293         if (vmx->nested.vmxon) {
6294                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6295                 skip_emulated_instruction(vcpu);
6296                 return 1;
6297         }
6298
6299         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6300                         != VMXON_NEEDED_FEATURES) {
6301                 kvm_inject_gp(vcpu, 0);
6302                 return 1;
6303         }
6304
6305         if (enable_shadow_vmcs) {
6306                 shadow_vmcs = alloc_vmcs();
6307                 if (!shadow_vmcs)
6308                         return -ENOMEM;
6309                 /* mark vmcs as shadow */
6310                 shadow_vmcs->revision_id |= (1u << 31);
6311                 /* init shadow vmcs */
6312                 vmcs_clear(shadow_vmcs);
6313                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6314         }
6315
6316         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6317         vmx->nested.vmcs02_num = 0;
6318
6319         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6320                      HRTIMER_MODE_REL);
6321         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6322
6323         vmx->nested.vmxon = true;
6324
6325         skip_emulated_instruction(vcpu);
6326         nested_vmx_succeed(vcpu);
6327         return 1;
6328 }
6329
6330 /*
6331  * Intel's VMX Instruction Reference specifies a common set of prerequisites
6332  * for running VMX instructions (except VMXON, whose prerequisites are
6333  * slightly different). It also specifies what exception to inject otherwise.
6334  */
6335 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6336 {
6337         struct kvm_segment cs;
6338         struct vcpu_vmx *vmx = to_vmx(vcpu);
6339
6340         if (!vmx->nested.vmxon) {
6341                 kvm_queue_exception(vcpu, UD_VECTOR);
6342                 return 0;
6343         }
6344
6345         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6346         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6347             (is_long_mode(vcpu) && !cs.l)) {
6348                 kvm_queue_exception(vcpu, UD_VECTOR);
6349                 return 0;
6350         }
6351
6352         if (vmx_get_cpl(vcpu)) {
6353                 kvm_inject_gp(vcpu, 0);
6354                 return 0;
6355         }
6356
6357         return 1;
6358 }
6359
6360 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6361 {
6362         u32 exec_control;
6363         if (vmx->nested.current_vmptr == -1ull)
6364                 return;
6365
6366         /* current_vmptr and current_vmcs12 are always set/reset together */
6367         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6368                 return;
6369
6370         if (enable_shadow_vmcs) {
6371                 /* copy to memory all shadowed fields in case
6372                    they were modified */
6373                 copy_shadow_to_vmcs12(vmx);
6374                 vmx->nested.sync_shadow_vmcs = false;
6375                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6376                 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6377                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6378                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6379         }
6380         kunmap(vmx->nested.current_vmcs12_page);
6381         nested_release_page(vmx->nested.current_vmcs12_page);
6382         vmx->nested.current_vmptr = -1ull;
6383         vmx->nested.current_vmcs12 = NULL;
6384 }
6385
6386 /*
6387  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6388  * just stops using VMX.
6389  */
6390 static void free_nested(struct vcpu_vmx *vmx)
6391 {
6392         if (!vmx->nested.vmxon)
6393                 return;
6394
6395         vmx->nested.vmxon = false;
6396         nested_release_vmcs12(vmx);
6397         if (enable_shadow_vmcs)
6398                 free_vmcs(vmx->nested.current_shadow_vmcs);
6399         /* Unpin physical memory we referred to in current vmcs02 */
6400         if (vmx->nested.apic_access_page) {
6401                 nested_release_page(vmx->nested.apic_access_page);
6402                 vmx->nested.apic_access_page = NULL;
6403         }
6404         if (vmx->nested.virtual_apic_page) {
6405                 nested_release_page(vmx->nested.virtual_apic_page);
6406                 vmx->nested.virtual_apic_page = NULL;
6407         }
6408
6409         nested_free_all_saved_vmcss(vmx);
6410 }
6411
6412 /* Emulate the VMXOFF instruction */
6413 static int handle_vmoff(struct kvm_vcpu *vcpu)
6414 {
6415         if (!nested_vmx_check_permission(vcpu))
6416                 return 1;
6417         free_nested(to_vmx(vcpu));
6418         skip_emulated_instruction(vcpu);
6419         nested_vmx_succeed(vcpu);
6420         return 1;
6421 }
6422
6423 /* Emulate the VMCLEAR instruction */
6424 static int handle_vmclear(struct kvm_vcpu *vcpu)
6425 {
6426         struct vcpu_vmx *vmx = to_vmx(vcpu);
6427         gpa_t vmptr;
6428         struct vmcs12 *vmcs12;
6429         struct page *page;
6430
6431         if (!nested_vmx_check_permission(vcpu))
6432                 return 1;
6433
6434         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
6435                 return 1;
6436
6437         if (vmptr == vmx->nested.current_vmptr)
6438                 nested_release_vmcs12(vmx);
6439
6440         page = nested_get_page(vcpu, vmptr);
6441         if (page == NULL) {
6442                 /*
6443                  * For accurate processor emulation, VMCLEAR beyond available
6444                  * physical memory should do nothing at all. However, it is
6445                  * possible that a nested vmx bug, not a guest hypervisor bug,
6446                  * resulted in this case, so let's shut down before doing any
6447                  * more damage:
6448                  */
6449                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6450                 return 1;
6451         }
6452         vmcs12 = kmap(page);
6453         vmcs12->launch_state = 0;
6454         kunmap(page);
6455         nested_release_page(page);
6456
6457         nested_free_vmcs02(vmx, vmptr);
6458
6459         skip_emulated_instruction(vcpu);
6460         nested_vmx_succeed(vcpu);
6461         return 1;
6462 }
6463
6464 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6465
6466 /* Emulate the VMLAUNCH instruction */
6467 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6468 {
6469         return nested_vmx_run(vcpu, true);
6470 }
6471
6472 /* Emulate the VMRESUME instruction */
6473 static int handle_vmresume(struct kvm_vcpu *vcpu)
6474 {
6475
6476         return nested_vmx_run(vcpu, false);
6477 }
6478
6479 enum vmcs_field_type {
6480         VMCS_FIELD_TYPE_U16 = 0,
6481         VMCS_FIELD_TYPE_U64 = 1,
6482         VMCS_FIELD_TYPE_U32 = 2,
6483         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6484 };
6485
6486 static inline int vmcs_field_type(unsigned long field)
6487 {
6488         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
6489                 return VMCS_FIELD_TYPE_U32;
6490         return (field >> 13) & 0x3 ;
6491 }
6492
6493 static inline int vmcs_field_readonly(unsigned long field)
6494 {
6495         return (((field >> 10) & 0x3) == 1);
6496 }
6497
6498 /*
6499  * Read a vmcs12 field. Since these can have varying lengths and we return
6500  * one type, we chose the biggest type (u64) and zero-extend the return value
6501  * to that size. Note that the caller, handle_vmread, might need to use only
6502  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6503  * 64-bit fields are to be returned).
6504  */
6505 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6506                                   unsigned long field, u64 *ret)
6507 {
6508         short offset = vmcs_field_to_offset(field);
6509         char *p;
6510
6511         if (offset < 0)
6512                 return offset;
6513
6514         p = ((char *)(get_vmcs12(vcpu))) + offset;
6515
6516         switch (vmcs_field_type(field)) {
6517         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6518                 *ret = *((natural_width *)p);
6519                 return 0;
6520         case VMCS_FIELD_TYPE_U16:
6521                 *ret = *((u16 *)p);
6522                 return 0;
6523         case VMCS_FIELD_TYPE_U32:
6524                 *ret = *((u32 *)p);
6525                 return 0;
6526         case VMCS_FIELD_TYPE_U64:
6527                 *ret = *((u64 *)p);
6528                 return 0;
6529         default:
6530                 WARN_ON(1);
6531                 return -ENOENT;
6532         }
6533 }
6534
6535
6536 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
6537                                    unsigned long field, u64 field_value){
6538         short offset = vmcs_field_to_offset(field);
6539         char *p = ((char *) get_vmcs12(vcpu)) + offset;
6540         if (offset < 0)
6541                 return offset;
6542
6543         switch (vmcs_field_type(field)) {
6544         case VMCS_FIELD_TYPE_U16:
6545                 *(u16 *)p = field_value;
6546                 return 0;
6547         case VMCS_FIELD_TYPE_U32:
6548                 *(u32 *)p = field_value;
6549                 return 0;
6550         case VMCS_FIELD_TYPE_U64:
6551                 *(u64 *)p = field_value;
6552                 return 0;
6553         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6554                 *(natural_width *)p = field_value;
6555                 return 0;
6556         default:
6557                 WARN_ON(1);
6558                 return -ENOENT;
6559         }
6560
6561 }
6562
6563 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6564 {
6565         int i;
6566         unsigned long field;
6567         u64 field_value;
6568         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6569         const unsigned long *fields = shadow_read_write_fields;
6570         const int num_fields = max_shadow_read_write_fields;
6571
6572         preempt_disable();
6573
6574         vmcs_load(shadow_vmcs);
6575
6576         for (i = 0; i < num_fields; i++) {
6577                 field = fields[i];
6578                 switch (vmcs_field_type(field)) {
6579                 case VMCS_FIELD_TYPE_U16:
6580                         field_value = vmcs_read16(field);
6581                         break;
6582                 case VMCS_FIELD_TYPE_U32:
6583                         field_value = vmcs_read32(field);
6584                         break;
6585                 case VMCS_FIELD_TYPE_U64:
6586                         field_value = vmcs_read64(field);
6587                         break;
6588                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6589                         field_value = vmcs_readl(field);
6590                         break;
6591                 default:
6592                         WARN_ON(1);
6593                         continue;
6594                 }
6595                 vmcs12_write_any(&vmx->vcpu, field, field_value);
6596         }
6597
6598         vmcs_clear(shadow_vmcs);
6599         vmcs_load(vmx->loaded_vmcs->vmcs);
6600
6601         preempt_enable();
6602 }
6603
6604 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6605 {
6606         const unsigned long *fields[] = {
6607                 shadow_read_write_fields,
6608                 shadow_read_only_fields
6609         };
6610         const int max_fields[] = {
6611                 max_shadow_read_write_fields,
6612                 max_shadow_read_only_fields
6613         };
6614         int i, q;
6615         unsigned long field;
6616         u64 field_value = 0;
6617         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6618
6619         vmcs_load(shadow_vmcs);
6620
6621         for (q = 0; q < ARRAY_SIZE(fields); q++) {
6622                 for (i = 0; i < max_fields[q]; i++) {
6623                         field = fields[q][i];
6624                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
6625
6626                         switch (vmcs_field_type(field)) {
6627                         case VMCS_FIELD_TYPE_U16:
6628                                 vmcs_write16(field, (u16)field_value);
6629                                 break;
6630                         case VMCS_FIELD_TYPE_U32:
6631                                 vmcs_write32(field, (u32)field_value);
6632                                 break;
6633                         case VMCS_FIELD_TYPE_U64:
6634                                 vmcs_write64(field, (u64)field_value);
6635                                 break;
6636                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6637                                 vmcs_writel(field, (long)field_value);
6638                                 break;
6639                         default:
6640                                 WARN_ON(1);
6641                                 break;
6642                         }
6643                 }
6644         }
6645
6646         vmcs_clear(shadow_vmcs);
6647         vmcs_load(vmx->loaded_vmcs->vmcs);
6648 }
6649
6650 /*
6651  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6652  * used before) all generate the same failure when it is missing.
6653  */
6654 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6655 {
6656         struct vcpu_vmx *vmx = to_vmx(vcpu);
6657         if (vmx->nested.current_vmptr == -1ull) {
6658                 nested_vmx_failInvalid(vcpu);
6659                 skip_emulated_instruction(vcpu);
6660                 return 0;
6661         }
6662         return 1;
6663 }
6664
6665 static int handle_vmread(struct kvm_vcpu *vcpu)
6666 {
6667         unsigned long field;
6668         u64 field_value;
6669         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6670         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6671         gva_t gva = 0;
6672
6673         if (!nested_vmx_check_permission(vcpu) ||
6674             !nested_vmx_check_vmcs12(vcpu))
6675                 return 1;
6676
6677         /* Decode instruction info and find the field to read */
6678         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6679         /* Read the field, zero-extended to a u64 field_value */
6680         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
6681                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6682                 skip_emulated_instruction(vcpu);
6683                 return 1;
6684         }
6685         /*
6686          * Now copy part of this value to register or memory, as requested.
6687          * Note that the number of bits actually copied is 32 or 64 depending
6688          * on the guest's mode (32 or 64 bit), not on the given field's length.
6689          */
6690         if (vmx_instruction_info & (1u << 10)) {
6691                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6692                         field_value);
6693         } else {
6694                 if (get_vmx_mem_address(vcpu, exit_qualification,
6695                                 vmx_instruction_info, &gva))
6696                         return 1;
6697                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6698                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6699                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6700         }
6701
6702         nested_vmx_succeed(vcpu);
6703         skip_emulated_instruction(vcpu);
6704         return 1;
6705 }
6706
6707
6708 static int handle_vmwrite(struct kvm_vcpu *vcpu)
6709 {
6710         unsigned long field;
6711         gva_t gva;
6712         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6713         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6714         /* The value to write might be 32 or 64 bits, depending on L1's long
6715          * mode, and eventually we need to write that into a field of several
6716          * possible lengths. The code below first zero-extends the value to 64
6717          * bit (field_value), and then copies only the approriate number of
6718          * bits into the vmcs12 field.
6719          */
6720         u64 field_value = 0;
6721         struct x86_exception e;
6722
6723         if (!nested_vmx_check_permission(vcpu) ||
6724             !nested_vmx_check_vmcs12(vcpu))
6725                 return 1;
6726
6727         if (vmx_instruction_info & (1u << 10))
6728                 field_value = kvm_register_readl(vcpu,
6729                         (((vmx_instruction_info) >> 3) & 0xf));
6730         else {
6731                 if (get_vmx_mem_address(vcpu, exit_qualification,
6732                                 vmx_instruction_info, &gva))
6733                         return 1;
6734                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6735                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
6736                         kvm_inject_page_fault(vcpu, &e);
6737                         return 1;
6738                 }
6739         }
6740
6741
6742         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6743         if (vmcs_field_readonly(field)) {
6744                 nested_vmx_failValid(vcpu,
6745                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6746                 skip_emulated_instruction(vcpu);
6747                 return 1;
6748         }
6749
6750         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
6751                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6752                 skip_emulated_instruction(vcpu);
6753                 return 1;
6754         }
6755
6756         nested_vmx_succeed(vcpu);
6757         skip_emulated_instruction(vcpu);
6758         return 1;
6759 }
6760
6761 /* Emulate the VMPTRLD instruction */
6762 static int handle_vmptrld(struct kvm_vcpu *vcpu)
6763 {
6764         struct vcpu_vmx *vmx = to_vmx(vcpu);
6765         gpa_t vmptr;
6766         u32 exec_control;
6767
6768         if (!nested_vmx_check_permission(vcpu))
6769                 return 1;
6770
6771         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
6772                 return 1;
6773
6774         if (vmx->nested.current_vmptr != vmptr) {
6775                 struct vmcs12 *new_vmcs12;
6776                 struct page *page;
6777                 page = nested_get_page(vcpu, vmptr);
6778                 if (page == NULL) {
6779                         nested_vmx_failInvalid(vcpu);
6780                         skip_emulated_instruction(vcpu);
6781                         return 1;
6782                 }
6783                 new_vmcs12 = kmap(page);
6784                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6785                         kunmap(page);
6786                         nested_release_page_clean(page);
6787                         nested_vmx_failValid(vcpu,
6788                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6789                         skip_emulated_instruction(vcpu);
6790                         return 1;
6791                 }
6792
6793                 nested_release_vmcs12(vmx);
6794                 vmx->nested.current_vmptr = vmptr;
6795                 vmx->nested.current_vmcs12 = new_vmcs12;
6796                 vmx->nested.current_vmcs12_page = page;
6797                 if (enable_shadow_vmcs) {
6798                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6799                         exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6800                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6801                         vmcs_write64(VMCS_LINK_POINTER,
6802                                      __pa(vmx->nested.current_shadow_vmcs));
6803                         vmx->nested.sync_shadow_vmcs = true;
6804                 }
6805         }
6806
6807         nested_vmx_succeed(vcpu);
6808         skip_emulated_instruction(vcpu);
6809         return 1;
6810 }
6811
6812 /* Emulate the VMPTRST instruction */
6813 static int handle_vmptrst(struct kvm_vcpu *vcpu)
6814 {
6815         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6816         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6817         gva_t vmcs_gva;
6818         struct x86_exception e;
6819
6820         if (!nested_vmx_check_permission(vcpu))
6821                 return 1;
6822
6823         if (get_vmx_mem_address(vcpu, exit_qualification,
6824                         vmx_instruction_info, &vmcs_gva))
6825                 return 1;
6826         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6827         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6828                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
6829                                  sizeof(u64), &e)) {
6830                 kvm_inject_page_fault(vcpu, &e);
6831                 return 1;
6832         }
6833         nested_vmx_succeed(vcpu);
6834         skip_emulated_instruction(vcpu);
6835         return 1;
6836 }
6837
6838 /* Emulate the INVEPT instruction */
6839 static int handle_invept(struct kvm_vcpu *vcpu)
6840 {
6841         u32 vmx_instruction_info, types;
6842         unsigned long type;
6843         gva_t gva;
6844         struct x86_exception e;
6845         struct {
6846                 u64 eptp, gpa;
6847         } operand;
6848
6849         if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6850             !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6851                 kvm_queue_exception(vcpu, UD_VECTOR);
6852                 return 1;
6853         }
6854
6855         if (!nested_vmx_check_permission(vcpu))
6856                 return 1;
6857
6858         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6859                 kvm_queue_exception(vcpu, UD_VECTOR);
6860                 return 1;
6861         }
6862
6863         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6864         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
6865
6866         types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6867
6868         if (!(types & (1UL << type))) {
6869                 nested_vmx_failValid(vcpu,
6870                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6871                 return 1;
6872         }
6873
6874         /* According to the Intel VMX instruction reference, the memory
6875          * operand is read even if it isn't needed (e.g., for type==global)
6876          */
6877         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6878                         vmx_instruction_info, &gva))
6879                 return 1;
6880         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6881                                 sizeof(operand), &e)) {
6882                 kvm_inject_page_fault(vcpu, &e);
6883                 return 1;
6884         }
6885
6886         switch (type) {
6887         case VMX_EPT_EXTENT_GLOBAL:
6888                 kvm_mmu_sync_roots(vcpu);
6889                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
6890                 nested_vmx_succeed(vcpu);
6891                 break;
6892         default:
6893                 /* Trap single context invalidation invept calls */
6894                 BUG_ON(1);
6895                 break;
6896         }
6897
6898         skip_emulated_instruction(vcpu);
6899         return 1;
6900 }
6901
6902 static int handle_invvpid(struct kvm_vcpu *vcpu)
6903 {
6904         kvm_queue_exception(vcpu, UD_VECTOR);
6905         return 1;
6906 }
6907
6908 /*
6909  * The exit handlers return 1 if the exit was handled fully and guest execution
6910  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
6911  * to be done to userspace and return 0.
6912  */
6913 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6914         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
6915         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
6916         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
6917         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
6918         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
6919         [EXIT_REASON_CR_ACCESS]               = handle_cr,
6920         [EXIT_REASON_DR_ACCESS]               = handle_dr,
6921         [EXIT_REASON_CPUID]                   = handle_cpuid,
6922         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
6923         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
6924         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
6925         [EXIT_REASON_HLT]                     = handle_halt,
6926         [EXIT_REASON_INVD]                    = handle_invd,
6927         [EXIT_REASON_INVLPG]                  = handle_invlpg,
6928         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
6929         [EXIT_REASON_VMCALL]                  = handle_vmcall,
6930         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
6931         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
6932         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
6933         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
6934         [EXIT_REASON_VMREAD]                  = handle_vmread,
6935         [EXIT_REASON_VMRESUME]                = handle_vmresume,
6936         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
6937         [EXIT_REASON_VMOFF]                   = handle_vmoff,
6938         [EXIT_REASON_VMON]                    = handle_vmon,
6939         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
6940         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
6941         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
6942         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
6943         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
6944         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
6945         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
6946         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
6947         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
6948         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
6949         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
6950         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
6951         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
6952         [EXIT_REASON_INVEPT]                  = handle_invept,
6953         [EXIT_REASON_INVVPID]                 = handle_invvpid,
6954 };
6955
6956 static const int kvm_vmx_max_exit_handlers =
6957         ARRAY_SIZE(kvm_vmx_exit_handlers);
6958
6959 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6960                                        struct vmcs12 *vmcs12)
6961 {
6962         unsigned long exit_qualification;
6963         gpa_t bitmap, last_bitmap;
6964         unsigned int port;
6965         int size;
6966         u8 b;
6967
6968         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
6969                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
6970
6971         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6972
6973         port = exit_qualification >> 16;
6974         size = (exit_qualification & 7) + 1;
6975
6976         last_bitmap = (gpa_t)-1;
6977         b = -1;
6978
6979         while (size > 0) {
6980                 if (port < 0x8000)
6981                         bitmap = vmcs12->io_bitmap_a;
6982                 else if (port < 0x10000)
6983                         bitmap = vmcs12->io_bitmap_b;
6984                 else
6985                         return 1;
6986                 bitmap += (port & 0x7fff) / 8;
6987
6988                 if (last_bitmap != bitmap)
6989                         if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6990                                 return 1;
6991                 if (b & (1 << (port & 7)))
6992                         return 1;
6993
6994                 port++;
6995                 size--;
6996                 last_bitmap = bitmap;
6997         }
6998
6999         return 0;
7000 }
7001
7002 /*
7003  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7004  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7005  * disinterest in the current event (read or write a specific MSR) by using an
7006  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7007  */
7008 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7009         struct vmcs12 *vmcs12, u32 exit_reason)
7010 {
7011         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7012         gpa_t bitmap;
7013
7014         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7015                 return 1;
7016
7017         /*
7018          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7019          * for the four combinations of read/write and low/high MSR numbers.
7020          * First we need to figure out which of the four to use:
7021          */
7022         bitmap = vmcs12->msr_bitmap;
7023         if (exit_reason == EXIT_REASON_MSR_WRITE)
7024                 bitmap += 2048;
7025         if (msr_index >= 0xc0000000) {
7026                 msr_index -= 0xc0000000;
7027                 bitmap += 1024;
7028         }
7029
7030         /* Then read the msr_index'th bit from this bitmap: */
7031         if (msr_index < 1024*8) {
7032                 unsigned char b;
7033                 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
7034                         return 1;
7035                 return 1 & (b >> (msr_index & 7));
7036         } else
7037                 return 1; /* let L1 handle the wrong parameter */
7038 }
7039
7040 /*
7041  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7042  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7043  * intercept (via guest_host_mask etc.) the current event.
7044  */
7045 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7046         struct vmcs12 *vmcs12)
7047 {
7048         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7049         int cr = exit_qualification & 15;
7050         int reg = (exit_qualification >> 8) & 15;
7051         unsigned long val = kvm_register_readl(vcpu, reg);
7052
7053         switch ((exit_qualification >> 4) & 3) {
7054         case 0: /* mov to cr */
7055                 switch (cr) {
7056                 case 0:
7057                         if (vmcs12->cr0_guest_host_mask &
7058                             (val ^ vmcs12->cr0_read_shadow))
7059                                 return 1;
7060                         break;
7061                 case 3:
7062                         if ((vmcs12->cr3_target_count >= 1 &&
7063                                         vmcs12->cr3_target_value0 == val) ||
7064                                 (vmcs12->cr3_target_count >= 2 &&
7065                                         vmcs12->cr3_target_value1 == val) ||
7066                                 (vmcs12->cr3_target_count >= 3 &&
7067                                         vmcs12->cr3_target_value2 == val) ||
7068                                 (vmcs12->cr3_target_count >= 4 &&
7069                                         vmcs12->cr3_target_value3 == val))
7070                                 return 0;
7071                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7072                                 return 1;
7073                         break;
7074                 case 4:
7075                         if (vmcs12->cr4_guest_host_mask &
7076                             (vmcs12->cr4_read_shadow ^ val))
7077                                 return 1;
7078                         break;
7079                 case 8:
7080                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7081                                 return 1;
7082                         break;
7083                 }
7084                 break;
7085         case 2: /* clts */
7086                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7087                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7088                         return 1;
7089                 break;
7090         case 1: /* mov from cr */
7091                 switch (cr) {
7092                 case 3:
7093                         if (vmcs12->cpu_based_vm_exec_control &
7094                             CPU_BASED_CR3_STORE_EXITING)
7095                                 return 1;
7096                         break;
7097                 case 8:
7098                         if (vmcs12->cpu_based_vm_exec_control &
7099                             CPU_BASED_CR8_STORE_EXITING)
7100                                 return 1;
7101                         break;
7102                 }
7103                 break;
7104         case 3: /* lmsw */
7105                 /*
7106                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7107                  * cr0. Other attempted changes are ignored, with no exit.
7108                  */
7109                 if (vmcs12->cr0_guest_host_mask & 0xe &
7110                     (val ^ vmcs12->cr0_read_shadow))
7111                         return 1;
7112                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7113                     !(vmcs12->cr0_read_shadow & 0x1) &&
7114                     (val & 0x1))
7115                         return 1;
7116                 break;
7117         }
7118         return 0;
7119 }
7120
7121 /*
7122  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7123  * should handle it ourselves in L0 (and then continue L2). Only call this
7124  * when in is_guest_mode (L2).
7125  */
7126 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7127 {
7128         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7129         struct vcpu_vmx *vmx = to_vmx(vcpu);
7130         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7131         u32 exit_reason = vmx->exit_reason;
7132
7133         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7134                                 vmcs_readl(EXIT_QUALIFICATION),
7135                                 vmx->idt_vectoring_info,
7136                                 intr_info,
7137                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7138                                 KVM_ISA_VMX);
7139
7140         if (vmx->nested.nested_run_pending)
7141                 return 0;
7142
7143         if (unlikely(vmx->fail)) {
7144                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7145                                     vmcs_read32(VM_INSTRUCTION_ERROR));
7146                 return 1;
7147         }
7148
7149         switch (exit_reason) {
7150         case EXIT_REASON_EXCEPTION_NMI:
7151                 if (!is_exception(intr_info))
7152                         return 0;
7153                 else if (is_page_fault(intr_info))
7154                         return enable_ept;
7155                 else if (is_no_device(intr_info) &&
7156                          !(vmcs12->guest_cr0 & X86_CR0_TS))
7157                         return 0;
7158                 return vmcs12->exception_bitmap &
7159                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7160         case EXIT_REASON_EXTERNAL_INTERRUPT:
7161                 return 0;
7162         case EXIT_REASON_TRIPLE_FAULT:
7163                 return 1;
7164         case EXIT_REASON_PENDING_INTERRUPT:
7165                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7166         case EXIT_REASON_NMI_WINDOW:
7167                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7168         case EXIT_REASON_TASK_SWITCH:
7169                 return 1;
7170         case EXIT_REASON_CPUID:
7171                 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7172                         return 0;
7173                 return 1;
7174         case EXIT_REASON_HLT:
7175                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7176         case EXIT_REASON_INVD:
7177                 return 1;
7178         case EXIT_REASON_INVLPG:
7179                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7180         case EXIT_REASON_RDPMC:
7181                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7182         case EXIT_REASON_RDTSC:
7183                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7184         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7185         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7186         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7187         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7188         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
7189         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
7190                 /*
7191                  * VMX instructions trap unconditionally. This allows L1 to
7192                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
7193                  */
7194                 return 1;
7195         case EXIT_REASON_CR_ACCESS:
7196                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7197         case EXIT_REASON_DR_ACCESS:
7198                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7199         case EXIT_REASON_IO_INSTRUCTION:
7200                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
7201         case EXIT_REASON_MSR_READ:
7202         case EXIT_REASON_MSR_WRITE:
7203                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7204         case EXIT_REASON_INVALID_STATE:
7205                 return 1;
7206         case EXIT_REASON_MWAIT_INSTRUCTION:
7207                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7208         case EXIT_REASON_MONITOR_INSTRUCTION:
7209                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7210         case EXIT_REASON_PAUSE_INSTRUCTION:
7211                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7212                         nested_cpu_has2(vmcs12,
7213                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7214         case EXIT_REASON_MCE_DURING_VMENTRY:
7215                 return 0;
7216         case EXIT_REASON_TPR_BELOW_THRESHOLD:
7217                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
7218         case EXIT_REASON_APIC_ACCESS:
7219                 return nested_cpu_has2(vmcs12,
7220                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7221         case EXIT_REASON_EPT_VIOLATION:
7222                 /*
7223                  * L0 always deals with the EPT violation. If nested EPT is
7224                  * used, and the nested mmu code discovers that the address is
7225                  * missing in the guest EPT table (EPT12), the EPT violation
7226                  * will be injected with nested_ept_inject_page_fault()
7227                  */
7228                 return 0;
7229         case EXIT_REASON_EPT_MISCONFIG:
7230                 /*
7231                  * L2 never uses directly L1's EPT, but rather L0's own EPT
7232                  * table (shadow on EPT) or a merged EPT table that L0 built
7233                  * (EPT on EPT). So any problems with the structure of the
7234                  * table is L0's fault.
7235                  */
7236                 return 0;
7237         case EXIT_REASON_WBINVD:
7238                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7239         case EXIT_REASON_XSETBV:
7240                 return 1;
7241         default:
7242                 return 1;
7243         }
7244 }
7245
7246 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7247 {
7248         *info1 = vmcs_readl(EXIT_QUALIFICATION);
7249         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7250 }
7251
7252 /*
7253  * The guest has exited.  See if we can fix it or if we need userspace
7254  * assistance.
7255  */
7256 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
7257 {
7258         struct vcpu_vmx *vmx = to_vmx(vcpu);
7259         u32 exit_reason = vmx->exit_reason;
7260         u32 vectoring_info = vmx->idt_vectoring_info;
7261
7262         /* If guest state is invalid, start emulating */
7263         if (vmx->emulation_required)
7264                 return handle_invalid_guest_state(vcpu);
7265
7266         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
7267                 nested_vmx_vmexit(vcpu, exit_reason,
7268                                   vmcs_read32(VM_EXIT_INTR_INFO),
7269                                   vmcs_readl(EXIT_QUALIFICATION));
7270                 return 1;
7271         }
7272
7273         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
7274                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7275                 vcpu->run->fail_entry.hardware_entry_failure_reason
7276                         = exit_reason;
7277                 return 0;
7278         }
7279
7280         if (unlikely(vmx->fail)) {
7281                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7282                 vcpu->run->fail_entry.hardware_entry_failure_reason
7283                         = vmcs_read32(VM_INSTRUCTION_ERROR);
7284                 return 0;
7285         }
7286
7287         /*
7288          * Note:
7289          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7290          * delivery event since it indicates guest is accessing MMIO.
7291          * The vm-exit can be triggered again after return to guest that
7292          * will cause infinite loop.
7293          */
7294         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
7295                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
7296                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
7297                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
7298                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7299                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7300                 vcpu->run->internal.ndata = 2;
7301                 vcpu->run->internal.data[0] = vectoring_info;
7302                 vcpu->run->internal.data[1] = exit_reason;
7303                 return 0;
7304         }
7305
7306         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7307             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
7308                                         get_vmcs12(vcpu))))) {
7309                 if (vmx_interrupt_allowed(vcpu)) {
7310                         vmx->soft_vnmi_blocked = 0;
7311                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
7312                            vcpu->arch.nmi_pending) {
7313                         /*
7314                          * This CPU don't support us in finding the end of an
7315                          * NMI-blocked window if the guest runs with IRQs
7316                          * disabled. So we pull the trigger after 1 s of
7317                          * futile waiting, but inform the user about this.
7318                          */
7319                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7320                                "state on VCPU %d after 1 s timeout\n",
7321                                __func__, vcpu->vcpu_id);
7322                         vmx->soft_vnmi_blocked = 0;
7323                 }
7324         }
7325
7326         if (exit_reason < kvm_vmx_max_exit_handlers
7327             && kvm_vmx_exit_handlers[exit_reason])
7328                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
7329         else {
7330                 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
7331                 kvm_queue_exception(vcpu, UD_VECTOR);
7332                 return 1;
7333         }
7334 }
7335
7336 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
7337 {
7338         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7339
7340         if (is_guest_mode(vcpu) &&
7341                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
7342                 return;
7343
7344         if (irr == -1 || tpr < irr) {
7345                 vmcs_write32(TPR_THRESHOLD, 0);
7346                 return;
7347         }
7348
7349         vmcs_write32(TPR_THRESHOLD, irr);
7350 }
7351
7352 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7353 {
7354         u32 sec_exec_control;
7355
7356         /*
7357          * There is not point to enable virtualize x2apic without enable
7358          * apicv
7359          */
7360         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7361                                 !vmx_vm_has_apicv(vcpu->kvm))
7362                 return;
7363
7364         if (!vm_need_tpr_shadow(vcpu->kvm))
7365                 return;
7366
7367         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7368
7369         if (set) {
7370                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7371                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7372         } else {
7373                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7374                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7375         }
7376         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7377
7378         vmx_set_msr_bitmap(vcpu);
7379 }
7380
7381 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
7382 {
7383         struct vcpu_vmx *vmx = to_vmx(vcpu);
7384
7385         /*
7386          * Currently we do not handle the nested case where L2 has an
7387          * APIC access page of its own; that page is still pinned.
7388          * Hence, we skip the case where the VCPU is in guest mode _and_
7389          * L1 prepared an APIC access page for L2.
7390          *
7391          * For the case where L1 and L2 share the same APIC access page
7392          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
7393          * in the vmcs12), this function will only update either the vmcs01
7394          * or the vmcs02.  If the former, the vmcs02 will be updated by
7395          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
7396          * the next L2->L1 exit.
7397          */
7398         if (!is_guest_mode(vcpu) ||
7399             !nested_cpu_has2(vmx->nested.current_vmcs12,
7400                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
7401                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
7402 }
7403
7404 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7405 {
7406         u16 status;
7407         u8 old;
7408
7409         if (!vmx_vm_has_apicv(kvm))
7410                 return;
7411
7412         if (isr == -1)
7413                 isr = 0;
7414
7415         status = vmcs_read16(GUEST_INTR_STATUS);
7416         old = status >> 8;
7417         if (isr != old) {
7418                 status &= 0xff;
7419                 status |= isr << 8;
7420                 vmcs_write16(GUEST_INTR_STATUS, status);
7421         }
7422 }
7423
7424 static void vmx_set_rvi(int vector)
7425 {
7426         u16 status;
7427         u8 old;
7428
7429         if (vector == -1)
7430                 vector = 0;
7431
7432         status = vmcs_read16(GUEST_INTR_STATUS);
7433         old = (u8)status & 0xff;
7434         if ((u8)vector != old) {
7435                 status &= ~0xff;
7436                 status |= (u8)vector;
7437                 vmcs_write16(GUEST_INTR_STATUS, status);
7438         }
7439 }
7440
7441 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7442 {
7443         if (!is_guest_mode(vcpu)) {
7444                 vmx_set_rvi(max_irr);
7445                 return;
7446         }
7447
7448         if (max_irr == -1)
7449                 return;
7450
7451         /*
7452          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
7453          * handles it.
7454          */
7455         if (nested_exit_on_intr(vcpu))
7456                 return;
7457
7458         /*
7459          * Else, fall back to pre-APICv interrupt injection since L2
7460          * is run without virtual interrupt delivery.
7461          */
7462         if (!kvm_event_needs_reinjection(vcpu) &&
7463             vmx_interrupt_allowed(vcpu)) {
7464                 kvm_queue_interrupt(vcpu, max_irr, false);
7465                 vmx_inject_irq(vcpu);
7466         }
7467 }
7468
7469 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7470 {
7471         if (!vmx_vm_has_apicv(vcpu->kvm))
7472                 return;
7473
7474         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7475         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7476         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7477         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7478 }
7479
7480 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
7481 {
7482         u32 exit_intr_info;
7483
7484         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7485               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7486                 return;
7487
7488         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7489         exit_intr_info = vmx->exit_intr_info;
7490
7491         /* Handle machine checks before interrupts are enabled */
7492         if (is_machine_check(exit_intr_info))
7493                 kvm_machine_check();
7494
7495         /* We need to handle NMIs before interrupts are enabled */
7496         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
7497             (exit_intr_info & INTR_INFO_VALID_MASK)) {
7498                 kvm_before_handle_nmi(&vmx->vcpu);
7499                 asm("int $2");
7500                 kvm_after_handle_nmi(&vmx->vcpu);
7501         }
7502 }
7503
7504 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7505 {
7506         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7507
7508         /*
7509          * If external interrupt exists, IF bit is set in rflags/eflags on the
7510          * interrupt stack frame, and interrupt will be enabled on a return
7511          * from interrupt handler.
7512          */
7513         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7514                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7515                 unsigned int vector;
7516                 unsigned long entry;
7517                 gate_desc *desc;
7518                 struct vcpu_vmx *vmx = to_vmx(vcpu);
7519 #ifdef CONFIG_X86_64
7520                 unsigned long tmp;
7521 #endif
7522
7523                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
7524                 desc = (gate_desc *)vmx->host_idt_base + vector;
7525                 entry = gate_offset(*desc);
7526                 asm volatile(
7527 #ifdef CONFIG_X86_64
7528                         "mov %%" _ASM_SP ", %[sp]\n\t"
7529                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7530                         "push $%c[ss]\n\t"
7531                         "push %[sp]\n\t"
7532 #endif
7533                         "pushf\n\t"
7534                         "orl $0x200, (%%" _ASM_SP ")\n\t"
7535                         __ASM_SIZE(push) " $%c[cs]\n\t"
7536                         "call *%[entry]\n\t"
7537                         :
7538 #ifdef CONFIG_X86_64
7539                         [sp]"=&r"(tmp)
7540 #endif
7541                         :
7542                         [entry]"r"(entry),
7543                         [ss]"i"(__KERNEL_DS),
7544                         [cs]"i"(__KERNEL_CS)
7545                         );
7546         } else
7547                 local_irq_enable();
7548 }
7549
7550 static bool vmx_mpx_supported(void)
7551 {
7552         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7553                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7554 }
7555
7556 static bool vmx_xsaves_supported(void)
7557 {
7558         return vmcs_config.cpu_based_2nd_exec_ctrl &
7559                 SECONDARY_EXEC_XSAVES;
7560 }
7561
7562 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7563 {
7564         u32 exit_intr_info;
7565         bool unblock_nmi;
7566         u8 vector;
7567         bool idtv_info_valid;
7568
7569         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
7570
7571         if (cpu_has_virtual_nmis()) {
7572                 if (vmx->nmi_known_unmasked)
7573                         return;
7574                 /*
7575                  * Can't use vmx->exit_intr_info since we're not sure what
7576                  * the exit reason is.
7577                  */
7578                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7579                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7580                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7581                 /*
7582                  * SDM 3: 27.7.1.2 (September 2008)
7583                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
7584                  * a guest IRET fault.
7585                  * SDM 3: 23.2.2 (September 2008)
7586                  * Bit 12 is undefined in any of the following cases:
7587                  *  If the VM exit sets the valid bit in the IDT-vectoring
7588                  *   information field.
7589                  *  If the VM exit is due to a double fault.
7590                  */
7591                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7592                     vector != DF_VECTOR && !idtv_info_valid)
7593                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7594                                       GUEST_INTR_STATE_NMI);
7595                 else
7596                         vmx->nmi_known_unmasked =
7597                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7598                                   & GUEST_INTR_STATE_NMI);
7599         } else if (unlikely(vmx->soft_vnmi_blocked))
7600                 vmx->vnmi_blocked_time +=
7601                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
7602 }
7603
7604 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
7605                                       u32 idt_vectoring_info,
7606                                       int instr_len_field,
7607                                       int error_code_field)
7608 {
7609         u8 vector;
7610         int type;
7611         bool idtv_info_valid;
7612
7613         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
7614
7615         vcpu->arch.nmi_injected = false;
7616         kvm_clear_exception_queue(vcpu);
7617         kvm_clear_interrupt_queue(vcpu);
7618
7619         if (!idtv_info_valid)
7620                 return;
7621
7622         kvm_make_request(KVM_REQ_EVENT, vcpu);
7623
7624         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7625         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
7626
7627         switch (type) {
7628         case INTR_TYPE_NMI_INTR:
7629                 vcpu->arch.nmi_injected = true;
7630                 /*
7631                  * SDM 3: 27.7.1.2 (September 2008)
7632                  * Clear bit "block by NMI" before VM entry if a NMI
7633                  * delivery faulted.
7634                  */
7635                 vmx_set_nmi_mask(vcpu, false);
7636                 break;
7637         case INTR_TYPE_SOFT_EXCEPTION:
7638                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
7639                 /* fall through */
7640         case INTR_TYPE_HARD_EXCEPTION:
7641                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
7642                         u32 err = vmcs_read32(error_code_field);
7643                         kvm_requeue_exception_e(vcpu, vector, err);
7644                 } else
7645                         kvm_requeue_exception(vcpu, vector);
7646                 break;
7647         case INTR_TYPE_SOFT_INTR:
7648                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
7649                 /* fall through */
7650         case INTR_TYPE_EXT_INTR:
7651                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
7652                 break;
7653         default:
7654                 break;
7655         }
7656 }
7657
7658 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7659 {
7660         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
7661                                   VM_EXIT_INSTRUCTION_LEN,
7662                                   IDT_VECTORING_ERROR_CODE);
7663 }
7664
7665 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7666 {
7667         __vmx_complete_interrupts(vcpu,
7668                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7669                                   VM_ENTRY_INSTRUCTION_LEN,
7670                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
7671
7672         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7673 }
7674
7675 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7676 {
7677         int i, nr_msrs;
7678         struct perf_guest_switch_msr *msrs;
7679
7680         msrs = perf_guest_get_msrs(&nr_msrs);
7681
7682         if (!msrs)
7683                 return;
7684
7685         for (i = 0; i < nr_msrs; i++)
7686                 if (msrs[i].host == msrs[i].guest)
7687                         clear_atomic_switch_msr(vmx, msrs[i].msr);
7688                 else
7689                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7690                                         msrs[i].host);
7691 }
7692
7693 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
7694 {
7695         struct vcpu_vmx *vmx = to_vmx(vcpu);
7696         unsigned long debugctlmsr, cr4;
7697
7698         /* Record the guest's net vcpu time for enforced NMI injections. */
7699         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7700                 vmx->entry_time = ktime_get();
7701
7702         /* Don't enter VMX if guest state is invalid, let the exit handler
7703            start emulation until we arrive back to a valid state */
7704         if (vmx->emulation_required)
7705                 return;
7706
7707         if (vmx->ple_window_dirty) {
7708                 vmx->ple_window_dirty = false;
7709                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
7710         }
7711
7712         if (vmx->nested.sync_shadow_vmcs) {
7713                 copy_vmcs12_to_shadow(vmx);
7714                 vmx->nested.sync_shadow_vmcs = false;
7715         }
7716
7717         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7718                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7719         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7720                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7721
7722         cr4 = read_cr4();
7723         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
7724                 vmcs_writel(HOST_CR4, cr4);
7725                 vmx->host_state.vmcs_host_cr4 = cr4;
7726         }
7727
7728         /* When single-stepping over STI and MOV SS, we must clear the
7729          * corresponding interruptibility bits in the guest state. Otherwise
7730          * vmentry fails as it then expects bit 14 (BS) in pending debug
7731          * exceptions being set, but that's not correct for the guest debugging
7732          * case. */
7733         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7734                 vmx_set_interrupt_shadow(vcpu, 0);
7735
7736         atomic_switch_perf_msrs(vmx);
7737         debugctlmsr = get_debugctlmsr();
7738
7739         vmx->__launched = vmx->loaded_vmcs->launched;
7740         asm(
7741                 /* Store host registers */
7742                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7743                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7744                 "push %%" _ASM_CX " \n\t"
7745                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7746                 "je 1f \n\t"
7747                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7748                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
7749                 "1: \n\t"
7750                 /* Reload cr2 if changed */
7751                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7752                 "mov %%cr2, %%" _ASM_DX " \n\t"
7753                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
7754                 "je 2f \n\t"
7755                 "mov %%" _ASM_AX", %%cr2 \n\t"
7756                 "2: \n\t"
7757                 /* Check if vmlaunch of vmresume is needed */
7758                 "cmpl $0, %c[launched](%0) \n\t"
7759                 /* Load guest registers.  Don't clobber flags. */
7760                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7761                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7762                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7763                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7764                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7765                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
7766 #ifdef CONFIG_X86_64
7767                 "mov %c[r8](%0),  %%r8  \n\t"
7768                 "mov %c[r9](%0),  %%r9  \n\t"
7769                 "mov %c[r10](%0), %%r10 \n\t"
7770                 "mov %c[r11](%0), %%r11 \n\t"
7771                 "mov %c[r12](%0), %%r12 \n\t"
7772                 "mov %c[r13](%0), %%r13 \n\t"
7773                 "mov %c[r14](%0), %%r14 \n\t"
7774                 "mov %c[r15](%0), %%r15 \n\t"
7775 #endif
7776                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
7777
7778                 /* Enter guest mode */
7779                 "jne 1f \n\t"
7780                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
7781                 "jmp 2f \n\t"
7782                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7783                 "2: "
7784                 /* Save guest registers, load host registers, keep flags */
7785                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
7786                 "pop %0 \n\t"
7787                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7788                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7789                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7790                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7791                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7792                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7793                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
7794 #ifdef CONFIG_X86_64
7795                 "mov %%r8,  %c[r8](%0) \n\t"
7796                 "mov %%r9,  %c[r9](%0) \n\t"
7797                 "mov %%r10, %c[r10](%0) \n\t"
7798                 "mov %%r11, %c[r11](%0) \n\t"
7799                 "mov %%r12, %c[r12](%0) \n\t"
7800                 "mov %%r13, %c[r13](%0) \n\t"
7801                 "mov %%r14, %c[r14](%0) \n\t"
7802                 "mov %%r15, %c[r15](%0) \n\t"
7803 #endif
7804                 "mov %%cr2, %%" _ASM_AX "   \n\t"
7805                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
7806
7807                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
7808                 "setbe %c[fail](%0) \n\t"
7809                 ".pushsection .rodata \n\t"
7810                 ".global vmx_return \n\t"
7811                 "vmx_return: " _ASM_PTR " 2b \n\t"
7812                 ".popsection"
7813               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
7814                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
7815                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
7816                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
7817                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7818                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7819                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7820                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7821                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7822                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7823                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
7824 #ifdef CONFIG_X86_64
7825                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7826                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7827                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7828                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7829                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7830                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7831                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7832                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
7833 #endif
7834                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7835                 [wordsize]"i"(sizeof(ulong))
7836               : "cc", "memory"
7837 #ifdef CONFIG_X86_64
7838                 , "rax", "rbx", "rdi", "rsi"
7839                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
7840 #else
7841                 , "eax", "ebx", "edi", "esi"
7842 #endif
7843               );
7844
7845         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7846         if (debugctlmsr)
7847                 update_debugctlmsr(debugctlmsr);
7848
7849 #ifndef CONFIG_X86_64
7850         /*
7851          * The sysexit path does not restore ds/es, so we must set them to
7852          * a reasonable value ourselves.
7853          *
7854          * We can't defer this to vmx_load_host_state() since that function
7855          * may be executed in interrupt context, which saves and restore segments
7856          * around it, nullifying its effect.
7857          */
7858         loadsegment(ds, __USER_DS);
7859         loadsegment(es, __USER_DS);
7860 #endif
7861
7862         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
7863                                   | (1 << VCPU_EXREG_RFLAGS)
7864                                   | (1 << VCPU_EXREG_PDPTR)
7865                                   | (1 << VCPU_EXREG_SEGMENTS)
7866                                   | (1 << VCPU_EXREG_CR3));
7867         vcpu->arch.regs_dirty = 0;
7868
7869         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7870
7871         vmx->loaded_vmcs->launched = 1;
7872
7873         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
7874         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
7875
7876         /*
7877          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7878          * we did not inject a still-pending event to L1 now because of
7879          * nested_run_pending, we need to re-enable this bit.
7880          */
7881         if (vmx->nested.nested_run_pending)
7882                 kvm_make_request(KVM_REQ_EVENT, vcpu);
7883
7884         vmx->nested.nested_run_pending = 0;
7885
7886         vmx_complete_atomic_exit(vmx);
7887         vmx_recover_nmi_blocking(vmx);
7888         vmx_complete_interrupts(vmx);
7889 }
7890
7891 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
7892 {
7893         struct vcpu_vmx *vmx = to_vmx(vcpu);
7894         int cpu;
7895
7896         if (vmx->loaded_vmcs == &vmx->vmcs01)
7897                 return;
7898
7899         cpu = get_cpu();
7900         vmx->loaded_vmcs = &vmx->vmcs01;
7901         vmx_vcpu_put(vcpu);
7902         vmx_vcpu_load(vcpu, cpu);
7903         vcpu->cpu = cpu;
7904         put_cpu();
7905 }
7906
7907 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7908 {
7909         struct vcpu_vmx *vmx = to_vmx(vcpu);
7910
7911         free_vpid(vmx);
7912         leave_guest_mode(vcpu);
7913         vmx_load_vmcs01(vcpu);
7914         free_nested(vmx);
7915         free_loaded_vmcs(vmx->loaded_vmcs);
7916         kfree(vmx->guest_msrs);
7917         kvm_vcpu_uninit(vcpu);
7918         kmem_cache_free(kvm_vcpu_cache, vmx);
7919 }
7920
7921 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
7922 {
7923         int err;
7924         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
7925         int cpu;
7926
7927         if (!vmx)
7928                 return ERR_PTR(-ENOMEM);
7929
7930         allocate_vpid(vmx);
7931
7932         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7933         if (err)
7934                 goto free_vcpu;
7935
7936         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
7937         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
7938                      > PAGE_SIZE);
7939
7940         err = -ENOMEM;
7941         if (!vmx->guest_msrs) {
7942                 goto uninit_vcpu;
7943         }
7944
7945         vmx->loaded_vmcs = &vmx->vmcs01;
7946         vmx->loaded_vmcs->vmcs = alloc_vmcs();
7947         if (!vmx->loaded_vmcs->vmcs)
7948                 goto free_msrs;
7949         if (!vmm_exclusive)
7950                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7951         loaded_vmcs_init(vmx->loaded_vmcs);
7952         if (!vmm_exclusive)
7953                 kvm_cpu_vmxoff();
7954
7955         cpu = get_cpu();
7956         vmx_vcpu_load(&vmx->vcpu, cpu);
7957         vmx->vcpu.cpu = cpu;
7958         err = vmx_vcpu_setup(vmx);
7959         vmx_vcpu_put(&vmx->vcpu);
7960         put_cpu();
7961         if (err)
7962                 goto free_vmcs;
7963         if (vm_need_virtualize_apic_accesses(kvm)) {
7964                 err = alloc_apic_access_page(kvm);
7965                 if (err)
7966                         goto free_vmcs;
7967         }
7968
7969         if (enable_ept) {
7970                 if (!kvm->arch.ept_identity_map_addr)
7971                         kvm->arch.ept_identity_map_addr =
7972                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
7973                 err = init_rmode_identity_map(kvm);
7974                 if (err)
7975                         goto free_vmcs;
7976         }
7977
7978         vmx->nested.current_vmptr = -1ull;
7979         vmx->nested.current_vmcs12 = NULL;
7980
7981         return &vmx->vcpu;
7982
7983 free_vmcs:
7984         free_loaded_vmcs(vmx->loaded_vmcs);
7985 free_msrs:
7986         kfree(vmx->guest_msrs);
7987 uninit_vcpu:
7988         kvm_vcpu_uninit(&vmx->vcpu);
7989 free_vcpu:
7990         free_vpid(vmx);
7991         kmem_cache_free(kvm_vcpu_cache, vmx);
7992         return ERR_PTR(err);
7993 }
7994
7995 static void __init vmx_check_processor_compat(void *rtn)
7996 {
7997         struct vmcs_config vmcs_conf;
7998
7999         *(int *)rtn = 0;
8000         if (setup_vmcs_config(&vmcs_conf) < 0)
8001                 *(int *)rtn = -EIO;
8002         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8003                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8004                                 smp_processor_id());
8005                 *(int *)rtn = -EIO;
8006         }
8007 }
8008
8009 static int get_ept_level(void)
8010 {
8011         return VMX_EPT_DEFAULT_GAW + 1;
8012 }
8013
8014 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
8015 {
8016         u64 ret;
8017
8018         /* For VT-d and EPT combination
8019          * 1. MMIO: always map as UC
8020          * 2. EPT with VT-d:
8021          *   a. VT-d without snooping control feature: can't guarantee the
8022          *      result, try to trust guest.
8023          *   b. VT-d with snooping control feature: snooping control feature of
8024          *      VT-d engine can guarantee the cache correctness. Just set it
8025          *      to WB to keep consistent with host. So the same as item 3.
8026          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8027          *    consistent with host MTRR
8028          */
8029         if (is_mmio)
8030                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
8031         else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
8032                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
8033                       VMX_EPT_MT_EPTE_SHIFT;
8034         else
8035                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
8036                         | VMX_EPT_IPAT_BIT;
8037
8038         return ret;
8039 }
8040
8041 static int vmx_get_lpage_level(void)
8042 {
8043         if (enable_ept && !cpu_has_vmx_ept_1g_page())
8044                 return PT_DIRECTORY_LEVEL;
8045         else
8046                 /* For shadow and EPT supported 1GB page */
8047                 return PT_PDPE_LEVEL;
8048 }
8049
8050 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8051 {
8052         struct kvm_cpuid_entry2 *best;
8053         struct vcpu_vmx *vmx = to_vmx(vcpu);
8054         u32 exec_control;
8055
8056         vmx->rdtscp_enabled = false;
8057         if (vmx_rdtscp_supported()) {
8058                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8059                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
8060                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
8061                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
8062                                 vmx->rdtscp_enabled = true;
8063                         else {
8064                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
8065                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8066                                                 exec_control);
8067                         }
8068                 }
8069         }
8070
8071         /* Exposing INVPCID only when PCID is exposed */
8072         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8073         if (vmx_invpcid_supported() &&
8074             best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
8075             guest_cpuid_has_pcid(vcpu)) {
8076                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8077                 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
8078                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8079                              exec_control);
8080         } else {
8081                 if (cpu_has_secondary_exec_ctrls()) {
8082                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8083                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8084                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8085                                      exec_control);
8086                 }
8087                 if (best)
8088                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
8089         }
8090 }
8091
8092 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8093 {
8094         if (func == 1 && nested)
8095                 entry->ecx |= bit(X86_FEATURE_VMX);
8096 }
8097
8098 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8099                 struct x86_exception *fault)
8100 {
8101         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8102         u32 exit_reason;
8103
8104         if (fault->error_code & PFERR_RSVD_MASK)
8105                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
8106         else
8107                 exit_reason = EXIT_REASON_EPT_VIOLATION;
8108         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
8109         vmcs12->guest_physical_address = fault->address;
8110 }
8111
8112 /* Callbacks for nested_ept_init_mmu_context: */
8113
8114 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
8115 {
8116         /* return the page table to be shadowed - in our case, EPT12 */
8117         return get_vmcs12(vcpu)->ept_pointer;
8118 }
8119
8120 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
8121 {
8122         kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
8123                         nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
8124
8125         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
8126         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
8127         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
8128
8129         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
8130 }
8131
8132 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
8133 {
8134         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
8135 }
8136
8137 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
8138                 struct x86_exception *fault)
8139 {
8140         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8141
8142         WARN_ON(!is_guest_mode(vcpu));
8143
8144         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
8145         if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
8146                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
8147                                   vmcs_read32(VM_EXIT_INTR_INFO),
8148                                   vmcs_readl(EXIT_QUALIFICATION));
8149         else
8150                 kvm_inject_page_fault(vcpu, fault);
8151 }
8152
8153 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
8154                                         struct vmcs12 *vmcs12)
8155 {
8156         struct vcpu_vmx *vmx = to_vmx(vcpu);
8157
8158         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
8159                 /* TODO: Also verify bits beyond physical address width are 0 */
8160                 if (!PAGE_ALIGNED(vmcs12->apic_access_addr))
8161                         return false;
8162
8163                 /*
8164                  * Translate L1 physical address to host physical
8165                  * address for vmcs02. Keep the page pinned, so this
8166                  * physical address remains valid. We keep a reference
8167                  * to it so we can release it later.
8168                  */
8169                 if (vmx->nested.apic_access_page) /* shouldn't happen */
8170                         nested_release_page(vmx->nested.apic_access_page);
8171                 vmx->nested.apic_access_page =
8172                         nested_get_page(vcpu, vmcs12->apic_access_addr);
8173         }
8174
8175         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
8176                 /* TODO: Also verify bits beyond physical address width are 0 */
8177                 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr))
8178                         return false;
8179
8180                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
8181                         nested_release_page(vmx->nested.virtual_apic_page);
8182                 vmx->nested.virtual_apic_page =
8183                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
8184
8185                 /*
8186                  * Failing the vm entry is _not_ what the processor does
8187                  * but it's basically the only possibility we have.
8188                  * We could still enter the guest if CR8 load exits are
8189                  * enabled, CR8 store exits are enabled, and virtualize APIC
8190                  * access is disabled; in this case the processor would never
8191                  * use the TPR shadow and we could simply clear the bit from
8192                  * the execution control.  But such a configuration is useless,
8193                  * so let's keep the code simple.
8194                  */
8195                 if (!vmx->nested.virtual_apic_page)
8196                         return false;
8197         }
8198
8199         return true;
8200 }
8201
8202 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
8203 {
8204         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
8205         struct vcpu_vmx *vmx = to_vmx(vcpu);
8206
8207         if (vcpu->arch.virtual_tsc_khz == 0)
8208                 return;
8209
8210         /* Make sure short timeouts reliably trigger an immediate vmexit.
8211          * hrtimer_start does not guarantee this. */
8212         if (preemption_timeout <= 1) {
8213                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
8214                 return;
8215         }
8216
8217         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8218         preemption_timeout *= 1000000;
8219         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
8220         hrtimer_start(&vmx->nested.preemption_timer,
8221                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
8222 }
8223
8224 /*
8225  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
8226  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
8227  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
8228  * guest in a way that will both be appropriate to L1's requests, and our
8229  * needs. In addition to modifying the active vmcs (which is vmcs02), this
8230  * function also has additional necessary side-effects, like setting various
8231  * vcpu->arch fields.
8232  */
8233 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8234 {
8235         struct vcpu_vmx *vmx = to_vmx(vcpu);
8236         u32 exec_control;
8237
8238         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
8239         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
8240         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
8241         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
8242         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
8243         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
8244         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
8245         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
8246         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
8247         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
8248         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
8249         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
8250         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
8251         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
8252         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
8253         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
8254         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
8255         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
8256         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
8257         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
8258         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
8259         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
8260         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
8261         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
8262         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
8263         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
8264         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
8265         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
8266         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
8267         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
8268         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
8269         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
8270         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
8271         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
8272         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
8273         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
8274
8275         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
8276                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
8277                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
8278         } else {
8279                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
8280                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
8281         }
8282         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
8283                 vmcs12->vm_entry_intr_info_field);
8284         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
8285                 vmcs12->vm_entry_exception_error_code);
8286         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
8287                 vmcs12->vm_entry_instruction_len);
8288         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
8289                 vmcs12->guest_interruptibility_info);
8290         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
8291         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
8292         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
8293                 vmcs12->guest_pending_dbg_exceptions);
8294         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
8295         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
8296
8297         vmcs_write64(VMCS_LINK_POINTER, -1ull);
8298
8299         exec_control = vmcs12->pin_based_vm_exec_control;
8300         exec_control |= vmcs_config.pin_based_exec_ctrl;
8301         exec_control &= ~(PIN_BASED_VMX_PREEMPTION_TIMER |
8302                           PIN_BASED_POSTED_INTR);
8303         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
8304
8305         vmx->nested.preemption_timer_expired = false;
8306         if (nested_cpu_has_preemption_timer(vmcs12))
8307                 vmx_start_preemption_timer(vcpu);
8308
8309         /*
8310          * Whether page-faults are trapped is determined by a combination of
8311          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
8312          * If enable_ept, L0 doesn't care about page faults and we should
8313          * set all of these to L1's desires. However, if !enable_ept, L0 does
8314          * care about (at least some) page faults, and because it is not easy
8315          * (if at all possible?) to merge L0 and L1's desires, we simply ask
8316          * to exit on each and every L2 page fault. This is done by setting
8317          * MASK=MATCH=0 and (see below) EB.PF=1.
8318          * Note that below we don't need special code to set EB.PF beyond the
8319          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
8320          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
8321          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
8322          *
8323          * A problem with this approach (when !enable_ept) is that L1 may be
8324          * injected with more page faults than it asked for. This could have
8325          * caused problems, but in practice existing hypervisors don't care.
8326          * To fix this, we will need to emulate the PFEC checking (on the L1
8327          * page tables), using walk_addr(), when injecting PFs to L1.
8328          */
8329         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
8330                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
8331         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
8332                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
8333
8334         if (cpu_has_secondary_exec_ctrls()) {
8335                 exec_control = vmx_secondary_exec_control(vmx);
8336                 if (!vmx->rdtscp_enabled)
8337                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
8338                 /* Take the following fields only from vmcs12 */
8339                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8340                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
8341                                   SECONDARY_EXEC_APIC_REGISTER_VIRT);
8342                 if (nested_cpu_has(vmcs12,
8343                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
8344                         exec_control |= vmcs12->secondary_vm_exec_control;
8345
8346                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
8347                         /*
8348                          * If translation failed, no matter: This feature asks
8349                          * to exit when accessing the given address, and if it
8350                          * can never be accessed, this feature won't do
8351                          * anything anyway.
8352                          */
8353                         if (!vmx->nested.apic_access_page)
8354                                 exec_control &=
8355                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8356                         else
8357                                 vmcs_write64(APIC_ACCESS_ADDR,
8358                                   page_to_phys(vmx->nested.apic_access_page));
8359                 } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) {
8360                         exec_control |=
8361                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8362                         kvm_vcpu_reload_apic_access_page(vcpu);
8363                 }
8364
8365                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
8366         }
8367
8368
8369         /*
8370          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
8371          * Some constant fields are set here by vmx_set_constant_host_state().
8372          * Other fields are different per CPU, and will be set later when
8373          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
8374          */
8375         vmx_set_constant_host_state(vmx);
8376
8377         /*
8378          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
8379          * entry, but only if the current (host) sp changed from the value
8380          * we wrote last (vmx->host_rsp). This cache is no longer relevant
8381          * if we switch vmcs, and rather than hold a separate cache per vmcs,
8382          * here we just force the write to happen on entry.
8383          */
8384         vmx->host_rsp = 0;
8385
8386         exec_control = vmx_exec_control(vmx); /* L0's desires */
8387         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
8388         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
8389         exec_control &= ~CPU_BASED_TPR_SHADOW;
8390         exec_control |= vmcs12->cpu_based_vm_exec_control;
8391
8392         if (exec_control & CPU_BASED_TPR_SHADOW) {
8393                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
8394                                 page_to_phys(vmx->nested.virtual_apic_page));
8395                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
8396         }
8397
8398         /*
8399          * Merging of IO and MSR bitmaps not currently supported.
8400          * Rather, exit every time.
8401          */
8402         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
8403         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
8404         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
8405
8406         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
8407
8408         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
8409          * bitwise-or of what L1 wants to trap for L2, and what we want to
8410          * trap. Note that CR0.TS also needs updating - we do this later.
8411          */
8412         update_exception_bitmap(vcpu);
8413         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
8414         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8415
8416         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
8417          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
8418          * bits are further modified by vmx_set_efer() below.
8419          */
8420         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8421
8422         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
8423          * emulated by vmx_set_efer(), below.
8424          */
8425         vm_entry_controls_init(vmx,
8426                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
8427                         ~VM_ENTRY_IA32E_MODE) |
8428                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
8429
8430         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
8431                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
8432                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
8433         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
8434                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
8435
8436
8437         set_cr4_guest_host_mask(vmx);
8438
8439         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
8440                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
8441
8442         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
8443                 vmcs_write64(TSC_OFFSET,
8444                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
8445         else
8446                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8447
8448         if (enable_vpid) {
8449                 /*
8450                  * Trivially support vpid by letting L2s share their parent
8451                  * L1's vpid. TODO: move to a more elaborate solution, giving
8452                  * each L2 its own vpid and exposing the vpid feature to L1.
8453                  */
8454                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
8455                 vmx_flush_tlb(vcpu);
8456         }
8457
8458         if (nested_cpu_has_ept(vmcs12)) {
8459                 kvm_mmu_unload(vcpu);
8460                 nested_ept_init_mmu_context(vcpu);
8461         }
8462
8463         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
8464                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
8465         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
8466                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8467         else
8468                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8469         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
8470         vmx_set_efer(vcpu, vcpu->arch.efer);
8471
8472         /*
8473          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
8474          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
8475          * The CR0_READ_SHADOW is what L2 should have expected to read given
8476          * the specifications by L1; It's not enough to take
8477          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
8478          * have more bits than L1 expected.
8479          */
8480         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
8481         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
8482
8483         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
8484         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
8485
8486         /* shadow page tables on either EPT or shadow page tables */
8487         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
8488         kvm_mmu_reset_context(vcpu);
8489
8490         if (!enable_ept)
8491                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
8492
8493         /*
8494          * L1 may access the L2's PDPTR, so save them to construct vmcs12
8495          */
8496         if (enable_ept) {
8497                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
8498                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
8499                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
8500                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
8501         }
8502
8503         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
8504         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
8505 }
8506
8507 /*
8508  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
8509  * for running an L2 nested guest.
8510  */
8511 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
8512 {
8513         struct vmcs12 *vmcs12;
8514         struct vcpu_vmx *vmx = to_vmx(vcpu);
8515         int cpu;
8516         struct loaded_vmcs *vmcs02;
8517         bool ia32e;
8518
8519         if (!nested_vmx_check_permission(vcpu) ||
8520             !nested_vmx_check_vmcs12(vcpu))
8521                 return 1;
8522
8523         skip_emulated_instruction(vcpu);
8524         vmcs12 = get_vmcs12(vcpu);
8525
8526         if (enable_shadow_vmcs)
8527                 copy_shadow_to_vmcs12(vmx);
8528
8529         /*
8530          * The nested entry process starts with enforcing various prerequisites
8531          * on vmcs12 as required by the Intel SDM, and act appropriately when
8532          * they fail: As the SDM explains, some conditions should cause the
8533          * instruction to fail, while others will cause the instruction to seem
8534          * to succeed, but return an EXIT_REASON_INVALID_STATE.
8535          * To speed up the normal (success) code path, we should avoid checking
8536          * for misconfigurations which will anyway be caught by the processor
8537          * when using the merged vmcs02.
8538          */
8539         if (vmcs12->launch_state == launch) {
8540                 nested_vmx_failValid(vcpu,
8541                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
8542                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
8543                 return 1;
8544         }
8545
8546         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
8547             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
8548                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8549                 return 1;
8550         }
8551
8552         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
8553                         !PAGE_ALIGNED(vmcs12->msr_bitmap)) {
8554                 /*TODO: Also verify bits beyond physical address width are 0*/
8555                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8556                 return 1;
8557         }
8558
8559         if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
8560                 /*TODO: Also verify bits beyond physical address width are 0*/
8561                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8562                 return 1;
8563         }
8564
8565         if (vmcs12->vm_entry_msr_load_count > 0 ||
8566             vmcs12->vm_exit_msr_load_count > 0 ||
8567             vmcs12->vm_exit_msr_store_count > 0) {
8568                 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
8569                                     __func__);
8570                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8571                 return 1;
8572         }
8573
8574         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
8575                                 nested_vmx_true_procbased_ctls_low,
8576                                 nested_vmx_procbased_ctls_high) ||
8577             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
8578               nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
8579             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
8580               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
8581             !vmx_control_verify(vmcs12->vm_exit_controls,
8582                                 nested_vmx_true_exit_ctls_low,
8583                                 nested_vmx_exit_ctls_high) ||
8584             !vmx_control_verify(vmcs12->vm_entry_controls,
8585                                 nested_vmx_true_entry_ctls_low,
8586                                 nested_vmx_entry_ctls_high))
8587         {
8588                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8589                 return 1;
8590         }
8591
8592         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
8593             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8594                 nested_vmx_failValid(vcpu,
8595                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
8596                 return 1;
8597         }
8598
8599         if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
8600             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8601                 nested_vmx_entry_failure(vcpu, vmcs12,
8602                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8603                 return 1;
8604         }
8605         if (vmcs12->vmcs_link_pointer != -1ull) {
8606                 nested_vmx_entry_failure(vcpu, vmcs12,
8607                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
8608                 return 1;
8609         }
8610
8611         /*
8612          * If the load IA32_EFER VM-entry control is 1, the following checks
8613          * are performed on the field for the IA32_EFER MSR:
8614          * - Bits reserved in the IA32_EFER MSR must be 0.
8615          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8616          *   the IA-32e mode guest VM-exit control. It must also be identical
8617          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8618          *   CR0.PG) is 1.
8619          */
8620         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
8621                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
8622                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
8623                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
8624                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
8625                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
8626                         nested_vmx_entry_failure(vcpu, vmcs12,
8627                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8628                         return 1;
8629                 }
8630         }
8631
8632         /*
8633          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8634          * IA32_EFER MSR must be 0 in the field for that register. In addition,
8635          * the values of the LMA and LME bits in the field must each be that of
8636          * the host address-space size VM-exit control.
8637          */
8638         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
8639                 ia32e = (vmcs12->vm_exit_controls &
8640                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
8641                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
8642                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
8643                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
8644                         nested_vmx_entry_failure(vcpu, vmcs12,
8645                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8646                         return 1;
8647                 }
8648         }
8649
8650         /*
8651          * We're finally done with prerequisite checking, and can start with
8652          * the nested entry.
8653          */
8654
8655         vmcs02 = nested_get_current_vmcs02(vmx);
8656         if (!vmcs02)
8657                 return -ENOMEM;
8658
8659         enter_guest_mode(vcpu);
8660
8661         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
8662
8663         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
8664                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8665
8666         cpu = get_cpu();
8667         vmx->loaded_vmcs = vmcs02;
8668         vmx_vcpu_put(vcpu);
8669         vmx_vcpu_load(vcpu, cpu);
8670         vcpu->cpu = cpu;
8671         put_cpu();
8672
8673         vmx_segment_cache_clear(vmx);
8674
8675         vmcs12->launch_state = 1;
8676
8677         prepare_vmcs02(vcpu, vmcs12);
8678
8679         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
8680                 return kvm_emulate_halt(vcpu);
8681
8682         vmx->nested.nested_run_pending = 1;
8683
8684         /*
8685          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8686          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8687          * returned as far as L1 is concerned. It will only return (and set
8688          * the success flag) when L2 exits (see nested_vmx_vmexit()).
8689          */
8690         return 1;
8691 }
8692
8693 /*
8694  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8695  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8696  * This function returns the new value we should put in vmcs12.guest_cr0.
8697  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8698  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8699  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8700  *     didn't trap the bit, because if L1 did, so would L0).
8701  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8702  *     been modified by L2, and L1 knows it. So just leave the old value of
8703  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8704  *     isn't relevant, because if L0 traps this bit it can set it to anything.
8705  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8706  *     changed these bits, and therefore they need to be updated, but L0
8707  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8708  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8709  */
8710 static inline unsigned long
8711 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8712 {
8713         return
8714         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8715         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8716         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8717                         vcpu->arch.cr0_guest_owned_bits));
8718 }
8719
8720 static inline unsigned long
8721 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8722 {
8723         return
8724         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8725         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8726         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8727                         vcpu->arch.cr4_guest_owned_bits));
8728 }
8729
8730 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8731                                        struct vmcs12 *vmcs12)
8732 {
8733         u32 idt_vectoring;
8734         unsigned int nr;
8735
8736         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
8737                 nr = vcpu->arch.exception.nr;
8738                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8739
8740                 if (kvm_exception_is_soft(nr)) {
8741                         vmcs12->vm_exit_instruction_len =
8742                                 vcpu->arch.event_exit_inst_len;
8743                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8744                 } else
8745                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8746
8747                 if (vcpu->arch.exception.has_error_code) {
8748                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8749                         vmcs12->idt_vectoring_error_code =
8750                                 vcpu->arch.exception.error_code;
8751                 }
8752
8753                 vmcs12->idt_vectoring_info_field = idt_vectoring;
8754         } else if (vcpu->arch.nmi_injected) {
8755                 vmcs12->idt_vectoring_info_field =
8756                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8757         } else if (vcpu->arch.interrupt.pending) {
8758                 nr = vcpu->arch.interrupt.nr;
8759                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8760
8761                 if (vcpu->arch.interrupt.soft) {
8762                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
8763                         vmcs12->vm_entry_instruction_len =
8764                                 vcpu->arch.event_exit_inst_len;
8765                 } else
8766                         idt_vectoring |= INTR_TYPE_EXT_INTR;
8767
8768                 vmcs12->idt_vectoring_info_field = idt_vectoring;
8769         }
8770 }
8771
8772 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
8773 {
8774         struct vcpu_vmx *vmx = to_vmx(vcpu);
8775
8776         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
8777             vmx->nested.preemption_timer_expired) {
8778                 if (vmx->nested.nested_run_pending)
8779                         return -EBUSY;
8780                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
8781                 return 0;
8782         }
8783
8784         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
8785                 if (vmx->nested.nested_run_pending ||
8786                     vcpu->arch.interrupt.pending)
8787                         return -EBUSY;
8788                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
8789                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
8790                                   INTR_INFO_VALID_MASK, 0);
8791                 /*
8792                  * The NMI-triggered VM exit counts as injection:
8793                  * clear this one and block further NMIs.
8794                  */
8795                 vcpu->arch.nmi_pending = 0;
8796                 vmx_set_nmi_mask(vcpu, true);
8797                 return 0;
8798         }
8799
8800         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
8801             nested_exit_on_intr(vcpu)) {
8802                 if (vmx->nested.nested_run_pending)
8803                         return -EBUSY;
8804                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
8805         }
8806
8807         return 0;
8808 }
8809
8810 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
8811 {
8812         ktime_t remaining =
8813                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
8814         u64 value;
8815
8816         if (ktime_to_ns(remaining) <= 0)
8817                 return 0;
8818
8819         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
8820         do_div(value, 1000000);
8821         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8822 }
8823
8824 /*
8825  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8826  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8827  * and this function updates it to reflect the changes to the guest state while
8828  * L2 was running (and perhaps made some exits which were handled directly by L0
8829  * without going back to L1), and to reflect the exit reason.
8830  * Note that we do not have to copy here all VMCS fields, just those that
8831  * could have changed by the L2 guest or the exit - i.e., the guest-state and
8832  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8833  * which already writes to vmcs12 directly.
8834  */
8835 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
8836                            u32 exit_reason, u32 exit_intr_info,
8837                            unsigned long exit_qualification)
8838 {
8839         /* update guest state fields: */
8840         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8841         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8842
8843         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8844         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8845         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8846
8847         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8848         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8849         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8850         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8851         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8852         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8853         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8854         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8855         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8856         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8857         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8858         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8859         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8860         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8861         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8862         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8863         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8864         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8865         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8866         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8867         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8868         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8869         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8870         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8871         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8872         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8873         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8874         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8875         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8876         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8877         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8878         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8879         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8880         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8881         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8882         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8883
8884         vmcs12->guest_interruptibility_info =
8885                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8886         vmcs12->guest_pending_dbg_exceptions =
8887                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
8888         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
8889                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
8890         else
8891                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
8892
8893         if (nested_cpu_has_preemption_timer(vmcs12)) {
8894                 if (vmcs12->vm_exit_controls &
8895                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
8896                         vmcs12->vmx_preemption_timer_value =
8897                                 vmx_get_preemption_timer_value(vcpu);
8898                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
8899         }
8900
8901         /*
8902          * In some cases (usually, nested EPT), L2 is allowed to change its
8903          * own CR3 without exiting. If it has changed it, we must keep it.
8904          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8905          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8906          *
8907          * Additionally, restore L2's PDPTR to vmcs12.
8908          */
8909         if (enable_ept) {
8910                 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8911                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8912                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8913                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8914                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8915         }
8916
8917         vmcs12->vm_entry_controls =
8918                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
8919                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
8920
8921         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
8922                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8923                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8924         }
8925
8926         /* TODO: These cannot have changed unless we have MSR bitmaps and
8927          * the relevant bit asks not to trap the change */
8928         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
8929                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
8930         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8931                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
8932         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8933         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8934         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
8935         if (vmx_mpx_supported())
8936                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
8937
8938         /* update exit information fields: */
8939
8940         vmcs12->vm_exit_reason = exit_reason;
8941         vmcs12->exit_qualification = exit_qualification;
8942
8943         vmcs12->vm_exit_intr_info = exit_intr_info;
8944         if ((vmcs12->vm_exit_intr_info &
8945              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8946             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8947                 vmcs12->vm_exit_intr_error_code =
8948                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
8949         vmcs12->idt_vectoring_info_field = 0;
8950         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8951         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8952
8953         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8954                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8955                  * instead of reading the real value. */
8956                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
8957
8958                 /*
8959                  * Transfer the event that L0 or L1 may wanted to inject into
8960                  * L2 to IDT_VECTORING_INFO_FIELD.
8961                  */
8962                 vmcs12_save_pending_event(vcpu, vmcs12);
8963         }
8964
8965         /*
8966          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8967          * preserved above and would only end up incorrectly in L1.
8968          */
8969         vcpu->arch.nmi_injected = false;
8970         kvm_clear_exception_queue(vcpu);
8971         kvm_clear_interrupt_queue(vcpu);
8972 }
8973
8974 /*
8975  * A part of what we need to when the nested L2 guest exits and we want to
8976  * run its L1 parent, is to reset L1's guest state to the host state specified
8977  * in vmcs12.
8978  * This function is to be called not only on normal nested exit, but also on
8979  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8980  * Failures During or After Loading Guest State").
8981  * This function should be called when the active VMCS is L1's (vmcs01).
8982  */
8983 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8984                                    struct vmcs12 *vmcs12)
8985 {
8986         struct kvm_segment seg;
8987
8988         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8989                 vcpu->arch.efer = vmcs12->host_ia32_efer;
8990         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8991                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8992         else
8993                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8994         vmx_set_efer(vcpu, vcpu->arch.efer);
8995
8996         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8997         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
8998         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
8999         /*
9000          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
9001          * actually changed, because it depends on the current state of
9002          * fpu_active (which may have changed).
9003          * Note that vmx_set_cr0 refers to efer set above.
9004          */
9005         vmx_set_cr0(vcpu, vmcs12->host_cr0);
9006         /*
9007          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
9008          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
9009          * but we also need to update cr0_guest_host_mask and exception_bitmap.
9010          */
9011         update_exception_bitmap(vcpu);
9012         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
9013         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9014
9015         /*
9016          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
9017          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
9018          */
9019         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
9020         kvm_set_cr4(vcpu, vmcs12->host_cr4);
9021
9022         nested_ept_uninit_mmu_context(vcpu);
9023
9024         kvm_set_cr3(vcpu, vmcs12->host_cr3);
9025         kvm_mmu_reset_context(vcpu);
9026
9027         if (!enable_ept)
9028                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
9029
9030         if (enable_vpid) {
9031                 /*
9032                  * Trivially support vpid by letting L2s share their parent
9033                  * L1's vpid. TODO: move to a more elaborate solution, giving
9034                  * each L2 its own vpid and exposing the vpid feature to L1.
9035                  */
9036                 vmx_flush_tlb(vcpu);
9037         }
9038
9039
9040         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
9041         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
9042         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
9043         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
9044         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
9045
9046         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
9047         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
9048                 vmcs_write64(GUEST_BNDCFGS, 0);
9049
9050         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
9051                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
9052                 vcpu->arch.pat = vmcs12->host_ia32_pat;
9053         }
9054         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
9055                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
9056                         vmcs12->host_ia32_perf_global_ctrl);
9057
9058         /* Set L1 segment info according to Intel SDM
9059             27.5.2 Loading Host Segment and Descriptor-Table Registers */
9060         seg = (struct kvm_segment) {
9061                 .base = 0,
9062                 .limit = 0xFFFFFFFF,
9063                 .selector = vmcs12->host_cs_selector,
9064                 .type = 11,
9065                 .present = 1,
9066                 .s = 1,
9067                 .g = 1
9068         };
9069         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
9070                 seg.l = 1;
9071         else
9072                 seg.db = 1;
9073         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
9074         seg = (struct kvm_segment) {
9075                 .base = 0,
9076                 .limit = 0xFFFFFFFF,
9077                 .type = 3,
9078                 .present = 1,
9079                 .s = 1,
9080                 .db = 1,
9081                 .g = 1
9082         };
9083         seg.selector = vmcs12->host_ds_selector;
9084         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
9085         seg.selector = vmcs12->host_es_selector;
9086         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
9087         seg.selector = vmcs12->host_ss_selector;
9088         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
9089         seg.selector = vmcs12->host_fs_selector;
9090         seg.base = vmcs12->host_fs_base;
9091         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
9092         seg.selector = vmcs12->host_gs_selector;
9093         seg.base = vmcs12->host_gs_base;
9094         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
9095         seg = (struct kvm_segment) {
9096                 .base = vmcs12->host_tr_base,
9097                 .limit = 0x67,
9098                 .selector = vmcs12->host_tr_selector,
9099                 .type = 11,
9100                 .present = 1
9101         };
9102         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
9103
9104         kvm_set_dr(vcpu, 7, 0x400);
9105         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
9106 }
9107
9108 /*
9109  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
9110  * and modify vmcs12 to make it see what it would expect to see there if
9111  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
9112  */
9113 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
9114                               u32 exit_intr_info,
9115                               unsigned long exit_qualification)
9116 {
9117         struct vcpu_vmx *vmx = to_vmx(vcpu);
9118         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9119
9120         /* trying to cancel vmlaunch/vmresume is a bug */
9121         WARN_ON_ONCE(vmx->nested.nested_run_pending);
9122
9123         leave_guest_mode(vcpu);
9124         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
9125                        exit_qualification);
9126
9127         vmx_load_vmcs01(vcpu);
9128
9129         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
9130             && nested_exit_intr_ack_set(vcpu)) {
9131                 int irq = kvm_cpu_get_interrupt(vcpu);
9132                 WARN_ON(irq < 0);
9133                 vmcs12->vm_exit_intr_info = irq |
9134                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
9135         }
9136
9137         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
9138                                        vmcs12->exit_qualification,
9139                                        vmcs12->idt_vectoring_info_field,
9140                                        vmcs12->vm_exit_intr_info,
9141                                        vmcs12->vm_exit_intr_error_code,
9142                                        KVM_ISA_VMX);
9143
9144         vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
9145         vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
9146         vmx_segment_cache_clear(vmx);
9147
9148         /* if no vmcs02 cache requested, remove the one we used */
9149         if (VMCS02_POOL_SIZE == 0)
9150                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
9151
9152         load_vmcs12_host_state(vcpu, vmcs12);
9153
9154         /* Update TSC_OFFSET if TSC was changed while L2 ran */
9155         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9156
9157         /* This is needed for same reason as it was needed in prepare_vmcs02 */
9158         vmx->host_rsp = 0;
9159
9160         /* Unpin physical memory we referred to in vmcs02 */
9161         if (vmx->nested.apic_access_page) {
9162                 nested_release_page(vmx->nested.apic_access_page);
9163                 vmx->nested.apic_access_page = NULL;
9164         }
9165         if (vmx->nested.virtual_apic_page) {
9166                 nested_release_page(vmx->nested.virtual_apic_page);
9167                 vmx->nested.virtual_apic_page = NULL;
9168         }
9169
9170         /*
9171          * We are now running in L2, mmu_notifier will force to reload the
9172          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
9173          */
9174         kvm_vcpu_reload_apic_access_page(vcpu);
9175
9176         /*
9177          * Exiting from L2 to L1, we're now back to L1 which thinks it just
9178          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
9179          * success or failure flag accordingly.
9180          */
9181         if (unlikely(vmx->fail)) {
9182                 vmx->fail = 0;
9183                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
9184         } else
9185                 nested_vmx_succeed(vcpu);
9186         if (enable_shadow_vmcs)
9187                 vmx->nested.sync_shadow_vmcs = true;
9188
9189         /* in case we halted in L2 */
9190         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9191 }
9192
9193 /*
9194  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
9195  */
9196 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
9197 {
9198         if (is_guest_mode(vcpu))
9199                 nested_vmx_vmexit(vcpu, -1, 0, 0);
9200         free_nested(to_vmx(vcpu));
9201 }
9202
9203 /*
9204  * L1's failure to enter L2 is a subset of a normal exit, as explained in
9205  * 23.7 "VM-entry failures during or after loading guest state" (this also
9206  * lists the acceptable exit-reason and exit-qualification parameters).
9207  * It should only be called before L2 actually succeeded to run, and when
9208  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
9209  */
9210 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
9211                         struct vmcs12 *vmcs12,
9212                         u32 reason, unsigned long qualification)
9213 {
9214         load_vmcs12_host_state(vcpu, vmcs12);
9215         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
9216         vmcs12->exit_qualification = qualification;
9217         nested_vmx_succeed(vcpu);
9218         if (enable_shadow_vmcs)
9219                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
9220 }
9221
9222 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
9223                                struct x86_instruction_info *info,
9224                                enum x86_intercept_stage stage)
9225 {
9226         return X86EMUL_CONTINUE;
9227 }
9228
9229 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
9230 {
9231         if (ple_gap)
9232                 shrink_ple_window(vcpu);
9233 }
9234
9235 static struct kvm_x86_ops vmx_x86_ops = {
9236         .cpu_has_kvm_support = cpu_has_kvm_support,
9237         .disabled_by_bios = vmx_disabled_by_bios,
9238         .hardware_setup = hardware_setup,
9239         .hardware_unsetup = hardware_unsetup,
9240         .check_processor_compatibility = vmx_check_processor_compat,
9241         .hardware_enable = hardware_enable,
9242         .hardware_disable = hardware_disable,
9243         .cpu_has_accelerated_tpr = report_flexpriority,
9244
9245         .vcpu_create = vmx_create_vcpu,
9246         .vcpu_free = vmx_free_vcpu,
9247         .vcpu_reset = vmx_vcpu_reset,
9248
9249         .prepare_guest_switch = vmx_save_host_state,
9250         .vcpu_load = vmx_vcpu_load,
9251         .vcpu_put = vmx_vcpu_put,
9252
9253         .update_db_bp_intercept = update_exception_bitmap,
9254         .get_msr = vmx_get_msr,
9255         .set_msr = vmx_set_msr,
9256         .get_segment_base = vmx_get_segment_base,
9257         .get_segment = vmx_get_segment,
9258         .set_segment = vmx_set_segment,
9259         .get_cpl = vmx_get_cpl,
9260         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
9261         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
9262         .decache_cr3 = vmx_decache_cr3,
9263         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
9264         .set_cr0 = vmx_set_cr0,
9265         .set_cr3 = vmx_set_cr3,
9266         .set_cr4 = vmx_set_cr4,
9267         .set_efer = vmx_set_efer,
9268         .get_idt = vmx_get_idt,
9269         .set_idt = vmx_set_idt,
9270         .get_gdt = vmx_get_gdt,
9271         .set_gdt = vmx_set_gdt,
9272         .get_dr6 = vmx_get_dr6,
9273         .set_dr6 = vmx_set_dr6,
9274         .set_dr7 = vmx_set_dr7,
9275         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
9276         .cache_reg = vmx_cache_reg,
9277         .get_rflags = vmx_get_rflags,
9278         .set_rflags = vmx_set_rflags,
9279         .fpu_deactivate = vmx_fpu_deactivate,
9280
9281         .tlb_flush = vmx_flush_tlb,
9282
9283         .run = vmx_vcpu_run,
9284         .handle_exit = vmx_handle_exit,
9285         .skip_emulated_instruction = skip_emulated_instruction,
9286         .set_interrupt_shadow = vmx_set_interrupt_shadow,
9287         .get_interrupt_shadow = vmx_get_interrupt_shadow,
9288         .patch_hypercall = vmx_patch_hypercall,
9289         .set_irq = vmx_inject_irq,
9290         .set_nmi = vmx_inject_nmi,
9291         .queue_exception = vmx_queue_exception,
9292         .cancel_injection = vmx_cancel_injection,
9293         .interrupt_allowed = vmx_interrupt_allowed,
9294         .nmi_allowed = vmx_nmi_allowed,
9295         .get_nmi_mask = vmx_get_nmi_mask,
9296         .set_nmi_mask = vmx_set_nmi_mask,
9297         .enable_nmi_window = enable_nmi_window,
9298         .enable_irq_window = enable_irq_window,
9299         .update_cr8_intercept = update_cr8_intercept,
9300         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
9301         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
9302         .vm_has_apicv = vmx_vm_has_apicv,
9303         .load_eoi_exitmap = vmx_load_eoi_exitmap,
9304         .hwapic_irr_update = vmx_hwapic_irr_update,
9305         .hwapic_isr_update = vmx_hwapic_isr_update,
9306         .sync_pir_to_irr = vmx_sync_pir_to_irr,
9307         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
9308
9309         .set_tss_addr = vmx_set_tss_addr,
9310         .get_tdp_level = get_ept_level,
9311         .get_mt_mask = vmx_get_mt_mask,
9312
9313         .get_exit_info = vmx_get_exit_info,
9314
9315         .get_lpage_level = vmx_get_lpage_level,
9316
9317         .cpuid_update = vmx_cpuid_update,
9318
9319         .rdtscp_supported = vmx_rdtscp_supported,
9320         .invpcid_supported = vmx_invpcid_supported,
9321
9322         .set_supported_cpuid = vmx_set_supported_cpuid,
9323
9324         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
9325
9326         .set_tsc_khz = vmx_set_tsc_khz,
9327         .read_tsc_offset = vmx_read_tsc_offset,
9328         .write_tsc_offset = vmx_write_tsc_offset,
9329         .adjust_tsc_offset = vmx_adjust_tsc_offset,
9330         .compute_tsc_offset = vmx_compute_tsc_offset,
9331         .read_l1_tsc = vmx_read_l1_tsc,
9332
9333         .set_tdp_cr3 = vmx_set_cr3,
9334
9335         .check_intercept = vmx_check_intercept,
9336         .handle_external_intr = vmx_handle_external_intr,
9337         .mpx_supported = vmx_mpx_supported,
9338         .xsaves_supported = vmx_xsaves_supported,
9339
9340         .check_nested_events = vmx_check_nested_events,
9341
9342         .sched_in = vmx_sched_in,
9343 };
9344
9345 static int __init vmx_init(void)
9346 {
9347         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
9348                      __alignof__(struct vcpu_vmx), THIS_MODULE);
9349         if (r)
9350                 return r;
9351
9352 #ifdef CONFIG_KEXEC
9353         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
9354                            crash_vmclear_local_loaded_vmcss);
9355 #endif
9356
9357         return 0;
9358 }
9359
9360 static void __exit vmx_exit(void)
9361 {
9362 #ifdef CONFIG_KEXEC
9363         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
9364         synchronize_rcu();
9365 #endif
9366
9367         kvm_exit();
9368 }
9369
9370 module_init(vmx_init)
9371 module_exit(vmx_exit)