arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  *
   9  * Authors:
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *   Yaniv Kamay  <yaniv@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/mm.h>
  25 #include <linux/highmem.h>
  26 #include <linux/sched.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/ftrace_event.h>
  29 #include "kvm_cache_regs.h"
  30 #include "x86.h"
  31
  32 #include <asm/io.h>
  33 #include <asm/desc.h>
  34 #include <asm/vmx.h>
  35 #include <asm/virtext.h>
  36 #include <asm/mce.h>
  37
  38 #include "trace.h"
  39
  40 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  41
  42 MODULE_AUTHOR("Qumranet");
  43 MODULE_LICENSE("GPL");
  44
  45 static int __read_mostly bypass_guest_pf = 1;
  46 module_param(bypass_guest_pf, bool, S_IRUGO);
  47
  48 static int __read_mostly enable_vpid = 1;
  49 module_param_named(vpid, enable_vpid, bool, 0444);
  50
  51 static int __read_mostly flexpriority_enabled = 1;
  52 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  53
  54 static int __read_mostly enable_ept = 1;
  55 module_param_named(ept, enable_ept, bool, S_IRUGO);
  56
  57 static int __read_mostly enable_unrestricted_guest = 1;
  58 module_param_named(unrestricted_guest,
  59                         enable_unrestricted_guest, bool, S_IRUGO);
  60
  61 static int __read_mostly emulate_invalid_guest_state = 0;
  62 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  63
  64 struct vmcs {
  65         u32 revision_id;
  66         u32 abort;
  67         char data[0];
  68 };
  69
  70 struct vcpu_vmx {
  71         struct kvm_vcpu       vcpu;
  72         struct list_head      local_vcpus_link;
  73         unsigned long         host_rsp;
  74         int                   launched;
  75         u8                    fail;
  76         u32                   idt_vectoring_info;
  77         struct kvm_msr_entry *guest_msrs;
  78         struct kvm_msr_entry *host_msrs;
  79         int                   nmsrs;
  80         int                   save_nmsrs;
  81         int                   msr_offset_efer;
  82 #ifdef CONFIG_X86_64
  83         int                   msr_offset_kernel_gs_base;
  84 #endif
  85         struct vmcs          *vmcs;
  86         struct {
  87                 int           loaded;
  88                 u16           fs_sel, gs_sel, ldt_sel;
  89                 int           gs_ldt_reload_needed;
  90                 int           fs_reload_needed;
  91                 int           guest_efer_loaded;
  92         } host_state;
  93         struct {
  94                 int vm86_active;
  95                 u8 save_iopl;
  96                 struct kvm_save_segment {
  97                         u16 selector;
  98                         unsigned long base;
  99                         u32 limit;
 100                         u32 ar;
 101                 } tr, es, ds, fs, gs;
 102                 struct {
 103                         bool pending;
 104                         u8 vector;
 105                         unsigned rip;
 106                 } irq;
 107         } rmode;
 108         int vpid;
 109         bool emulation_required;
 110         enum emulation_result invalid_state_emulation_result;
 111
 112         /* Support for vnmi-less CPUs */
 113         int soft_vnmi_blocked;
 114         ktime_t entry_time;
 115         s64 vnmi_blocked_time;
 116         u32 exit_reason;
 117 };
 118
 119 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 120 {
 121         return container_of(vcpu, struct vcpu_vmx, vcpu);
 122 }
 123
 124 static int init_rmode(struct kvm *kvm);
 125 static u64 construct_eptp(unsigned long root_hpa);
 126
 127 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 128 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 129 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
 130
 131 static unsigned long *vmx_io_bitmap_a;
 132 static unsigned long *vmx_io_bitmap_b;
 133 static unsigned long *vmx_msr_bitmap_legacy;
 134 static unsigned long *vmx_msr_bitmap_longmode;
 135
 136 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 137 static DEFINE_SPINLOCK(vmx_vpid_lock);
 138
 139 static struct vmcs_config {
 140         int size;
 141         int order;
 142         u32 revision_id;
 143         u32 pin_based_exec_ctrl;
 144         u32 cpu_based_exec_ctrl;
 145         u32 cpu_based_2nd_exec_ctrl;
 146         u32 vmexit_ctrl;
 147         u32 vmentry_ctrl;
 148 } vmcs_config;
 149
 150 static struct vmx_capability {
 151         u32 ept;
 152         u32 vpid;
 153 } vmx_capability;
 154
 155 #define VMX_SEGMENT_FIELD(seg)                                  \
 156         [VCPU_SREG_##seg] = {                                   \
 157                 .selector = GUEST_##seg##_SELECTOR,             \
 158                 .base = GUEST_##seg##_BASE,                     \
 159                 .limit = GUEST_##seg##_LIMIT,                   \
 160                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 161         }
 162
 163 static struct kvm_vmx_segment_field {
 164         unsigned selector;
 165         unsigned base;
 166         unsigned limit;
 167         unsigned ar_bytes;
 168 } kvm_vmx_segment_fields[] = {
 169         VMX_SEGMENT_FIELD(CS),
 170         VMX_SEGMENT_FIELD(DS),
 171         VMX_SEGMENT_FIELD(ES),
 172         VMX_SEGMENT_FIELD(FS),
 173         VMX_SEGMENT_FIELD(GS),
 174         VMX_SEGMENT_FIELD(SS),
 175         VMX_SEGMENT_FIELD(TR),
 176         VMX_SEGMENT_FIELD(LDTR),
 177 };
 178
 179 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 180
 181 /*
 182  * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
 183  * away by decrementing the array size.
 184  */
 185 static const u32 vmx_msr_index[] = {
 186 #ifdef CONFIG_X86_64
 187         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
 188 #endif
 189         MSR_EFER, MSR_K6_STAR,
 190 };
 191 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 192
 193 static void load_msrs(struct kvm_msr_entry *e, int n)
 194 {
 195         int i;
 196
 197         for (i = 0; i < n; ++i)
 198                 wrmsrl(e[i].index, e[i].data);
 199 }
 200
 201 static void save_msrs(struct kvm_msr_entry *e, int n)
 202 {
 203         int i;
 204
 205         for (i = 0; i < n; ++i)
 206                 rdmsrl(e[i].index, e[i].data);
 207 }
 208
 209 static inline int is_page_fault(u32 intr_info)
 210 {
 211         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 212                              INTR_INFO_VALID_MASK)) ==
 213                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 214 }
 215
 216 static inline int is_no_device(u32 intr_info)
 217 {
 218         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 219                              INTR_INFO_VALID_MASK)) ==
 220                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 221 }
 222
 223 static inline int is_invalid_opcode(u32 intr_info)
 224 {
 225         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 226                              INTR_INFO_VALID_MASK)) ==
 227                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 228 }
 229
 230 static inline int is_external_interrupt(u32 intr_info)
 231 {
 232         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 233                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 234 }
 235
 236 static inline int is_machine_check(u32 intr_info)
 237 {
 238         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 239                              INTR_INFO_VALID_MASK)) ==
 240                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 241 }
 242
 243 static inline int cpu_has_vmx_msr_bitmap(void)
 244 {
 245         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 246 }
 247
 248 static inline int cpu_has_vmx_tpr_shadow(void)
 249 {
 250         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 251 }
 252
 253 static inline int vm_need_tpr_shadow(struct kvm *kvm)
 254 {
 255         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 256 }
 257
 258 static inline int cpu_has_secondary_exec_ctrls(void)
 259 {
 260         return vmcs_config.cpu_based_exec_ctrl &
 261                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 262 }
 263
 264 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 265 {
 266         return vmcs_config.cpu_based_2nd_exec_ctrl &
 267                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 268 }
 269
 270 static inline bool cpu_has_vmx_flexpriority(void)
 271 {
 272         return cpu_has_vmx_tpr_shadow() &&
 273                 cpu_has_vmx_virtualize_apic_accesses();
 274 }
 275
 276 static inline bool cpu_has_vmx_ept_execute_only(void)
 277 {
 278         return !!(vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT);
 279 }
 280
 281 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 282 {
 283         return !!(vmx_capability.ept & VMX_EPTP_UC_BIT);
 284 }
 285
 286 static inline bool cpu_has_vmx_eptp_writeback(void)
 287 {
 288         return !!(vmx_capability.ept & VMX_EPTP_WB_BIT);
 289 }
 290
 291 static inline bool cpu_has_vmx_ept_2m_page(void)
 292 {
 293         return !!(vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT);
 294 }
 295
 296 static inline int cpu_has_vmx_invept_individual_addr(void)
 297 {
 298         return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
 299 }
 300
 301 static inline int cpu_has_vmx_invept_context(void)
 302 {
 303         return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT);
 304 }
 305
 306 static inline int cpu_has_vmx_invept_global(void)
 307 {
 308         return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT);
 309 }
 310
 311 static inline int cpu_has_vmx_ept(void)
 312 {
 313         return vmcs_config.cpu_based_2nd_exec_ctrl &
 314                 SECONDARY_EXEC_ENABLE_EPT;
 315 }
 316
 317 static inline int cpu_has_vmx_unrestricted_guest(void)
 318 {
 319         return vmcs_config.cpu_based_2nd_exec_ctrl &
 320                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 321 }
 322
 323 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
 324 {
 325         return flexpriority_enabled &&
 326                 (cpu_has_vmx_virtualize_apic_accesses()) &&
 327                 (irqchip_in_kernel(kvm));
 328 }
 329
 330 static inline int cpu_has_vmx_vpid(void)
 331 {
 332         return vmcs_config.cpu_based_2nd_exec_ctrl &
 333                 SECONDARY_EXEC_ENABLE_VPID;
 334 }
 335
 336 static inline int cpu_has_virtual_nmis(void)
 337 {
 338         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 339 }
 340
 341 static inline bool report_flexpriority(void)
 342 {
 343         return flexpriority_enabled;
 344 }
 345
 346 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 347 {
 348         int i;
 349
 350         for (i = 0; i < vmx->nmsrs; ++i)
 351                 if (vmx->guest_msrs[i].index == msr)
 352                         return i;
 353         return -1;
 354 }
 355
 356 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 357 {
 358     struct {
 359         u64 vpid : 16;
 360         u64 rsvd : 48;
 361         u64 gva;
 362     } operand = { vpid, 0, gva };
 363
 364     asm volatile (__ex(ASM_VMX_INVVPID)
 365                   /* CF==1 or ZF==1 --> rc = -1 */
 366                   "; ja 1f ; ud2 ; 1:"
 367                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 368 }
 369
 370 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 371 {
 372         struct {
 373                 u64 eptp, gpa;
 374         } operand = {eptp, gpa};
 375
 376         asm volatile (__ex(ASM_VMX_INVEPT)
 377                         /* CF==1 or ZF==1 --> rc = -1 */
 378                         "; ja 1f ; ud2 ; 1:\n"
 379                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 380 }
 381
 382 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 383 {
 384         int i;
 385
 386         i = __find_msr_index(vmx, msr);
 387         if (i >= 0)
 388                 return &vmx->guest_msrs[i];
 389         return NULL;
 390 }
 391
 392 static void vmcs_clear(struct vmcs *vmcs)
 393 {
 394         u64 phys_addr = __pa(vmcs);
 395         u8 error;
 396
 397         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 398                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 399                       : "cc", "memory");
 400         if (error)
 401                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 402                        vmcs, phys_addr);
 403 }
 404
 405 static void __vcpu_clear(void *arg)
 406 {
 407         struct vcpu_vmx *vmx = arg;
 408         int cpu = raw_smp_processor_id();
 409
 410         if (vmx->vcpu.cpu == cpu)
 411                 vmcs_clear(vmx->vmcs);
 412         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 413                 per_cpu(current_vmcs, cpu) = NULL;
 414         rdtscll(vmx->vcpu.arch.host_tsc);
 415         list_del(&vmx->local_vcpus_link);
 416         vmx->vcpu.cpu = -1;
 417         vmx->launched = 0;
 418 }
 419
 420 static void vcpu_clear(struct vcpu_vmx *vmx)
 421 {
 422         if (vmx->vcpu.cpu == -1)
 423                 return;
 424         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
 425 }
 426
 427 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
 428 {
 429         if (vmx->vpid == 0)
 430                 return;
 431
 432         __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 433 }
 434
 435 static inline void ept_sync_global(void)
 436 {
 437         if (cpu_has_vmx_invept_global())
 438                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 439 }
 440
 441 static inline void ept_sync_context(u64 eptp)
 442 {
 443         if (enable_ept) {
 444                 if (cpu_has_vmx_invept_context())
 445                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
 446                 else
 447                         ept_sync_global();
 448         }
 449 }
 450
 451 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
 452 {
 453         if (enable_ept) {
 454                 if (cpu_has_vmx_invept_individual_addr())
 455                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
 456                                         eptp, gpa);
 457                 else
 458                         ept_sync_context(eptp);
 459         }
 460 }
 461
 462 static unsigned long vmcs_readl(unsigned long field)
 463 {
 464         unsigned long value;
 465
 466         asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
 467                       : "=a"(value) : "d"(field) : "cc");
 468         return value;
 469 }
 470
 471 static u16 vmcs_read16(unsigned long field)
 472 {
 473         return vmcs_readl(field);
 474 }
 475
 476 static u32 vmcs_read32(unsigned long field)
 477 {
 478         return vmcs_readl(field);
 479 }
 480
 481 static u64 vmcs_read64(unsigned long field)
 482 {
 483 #ifdef CONFIG_X86_64
 484         return vmcs_readl(field);
 485 #else
 486         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 487 #endif
 488 }
 489
 490 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 491 {
 492         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 493                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 494         dump_stack();
 495 }
 496
 497 static void vmcs_writel(unsigned long field, unsigned long value)
 498 {
 499         u8 error;
 500
 501         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
 502                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 503         if (unlikely(error))
 504                 vmwrite_error(field, value);
 505 }
 506
 507 static void vmcs_write16(unsigned long field, u16 value)
 508 {
 509         vmcs_writel(field, value);
 510 }
 511
 512 static void vmcs_write32(unsigned long field, u32 value)
 513 {
 514         vmcs_writel(field, value);
 515 }
 516
 517 static void vmcs_write64(unsigned long field, u64 value)
 518 {
 519         vmcs_writel(field, value);
 520 #ifndef CONFIG_X86_64
 521         asm volatile ("");
 522         vmcs_writel(field+1, value >> 32);
 523 #endif
 524 }
 525
 526 static void vmcs_clear_bits(unsigned long field, u32 mask)
 527 {
 528         vmcs_writel(field, vmcs_readl(field) & ~mask);
 529 }
 530
 531 static void vmcs_set_bits(unsigned long field, u32 mask)
 532 {
 533         vmcs_writel(field, vmcs_readl(field) | mask);
 534 }
 535
 536 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 537 {
 538         u32 eb;
 539
 540         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR);
 541         if (!vcpu->fpu_active)
 542                 eb |= 1u << NM_VECTOR;
 543         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
 544                 if (vcpu->guest_debug &
 545                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
 546                         eb |= 1u << DB_VECTOR;
 547                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
 548                         eb |= 1u << BP_VECTOR;
 549         }
 550         if (to_vmx(vcpu)->rmode.vm86_active)
 551                 eb = ~0;
 552         if (enable_ept)
 553                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 554         vmcs_write32(EXCEPTION_BITMAP, eb);
 555 }
 556
 557 static void reload_tss(void)
 558 {
 559         /*
 560          * VT restores TR but not its size.  Useless.
 561          */
 562         struct descriptor_table gdt;
 563         struct desc_struct *descs;
 564
 565         kvm_get_gdt(&gdt);
 566         descs = (void *)gdt.base;
 567         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 568         load_TR_desc();
 569 }
 570
 571 static void load_transition_efer(struct vcpu_vmx *vmx)
 572 {
 573         int efer_offset = vmx->msr_offset_efer;
 574         u64 host_efer;
 575         u64 guest_efer;
 576         u64 ignore_bits;
 577
 578         if (efer_offset < 0)
 579                 return;
 580         host_efer = vmx->host_msrs[efer_offset].data;
 581         guest_efer = vmx->guest_msrs[efer_offset].data;
 582
 583         /*
 584          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 585          * outside long mode
 586          */
 587         ignore_bits = EFER_NX | EFER_SCE;
 588 #ifdef CONFIG_X86_64
 589         ignore_bits |= EFER_LMA | EFER_LME;
 590         /* SCE is meaningful only in long mode on Intel */
 591         if (guest_efer & EFER_LMA)
 592                 ignore_bits &= ~(u64)EFER_SCE;
 593 #endif
 594         if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
 595                 return;
 596
 597         vmx->host_state.guest_efer_loaded = 1;
 598         guest_efer &= ~ignore_bits;
 599         guest_efer |= host_efer & ignore_bits;
 600         wrmsrl(MSR_EFER, guest_efer);
 601         vmx->vcpu.stat.efer_reload++;
 602 }
 603
 604 static void reload_host_efer(struct vcpu_vmx *vmx)
 605 {
 606         if (vmx->host_state.guest_efer_loaded) {
 607                 vmx->host_state.guest_efer_loaded = 0;
 608                 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
 609         }
 610 }
 611
 612 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 613 {
 614         struct vcpu_vmx *vmx = to_vmx(vcpu);
 615
 616         if (vmx->host_state.loaded)
 617                 return;
 618
 619         vmx->host_state.loaded = 1;
 620         /*
 621          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 622          * allow segment selectors with cpl > 0 or ti == 1.
 623          */
 624         vmx->host_state.ldt_sel = kvm_read_ldt();
 625         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 626         vmx->host_state.fs_sel = kvm_read_fs();
 627         if (!(vmx->host_state.fs_sel & 7)) {
 628                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 629                 vmx->host_state.fs_reload_needed = 0;
 630         } else {
 631                 vmcs_write16(HOST_FS_SELECTOR, 0);
 632                 vmx->host_state.fs_reload_needed = 1;
 633         }
 634         vmx->host_state.gs_sel = kvm_read_gs();
 635         if (!(vmx->host_state.gs_sel & 7))
 636                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 637         else {
 638                 vmcs_write16(HOST_GS_SELECTOR, 0);
 639                 vmx->host_state.gs_ldt_reload_needed = 1;
 640         }
 641
 642 #ifdef CONFIG_X86_64
 643         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 644         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 645 #else
 646         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 647         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 648 #endif
 649
 650 #ifdef CONFIG_X86_64
 651         if (is_long_mode(&vmx->vcpu))
 652                 save_msrs(vmx->host_msrs +
 653                           vmx->msr_offset_kernel_gs_base, 1);
 654
 655 #endif
 656         load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 657         load_transition_efer(vmx);
 658 }
 659
 660 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
 661 {
 662         unsigned long flags;
 663
 664         if (!vmx->host_state.loaded)
 665                 return;
 666
 667         ++vmx->vcpu.stat.host_state_reload;
 668         vmx->host_state.loaded = 0;
 669         if (vmx->host_state.fs_reload_needed)
 670                 kvm_load_fs(vmx->host_state.fs_sel);
 671         if (vmx->host_state.gs_ldt_reload_needed) {
 672                 kvm_load_ldt(vmx->host_state.ldt_sel);
 673                 /*
 674                  * If we have to reload gs, we must take care to
 675                  * preserve our gs base.
 676                  */
 677                 local_irq_save(flags);
 678                 kvm_load_gs(vmx->host_state.gs_sel);
 679 #ifdef CONFIG_X86_64
 680                 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
 681 #endif
 682                 local_irq_restore(flags);
 683         }
 684         reload_tss();
 685         save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 686         load_msrs(vmx->host_msrs, vmx->save_nmsrs);
 687         reload_host_efer(vmx);
 688 }
 689
 690 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 691 {
 692         preempt_disable();
 693         __vmx_load_host_state(vmx);
 694         preempt_enable();
 695 }
 696
 697 /*
 698  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 699  * vcpu mutex is already taken.
 700  */
 701 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 702 {
 703         struct vcpu_vmx *vmx = to_vmx(vcpu);
 704         u64 phys_addr = __pa(vmx->vmcs);
 705         u64 tsc_this, delta, new_offset;
 706
 707         if (vcpu->cpu != cpu) {
 708                 vcpu_clear(vmx);
 709                 kvm_migrate_timers(vcpu);
 710                 vpid_sync_vcpu_all(vmx);
 711                 local_irq_disable();
 712                 list_add(&vmx->local_vcpus_link,
 713                          &per_cpu(vcpus_on_cpu, cpu));
 714                 local_irq_enable();
 715         }
 716
 717         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 718                 u8 error;
 719
 720                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 721                 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 722                               : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 723                               : "cc");
 724                 if (error)
 725                         printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 726                                vmx->vmcs, phys_addr);
 727         }
 728
 729         if (vcpu->cpu != cpu) {
 730                 struct descriptor_table dt;
 731                 unsigned long sysenter_esp;
 732
 733                 vcpu->cpu = cpu;
 734                 /*
 735                  * Linux uses per-cpu TSS and GDT, so set these when switching
 736                  * processors.
 737                  */
 738                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
 739                 kvm_get_gdt(&dt);
 740                 vmcs_writel(HOST_GDTR_BASE, dt.base);   /* 22.2.4 */
 741
 742                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 743                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 744
 745                 /*
 746                  * Make sure the time stamp counter is monotonous.
 747                  */
 748                 rdtscll(tsc_this);
 749                 if (tsc_this < vcpu->arch.host_tsc) {
 750                         delta = vcpu->arch.host_tsc - tsc_this;
 751                         new_offset = vmcs_read64(TSC_OFFSET) + delta;
 752                         vmcs_write64(TSC_OFFSET, new_offset);
 753                 }
 754         }
 755 }
 756
 757 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 758 {
 759         __vmx_load_host_state(to_vmx(vcpu));
 760 }
 761
 762 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 763 {
 764         if (vcpu->fpu_active)
 765                 return;
 766         vcpu->fpu_active = 1;
 767         vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
 768         if (vcpu->arch.cr0 & X86_CR0_TS)
 769                 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 770         update_exception_bitmap(vcpu);
 771 }
 772
 773 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 774 {
 775         if (!vcpu->fpu_active)
 776                 return;
 777         vcpu->fpu_active = 0;
 778         vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 779         update_exception_bitmap(vcpu);
 780 }
 781
 782 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 783 {
 784         unsigned long rflags;
 785
 786         rflags = vmcs_readl(GUEST_RFLAGS);
 787         if (to_vmx(vcpu)->rmode.vm86_active)
 788                 rflags &= ~(unsigned long)(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
 789         return rflags;
 790 }
 791
 792 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 793 {
 794         if (to_vmx(vcpu)->rmode.vm86_active)
 795                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 796         vmcs_writel(GUEST_RFLAGS, rflags);
 797 }
 798
 799 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 800 {
 801         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 802         int ret = 0;
 803
 804         if (interruptibility & GUEST_INTR_STATE_STI)
 805                 ret |= X86_SHADOW_INT_STI;
 806         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
 807                 ret |= X86_SHADOW_INT_MOV_SS;
 808
 809         return ret & mask;
 810 }
 811
 812 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 813 {
 814         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 815         u32 interruptibility = interruptibility_old;
 816
 817         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
 818
 819         if (mask & X86_SHADOW_INT_MOV_SS)
 820                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
 821         if (mask & X86_SHADOW_INT_STI)
 822                 interruptibility |= GUEST_INTR_STATE_STI;
 823
 824         if ((interruptibility != interruptibility_old))
 825                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
 826 }
 827
 828 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 829 {
 830         unsigned long rip;
 831
 832         rip = kvm_rip_read(vcpu);
 833         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
 834         kvm_rip_write(vcpu, rip);
 835
 836         /* skipping an emulated instruction also counts */
 837         vmx_set_interrupt_shadow(vcpu, 0);
 838 }
 839
 840 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 841                                 bool has_error_code, u32 error_code)
 842 {
 843         struct vcpu_vmx *vmx = to_vmx(vcpu);
 844         u32 intr_info = nr | INTR_INFO_VALID_MASK;
 845
 846         if (has_error_code) {
 847                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
 848                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
 849         }
 850
 851         if (vmx->rmode.vm86_active) {
 852                 vmx->rmode.irq.pending = true;
 853                 vmx->rmode.irq.vector = nr;
 854                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
 855                 if (kvm_exception_is_soft(nr))
 856                         vmx->rmode.irq.rip +=
 857                                 vmx->vcpu.arch.event_exit_inst_len;
 858                 intr_info |= INTR_TYPE_SOFT_INTR;
 859                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
 860                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
 861                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
 862                 return;
 863         }
 864
 865         if (kvm_exception_is_soft(nr)) {
 866                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
 867                              vmx->vcpu.arch.event_exit_inst_len);
 868                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
 869         } else
 870                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
 871
 872         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
 873 }
 874
 875 /*
 876  * Swap MSR entry in host/guest MSR entry array.
 877  */
 878 #ifdef CONFIG_X86_64
 879 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
 880 {
 881         struct kvm_msr_entry tmp;
 882
 883         tmp = vmx->guest_msrs[to];
 884         vmx->guest_msrs[to] = vmx->guest_msrs[from];
 885         vmx->guest_msrs[from] = tmp;
 886         tmp = vmx->host_msrs[to];
 887         vmx->host_msrs[to] = vmx->host_msrs[from];
 888         vmx->host_msrs[from] = tmp;
 889 }
 890 #endif
 891
 892 /*
 893  * Set up the vmcs to automatically save and restore system
 894  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
 895  * mode, as fiddling with msrs is very expensive.
 896  */
 897 static void setup_msrs(struct vcpu_vmx *vmx)
 898 {
 899         int save_nmsrs;
 900         unsigned long *msr_bitmap;
 901
 902         vmx_load_host_state(vmx);
 903         save_nmsrs = 0;
 904 #ifdef CONFIG_X86_64
 905         if (is_long_mode(&vmx->vcpu)) {
 906                 int index;
 907
 908                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
 909                 if (index >= 0)
 910                         move_msr_up(vmx, index, save_nmsrs++);
 911                 index = __find_msr_index(vmx, MSR_LSTAR);
 912                 if (index >= 0)
 913                         move_msr_up(vmx, index, save_nmsrs++);
 914                 index = __find_msr_index(vmx, MSR_CSTAR);
 915                 if (index >= 0)
 916                         move_msr_up(vmx, index, save_nmsrs++);
 917                 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 918                 if (index >= 0)
 919                         move_msr_up(vmx, index, save_nmsrs++);
 920                 /*
 921                  * MSR_K6_STAR is only needed on long mode guests, and only
 922                  * if efer.sce is enabled.
 923                  */
 924                 index = __find_msr_index(vmx, MSR_K6_STAR);
 925                 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
 926                         move_msr_up(vmx, index, save_nmsrs++);
 927         }
 928 #endif
 929         vmx->save_nmsrs = save_nmsrs;
 930
 931 #ifdef CONFIG_X86_64
 932         vmx->msr_offset_kernel_gs_base =
 933                 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 934 #endif
 935         vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
 936
 937         if (cpu_has_vmx_msr_bitmap()) {
 938                 if (is_long_mode(&vmx->vcpu))
 939                         msr_bitmap = vmx_msr_bitmap_longmode;
 940                 else
 941                         msr_bitmap = vmx_msr_bitmap_legacy;
 942
 943                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
 944         }
 945 }
 946
 947 /*
 948  * reads and returns guest's timestamp counter "register"
 949  * guest_tsc = host_tsc + tsc_offset    -- 21.3
 950  */
 951 static u64 guest_read_tsc(void)
 952 {
 953         u64 host_tsc, tsc_offset;
 954
 955         rdtscll(host_tsc);
 956         tsc_offset = vmcs_read64(TSC_OFFSET);
 957         return host_tsc + tsc_offset;
 958 }
 959
 960 /*
 961  * writes 'guest_tsc' into guest's timestamp counter "register"
 962  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
 963  */
 964 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
 965 {
 966         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
 967 }
 968
 969 /*
 970  * Reads an msr value (of 'msr_index') into 'pdata'.
 971  * Returns 0 on success, non-0 otherwise.
 972  * Assumes vcpu_load() was already called.
 973  */
 974 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
 975 {
 976         u64 data;
 977         struct kvm_msr_entry *msr;
 978
 979         if (!pdata) {
 980                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
 981                 return -EINVAL;
 982         }
 983
 984         switch (msr_index) {
 985 #ifdef CONFIG_X86_64
 986         case MSR_FS_BASE:
 987                 data = vmcs_readl(GUEST_FS_BASE);
 988                 break;
 989         case MSR_GS_BASE:
 990                 data = vmcs_readl(GUEST_GS_BASE);
 991                 break;
 992         case MSR_EFER:
 993                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 994 #endif
 995         case MSR_IA32_TSC:
 996                 data = guest_read_tsc();
 997                 break;
 998         case MSR_IA32_SYSENTER_CS:
 999                 data = vmcs_read32(GUEST_SYSENTER_CS);
1000                 break;
1001         case MSR_IA32_SYSENTER_EIP:
1002                 data = vmcs_readl(GUEST_SYSENTER_EIP);
1003                 break;
1004         case MSR_IA32_SYSENTER_ESP:
1005                 data = vmcs_readl(GUEST_SYSENTER_ESP);
1006                 break;
1007         default:
1008                 vmx_load_host_state(to_vmx(vcpu));
1009                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1010                 if (msr) {
1011                         data = msr->data;
1012                         break;
1013                 }
1014                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1015         }
1016
1017         *pdata = data;
1018         return 0;
1019 }
1020
1021 /*
1022  * Writes msr value into into the appropriate "register".
1023  * Returns 0 on success, non-0 otherwise.
1024  * Assumes vcpu_load() was already called.
1025  */
1026 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1027 {
1028         struct vcpu_vmx *vmx = to_vmx(vcpu);
1029         struct kvm_msr_entry *msr;
1030         u64 host_tsc;
1031         int ret = 0;
1032
1033         switch (msr_index) {
1034         case MSR_EFER:
1035                 vmx_load_host_state(vmx);
1036                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1037                 break;
1038 #ifdef CONFIG_X86_64
1039         case MSR_FS_BASE:
1040                 vmcs_writel(GUEST_FS_BASE, data);
1041                 break;
1042         case MSR_GS_BASE:
1043                 vmcs_writel(GUEST_GS_BASE, data);
1044                 break;
1045 #endif
1046         case MSR_IA32_SYSENTER_CS:
1047                 vmcs_write32(GUEST_SYSENTER_CS, data);
1048                 break;
1049         case MSR_IA32_SYSENTER_EIP:
1050                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1051                 break;
1052         case MSR_IA32_SYSENTER_ESP:
1053                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1054                 break;
1055         case MSR_IA32_TSC:
1056                 rdtscll(host_tsc);
1057                 guest_write_tsc(data, host_tsc);
1058                 break;
1059         case MSR_IA32_CR_PAT:
1060                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1061                         vmcs_write64(GUEST_IA32_PAT, data);
1062                         vcpu->arch.pat = data;
1063                         break;
1064                 }
1065                 /* Otherwise falls through to kvm_set_msr_common */
1066         default:
1067                 vmx_load_host_state(vmx);
1068                 msr = find_msr_entry(vmx, msr_index);
1069                 if (msr) {
1070                         msr->data = data;
1071                         break;
1072                 }
1073                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1074         }
1075
1076         return ret;
1077 }
1078
1079 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1080 {
1081         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1082         switch (reg) {
1083         case VCPU_REGS_RSP:
1084                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1085                 break;
1086         case VCPU_REGS_RIP:
1087                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1088                 break;
1089         case VCPU_EXREG_PDPTR:
1090                 if (enable_ept)
1091                         ept_save_pdptrs(vcpu);
1092                 break;
1093         default:
1094                 break;
1095         }
1096 }
1097
1098 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1099 {
1100         int old_debug = vcpu->guest_debug;
1101         unsigned long flags;
1102
1103         vcpu->guest_debug = dbg->control;
1104         if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
1105                 vcpu->guest_debug = 0;
1106
1107         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1108                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1109         else
1110                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1111
1112         flags = vmcs_readl(GUEST_RFLAGS);
1113         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1114                 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1115         else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1116                 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1117         vmcs_writel(GUEST_RFLAGS, flags);
1118
1119         update_exception_bitmap(vcpu);
1120
1121         return 0;
1122 }
1123
1124 static __init int cpu_has_kvm_support(void)
1125 {
1126         return cpu_has_vmx();
1127 }
1128
1129 static __init int vmx_disabled_by_bios(void)
1130 {
1131         u64 msr;
1132
1133         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1134         return (msr & (FEATURE_CONTROL_LOCKED |
1135                        FEATURE_CONTROL_VMXON_ENABLED))
1136             == FEATURE_CONTROL_LOCKED;
1137         /* locked but not enabled */
1138 }
1139
1140 static void hardware_enable(void *garbage)
1141 {
1142         int cpu = raw_smp_processor_id();
1143         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1144         u64 old;
1145
1146         INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1147         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1148         if ((old & (FEATURE_CONTROL_LOCKED |
1149                     FEATURE_CONTROL_VMXON_ENABLED))
1150             != (FEATURE_CONTROL_LOCKED |
1151                 FEATURE_CONTROL_VMXON_ENABLED))
1152                 /* enable and lock */
1153                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1154                        FEATURE_CONTROL_LOCKED |
1155                        FEATURE_CONTROL_VMXON_ENABLED);
1156         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1157         asm volatile (ASM_VMX_VMXON_RAX
1158                       : : "a"(&phys_addr), "m"(phys_addr)
1159                       : "memory", "cc");
1160 }
1161
1162 static void vmclear_local_vcpus(void)
1163 {
1164         int cpu = raw_smp_processor_id();
1165         struct vcpu_vmx *vmx, *n;
1166
1167         list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1168                                  local_vcpus_link)
1169                 __vcpu_clear(vmx);
1170 }
1171
1172
1173 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1174  * tricks.
1175  */
1176 static void kvm_cpu_vmxoff(void)
1177 {
1178         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1179         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1180 }
1181
1182 static void hardware_disable(void *garbage)
1183 {
1184         vmclear_local_vcpus();
1185         kvm_cpu_vmxoff();
1186 }
1187
1188 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1189                                       u32 msr, u32 *result)
1190 {
1191         u32 vmx_msr_low, vmx_msr_high;
1192         u32 ctl = ctl_min | ctl_opt;
1193
1194         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1195
1196         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1197         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1198
1199         /* Ensure minimum (required) set of control bits are supported. */
1200         if (ctl_min & ~ctl)
1201                 return -EIO;
1202
1203         *result = ctl;
1204         return 0;
1205 }
1206
1207 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1208 {
1209         u32 vmx_msr_low, vmx_msr_high;
1210         u32 min, opt, min2, opt2;
1211         u32 _pin_based_exec_control = 0;
1212         u32 _cpu_based_exec_control = 0;
1213         u32 _cpu_based_2nd_exec_control = 0;
1214         u32 _vmexit_control = 0;
1215         u32 _vmentry_control = 0;
1216
1217         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1218         opt = PIN_BASED_VIRTUAL_NMIS;
1219         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1220                                 &_pin_based_exec_control) < 0)
1221                 return -EIO;
1222
1223         min = CPU_BASED_HLT_EXITING |
1224 #ifdef CONFIG_X86_64
1225               CPU_BASED_CR8_LOAD_EXITING |
1226               CPU_BASED_CR8_STORE_EXITING |
1227 #endif
1228               CPU_BASED_CR3_LOAD_EXITING |
1229               CPU_BASED_CR3_STORE_EXITING |
1230               CPU_BASED_USE_IO_BITMAPS |
1231               CPU_BASED_MOV_DR_EXITING |
1232               CPU_BASED_USE_TSC_OFFSETING |
1233               CPU_BASED_INVLPG_EXITING;
1234         opt = CPU_BASED_TPR_SHADOW |
1235               CPU_BASED_USE_MSR_BITMAPS |
1236               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1237         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1238                                 &_cpu_based_exec_control) < 0)
1239                 return -EIO;
1240 #ifdef CONFIG_X86_64
1241         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1242                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1243                                            ~CPU_BASED_CR8_STORE_EXITING;
1244 #endif
1245         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1246                 min2 = 0;
1247                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1248                         SECONDARY_EXEC_WBINVD_EXITING |
1249                         SECONDARY_EXEC_ENABLE_VPID |
1250                         SECONDARY_EXEC_ENABLE_EPT |
1251                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
1252                 if (adjust_vmx_controls(min2, opt2,
1253                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1254                                         &_cpu_based_2nd_exec_control) < 0)
1255                         return -EIO;
1256         }
1257 #ifndef CONFIG_X86_64
1258         if (!(_cpu_based_2nd_exec_control &
1259                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1260                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1261 #endif
1262         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1263                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1264                    enabled */
1265                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1266                                              CPU_BASED_CR3_STORE_EXITING |
1267                                              CPU_BASED_INVLPG_EXITING);
1268                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1269                       vmx_capability.ept, vmx_capability.vpid);
1270         }
1271
1272         min = 0;
1273 #ifdef CONFIG_X86_64
1274         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1275 #endif
1276         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1277         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1278                                 &_vmexit_control) < 0)
1279                 return -EIO;
1280
1281         min = 0;
1282         opt = VM_ENTRY_LOAD_IA32_PAT;
1283         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1284                                 &_vmentry_control) < 0)
1285                 return -EIO;
1286
1287         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1288
1289         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1290         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1291                 return -EIO;
1292
1293 #ifdef CONFIG_X86_64
1294         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1295         if (vmx_msr_high & (1u<<16))
1296                 return -EIO;
1297 #endif
1298
1299         /* Require Write-Back (WB) memory type for VMCS accesses. */
1300         if (((vmx_msr_high >> 18) & 15) != 6)
1301                 return -EIO;
1302
1303         vmcs_conf->size = vmx_msr_high & 0x1fff;
1304         vmcs_conf->order = get_order(vmcs_config.size);
1305         vmcs_conf->revision_id = vmx_msr_low;
1306
1307         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1308         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1309         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1310         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1311         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1312
1313         return 0;
1314 }
1315
1316 static struct vmcs *alloc_vmcs_cpu(int cpu)
1317 {
1318         int node = cpu_to_node(cpu);
1319         struct page *pages;
1320         struct vmcs *vmcs;
1321
1322         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1323         if (!pages)
1324                 return NULL;
1325         vmcs = page_address(pages);
1326         memset(vmcs, 0, vmcs_config.size);
1327         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1328         return vmcs;
1329 }
1330
1331 static struct vmcs *alloc_vmcs(void)
1332 {
1333         return alloc_vmcs_cpu(raw_smp_processor_id());
1334 }
1335
1336 static void free_vmcs(struct vmcs *vmcs)
1337 {
1338         free_pages((unsigned long)vmcs, vmcs_config.order);
1339 }
1340
1341 static void free_kvm_area(void)
1342 {
1343         int cpu;
1344
1345         for_each_online_cpu(cpu)
1346                 free_vmcs(per_cpu(vmxarea, cpu));
1347 }
1348
1349 static __init int alloc_kvm_area(void)
1350 {
1351         int cpu;
1352
1353         for_each_online_cpu(cpu) {
1354                 struct vmcs *vmcs;
1355
1356                 vmcs = alloc_vmcs_cpu(cpu);
1357                 if (!vmcs) {
1358                         free_kvm_area();
1359                         return -ENOMEM;
1360                 }
1361
1362                 per_cpu(vmxarea, cpu) = vmcs;
1363         }
1364         return 0;
1365 }
1366
1367 static __init int hardware_setup(void)
1368 {
1369         if (setup_vmcs_config(&vmcs_config) < 0)
1370                 return -EIO;
1371
1372         if (boot_cpu_has(X86_FEATURE_NX))
1373                 kvm_enable_efer_bits(EFER_NX);
1374
1375         if (!cpu_has_vmx_vpid())
1376                 enable_vpid = 0;
1377
1378         if (!cpu_has_vmx_ept()) {
1379                 enable_ept = 0;
1380                 enable_unrestricted_guest = 0;
1381         }
1382
1383         if (!cpu_has_vmx_unrestricted_guest())
1384                 enable_unrestricted_guest = 0;
1385
1386         if (!cpu_has_vmx_flexpriority())
1387                 flexpriority_enabled = 0;
1388
1389         if (!cpu_has_vmx_tpr_shadow())
1390                 kvm_x86_ops->update_cr8_intercept = NULL;
1391
1392         if (enable_ept && !cpu_has_vmx_ept_2m_page())
1393                 kvm_disable_largepages();
1394
1395         return alloc_kvm_area();
1396 }
1397
1398 static __exit void hardware_unsetup(void)
1399 {
1400         free_kvm_area();
1401 }
1402
1403 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1404 {
1405         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1406
1407         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1408                 vmcs_write16(sf->selector, save->selector);
1409                 vmcs_writel(sf->base, save->base);
1410                 vmcs_write32(sf->limit, save->limit);
1411                 vmcs_write32(sf->ar_bytes, save->ar);
1412         } else {
1413                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1414                         << AR_DPL_SHIFT;
1415                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1416         }
1417 }
1418
1419 static void enter_pmode(struct kvm_vcpu *vcpu)
1420 {
1421         unsigned long flags;
1422         struct vcpu_vmx *vmx = to_vmx(vcpu);
1423
1424         vmx->emulation_required = 1;
1425         vmx->rmode.vm86_active = 0;
1426
1427         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1428         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1429         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1430
1431         flags = vmcs_readl(GUEST_RFLAGS);
1432         flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1433         flags |= (vmx->rmode.save_iopl << IOPL_SHIFT);
1434         vmcs_writel(GUEST_RFLAGS, flags);
1435
1436         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1437                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1438
1439         update_exception_bitmap(vcpu);
1440
1441         if (emulate_invalid_guest_state)
1442                 return;
1443
1444         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1445         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1446         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1447         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1448
1449         vmcs_write16(GUEST_SS_SELECTOR, 0);
1450         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1451
1452         vmcs_write16(GUEST_CS_SELECTOR,
1453                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1454         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1455 }
1456
1457 static gva_t rmode_tss_base(struct kvm *kvm)
1458 {
1459         if (!kvm->arch.tss_addr) {
1460                 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1461                                  kvm->memslots[0].npages - 3;
1462                 return base_gfn << PAGE_SHIFT;
1463         }
1464         return kvm->arch.tss_addr;
1465 }
1466
1467 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1468 {
1469         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1470
1471         save->selector = vmcs_read16(sf->selector);
1472         save->base = vmcs_readl(sf->base);
1473         save->limit = vmcs_read32(sf->limit);
1474         save->ar = vmcs_read32(sf->ar_bytes);
1475         vmcs_write16(sf->selector, save->base >> 4);
1476         vmcs_write32(sf->base, save->base & 0xfffff);
1477         vmcs_write32(sf->limit, 0xffff);
1478         vmcs_write32(sf->ar_bytes, 0xf3);
1479 }
1480
1481 static void enter_rmode(struct kvm_vcpu *vcpu)
1482 {
1483         unsigned long flags;
1484         struct vcpu_vmx *vmx = to_vmx(vcpu);
1485
1486         if (enable_unrestricted_guest)
1487                 return;
1488
1489         vmx->emulation_required = 1;
1490         vmx->rmode.vm86_active = 1;
1491
1492         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1493         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1494
1495         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1496         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1497
1498         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1499         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1500
1501         flags = vmcs_readl(GUEST_RFLAGS);
1502         vmx->rmode.save_iopl
1503                 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1504
1505         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1506
1507         vmcs_writel(GUEST_RFLAGS, flags);
1508         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1509         update_exception_bitmap(vcpu);
1510
1511         if (emulate_invalid_guest_state)
1512                 goto continue_rmode;
1513
1514         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1515         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1516         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1517
1518         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1519         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1520         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1521                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1522         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1523
1524         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1525         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1526         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1527         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1528
1529 continue_rmode:
1530         kvm_mmu_reset_context(vcpu);
1531         init_rmode(vcpu->kvm);
1532 }
1533
1534 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1535 {
1536         struct vcpu_vmx *vmx = to_vmx(vcpu);
1537         struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1538
1539         vcpu->arch.shadow_efer = efer;
1540         if (!msr)
1541                 return;
1542         if (efer & EFER_LMA) {
1543                 vmcs_write32(VM_ENTRY_CONTROLS,
1544                              vmcs_read32(VM_ENTRY_CONTROLS) |
1545                              VM_ENTRY_IA32E_MODE);
1546                 msr->data = efer;
1547         } else {
1548                 vmcs_write32(VM_ENTRY_CONTROLS,
1549                              vmcs_read32(VM_ENTRY_CONTROLS) &
1550                              ~VM_ENTRY_IA32E_MODE);
1551
1552                 msr->data = efer & ~EFER_LME;
1553         }
1554         setup_msrs(vmx);
1555 }
1556
1557 #ifdef CONFIG_X86_64
1558
1559 static void enter_lmode(struct kvm_vcpu *vcpu)
1560 {
1561         u32 guest_tr_ar;
1562
1563         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1564         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1565                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1566                        __func__);
1567                 vmcs_write32(GUEST_TR_AR_BYTES,
1568                              (guest_tr_ar & ~AR_TYPE_MASK)
1569                              | AR_TYPE_BUSY_64_TSS);
1570         }
1571         vcpu->arch.shadow_efer |= EFER_LMA;
1572         vmx_set_efer(vcpu, vcpu->arch.shadow_efer);
1573 }
1574
1575 static void exit_lmode(struct kvm_vcpu *vcpu)
1576 {
1577         vcpu->arch.shadow_efer &= ~EFER_LMA;
1578
1579         vmcs_write32(VM_ENTRY_CONTROLS,
1580                      vmcs_read32(VM_ENTRY_CONTROLS)
1581                      & ~VM_ENTRY_IA32E_MODE);
1582 }
1583
1584 #endif
1585
1586 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1587 {
1588         vpid_sync_vcpu_all(to_vmx(vcpu));
1589         if (enable_ept)
1590                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1591 }
1592
1593 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1594 {
1595         vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1596         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1597 }
1598
1599 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1600 {
1601         if (!test_bit(VCPU_EXREG_PDPTR,
1602                       (unsigned long *)&vcpu->arch.regs_dirty))
1603                 return;
1604
1605         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1606                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1607                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1608                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1609                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1610         }
1611 }
1612
1613 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1614 {
1615         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1616                 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1617                 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1618                 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1619                 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1620         }
1621
1622         __set_bit(VCPU_EXREG_PDPTR,
1623                   (unsigned long *)&vcpu->arch.regs_avail);
1624         __set_bit(VCPU_EXREG_PDPTR,
1625                   (unsigned long *)&vcpu->arch.regs_dirty);
1626 }
1627
1628 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1629
1630 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1631                                         unsigned long cr0,
1632                                         struct kvm_vcpu *vcpu)
1633 {
1634         if (!(cr0 & X86_CR0_PG)) {
1635                 /* From paging/starting to nonpaging */
1636                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1637                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1638                              (CPU_BASED_CR3_LOAD_EXITING |
1639                               CPU_BASED_CR3_STORE_EXITING));
1640                 vcpu->arch.cr0 = cr0;
1641                 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1642         } else if (!is_paging(vcpu)) {
1643                 /* From nonpaging to paging */
1644                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1645                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1646                              ~(CPU_BASED_CR3_LOAD_EXITING |
1647                                CPU_BASED_CR3_STORE_EXITING));
1648                 vcpu->arch.cr0 = cr0;
1649                 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1650         }
1651
1652         if (!(cr0 & X86_CR0_WP))
1653                 *hw_cr0 &= ~X86_CR0_WP;
1654 }
1655
1656 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1657                                         struct kvm_vcpu *vcpu)
1658 {
1659         if (!is_paging(vcpu)) {
1660                 *hw_cr4 &= ~X86_CR4_PAE;
1661                 *hw_cr4 |= X86_CR4_PSE;
1662         } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1663                 *hw_cr4 &= ~X86_CR4_PAE;
1664 }
1665
1666 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1667 {
1668         struct vcpu_vmx *vmx = to_vmx(vcpu);
1669         unsigned long hw_cr0;
1670
1671         if (enable_unrestricted_guest)
1672                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1673                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1674         else
1675                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1676
1677         vmx_fpu_deactivate(vcpu);
1678
1679         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1680                 enter_pmode(vcpu);
1681
1682         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1683                 enter_rmode(vcpu);
1684
1685 #ifdef CONFIG_X86_64
1686         if (vcpu->arch.shadow_efer & EFER_LME) {
1687                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1688                         enter_lmode(vcpu);
1689                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1690                         exit_lmode(vcpu);
1691         }
1692 #endif
1693
1694         if (enable_ept)
1695                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1696
1697         vmcs_writel(CR0_READ_SHADOW, cr0);
1698         vmcs_writel(GUEST_CR0, hw_cr0);
1699         vcpu->arch.cr0 = cr0;
1700
1701         if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1702                 vmx_fpu_activate(vcpu);
1703 }
1704
1705 static u64 construct_eptp(unsigned long root_hpa)
1706 {
1707         u64 eptp;
1708
1709         /* TODO write the value reading from MSR */
1710         eptp = VMX_EPT_DEFAULT_MT |
1711                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1712         eptp |= (root_hpa & PAGE_MASK);
1713
1714         return eptp;
1715 }
1716
1717 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1718 {
1719         unsigned long guest_cr3;
1720         u64 eptp;
1721
1722         guest_cr3 = cr3;
1723         if (enable_ept) {
1724                 eptp = construct_eptp(cr3);
1725                 vmcs_write64(EPT_POINTER, eptp);
1726                 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1727                         vcpu->kvm->arch.ept_identity_map_addr;
1728         }
1729
1730         vmx_flush_tlb(vcpu);
1731         vmcs_writel(GUEST_CR3, guest_cr3);
1732         if (vcpu->arch.cr0 & X86_CR0_PE)
1733                 vmx_fpu_deactivate(vcpu);
1734 }
1735
1736 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1737 {
1738         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1739                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1740
1741         vcpu->arch.cr4 = cr4;
1742         if (enable_ept)
1743                 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1744
1745         vmcs_writel(CR4_READ_SHADOW, cr4);
1746         vmcs_writel(GUEST_CR4, hw_cr4);
1747 }
1748
1749 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1750 {
1751         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1752
1753         return vmcs_readl(sf->base);
1754 }
1755
1756 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1757                             struct kvm_segment *var, int seg)
1758 {
1759         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1760         u32 ar;
1761
1762         var->base = vmcs_readl(sf->base);
1763         var->limit = vmcs_read32(sf->limit);
1764         var->selector = vmcs_read16(sf->selector);
1765         ar = vmcs_read32(sf->ar_bytes);
1766         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
1767                 ar = 0;
1768         var->type = ar & 15;
1769         var->s = (ar >> 4) & 1;
1770         var->dpl = (ar >> 5) & 3;
1771         var->present = (ar >> 7) & 1;
1772         var->avl = (ar >> 12) & 1;
1773         var->l = (ar >> 13) & 1;
1774         var->db = (ar >> 14) & 1;
1775         var->g = (ar >> 15) & 1;
1776         var->unusable = (ar >> 16) & 1;
1777 }
1778
1779 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1780 {
1781         if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1782                 return 0;
1783
1784         if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1785                 return 3;
1786
1787         return vmcs_read16(GUEST_CS_SELECTOR) & 3;
1788 }
1789
1790 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1791 {
1792         u32 ar;
1793
1794         if (var->unusable)
1795                 ar = 1 << 16;
1796         else {
1797                 ar = var->type & 15;
1798                 ar |= (var->s & 1) << 4;
1799                 ar |= (var->dpl & 3) << 5;
1800                 ar |= (var->present & 1) << 7;
1801                 ar |= (var->avl & 1) << 12;
1802                 ar |= (var->l & 1) << 13;
1803                 ar |= (var->db & 1) << 14;
1804                 ar |= (var->g & 1) << 15;
1805         }
1806         if (ar == 0) /* a 0 value means unusable */
1807                 ar = AR_UNUSABLE_MASK;
1808
1809         return ar;
1810 }
1811
1812 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1813                             struct kvm_segment *var, int seg)
1814 {
1815         struct vcpu_vmx *vmx = to_vmx(vcpu);
1816         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1817         u32 ar;
1818
1819         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1820                 vmx->rmode.tr.selector = var->selector;
1821                 vmx->rmode.tr.base = var->base;
1822                 vmx->rmode.tr.limit = var->limit;
1823                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
1824                 return;
1825         }
1826         vmcs_writel(sf->base, var->base);
1827         vmcs_write32(sf->limit, var->limit);
1828         vmcs_write16(sf->selector, var->selector);
1829         if (vmx->rmode.vm86_active && var->s) {
1830                 /*
1831                  * Hack real-mode segments into vm86 compatibility.
1832                  */
1833                 if (var->base == 0xffff0000 && var->selector == 0xf000)
1834                         vmcs_writel(sf->base, 0xf0000);
1835                 ar = 0xf3;
1836         } else
1837                 ar = vmx_segment_access_rights(var);
1838
1839         /*
1840          *   Fix the "Accessed" bit in AR field of segment registers for older
1841          * qemu binaries.
1842          *   IA32 arch specifies that at the time of processor reset the
1843          * "Accessed" bit in the AR field of segment registers is 1. And qemu
1844          * is setting it to 0 in the usedland code. This causes invalid guest
1845          * state vmexit when "unrestricted guest" mode is turned on.
1846          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
1847          * tree. Newer qemu binaries with that qemu fix would not need this
1848          * kvm hack.
1849          */
1850         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
1851                 ar |= 0x1; /* Accessed */
1852
1853         vmcs_write32(sf->ar_bytes, ar);
1854 }
1855
1856 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1857 {
1858         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1859
1860         *db = (ar >> 14) & 1;
1861         *l = (ar >> 13) & 1;
1862 }
1863
1864 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1865 {
1866         dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1867         dt->base = vmcs_readl(GUEST_IDTR_BASE);
1868 }
1869
1870 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1871 {
1872         vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1873         vmcs_writel(GUEST_IDTR_BASE, dt->base);
1874 }
1875
1876 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1877 {
1878         dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1879         dt->base = vmcs_readl(GUEST_GDTR_BASE);
1880 }
1881
1882 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1883 {
1884         vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1885         vmcs_writel(GUEST_GDTR_BASE, dt->base);
1886 }
1887
1888 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1889 {
1890         struct kvm_segment var;
1891         u32 ar;
1892
1893         vmx_get_segment(vcpu, &var, seg);
1894         ar = vmx_segment_access_rights(&var);
1895
1896         if (var.base != (var.selector << 4))
1897                 return false;
1898         if (var.limit != 0xffff)
1899                 return false;
1900         if (ar != 0xf3)
1901                 return false;
1902
1903         return true;
1904 }
1905
1906 static bool code_segment_valid(struct kvm_vcpu *vcpu)
1907 {
1908         struct kvm_segment cs;
1909         unsigned int cs_rpl;
1910
1911         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1912         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1913
1914         if (cs.unusable)
1915                 return false;
1916         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1917                 return false;
1918         if (!cs.s)
1919                 return false;
1920         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
1921                 if (cs.dpl > cs_rpl)
1922                         return false;
1923         } else {
1924                 if (cs.dpl != cs_rpl)
1925                         return false;
1926         }
1927         if (!cs.present)
1928                 return false;
1929
1930         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1931         return true;
1932 }
1933
1934 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1935 {
1936         struct kvm_segment ss;
1937         unsigned int ss_rpl;
1938
1939         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1940         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1941
1942         if (ss.unusable)
1943                 return true;
1944         if (ss.type != 3 && ss.type != 7)
1945                 return false;
1946         if (!ss.s)
1947                 return false;
1948         if (ss.dpl != ss_rpl) /* DPL != RPL */
1949                 return false;
1950         if (!ss.present)
1951                 return false;
1952
1953         return true;
1954 }
1955
1956 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1957 {
1958         struct kvm_segment var;
1959         unsigned int rpl;
1960
1961         vmx_get_segment(vcpu, &var, seg);
1962         rpl = var.selector & SELECTOR_RPL_MASK;
1963
1964         if (var.unusable)
1965                 return true;
1966         if (!var.s)
1967                 return false;
1968         if (!var.present)
1969                 return false;
1970         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1971                 if (var.dpl < rpl) /* DPL < RPL */
1972                         return false;
1973         }
1974
1975         /* TODO: Add other members to kvm_segment_field to allow checking for other access
1976          * rights flags
1977          */
1978         return true;
1979 }
1980
1981 static bool tr_valid(struct kvm_vcpu *vcpu)
1982 {
1983         struct kvm_segment tr;
1984
1985         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1986
1987         if (tr.unusable)
1988                 return false;
1989         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
1990                 return false;
1991         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
1992                 return false;
1993         if (!tr.present)
1994                 return false;
1995
1996         return true;
1997 }
1998
1999 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2000 {
2001         struct kvm_segment ldtr;
2002
2003         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2004
2005         if (ldtr.unusable)
2006                 return true;
2007         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
2008                 return false;
2009         if (ldtr.type != 2)
2010                 return false;
2011         if (!ldtr.present)
2012                 return false;
2013
2014         return true;
2015 }
2016
2017 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2018 {
2019         struct kvm_segment cs, ss;
2020
2021         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2022         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2023
2024         return ((cs.selector & SELECTOR_RPL_MASK) ==
2025                  (ss.selector & SELECTOR_RPL_MASK));
2026 }
2027
2028 /*
2029  * Check if guest state is valid. Returns true if valid, false if
2030  * not.
2031  * We assume that registers are always usable
2032  */
2033 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2034 {
2035         /* real mode guest state checks */
2036         if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
2037                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2038                         return false;
2039                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2040                         return false;
2041                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2042                         return false;
2043                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2044                         return false;
2045                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2046                         return false;
2047                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2048                         return false;
2049         } else {
2050         /* protected mode guest state checks */
2051                 if (!cs_ss_rpl_check(vcpu))
2052                         return false;
2053                 if (!code_segment_valid(vcpu))
2054                         return false;
2055                 if (!stack_segment_valid(vcpu))
2056                         return false;
2057                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2058                         return false;
2059                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2060                         return false;
2061                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2062                         return false;
2063                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2064                         return false;
2065                 if (!tr_valid(vcpu))
2066                         return false;
2067                 if (!ldtr_valid(vcpu))
2068                         return false;
2069         }
2070         /* TODO:
2071          * - Add checks on RIP
2072          * - Add checks on RFLAGS
2073          */
2074
2075         return true;
2076 }
2077
2078 static int init_rmode_tss(struct kvm *kvm)
2079 {
2080         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2081         u16 data = 0;
2082         int ret = 0;
2083         int r;
2084
2085         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2086         if (r < 0)
2087                 goto out;
2088         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2089         r = kvm_write_guest_page(kvm, fn++, &data,
2090                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
2091         if (r < 0)
2092                 goto out;
2093         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2094         if (r < 0)
2095                 goto out;
2096         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2097         if (r < 0)
2098                 goto out;
2099         data = ~0;
2100         r = kvm_write_guest_page(kvm, fn, &data,
2101                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2102                                  sizeof(u8));
2103         if (r < 0)
2104                 goto out;
2105
2106         ret = 1;
2107 out:
2108         return ret;
2109 }
2110
2111 static int init_rmode_identity_map(struct kvm *kvm)
2112 {
2113         int i, r, ret;
2114         pfn_t identity_map_pfn;
2115         u32 tmp;
2116
2117         if (!enable_ept)
2118                 return 1;
2119         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2120                 printk(KERN_ERR "EPT: identity-mapping pagetable "
2121                         "haven't been allocated!\n");
2122                 return 0;
2123         }
2124         if (likely(kvm->arch.ept_identity_pagetable_done))
2125                 return 1;
2126         ret = 0;
2127         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2128         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2129         if (r < 0)
2130                 goto out;
2131         /* Set up identity-mapping pagetable for EPT in real mode */
2132         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2133                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2134                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2135                 r = kvm_write_guest_page(kvm, identity_map_pfn,
2136                                 &tmp, i * sizeof(tmp), sizeof(tmp));
2137                 if (r < 0)
2138                         goto out;
2139         }
2140         kvm->arch.ept_identity_pagetable_done = true;
2141         ret = 1;
2142 out:
2143         return ret;
2144 }
2145
2146 static void seg_setup(int seg)
2147 {
2148         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2149         unsigned int ar;
2150
2151         vmcs_write16(sf->selector, 0);
2152         vmcs_writel(sf->base, 0);
2153         vmcs_write32(sf->limit, 0xffff);
2154         if (enable_unrestricted_guest) {
2155                 ar = 0x93;
2156                 if (seg == VCPU_SREG_CS)
2157                         ar |= 0x08; /* code segment */
2158         } else
2159                 ar = 0xf3;
2160
2161         vmcs_write32(sf->ar_bytes, ar);
2162 }
2163
2164 static int alloc_apic_access_page(struct kvm *kvm)
2165 {
2166         struct kvm_userspace_memory_region kvm_userspace_mem;
2167         int r = 0;
2168
2169         down_write(&kvm->slots_lock);
2170         if (kvm->arch.apic_access_page)
2171                 goto out;
2172         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2173         kvm_userspace_mem.flags = 0;
2174         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2175         kvm_userspace_mem.memory_size = PAGE_SIZE;
2176         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2177         if (r)
2178                 goto out;
2179
2180         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2181 out:
2182         up_write(&kvm->slots_lock);
2183         return r;
2184 }
2185
2186 static int alloc_identity_pagetable(struct kvm *kvm)
2187 {
2188         struct kvm_userspace_memory_region kvm_userspace_mem;
2189         int r = 0;
2190
2191         down_write(&kvm->slots_lock);
2192         if (kvm->arch.ept_identity_pagetable)
2193                 goto out;
2194         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2195         kvm_userspace_mem.flags = 0;
2196         kvm_userspace_mem.guest_phys_addr =
2197                 kvm->arch.ept_identity_map_addr;
2198         kvm_userspace_mem.memory_size = PAGE_SIZE;
2199         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2200         if (r)
2201                 goto out;
2202
2203         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2204                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2205 out:
2206         up_write(&kvm->slots_lock);
2207         return r;
2208 }
2209
2210 static void allocate_vpid(struct vcpu_vmx *vmx)
2211 {
2212         int vpid;
2213
2214         vmx->vpid = 0;
2215         if (!enable_vpid)
2216                 return;
2217         spin_lock(&vmx_vpid_lock);
2218         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2219         if (vpid < VMX_NR_VPIDS) {
2220                 vmx->vpid = vpid;
2221                 __set_bit(vpid, vmx_vpid_bitmap);
2222         }
2223         spin_unlock(&vmx_vpid_lock);
2224 }
2225
2226 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2227 {
2228         int f = sizeof(unsigned long);
2229
2230         if (!cpu_has_vmx_msr_bitmap())
2231                 return;
2232
2233         /*
2234          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2235          * have the write-low and read-high bitmap offsets the wrong way round.
2236          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2237          */
2238         if (msr <= 0x1fff) {
2239                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2240                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2241         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2242                 msr &= 0x1fff;
2243                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2244                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2245         }
2246 }
2247
2248 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2249 {
2250         if (!longmode_only)
2251                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2252         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2253 }
2254
2255 /*
2256  * Sets up the vmcs for emulated real mode.
2257  */
2258 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2259 {
2260         u32 host_sysenter_cs, msr_low, msr_high;
2261         u32 junk;
2262         u64 host_pat, tsc_this, tsc_base;
2263         unsigned long a;
2264         struct descriptor_table dt;
2265         int i;
2266         unsigned long kvm_vmx_return;
2267         u32 exec_control;
2268
2269         /* I/O */
2270         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2271         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2272
2273         if (cpu_has_vmx_msr_bitmap())
2274                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2275
2276         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2277
2278         /* Control */
2279         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2280                 vmcs_config.pin_based_exec_ctrl);
2281
2282         exec_control = vmcs_config.cpu_based_exec_ctrl;
2283         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2284                 exec_control &= ~CPU_BASED_TPR_SHADOW;
2285 #ifdef CONFIG_X86_64
2286                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2287                                 CPU_BASED_CR8_LOAD_EXITING;
2288 #endif
2289         }
2290         if (!enable_ept)
2291                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2292                                 CPU_BASED_CR3_LOAD_EXITING  |
2293                                 CPU_BASED_INVLPG_EXITING;
2294         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2295
2296         if (cpu_has_secondary_exec_ctrls()) {
2297                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2298                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2299                         exec_control &=
2300                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2301                 if (vmx->vpid == 0)
2302                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2303                 if (!enable_ept)
2304                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2305                 if (!enable_unrestricted_guest)
2306                         exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2307                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2308         }
2309
2310         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2311         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2312         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
2313
2314         vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
2315         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
2316         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
2317
2318         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
2319         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2320         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2321         vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs());    /* 22.2.4 */
2322         vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs());    /* 22.2.4 */
2323         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2324 #ifdef CONFIG_X86_64
2325         rdmsrl(MSR_FS_BASE, a);
2326         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2327         rdmsrl(MSR_GS_BASE, a);
2328         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2329 #else
2330         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2331         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2332 #endif
2333
2334         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
2335
2336         kvm_get_idt(&dt);
2337         vmcs_writel(HOST_IDTR_BASE, dt.base);   /* 22.2.4 */
2338
2339         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2340         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2341         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2342         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2343         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2344
2345         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2346         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2347         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2348         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
2349         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2350         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
2351
2352         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2353                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2354                 host_pat = msr_low | ((u64) msr_high << 32);
2355                 vmcs_write64(HOST_IA32_PAT, host_pat);
2356         }
2357         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2358                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2359                 host_pat = msr_low | ((u64) msr_high << 32);
2360                 /* Write the default value follow host pat */
2361                 vmcs_write64(GUEST_IA32_PAT, host_pat);
2362                 /* Keep arch.pat sync with GUEST_IA32_PAT */
2363                 vmx->vcpu.arch.pat = host_pat;
2364         }
2365
2366         for (i = 0; i < NR_VMX_MSR; ++i) {
2367                 u32 index = vmx_msr_index[i];
2368                 u32 data_low, data_high;
2369                 u64 data;
2370                 int j = vmx->nmsrs;
2371
2372                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2373                         continue;
2374                 if (wrmsr_safe(index, data_low, data_high) < 0)
2375                         continue;
2376                 data = data_low | ((u64)data_high << 32);
2377                 vmx->host_msrs[j].index = index;
2378                 vmx->host_msrs[j].reserved = 0;
2379                 vmx->host_msrs[j].data = data;
2380                 vmx->guest_msrs[j] = vmx->host_msrs[j];
2381                 ++vmx->nmsrs;
2382         }
2383
2384         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2385
2386         /* 22.2.1, 20.8.1 */
2387         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2388
2389         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2390         vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2391
2392         tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2393         rdtscll(tsc_this);
2394         if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2395                 tsc_base = tsc_this;
2396
2397         guest_write_tsc(0, tsc_base);
2398
2399         return 0;
2400 }
2401
2402 static int init_rmode(struct kvm *kvm)
2403 {
2404         if (!init_rmode_tss(kvm))
2405                 return 0;
2406         if (!init_rmode_identity_map(kvm))
2407                 return 0;
2408         return 1;
2409 }
2410
2411 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2412 {
2413         struct vcpu_vmx *vmx = to_vmx(vcpu);
2414         u64 msr;
2415         int ret;
2416
2417         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2418         down_read(&vcpu->kvm->slots_lock);
2419         if (!init_rmode(vmx->vcpu.kvm)) {
2420                 ret = -ENOMEM;
2421                 goto out;
2422         }
2423
2424         vmx->rmode.vm86_active = 0;
2425
2426         vmx->soft_vnmi_blocked = 0;
2427
2428         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2429         kvm_set_cr8(&vmx->vcpu, 0);
2430         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2431         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2432                 msr |= MSR_IA32_APICBASE_BSP;
2433         kvm_set_apic_base(&vmx->vcpu, msr);
2434
2435         fx_init(&vmx->vcpu);
2436
2437         seg_setup(VCPU_SREG_CS);
2438         /*
2439          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2440          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
2441          */
2442         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2443                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2444                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2445         } else {
2446                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2447                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2448         }
2449
2450         seg_setup(VCPU_SREG_DS);
2451         seg_setup(VCPU_SREG_ES);
2452         seg_setup(VCPU_SREG_FS);
2453         seg_setup(VCPU_SREG_GS);
2454         seg_setup(VCPU_SREG_SS);
2455
2456         vmcs_write16(GUEST_TR_SELECTOR, 0);
2457         vmcs_writel(GUEST_TR_BASE, 0);
2458         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2459         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2460
2461         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2462         vmcs_writel(GUEST_LDTR_BASE, 0);
2463         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2464         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2465
2466         vmcs_write32(GUEST_SYSENTER_CS, 0);
2467         vmcs_writel(GUEST_SYSENTER_ESP, 0);
2468         vmcs_writel(GUEST_SYSENTER_EIP, 0);
2469
2470         vmcs_writel(GUEST_RFLAGS, 0x02);
2471         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2472                 kvm_rip_write(vcpu, 0xfff0);
2473         else
2474                 kvm_rip_write(vcpu, 0);
2475         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2476
2477         vmcs_writel(GUEST_DR7, 0x400);
2478
2479         vmcs_writel(GUEST_GDTR_BASE, 0);
2480         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2481
2482         vmcs_writel(GUEST_IDTR_BASE, 0);
2483         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2484
2485         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2486         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2487         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2488
2489         /* Special registers */
2490         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2491
2492         setup_msrs(vmx);
2493
2494         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
2495
2496         if (cpu_has_vmx_tpr_shadow()) {
2497                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2498                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2499                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2500                                 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2501                 vmcs_write32(TPR_THRESHOLD, 0);
2502         }
2503
2504         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2505                 vmcs_write64(APIC_ACCESS_ADDR,
2506                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2507
2508         if (vmx->vpid != 0)
2509                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2510
2511         vmx->vcpu.arch.cr0 = 0x60000010;
2512         vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2513         vmx_set_cr4(&vmx->vcpu, 0);
2514         vmx_set_efer(&vmx->vcpu, 0);
2515         vmx_fpu_activate(&vmx->vcpu);
2516         update_exception_bitmap(&vmx->vcpu);
2517
2518         vpid_sync_vcpu_all(vmx);
2519
2520         ret = 0;
2521
2522         /* HACK: Don't enable emulation on guest boot/reset */
2523         vmx->emulation_required = 0;
2524
2525 out:
2526         up_read(&vcpu->kvm->slots_lock);
2527         return ret;
2528 }
2529
2530 static void enable_irq_window(struct kvm_vcpu *vcpu)
2531 {
2532         u32 cpu_based_vm_exec_control;
2533
2534         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2535         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2536         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2537 }
2538
2539 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2540 {
2541         u32 cpu_based_vm_exec_control;
2542
2543         if (!cpu_has_virtual_nmis()) {
2544                 enable_irq_window(vcpu);
2545                 return;
2546         }
2547
2548         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2549         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2550         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2551 }
2552
2553 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2554 {
2555         struct vcpu_vmx *vmx = to_vmx(vcpu);
2556         uint32_t intr;
2557         int irq = vcpu->arch.interrupt.nr;
2558
2559         trace_kvm_inj_virq(irq);
2560
2561         ++vcpu->stat.irq_injections;
2562         if (vmx->rmode.vm86_active) {
2563                 vmx->rmode.irq.pending = true;
2564                 vmx->rmode.irq.vector = irq;
2565                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2566                 if (vcpu->arch.interrupt.soft)
2567                         vmx->rmode.irq.rip +=
2568                                 vmx->vcpu.arch.event_exit_inst_len;
2569                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2570                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2571                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2572                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2573                 return;
2574         }
2575         intr = irq | INTR_INFO_VALID_MASK;
2576         if (vcpu->arch.interrupt.soft) {
2577                 intr |= INTR_TYPE_SOFT_INTR;
2578                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2579                              vmx->vcpu.arch.event_exit_inst_len);
2580         } else
2581                 intr |= INTR_TYPE_EXT_INTR;
2582         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2583 }
2584
2585 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2586 {
2587         struct vcpu_vmx *vmx = to_vmx(vcpu);
2588
2589         if (!cpu_has_virtual_nmis()) {
2590                 /*
2591                  * Tracking the NMI-blocked state in software is built upon
2592                  * finding the next open IRQ window. This, in turn, depends on
2593                  * well-behaving guests: They have to keep IRQs disabled at
2594                  * least as long as the NMI handler runs. Otherwise we may
2595                  * cause NMI nesting, maybe breaking the guest. But as this is
2596                  * highly unlikely, we can live with the residual risk.
2597                  */
2598                 vmx->soft_vnmi_blocked = 1;
2599                 vmx->vnmi_blocked_time = 0;
2600         }
2601
2602         ++vcpu->stat.nmi_injections;
2603         if (vmx->rmode.vm86_active) {
2604                 vmx->rmode.irq.pending = true;
2605                 vmx->rmode.irq.vector = NMI_VECTOR;
2606                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2607                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2608                              NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2609                              INTR_INFO_VALID_MASK);
2610                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2611                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2612                 return;
2613         }
2614         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2615                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2616 }
2617
2618 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2619 {
2620         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2621                 return 0;
2622
2623         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2624                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2625                                 GUEST_INTR_STATE_NMI));
2626 }
2627
2628 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2629 {
2630         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2631                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2632                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2633 }
2634
2635 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2636 {
2637         int ret;
2638         struct kvm_userspace_memory_region tss_mem = {
2639                 .slot = TSS_PRIVATE_MEMSLOT,
2640                 .guest_phys_addr = addr,
2641                 .memory_size = PAGE_SIZE * 3,
2642                 .flags = 0,
2643         };
2644
2645         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2646         if (ret)
2647                 return ret;
2648         kvm->arch.tss_addr = addr;
2649         return 0;
2650 }
2651
2652 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2653                                   int vec, u32 err_code)
2654 {
2655         /*
2656          * Instruction with address size override prefix opcode 0x67
2657          * Cause the #SS fault with 0 error code in VM86 mode.
2658          */
2659         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2660                 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
2661                         return 1;
2662         /*
2663          * Forward all other exceptions that are valid in real mode.
2664          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2665          *        the required debugging infrastructure rework.
2666          */
2667         switch (vec) {
2668         case DB_VECTOR:
2669                 if (vcpu->guest_debug &
2670                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2671                         return 0;
2672                 kvm_queue_exception(vcpu, vec);
2673                 return 1;
2674         case BP_VECTOR:
2675                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2676                         return 0;
2677                 /* fall through */
2678         case DE_VECTOR:
2679         case OF_VECTOR:
2680         case BR_VECTOR:
2681         case UD_VECTOR:
2682         case DF_VECTOR:
2683         case SS_VECTOR:
2684         case GP_VECTOR:
2685         case MF_VECTOR:
2686                 kvm_queue_exception(vcpu, vec);
2687                 return 1;
2688         }
2689         return 0;
2690 }
2691
2692 /*
2693  * Trigger machine check on the host. We assume all the MSRs are already set up
2694  * by the CPU and that we still run on the same CPU as the MCE occurred on.
2695  * We pass a fake environment to the machine check handler because we want
2696  * the guest to be always treated like user space, no matter what context
2697  * it used internally.
2698  */
2699 static void kvm_machine_check(void)
2700 {
2701 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2702         struct pt_regs regs = {
2703                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2704                 .flags = X86_EFLAGS_IF,
2705         };
2706
2707         do_machine_check(&regs, 0);
2708 #endif
2709 }
2710
2711 static int handle_machine_check(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2712 {
2713         /* already handled by vcpu_run */
2714         return 1;
2715 }
2716
2717 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2718 {
2719         struct vcpu_vmx *vmx = to_vmx(vcpu);
2720         u32 intr_info, ex_no, error_code;
2721         unsigned long cr2, rip, dr6;
2722         u32 vect_info;
2723         enum emulation_result er;
2724
2725         vect_info = vmx->idt_vectoring_info;
2726         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2727
2728         if (is_machine_check(intr_info))
2729                 return handle_machine_check(vcpu, kvm_run);
2730
2731         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2732                                                 !is_page_fault(intr_info))
2733                 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
2734                        "intr info 0x%x\n", __func__, vect_info, intr_info);
2735
2736         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2737                 return 1;  /* already handled by vmx_vcpu_run() */
2738
2739         if (is_no_device(intr_info)) {
2740                 vmx_fpu_activate(vcpu);
2741                 return 1;
2742         }
2743
2744         if (is_invalid_opcode(intr_info)) {
2745                 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
2746                 if (er != EMULATE_DONE)
2747                         kvm_queue_exception(vcpu, UD_VECTOR);
2748                 return 1;
2749         }
2750
2751         error_code = 0;
2752         rip = kvm_rip_read(vcpu);
2753         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2754                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2755         if (is_page_fault(intr_info)) {
2756                 /* EPT won't cause page fault directly */
2757                 if (enable_ept)
2758                         BUG();
2759                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2760                 trace_kvm_page_fault(cr2, error_code);
2761
2762                 if (kvm_event_needs_reinjection(vcpu))
2763                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
2764                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2765         }
2766
2767         if (vmx->rmode.vm86_active &&
2768             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2769                                                                 error_code)) {
2770                 if (vcpu->arch.halt_request) {
2771                         vcpu->arch.halt_request = 0;
2772                         return kvm_emulate_halt(vcpu);
2773                 }
2774                 return 1;
2775         }
2776
2777         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
2778         switch (ex_no) {
2779         case DB_VECTOR:
2780                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2781                 if (!(vcpu->guest_debug &
2782                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2783                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2784                         kvm_queue_exception(vcpu, DB_VECTOR);
2785                         return 1;
2786                 }
2787                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2788                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2789                 /* fall through */
2790         case BP_VECTOR:
2791                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2792                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2793                 kvm_run->debug.arch.exception = ex_no;
2794                 break;
2795         default:
2796                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2797                 kvm_run->ex.exception = ex_no;
2798                 kvm_run->ex.error_code = error_code;
2799                 break;
2800         }
2801         return 0;
2802 }
2803
2804 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2805                                      struct kvm_run *kvm_run)
2806 {
2807         ++vcpu->stat.irq_exits;
2808         return 1;
2809 }
2810
2811 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2812 {
2813         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2814         return 0;
2815 }
2816
2817 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2818 {
2819         unsigned long exit_qualification;
2820         int size, in, string;
2821         unsigned port;
2822
2823         ++vcpu->stat.io_exits;
2824         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2825         string = (exit_qualification & 16) != 0;
2826
2827         if (string) {
2828                 if (emulate_instruction(vcpu,
2829                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
2830                         return 0;
2831                 return 1;
2832         }
2833
2834         size = (exit_qualification & 7) + 1;
2835         in = (exit_qualification & 8) != 0;
2836         port = exit_qualification >> 16;
2837
2838         skip_emulated_instruction(vcpu);
2839         return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
2840 }
2841
2842 static void
2843 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2844 {
2845         /*
2846          * Patch in the VMCALL instruction:
2847          */
2848         hypercall[0] = 0x0f;
2849         hypercall[1] = 0x01;
2850         hypercall[2] = 0xc1;
2851 }
2852
2853 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2854 {
2855         unsigned long exit_qualification, val;
2856         int cr;
2857         int reg;
2858
2859         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2860         cr = exit_qualification & 15;
2861         reg = (exit_qualification >> 8) & 15;
2862         switch ((exit_qualification >> 4) & 3) {
2863         case 0: /* mov to cr */
2864                 val = kvm_register_read(vcpu, reg);
2865                 trace_kvm_cr_write(cr, val);
2866                 switch (cr) {
2867                 case 0:
2868                         kvm_set_cr0(vcpu, val);
2869                         skip_emulated_instruction(vcpu);
2870                         return 1;
2871                 case 3:
2872                         kvm_set_cr3(vcpu, val);
2873                         skip_emulated_instruction(vcpu);
2874                         return 1;
2875                 case 4:
2876                         kvm_set_cr4(vcpu, val);
2877                         skip_emulated_instruction(vcpu);
2878                         return 1;
2879                 case 8: {
2880                                 u8 cr8_prev = kvm_get_cr8(vcpu);
2881                                 u8 cr8 = kvm_register_read(vcpu, reg);
2882                                 kvm_set_cr8(vcpu, cr8);
2883                                 skip_emulated_instruction(vcpu);
2884                                 if (irqchip_in_kernel(vcpu->kvm))
2885                                         return 1;
2886                                 if (cr8_prev <= cr8)
2887                                         return 1;
2888                                 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2889                                 return 0;
2890                         }
2891                 };
2892                 break;
2893         case 2: /* clts */
2894                 vmx_fpu_deactivate(vcpu);
2895                 vcpu->arch.cr0 &= ~X86_CR0_TS;
2896                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2897                 vmx_fpu_activate(vcpu);
2898                 skip_emulated_instruction(vcpu);
2899                 return 1;
2900         case 1: /*mov from cr*/
2901                 switch (cr) {
2902                 case 3:
2903                         kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2904                         trace_kvm_cr_read(cr, vcpu->arch.cr3);
2905                         skip_emulated_instruction(vcpu);
2906                         return 1;
2907                 case 8:
2908                         val = kvm_get_cr8(vcpu);
2909                         kvm_register_write(vcpu, reg, val);
2910                         trace_kvm_cr_read(cr, val);
2911                         skip_emulated_instruction(vcpu);
2912                         return 1;
2913                 }
2914                 break;
2915         case 3: /* lmsw */
2916                 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2917
2918                 skip_emulated_instruction(vcpu);
2919                 return 1;
2920         default:
2921                 break;
2922         }
2923         kvm_run->exit_reason = 0;
2924         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2925                (int)(exit_qualification >> 4) & 3, cr);
2926         return 0;
2927 }
2928
2929 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2930 {
2931         unsigned long exit_qualification;
2932         unsigned long val;
2933         int dr, reg;
2934
2935         dr = vmcs_readl(GUEST_DR7);
2936         if (dr & DR7_GD) {
2937                 /*
2938                  * As the vm-exit takes precedence over the debug trap, we
2939                  * need to emulate the latter, either for the host or the
2940                  * guest debugging itself.
2941                  */
2942                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
2943                         kvm_run->debug.arch.dr6 = vcpu->arch.dr6;
2944                         kvm_run->debug.arch.dr7 = dr;
2945                         kvm_run->debug.arch.pc =
2946                                 vmcs_readl(GUEST_CS_BASE) +
2947                                 vmcs_readl(GUEST_RIP);
2948                         kvm_run->debug.arch.exception = DB_VECTOR;
2949                         kvm_run->exit_reason = KVM_EXIT_DEBUG;
2950                         return 0;
2951                 } else {
2952                         vcpu->arch.dr7 &= ~DR7_GD;
2953                         vcpu->arch.dr6 |= DR6_BD;
2954                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2955                         kvm_queue_exception(vcpu, DB_VECTOR);
2956                         return 1;
2957                 }
2958         }
2959
2960         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2961         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
2962         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
2963         if (exit_qualification & TYPE_MOV_FROM_DR) {
2964                 switch (dr) {
2965                 case 0 ... 3:
2966                         val = vcpu->arch.db[dr];
2967                         break;
2968                 case 6:
2969                         val = vcpu->arch.dr6;
2970                         break;
2971                 case 7:
2972                         val = vcpu->arch.dr7;
2973                         break;
2974                 default:
2975                         val = 0;
2976                 }
2977                 kvm_register_write(vcpu, reg, val);
2978         } else {
2979                 val = vcpu->arch.regs[reg];
2980                 switch (dr) {
2981                 case 0 ... 3:
2982                         vcpu->arch.db[dr] = val;
2983                         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
2984                                 vcpu->arch.eff_db[dr] = val;
2985                         break;
2986                 case 4 ... 5:
2987                         if (vcpu->arch.cr4 & X86_CR4_DE)
2988                                 kvm_queue_exception(vcpu, UD_VECTOR);
2989                         break;
2990                 case 6:
2991                         if (val & 0xffffffff00000000ULL) {
2992                                 kvm_queue_exception(vcpu, GP_VECTOR);
2993                                 break;
2994                         }
2995                         vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
2996                         break;
2997                 case 7:
2998                         if (val & 0xffffffff00000000ULL) {
2999                                 kvm_queue_exception(vcpu, GP_VECTOR);
3000                                 break;
3001                         }
3002                         vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
3003                         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
3004                                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3005                                 vcpu->arch.switch_db_regs =
3006                                         (val & DR7_BP_EN_MASK);
3007                         }
3008                         break;
3009                 }
3010         }
3011         skip_emulated_instruction(vcpu);
3012         return 1;
3013 }
3014
3015 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3016 {
3017         kvm_emulate_cpuid(vcpu);
3018         return 1;
3019 }
3020
3021 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3022 {
3023         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3024         u64 data;
3025
3026         if (vmx_get_msr(vcpu, ecx, &data)) {
3027                 kvm_inject_gp(vcpu, 0);
3028                 return 1;
3029         }
3030
3031         trace_kvm_msr_read(ecx, data);
3032
3033         /* FIXME: handling of bits 32:63 of rax, rdx */
3034         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3035         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3036         skip_emulated_instruction(vcpu);
3037         return 1;
3038 }
3039
3040 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3041 {
3042         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3043         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3044                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3045
3046         trace_kvm_msr_write(ecx, data);
3047
3048         if (vmx_set_msr(vcpu, ecx, data) != 0) {
3049                 kvm_inject_gp(vcpu, 0);
3050                 return 1;
3051         }
3052
3053         skip_emulated_instruction(vcpu);
3054         return 1;
3055 }
3056
3057 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
3058                                       struct kvm_run *kvm_run)
3059 {
3060         return 1;
3061 }
3062
3063 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
3064                                    struct kvm_run *kvm_run)
3065 {
3066         u32 cpu_based_vm_exec_control;
3067
3068         /* clear pending irq */
3069         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3070         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3071         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3072
3073         ++vcpu->stat.irq_window_exits;
3074
3075         /*
3076          * If the user space waits to inject interrupts, exit as soon as
3077          * possible
3078          */
3079         if (!irqchip_in_kernel(vcpu->kvm) &&
3080             kvm_run->request_interrupt_window &&
3081             !kvm_cpu_has_interrupt(vcpu)) {
3082                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3083                 return 0;
3084         }
3085         return 1;
3086 }
3087
3088 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3089 {
3090         skip_emulated_instruction(vcpu);
3091         return kvm_emulate_halt(vcpu);
3092 }
3093
3094 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3095 {
3096         skip_emulated_instruction(vcpu);
3097         kvm_emulate_hypercall(vcpu);
3098         return 1;
3099 }
3100
3101 static int handle_vmx_insn(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3102 {
3103         kvm_queue_exception(vcpu, UD_VECTOR);
3104         return 1;
3105 }
3106
3107 static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3108 {
3109         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3110
3111         kvm_mmu_invlpg(vcpu, exit_qualification);
3112         skip_emulated_instruction(vcpu);
3113         return 1;
3114 }
3115
3116 static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3117 {
3118         skip_emulated_instruction(vcpu);
3119         /* TODO: Add support for VT-d/pass-through device */
3120         return 1;
3121 }
3122
3123 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3124 {
3125         unsigned long exit_qualification;
3126         enum emulation_result er;
3127         unsigned long offset;
3128
3129         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3130         offset = exit_qualification & 0xffful;
3131
3132         er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3133
3134         if (er !=  EMULATE_DONE) {
3135                 printk(KERN_ERR
3136                        "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3137                        offset);
3138                 return -ENOEXEC;
3139         }
3140         return 1;
3141 }
3142
3143 static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3144 {
3145         struct vcpu_vmx *vmx = to_vmx(vcpu);
3146         unsigned long exit_qualification;
3147         u16 tss_selector;
3148         int reason, type, idt_v;
3149
3150         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3151         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3152
3153         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3154
3155         reason = (u32)exit_qualification >> 30;
3156         if (reason == TASK_SWITCH_GATE && idt_v) {
3157                 switch (type) {
3158                 case INTR_TYPE_NMI_INTR:
3159                         vcpu->arch.nmi_injected = false;
3160                         if (cpu_has_virtual_nmis())
3161                                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3162                                               GUEST_INTR_STATE_NMI);
3163                         break;
3164                 case INTR_TYPE_EXT_INTR:
3165                 case INTR_TYPE_SOFT_INTR:
3166                         kvm_clear_interrupt_queue(vcpu);
3167                         break;
3168                 case INTR_TYPE_HARD_EXCEPTION:
3169                 case INTR_TYPE_SOFT_EXCEPTION:
3170                         kvm_clear_exception_queue(vcpu);
3171                         break;
3172                 default:
3173                         break;
3174                 }
3175         }
3176         tss_selector = exit_qualification;
3177
3178         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3179                        type != INTR_TYPE_EXT_INTR &&
3180                        type != INTR_TYPE_NMI_INTR))
3181                 skip_emulated_instruction(vcpu);
3182
3183         if (!kvm_task_switch(vcpu, tss_selector, reason))
3184                 return 0;
3185
3186         /* clear all local breakpoint enable flags */
3187         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3188
3189         /*
3190          * TODO: What about debug traps on tss switch?
3191          *       Are we supposed to inject them and update dr6?
3192          */
3193
3194         return 1;
3195 }
3196
3197 static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3198 {
3199         unsigned long exit_qualification;
3200         gpa_t gpa;
3201         int gla_validity;
3202
3203         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3204
3205         if (exit_qualification & (1 << 6)) {
3206                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3207                 return -EINVAL;
3208         }
3209
3210         gla_validity = (exit_qualification >> 7) & 0x3;
3211         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3212                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3213                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3214                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3215                         vmcs_readl(GUEST_LINEAR_ADDRESS));
3216                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3217                         (long unsigned int)exit_qualification);
3218                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3219                 kvm_run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3220                 return 0;
3221         }
3222
3223         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3224         trace_kvm_page_fault(gpa, exit_qualification);
3225         return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3226 }
3227
3228 static u64 ept_rsvd_mask(u64 spte, int level)
3229 {
3230         int i;
3231         u64 mask = 0;
3232
3233         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3234                 mask |= (1ULL << i);
3235
3236         if (level > 2)
3237                 /* bits 7:3 reserved */
3238                 mask |= 0xf8;
3239         else if (level == 2) {
3240                 if (spte & (1ULL << 7))
3241                         /* 2MB ref, bits 20:12 reserved */
3242                         mask |= 0x1ff000;
3243                 else
3244                         /* bits 6:3 reserved */
3245                         mask |= 0x78;
3246         }
3247
3248         return mask;
3249 }
3250
3251 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3252                                        int level)
3253 {
3254         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3255
3256         /* 010b (write-only) */
3257         WARN_ON((spte & 0x7) == 0x2);
3258
3259         /* 110b (write/execute) */
3260         WARN_ON((spte & 0x7) == 0x6);
3261
3262         /* 100b (execute-only) and value not supported by logical processor */
3263         if (!cpu_has_vmx_ept_execute_only())
3264                 WARN_ON((spte & 0x7) == 0x4);
3265
3266         /* not 000b */
3267         if ((spte & 0x7)) {
3268                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3269
3270                 if (rsvd_bits != 0) {
3271                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3272                                          __func__, rsvd_bits);
3273                         WARN_ON(1);
3274                 }
3275
3276                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3277                         u64 ept_mem_type = (spte & 0x38) >> 3;
3278
3279                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
3280                             ept_mem_type == 7) {
3281                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3282                                                 __func__, ept_mem_type);
3283                                 WARN_ON(1);
3284                         }
3285                 }
3286         }
3287 }
3288
3289 static int handle_ept_misconfig(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3290 {
3291         u64 sptes[4];
3292         int nr_sptes, i;
3293         gpa_t gpa;
3294
3295         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3296
3297         printk(KERN_ERR "EPT: Misconfiguration.\n");
3298         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3299
3300         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3301
3302         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3303                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3304
3305         kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3306         kvm_run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3307
3308         return 0;
3309 }
3310
3311 static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3312 {
3313         u32 cpu_based_vm_exec_control;
3314
3315         /* clear pending NMI */
3316         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3317         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3318         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3319         ++vcpu->stat.nmi_window_exits;
3320
3321         return 1;
3322 }
3323
3324 static void handle_invalid_guest_state(struct kvm_vcpu *vcpu,
3325                                 struct kvm_run *kvm_run)
3326 {
3327         struct vcpu_vmx *vmx = to_vmx(vcpu);
3328         enum emulation_result err = EMULATE_DONE;
3329
3330         local_irq_enable();
3331         preempt_enable();
3332
3333         while (!guest_state_valid(vcpu)) {
3334                 err = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3335
3336                 if (err == EMULATE_DO_MMIO)
3337                         break;
3338
3339                 if (err != EMULATE_DONE) {
3340                         kvm_report_emulation_failure(vcpu, "emulation failure");
3341                         break;
3342                 }
3343
3344                 if (signal_pending(current))
3345                         break;
3346                 if (need_resched())
3347                         schedule();
3348         }
3349
3350         preempt_disable();
3351         local_irq_disable();
3352
3353         vmx->invalid_state_emulation_result = err;
3354 }
3355
3356 /*
3357  * The exit handlers return 1 if the exit was handled fully and guest execution
3358  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
3359  * to be done to userspace and return 0.
3360  */
3361 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
3362                                       struct kvm_run *kvm_run) = {
3363         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
3364         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
3365         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
3366         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
3367         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
3368         [EXIT_REASON_CR_ACCESS]               = handle_cr,
3369         [EXIT_REASON_DR_ACCESS]               = handle_dr,
3370         [EXIT_REASON_CPUID]                   = handle_cpuid,
3371         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
3372         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
3373         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
3374         [EXIT_REASON_HLT]                     = handle_halt,
3375         [EXIT_REASON_INVLPG]                  = handle_invlpg,
3376         [EXIT_REASON_VMCALL]                  = handle_vmcall,
3377         [EXIT_REASON_VMCLEAR]                 = handle_vmx_insn,
3378         [EXIT_REASON_VMLAUNCH]                = handle_vmx_insn,
3379         [EXIT_REASON_VMPTRLD]                 = handle_vmx_insn,
3380         [EXIT_REASON_VMPTRST]                 = handle_vmx_insn,
3381         [EXIT_REASON_VMREAD]                  = handle_vmx_insn,
3382         [EXIT_REASON_VMRESUME]                = handle_vmx_insn,
3383         [EXIT_REASON_VMWRITE]                 = handle_vmx_insn,
3384         [EXIT_REASON_VMOFF]                   = handle_vmx_insn,
3385         [EXIT_REASON_VMON]                    = handle_vmx_insn,
3386         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
3387         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
3388         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
3389         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
3390         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
3391         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
3392         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
3393 };
3394
3395 static const int kvm_vmx_max_exit_handlers =
3396         ARRAY_SIZE(kvm_vmx_exit_handlers);
3397
3398 /*
3399  * The guest has exited.  See if we can fix it or if we need userspace
3400  * assistance.
3401  */
3402 static int vmx_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
3403 {
3404         struct vcpu_vmx *vmx = to_vmx(vcpu);
3405         u32 exit_reason = vmx->exit_reason;
3406         u32 vectoring_info = vmx->idt_vectoring_info;
3407
3408         trace_kvm_exit(exit_reason, kvm_rip_read(vcpu));
3409
3410         /* If we need to emulate an MMIO from handle_invalid_guest_state
3411          * we just return 0 */
3412         if (vmx->emulation_required && emulate_invalid_guest_state) {
3413                 if (guest_state_valid(vcpu))
3414                         vmx->emulation_required = 0;
3415                 return vmx->invalid_state_emulation_result != EMULATE_DO_MMIO;
3416         }
3417
3418         /* Access CR3 don't cause VMExit in paging mode, so we need
3419          * to sync with guest real CR3. */
3420         if (enable_ept && is_paging(vcpu))
3421                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3422
3423         if (unlikely(vmx->fail)) {
3424                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3425                 kvm_run->fail_entry.hardware_entry_failure_reason
3426                         = vmcs_read32(VM_INSTRUCTION_ERROR);
3427                 return 0;
3428         }
3429
3430         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3431                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3432                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
3433                         exit_reason != EXIT_REASON_TASK_SWITCH))
3434                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3435                        "(0x%x) and exit reason is 0x%x\n",
3436                        __func__, vectoring_info, exit_reason);
3437
3438         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3439                 if (vmx_interrupt_allowed(vcpu)) {
3440                         vmx->soft_vnmi_blocked = 0;
3441                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3442                            vcpu->arch.nmi_pending) {
3443                         /*
3444                          * This CPU don't support us in finding the end of an
3445                          * NMI-blocked window if the guest runs with IRQs
3446                          * disabled. So we pull the trigger after 1 s of
3447                          * futile waiting, but inform the user about this.
3448                          */
3449                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3450                                "state on VCPU %d after 1 s timeout\n",
3451                                __func__, vcpu->vcpu_id);
3452                         vmx->soft_vnmi_blocked = 0;
3453                 }
3454         }
3455
3456         if (exit_reason < kvm_vmx_max_exit_handlers
3457             && kvm_vmx_exit_handlers[exit_reason])
3458                 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
3459         else {
3460                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3461                 kvm_run->hw.hardware_exit_reason = exit_reason;
3462         }
3463         return 0;
3464 }
3465
3466 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3467 {
3468         if (irr == -1 || tpr < irr) {
3469                 vmcs_write32(TPR_THRESHOLD, 0);
3470                 return;
3471         }
3472
3473         vmcs_write32(TPR_THRESHOLD, irr);
3474 }
3475
3476 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3477 {
3478         u32 exit_intr_info;
3479         u32 idt_vectoring_info = vmx->idt_vectoring_info;
3480         bool unblock_nmi;
3481         u8 vector;
3482         int type;
3483         bool idtv_info_valid;
3484
3485         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3486
3487         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3488
3489         /* Handle machine checks before interrupts are enabled */
3490         if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3491             || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3492                 && is_machine_check(exit_intr_info)))
3493                 kvm_machine_check();
3494
3495         /* We need to handle NMIs before interrupts are enabled */
3496         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3497             (exit_intr_info & INTR_INFO_VALID_MASK))
3498                 asm("int $2");
3499
3500         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3501
3502         if (cpu_has_virtual_nmis()) {
3503                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3504                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3505                 /*
3506                  * SDM 3: 27.7.1.2 (September 2008)
3507                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
3508                  * a guest IRET fault.
3509                  * SDM 3: 23.2.2 (September 2008)
3510                  * Bit 12 is undefined in any of the following cases:
3511                  *  If the VM exit sets the valid bit in the IDT-vectoring
3512                  *   information field.
3513                  *  If the VM exit is due to a double fault.
3514                  */
3515                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3516                     vector != DF_VECTOR && !idtv_info_valid)
3517                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3518                                       GUEST_INTR_STATE_NMI);
3519         } else if (unlikely(vmx->soft_vnmi_blocked))
3520                 vmx->vnmi_blocked_time +=
3521                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3522
3523         vmx->vcpu.arch.nmi_injected = false;
3524         kvm_clear_exception_queue(&vmx->vcpu);
3525         kvm_clear_interrupt_queue(&vmx->vcpu);
3526
3527         if (!idtv_info_valid)
3528                 return;
3529
3530         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3531         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3532
3533         switch (type) {
3534         case INTR_TYPE_NMI_INTR:
3535                 vmx->vcpu.arch.nmi_injected = true;
3536                 /*
3537                  * SDM 3: 27.7.1.2 (September 2008)
3538                  * Clear bit "block by NMI" before VM entry if a NMI
3539                  * delivery faulted.
3540                  */
3541                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3542                                 GUEST_INTR_STATE_NMI);
3543                 break;
3544         case INTR_TYPE_SOFT_EXCEPTION:
3545                 vmx->vcpu.arch.event_exit_inst_len =
3546                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3547                 /* fall through */
3548         case INTR_TYPE_HARD_EXCEPTION:
3549                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3550                         u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3551                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
3552                 } else
3553                         kvm_queue_exception(&vmx->vcpu, vector);
3554                 break;
3555         case INTR_TYPE_SOFT_INTR:
3556                 vmx->vcpu.arch.event_exit_inst_len =
3557                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3558                 /* fall through */
3559         case INTR_TYPE_EXT_INTR:
3560                 kvm_queue_interrupt(&vmx->vcpu, vector,
3561                         type == INTR_TYPE_SOFT_INTR);
3562                 break;
3563         default:
3564                 break;
3565         }
3566 }
3567
3568 /*
3569  * Failure to inject an interrupt should give us the information
3570  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
3571  * when fetching the interrupt redirection bitmap in the real-mode
3572  * tss, this doesn't happen.  So we do it ourselves.
3573  */
3574 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3575 {
3576         vmx->rmode.irq.pending = 0;
3577         if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3578                 return;
3579         kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3580         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3581                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3582                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3583                 return;
3584         }
3585         vmx->idt_vectoring_info =
3586                 VECTORING_INFO_VALID_MASK
3587                 | INTR_TYPE_EXT_INTR
3588                 | vmx->rmode.irq.vector;
3589 }
3590
3591 #ifdef CONFIG_X86_64
3592 #define R "r"
3593 #define Q "q"
3594 #else
3595 #define R "e"
3596 #define Q "l"
3597 #endif
3598
3599 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3600 {
3601         struct vcpu_vmx *vmx = to_vmx(vcpu);
3602
3603         if (enable_ept && is_paging(vcpu)) {
3604                 vmcs_writel(GUEST_CR3, vcpu->arch.cr3);
3605                 ept_load_pdptrs(vcpu);
3606         }
3607         /* Record the guest's net vcpu time for enforced NMI injections. */
3608         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3609                 vmx->entry_time = ktime_get();
3610
3611         /* Handle invalid guest state instead of entering VMX */
3612         if (vmx->emulation_required && emulate_invalid_guest_state) {
3613                 handle_invalid_guest_state(vcpu, kvm_run);
3614                 return;
3615         }
3616
3617         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3618                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3619         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3620                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3621
3622         /* When single-stepping over STI and MOV SS, we must clear the
3623          * corresponding interruptibility bits in the guest state. Otherwise
3624          * vmentry fails as it then expects bit 14 (BS) in pending debug
3625          * exceptions being set, but that's not correct for the guest debugging
3626          * case. */
3627         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3628                 vmx_set_interrupt_shadow(vcpu, 0);
3629
3630         /*
3631          * Loading guest fpu may have cleared host cr0.ts
3632          */
3633         vmcs_writel(HOST_CR0, read_cr0());
3634
3635         set_debugreg(vcpu->arch.dr6, 6);
3636
3637         asm(
3638                 /* Store host registers */
3639                 "push %%"R"dx; push %%"R"bp;"
3640                 "push %%"R"cx \n\t"
3641                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3642                 "je 1f \n\t"
3643                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3644                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3645                 "1: \n\t"
3646                 /* Reload cr2 if changed */
3647                 "mov %c[cr2](%0), %%"R"ax \n\t"
3648                 "mov %%cr2, %%"R"dx \n\t"
3649                 "cmp %%"R"ax, %%"R"dx \n\t"
3650                 "je 2f \n\t"
3651                 "mov %%"R"ax, %%cr2 \n\t"
3652                 "2: \n\t"
3653                 /* Check if vmlaunch of vmresume is needed */
3654                 "cmpl $0, %c[launched](%0) \n\t"
3655                 /* Load guest registers.  Don't clobber flags. */
3656                 "mov %c[rax](%0), %%"R"ax \n\t"
3657                 "mov %c[rbx](%0), %%"R"bx \n\t"
3658                 "mov %c[rdx](%0), %%"R"dx \n\t"
3659                 "mov %c[rsi](%0), %%"R"si \n\t"
3660                 "mov %c[rdi](%0), %%"R"di \n\t"
3661                 "mov %c[rbp](%0), %%"R"bp \n\t"
3662 #ifdef CONFIG_X86_64
3663                 "mov %c[r8](%0),  %%r8  \n\t"
3664                 "mov %c[r9](%0),  %%r9  \n\t"
3665                 "mov %c[r10](%0), %%r10 \n\t"
3666                 "mov %c[r11](%0), %%r11 \n\t"
3667                 "mov %c[r12](%0), %%r12 \n\t"
3668                 "mov %c[r13](%0), %%r13 \n\t"
3669                 "mov %c[r14](%0), %%r14 \n\t"
3670                 "mov %c[r15](%0), %%r15 \n\t"
3671 #endif
3672                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3673
3674                 /* Enter guest mode */
3675                 "jne .Llaunched \n\t"
3676                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3677                 "jmp .Lkvm_vmx_return \n\t"
3678                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3679                 ".Lkvm_vmx_return: "
3680                 /* Save guest registers, load host registers, keep flags */
3681                 "xchg %0,     (%%"R"sp) \n\t"
3682                 "mov %%"R"ax, %c[rax](%0) \n\t"
3683                 "mov %%"R"bx, %c[rbx](%0) \n\t"
3684                 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3685                 "mov %%"R"dx, %c[rdx](%0) \n\t"
3686                 "mov %%"R"si, %c[rsi](%0) \n\t"
3687                 "mov %%"R"di, %c[rdi](%0) \n\t"
3688                 "mov %%"R"bp, %c[rbp](%0) \n\t"
3689 #ifdef CONFIG_X86_64
3690                 "mov %%r8,  %c[r8](%0) \n\t"
3691                 "mov %%r9,  %c[r9](%0) \n\t"
3692                 "mov %%r10, %c[r10](%0) \n\t"
3693                 "mov %%r11, %c[r11](%0) \n\t"
3694                 "mov %%r12, %c[r12](%0) \n\t"
3695                 "mov %%r13, %c[r13](%0) \n\t"
3696                 "mov %%r14, %c[r14](%0) \n\t"
3697                 "mov %%r15, %c[r15](%0) \n\t"
3698 #endif
3699                 "mov %%cr2, %%"R"ax   \n\t"
3700                 "mov %%"R"ax, %c[cr2](%0) \n\t"
3701
3702                 "pop  %%"R"bp; pop  %%"R"bp; pop  %%"R"dx \n\t"
3703                 "setbe %c[fail](%0) \n\t"
3704               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3705                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3706                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3707                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3708                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3709                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3710                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3711                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3712                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3713                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3714                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3715 #ifdef CONFIG_X86_64
3716                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3717                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3718                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3719                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3720                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3721                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3722                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3723                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3724 #endif
3725                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3726               : "cc", "memory"
3727                 , R"bx", R"di", R"si"
3728 #ifdef CONFIG_X86_64
3729                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3730 #endif
3731               );
3732
3733         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3734                                   | (1 << VCPU_EXREG_PDPTR));
3735         vcpu->arch.regs_dirty = 0;
3736
3737         get_debugreg(vcpu->arch.dr6, 6);
3738
3739         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3740         if (vmx->rmode.irq.pending)
3741                 fixup_rmode_irq(vmx);
3742
3743         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3744         vmx->launched = 1;
3745
3746         vmx_complete_interrupts(vmx);
3747 }
3748
3749 #undef R
3750 #undef Q
3751
3752 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3753 {
3754         struct vcpu_vmx *vmx = to_vmx(vcpu);
3755
3756         if (vmx->vmcs) {
3757                 vcpu_clear(vmx);
3758                 free_vmcs(vmx->vmcs);
3759                 vmx->vmcs = NULL;
3760         }
3761 }
3762
3763 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3764 {
3765         struct vcpu_vmx *vmx = to_vmx(vcpu);
3766
3767         spin_lock(&vmx_vpid_lock);
3768         if (vmx->vpid != 0)
3769                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3770         spin_unlock(&vmx_vpid_lock);
3771         vmx_free_vmcs(vcpu);
3772         kfree(vmx->host_msrs);
3773         kfree(vmx->guest_msrs);
3774         kvm_vcpu_uninit(vcpu);
3775         kmem_cache_free(kvm_vcpu_cache, vmx);
3776 }
3777
3778 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3779 {
3780         int err;
3781         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3782         int cpu;
3783
3784         if (!vmx)
3785                 return ERR_PTR(-ENOMEM);
3786
3787         allocate_vpid(vmx);
3788
3789         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3790         if (err)
3791                 goto free_vcpu;
3792
3793         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3794         if (!vmx->guest_msrs) {
3795                 err = -ENOMEM;
3796                 goto uninit_vcpu;
3797         }
3798
3799         vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3800         if (!vmx->host_msrs)
3801                 goto free_guest_msrs;
3802
3803         vmx->vmcs = alloc_vmcs();
3804         if (!vmx->vmcs)
3805                 goto free_msrs;
3806
3807         vmcs_clear(vmx->vmcs);
3808
3809         cpu = get_cpu();
3810         vmx_vcpu_load(&vmx->vcpu, cpu);
3811         err = vmx_vcpu_setup(vmx);
3812         vmx_vcpu_put(&vmx->vcpu);
3813         put_cpu();
3814         if (err)
3815                 goto free_vmcs;
3816         if (vm_need_virtualize_apic_accesses(kvm))
3817                 if (alloc_apic_access_page(kvm) != 0)
3818                         goto free_vmcs;
3819
3820         if (enable_ept) {
3821                 if (!kvm->arch.ept_identity_map_addr)
3822                         kvm->arch.ept_identity_map_addr =
3823                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3824                 if (alloc_identity_pagetable(kvm) != 0)
3825                         goto free_vmcs;
3826         }
3827
3828         return &vmx->vcpu;
3829
3830 free_vmcs:
3831         free_vmcs(vmx->vmcs);
3832 free_msrs:
3833         kfree(vmx->host_msrs);
3834 free_guest_msrs:
3835         kfree(vmx->guest_msrs);
3836 uninit_vcpu:
3837         kvm_vcpu_uninit(&vmx->vcpu);
3838 free_vcpu:
3839         kmem_cache_free(kvm_vcpu_cache, vmx);
3840         return ERR_PTR(err);
3841 }
3842
3843 static void __init vmx_check_processor_compat(void *rtn)
3844 {
3845         struct vmcs_config vmcs_conf;
3846
3847         *(int *)rtn = 0;
3848         if (setup_vmcs_config(&vmcs_conf) < 0)
3849                 *(int *)rtn = -EIO;
3850         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3851                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3852                                 smp_processor_id());
3853                 *(int *)rtn = -EIO;
3854         }
3855 }
3856
3857 static int get_ept_level(void)
3858 {
3859         return VMX_EPT_DEFAULT_GAW + 1;
3860 }
3861
3862 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3863 {
3864         u64 ret;
3865
3866         /* For VT-d and EPT combination
3867          * 1. MMIO: always map as UC
3868          * 2. EPT with VT-d:
3869          *   a. VT-d without snooping control feature: can't guarantee the
3870          *      result, try to trust guest.
3871          *   b. VT-d with snooping control feature: snooping control feature of
3872          *      VT-d engine can guarantee the cache correctness. Just set it
3873          *      to WB to keep consistent with host. So the same as item 3.
3874          * 3. EPT without VT-d: always map as WB and set IGMT=1 to keep
3875          *    consistent with host MTRR
3876          */
3877         if (is_mmio)
3878                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
3879         else if (vcpu->kvm->arch.iommu_domain &&
3880                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
3881                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
3882                       VMX_EPT_MT_EPTE_SHIFT;
3883         else
3884                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
3885                         | VMX_EPT_IGMT_BIT;
3886
3887         return ret;
3888 }
3889
3890 static const struct trace_print_flags vmx_exit_reasons_str[] = {
3891         { EXIT_REASON_EXCEPTION_NMI,           "exception" },
3892         { EXIT_REASON_EXTERNAL_INTERRUPT,      "ext_irq" },
3893         { EXIT_REASON_TRIPLE_FAULT,            "triple_fault" },
3894         { EXIT_REASON_NMI_WINDOW,              "nmi_window" },
3895         { EXIT_REASON_IO_INSTRUCTION,          "io_instruction" },
3896         { EXIT_REASON_CR_ACCESS,               "cr_access" },
3897         { EXIT_REASON_DR_ACCESS,               "dr_access" },
3898         { EXIT_REASON_CPUID,                   "cpuid" },
3899         { EXIT_REASON_MSR_READ,                "rdmsr" },
3900         { EXIT_REASON_MSR_WRITE,               "wrmsr" },
3901         { EXIT_REASON_PENDING_INTERRUPT,       "interrupt_window" },
3902         { EXIT_REASON_HLT,                     "halt" },
3903         { EXIT_REASON_INVLPG,                  "invlpg" },
3904         { EXIT_REASON_VMCALL,                  "hypercall" },
3905         { EXIT_REASON_TPR_BELOW_THRESHOLD,     "tpr_below_thres" },
3906         { EXIT_REASON_APIC_ACCESS,             "apic_access" },
3907         { EXIT_REASON_WBINVD,                  "wbinvd" },
3908         { EXIT_REASON_TASK_SWITCH,             "task_switch" },
3909         { EXIT_REASON_EPT_VIOLATION,           "ept_violation" },
3910         { -1, NULL }
3911 };
3912
3913 static bool vmx_gb_page_enable(void)
3914 {
3915         return false;
3916 }
3917
3918 static struct kvm_x86_ops vmx_x86_ops = {
3919         .cpu_has_kvm_support = cpu_has_kvm_support,
3920         .disabled_by_bios = vmx_disabled_by_bios,
3921         .hardware_setup = hardware_setup,
3922         .hardware_unsetup = hardware_unsetup,
3923         .check_processor_compatibility = vmx_check_processor_compat,
3924         .hardware_enable = hardware_enable,
3925         .hardware_disable = hardware_disable,
3926         .cpu_has_accelerated_tpr = report_flexpriority,
3927
3928         .vcpu_create = vmx_create_vcpu,
3929         .vcpu_free = vmx_free_vcpu,
3930         .vcpu_reset = vmx_vcpu_reset,
3931
3932         .prepare_guest_switch = vmx_save_host_state,
3933         .vcpu_load = vmx_vcpu_load,
3934         .vcpu_put = vmx_vcpu_put,
3935
3936         .set_guest_debug = set_guest_debug,
3937         .get_msr = vmx_get_msr,
3938         .set_msr = vmx_set_msr,
3939         .get_segment_base = vmx_get_segment_base,
3940         .get_segment = vmx_get_segment,
3941         .set_segment = vmx_set_segment,
3942         .get_cpl = vmx_get_cpl,
3943         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
3944         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
3945         .set_cr0 = vmx_set_cr0,
3946         .set_cr3 = vmx_set_cr3,
3947         .set_cr4 = vmx_set_cr4,
3948         .set_efer = vmx_set_efer,
3949         .get_idt = vmx_get_idt,
3950         .set_idt = vmx_set_idt,
3951         .get_gdt = vmx_get_gdt,
3952         .set_gdt = vmx_set_gdt,
3953         .cache_reg = vmx_cache_reg,
3954         .get_rflags = vmx_get_rflags,
3955         .set_rflags = vmx_set_rflags,
3956
3957         .tlb_flush = vmx_flush_tlb,
3958
3959         .run = vmx_vcpu_run,
3960         .handle_exit = vmx_handle_exit,
3961         .skip_emulated_instruction = skip_emulated_instruction,
3962         .set_interrupt_shadow = vmx_set_interrupt_shadow,
3963         .get_interrupt_shadow = vmx_get_interrupt_shadow,
3964         .patch_hypercall = vmx_patch_hypercall,
3965         .set_irq = vmx_inject_irq,
3966         .set_nmi = vmx_inject_nmi,
3967         .queue_exception = vmx_queue_exception,
3968         .interrupt_allowed = vmx_interrupt_allowed,
3969         .nmi_allowed = vmx_nmi_allowed,
3970         .enable_nmi_window = enable_nmi_window,
3971         .enable_irq_window = enable_irq_window,
3972         .update_cr8_intercept = update_cr8_intercept,
3973
3974         .set_tss_addr = vmx_set_tss_addr,
3975         .get_tdp_level = get_ept_level,
3976         .get_mt_mask = vmx_get_mt_mask,
3977
3978         .exit_reasons_str = vmx_exit_reasons_str,
3979         .gb_page_enable = vmx_gb_page_enable,
3980 };
3981
3982 static int __init vmx_init(void)
3983 {
3984         int r;
3985
3986         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
3987         if (!vmx_io_bitmap_a)
3988                 return -ENOMEM;
3989
3990         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
3991         if (!vmx_io_bitmap_b) {
3992                 r = -ENOMEM;
3993                 goto out;
3994         }
3995
3996         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
3997         if (!vmx_msr_bitmap_legacy) {
3998                 r = -ENOMEM;
3999                 goto out1;
4000         }
4001
4002         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4003         if (!vmx_msr_bitmap_longmode) {
4004                 r = -ENOMEM;
4005                 goto out2;
4006         }
4007
4008         /*
4009          * Allow direct access to the PC debug port (it is often used for I/O
4010          * delays, but the vmexits simply slow things down).
4011          */
4012         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4013         clear_bit(0x80, vmx_io_bitmap_a);
4014
4015         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4016
4017         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4018         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4019
4020         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4021
4022         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
4023         if (r)
4024                 goto out3;
4025
4026         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4027         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4028         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4029         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4030         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4031         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4032
4033         if (enable_ept) {
4034                 bypass_guest_pf = 0;
4035                 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
4036                         VMX_EPT_WRITABLE_MASK);
4037                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4038                                 VMX_EPT_EXECUTABLE_MASK);
4039                 kvm_enable_tdp();
4040         } else
4041                 kvm_disable_tdp();
4042
4043         if (bypass_guest_pf)
4044                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4045
4046         ept_sync_global();
4047
4048         return 0;
4049
4050 out3:
4051         free_page((unsigned long)vmx_msr_bitmap_longmode);
4052 out2:
4053         free_page((unsigned long)vmx_msr_bitmap_legacy);
4054 out1:
4055         free_page((unsigned long)vmx_io_bitmap_b);
4056 out:
4057         free_page((unsigned long)vmx_io_bitmap_a);
4058         return r;
4059 }
4060
4061 static void __exit vmx_exit(void)
4062 {
4063         free_page((unsigned long)vmx_msr_bitmap_legacy);
4064         free_page((unsigned long)vmx_msr_bitmap_longmode);
4065         free_page((unsigned long)vmx_io_bitmap_b);
4066         free_page((unsigned long)vmx_io_bitmap_a);
4067
4068         kvm_exit();
4069 }
4070
4071 module_init(vmx_init)
4072 module_exit(vmx_exit)