2 * Copyright (C) 2015 Broadcom Corporation
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/err.h>
16 #include <linux/clk-provider.h>
19 #include <linux/of_address.h>
21 #include <dt-bindings/clock/bcm-nsp.h>
22 #include "clk-iproc.h"
24 #define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, }
26 #define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
27 .pwr_shift = ps, .iso_shift = is }
29 #define RESET_VAL(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \
30 .reset_shift = rs, .p_reset_shift = prs, .ki_shift = kis, \
31 .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \
34 #define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \
35 .hold_shift = hs, .bypass_shift = bs }
37 static void __init nsp_armpll_init(struct device_node *node)
39 iproc_armpll_setup(node);
41 CLK_OF_DECLARE(nsp_armpll, "brcm,nsp-armpll", nsp_armpll_init);
43 static const struct iproc_pll_ctrl genpll = {
44 .flags = IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_EMBED_PWRCTRL,
45 .aon = AON_VAL(0x0, 1, 12, 0),
46 .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 3),
47 .ndiv_int = REG_VAL(0x14, 20, 10),
48 .ndiv_frac = REG_VAL(0x14, 0, 20),
49 .pdiv = REG_VAL(0x18, 24, 3),
50 .status = REG_VAL(0x20, 12, 1),
53 static const struct iproc_clk_ctrl genpll_clk[] = {
54 [BCM_NSP_GENPLL_PHY_CLK] = {
55 .channel = BCM_NSP_GENPLL_PHY_CLK,
56 .flags = IPROC_CLK_AON,
57 .enable = ENABLE_VAL(0x4, 12, 6, 18),
58 .mdiv = REG_VAL(0x18, 16, 8),
60 [BCM_NSP_GENPLL_ENET_SW_CLK] = {
61 .channel = BCM_NSP_GENPLL_ENET_SW_CLK,
62 .flags = IPROC_CLK_AON,
63 .enable = ENABLE_VAL(0x4, 13, 7, 19),
64 .mdiv = REG_VAL(0x18, 8, 8),
66 [BCM_NSP_GENPLL_USB_PHY_REF_CLK] = {
67 .channel = BCM_NSP_GENPLL_USB_PHY_REF_CLK,
68 .flags = IPROC_CLK_AON,
69 .enable = ENABLE_VAL(0x4, 14, 8, 20),
70 .mdiv = REG_VAL(0x18, 0, 8),
72 [BCM_NSP_GENPLL_IPROCFAST_CLK] = {
73 .channel = BCM_NSP_GENPLL_IPROCFAST_CLK,
74 .flags = IPROC_CLK_AON,
75 .enable = ENABLE_VAL(0x4, 15, 9, 21),
76 .mdiv = REG_VAL(0x1c, 16, 8),
78 [BCM_NSP_GENPLL_SATA1_CLK] = {
79 .channel = BCM_NSP_GENPLL_SATA1_CLK,
80 .flags = IPROC_CLK_AON,
81 .enable = ENABLE_VAL(0x4, 16, 10, 22),
82 .mdiv = REG_VAL(0x1c, 8, 8),
84 [BCM_NSP_GENPLL_SATA2_CLK] = {
85 .channel = BCM_NSP_GENPLL_SATA2_CLK,
86 .flags = IPROC_CLK_AON,
87 .enable = ENABLE_VAL(0x4, 17, 11, 23),
88 .mdiv = REG_VAL(0x1c, 0, 8),
92 static void __init nsp_genpll_clk_init(struct device_node *node)
94 iproc_pll_clk_setup(node, &genpll, NULL, 0, genpll_clk,
95 ARRAY_SIZE(genpll_clk));
97 CLK_OF_DECLARE(nsp_genpll_clk, "brcm,nsp-genpll", nsp_genpll_clk_init);
99 static const struct iproc_pll_ctrl lcpll0 = {
100 .flags = IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_EMBED_PWRCTRL,
101 .aon = AON_VAL(0x0, 1, 24, 0),
102 .reset = RESET_VAL(0x0, 23, 22, 16, 3, 12, 4, 19, 4),
103 .ndiv_int = REG_VAL(0x4, 20, 8),
104 .ndiv_frac = REG_VAL(0x4, 0, 20),
105 .pdiv = REG_VAL(0x4, 28, 3),
106 .status = REG_VAL(0x10, 12, 1),
109 static const struct iproc_clk_ctrl lcpll0_clk[] = {
110 [BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK] = {
111 .channel = BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK,
112 .flags = IPROC_CLK_AON,
113 .enable = ENABLE_VAL(0x0, 6, 3, 9),
114 .mdiv = REG_VAL(0x8, 24, 8),
116 [BCM_NSP_LCPLL0_SDIO_CLK] = {
117 .channel = BCM_NSP_LCPLL0_SDIO_CLK,
118 .flags = IPROC_CLK_AON,
119 .enable = ENABLE_VAL(0x0, 7, 4, 10),
120 .mdiv = REG_VAL(0x8, 16, 8),
122 [BCM_NSP_LCPLL0_DDR_PHY_CLK] = {
123 .channel = BCM_NSP_LCPLL0_DDR_PHY_CLK,
124 .flags = IPROC_CLK_AON,
125 .enable = ENABLE_VAL(0x0, 8, 5, 11),
126 .mdiv = REG_VAL(0x8, 8, 8),
130 static void __init nsp_lcpll0_clk_init(struct device_node *node)
132 iproc_pll_clk_setup(node, &lcpll0, NULL, 0, lcpll0_clk,
133 ARRAY_SIZE(lcpll0_clk));
135 CLK_OF_DECLARE(nsp_lcpll0_clk, "brcm,nsp-lcpll0", nsp_lcpll0_clk_init);