2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: James Liao <jamesjj.liao@mediatek.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #ifndef __DRV_CLK_MTK_H
16 #define __DRV_CLK_MTK_H
18 #include <linux/regmap.h>
19 #include <linux/bitops.h>
20 #include <linux/clk-provider.h>
24 #define MAX_MUX_GATE_BIT 31
25 #define INVALID_MUX_GATE_BIT (MAX_MUX_GATE_BIT + 1)
27 #define MHZ (1000 * 1000)
29 struct mtk_fixed_clk {
36 #define FIXED_CLK(_id, _name, _parent, _rate) { \
43 void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks,
44 int num, struct clk_onecell_data *clk_data);
46 struct mtk_fixed_factor {
49 const char *parent_name;
54 #define FACTOR(_id, _name, _parent, _mult, _div) { \
57 .parent_name = _parent, \
62 void mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
63 int num, struct clk_onecell_data *clk_data);
65 struct mtk_composite {
68 const char * const *parent_names;
76 signed char mux_shift;
77 signed char mux_width;
78 signed char gate_shift;
80 signed char divider_shift;
81 signed char divider_width;
83 signed char num_parents;
87 * In case the rate change propagation to parent clocks is undesirable,
88 * this macro allows to specify the clock flags manually.
90 #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) { \
94 .mux_shift = _shift, \
95 .mux_width = _width, \
97 .gate_shift = _gate, \
98 .divider_shift = -1, \
99 .parent_names = _parents, \
100 .num_parents = ARRAY_SIZE(_parents), \
105 * Unless necessary, all MUX_GATE clocks propagate rate changes to their
106 * parent clock by default.
108 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \
109 MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, _gate, CLK_SET_RATE_PARENT)
111 #define MUX(_id, _name, _parents, _reg, _shift, _width) { \
115 .mux_shift = _shift, \
116 .mux_width = _width, \
118 .divider_shift = -1, \
119 .parent_names = _parents, \
120 .num_parents = ARRAY_SIZE(_parents), \
121 .flags = CLK_SET_RATE_PARENT, \
124 #define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, _div_width, _div_shift) { \
128 .divider_reg = _div_reg, \
129 .divider_shift = _div_shift, \
130 .divider_width = _div_width, \
131 .gate_reg = _gate_reg, \
132 .gate_shift = _gate_shift, \
137 struct clk *mtk_clk_register_composite(const struct mtk_composite *mc,
138 void __iomem *base, spinlock_t *lock);
140 void mtk_clk_register_composites(const struct mtk_composite *mcs,
141 int num, void __iomem *base, spinlock_t *lock,
142 struct clk_onecell_data *clk_data);
144 struct mtk_gate_regs {
153 const char *parent_name;
154 const struct mtk_gate_regs *regs;
156 const struct clk_ops *ops;
159 int mtk_clk_register_gates(struct device_node *node, const struct mtk_gate *clks,
160 int num, struct clk_onecell_data *clk_data);
162 struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num);
164 #define HAVE_RST_BAR BIT(0)
166 struct mtk_pll_div_table {
171 struct mtk_pll_data {
181 const struct clk_ops *ops;
187 const struct mtk_pll_div_table *div_table;
190 void mtk_clk_register_plls(struct device_node *node,
191 const struct mtk_pll_data *plls, int num_plls,
192 struct clk_onecell_data *clk_data);
194 struct clk *mtk_clk_register_ref2usb_tx(const char *name,
195 const char *parent_name, void __iomem *reg);
197 #ifdef CONFIG_RESET_CONTROLLER
198 void mtk_register_reset_controller(struct device_node *np,
199 unsigned int num_regs, int regofs);
201 static inline void mtk_register_reset_controller(struct device_node *np,
202 unsigned int num_regs, int regofs)
207 #endif /* __DRV_CLK_MTK_H */