2 * Copyright (c) 2015 Endless Mobile, Inc.
3 * Author: Carlo Caione <carlo@endlessm.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/clk.h>
19 #include <linux/clk-provider.h>
20 #include <linux/kernel.h>
22 #include <linux/of_address.h>
23 #include <linux/slab.h>
24 #include <dt-bindings/clock/meson8b-clkc.h>
29 * Clock controller register offsets
31 * Register offsets from the HardKernel[0] data sheet are listed in comment
32 * blocks below. Those offsets must be multiplied by 4 before adding them to
33 * the base address to get the right value
35 * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
37 #define MESON8B_REG_SYS_CPU_CNTL1 0x015c /* 0x57 offset in data sheet */
38 #define MESON8B_REG_HHI_MPEG 0x0174 /* 0x5d offset in data sheet */
39 #define MESON8B_REG_MALI 0x01b0 /* 0x6c offset in data sheet */
40 #define MESON8B_REG_PLL_FIXED 0x0280
41 #define MESON8B_REG_PLL_SYS 0x0300
42 #define MESON8B_REG_PLL_VID 0x0320
44 static const struct pll_rate_table sys_pll_rate_table[] = {
45 PLL_RATE(312000000, 52, 1, 2),
46 PLL_RATE(336000000, 56, 1, 2),
47 PLL_RATE(360000000, 60, 1, 2),
48 PLL_RATE(384000000, 64, 1, 2),
49 PLL_RATE(408000000, 68, 1, 2),
50 PLL_RATE(432000000, 72, 1, 2),
51 PLL_RATE(456000000, 76, 1, 2),
52 PLL_RATE(480000000, 80, 1, 2),
53 PLL_RATE(504000000, 84, 1, 2),
54 PLL_RATE(528000000, 88, 1, 2),
55 PLL_RATE(552000000, 92, 1, 2),
56 PLL_RATE(576000000, 96, 1, 2),
57 PLL_RATE(600000000, 50, 1, 1),
58 PLL_RATE(624000000, 52, 1, 1),
59 PLL_RATE(648000000, 54, 1, 1),
60 PLL_RATE(672000000, 56, 1, 1),
61 PLL_RATE(696000000, 58, 1, 1),
62 PLL_RATE(720000000, 60, 1, 1),
63 PLL_RATE(744000000, 62, 1, 1),
64 PLL_RATE(768000000, 64, 1, 1),
65 PLL_RATE(792000000, 66, 1, 1),
66 PLL_RATE(816000000, 68, 1, 1),
67 PLL_RATE(840000000, 70, 1, 1),
68 PLL_RATE(864000000, 72, 1, 1),
69 PLL_RATE(888000000, 74, 1, 1),
70 PLL_RATE(912000000, 76, 1, 1),
71 PLL_RATE(936000000, 78, 1, 1),
72 PLL_RATE(960000000, 80, 1, 1),
73 PLL_RATE(984000000, 82, 1, 1),
74 PLL_RATE(1008000000, 84, 1, 1),
75 PLL_RATE(1032000000, 86, 1, 1),
76 PLL_RATE(1056000000, 88, 1, 1),
77 PLL_RATE(1080000000, 90, 1, 1),
78 PLL_RATE(1104000000, 92, 1, 1),
79 PLL_RATE(1128000000, 94, 1, 1),
80 PLL_RATE(1152000000, 96, 1, 1),
81 PLL_RATE(1176000000, 98, 1, 1),
82 PLL_RATE(1200000000, 50, 1, 0),
83 PLL_RATE(1224000000, 51, 1, 0),
84 PLL_RATE(1248000000, 52, 1, 0),
85 PLL_RATE(1272000000, 53, 1, 0),
86 PLL_RATE(1296000000, 54, 1, 0),
87 PLL_RATE(1320000000, 55, 1, 0),
88 PLL_RATE(1344000000, 56, 1, 0),
89 PLL_RATE(1368000000, 57, 1, 0),
90 PLL_RATE(1392000000, 58, 1, 0),
91 PLL_RATE(1416000000, 59, 1, 0),
92 PLL_RATE(1440000000, 60, 1, 0),
93 PLL_RATE(1464000000, 61, 1, 0),
94 PLL_RATE(1488000000, 62, 1, 0),
95 PLL_RATE(1512000000, 63, 1, 0),
96 PLL_RATE(1536000000, 64, 1, 0),
100 static const struct clk_div_table cpu_div_table[] = {
101 { .val = 1, .div = 1 },
102 { .val = 2, .div = 2 },
103 { .val = 3, .div = 3 },
104 { .val = 2, .div = 4 },
105 { .val = 3, .div = 6 },
106 { .val = 4, .div = 8 },
107 { .val = 5, .div = 10 },
108 { .val = 6, .div = 12 },
109 { .val = 7, .div = 14 },
110 { .val = 8, .div = 16 },
114 PNAME(p_clk81) = { "fclk_div3", "fclk_div4", "fclk_div5" };
115 PNAME(p_mali) = { "fclk_div3", "fclk_div4", "fclk_div5",
116 "fclk_div7", "zero" };
118 static u32 mux_table_clk81[] = { 6, 5, 7 };
119 static u32 mux_table_mali[] = { 6, 5, 7, 4, 0 };
121 static const struct composite_conf clk81_conf __initconst = {
122 .mux_table = mux_table_clk81,
123 .mux_flags = CLK_MUX_READ_ONLY,
124 .mux_parm = PARM(0x00, 12, 3),
125 .div_parm = PARM(0x00, 0, 7),
126 .gate_parm = PARM(0x00, 7, 1),
129 static const struct composite_conf mali_conf __initconst = {
130 .mux_table = mux_table_mali,
131 .mux_parm = PARM(0x00, 9, 3),
132 .div_parm = PARM(0x00, 0, 7),
133 .gate_parm = PARM(0x00, 8, 1),
136 static struct clk_fixed_rate meson8b_xtal = {
137 .fixed_rate = 24000000,
138 .hw.init = &(struct clk_init_data){
141 .ops = &clk_fixed_rate_ops,
145 static struct clk_fixed_rate meson8b_zero = {
147 .hw.init = &(struct clk_init_data){
150 .ops = &clk_fixed_rate_ops,
154 static struct meson_clk_pll meson8b_fixed_pll = {
156 .reg_off = MESON8B_REG_PLL_FIXED,
161 .reg_off = MESON8B_REG_PLL_FIXED,
166 .reg_off = MESON8B_REG_PLL_FIXED,
171 .hw.init = &(struct clk_init_data){
173 .ops = &meson_clk_pll_ro_ops,
174 .parent_names = (const char *[]){ "xtal" },
176 .flags = CLK_GET_RATE_NOCACHE,
180 static struct meson_clk_pll meson8b_vid_pll = {
182 .reg_off = MESON8B_REG_PLL_VID,
187 .reg_off = MESON8B_REG_PLL_VID,
192 .reg_off = MESON8B_REG_PLL_VID,
197 .hw.init = &(struct clk_init_data){
199 .ops = &meson_clk_pll_ro_ops,
200 .parent_names = (const char *[]){ "xtal" },
202 .flags = CLK_GET_RATE_NOCACHE,
206 static struct meson_clk_pll meson8b_sys_pll = {
208 .reg_off = MESON8B_REG_PLL_SYS,
213 .reg_off = MESON8B_REG_PLL_SYS,
218 .reg_off = MESON8B_REG_PLL_SYS,
222 .rate_table = sys_pll_rate_table,
223 .rate_count = ARRAY_SIZE(sys_pll_rate_table),
225 .hw.init = &(struct clk_init_data){
227 .ops = &meson_clk_pll_ops,
228 .parent_names = (const char *[]){ "xtal" },
230 .flags = CLK_GET_RATE_NOCACHE,
234 static struct clk_fixed_factor meson8b_fclk_div2 = {
237 .hw.init = &(struct clk_init_data){
239 .ops = &clk_fixed_factor_ops,
240 .parent_names = (const char *[]){ "fixed_pll" },
245 static struct clk_fixed_factor meson8b_fclk_div3 = {
248 .hw.init = &(struct clk_init_data){
250 .ops = &clk_fixed_factor_ops,
251 .parent_names = (const char *[]){ "fixed_pll" },
256 static struct clk_fixed_factor meson8b_fclk_div4 = {
259 .hw.init = &(struct clk_init_data){
261 .ops = &clk_fixed_factor_ops,
262 .parent_names = (const char *[]){ "fixed_pll" },
267 static struct clk_fixed_factor meson8b_fclk_div5 = {
270 .hw.init = &(struct clk_init_data){
272 .ops = &clk_fixed_factor_ops,
273 .parent_names = (const char *[]){ "fixed_pll" },
278 static struct clk_fixed_factor meson8b_fclk_div7 = {
281 .hw.init = &(struct clk_init_data){
283 .ops = &clk_fixed_factor_ops,
284 .parent_names = (const char *[]){ "fixed_pll" },
289 static struct meson_clk_cpu meson8b_cpu_clk = {
290 .reg_off = MESON8B_REG_SYS_CPU_CNTL1,
291 .div_table = cpu_div_table,
292 .clk_nb.notifier_call = meson_clk_cpu_notifier_cb,
293 .hw.init = &(struct clk_init_data){
295 .ops = &meson_clk_cpu_ops,
296 .parent_names = (const char *[]){ "sys_pll" },
301 static const struct clk_conf meson8b_clk_confs[] __initconst = {
302 COMPOSITE(MESON8B_REG_HHI_MPEG, CLKID_CLK81, "clk81", p_clk81,
303 CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED, &clk81_conf),
304 COMPOSITE(MESON8B_REG_MALI, CLKID_MALI, "mali", p_mali,
305 CLK_IGNORE_UNUSED, &mali_conf),
309 * FIXME we cannot register two providers w/o breaking things. Luckily only
310 * clk81 is actually used by any drivers. Convert clk81 to use
311 * clk_hw_onecell_data last and flip the switch to call of_clk_add_hw_provider
312 * instead of of_clk_add_provider in the clk81 conversion patch to keep from
313 * breaking bisect. Then delete this comment ;-)
315 static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
317 [CLKID_XTAL] = &meson8b_xtal.hw,
318 [CLKID_ZERO] = &meson8b_zero.hw,
319 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
320 [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
321 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
322 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
323 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
324 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
325 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
326 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
327 [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
332 static struct meson_clk_pll *const meson8b_clk_plls[] = {
338 static void __init meson8b_clkc_init(struct device_node *np)
340 void __iomem *clk_base;
342 struct clk_hw *parent_hw;
343 struct clk *parent_clk;
345 if (!meson_clk_init(np, CLK_NR_CLKS))
348 /* Generic clocks and PLLs */
349 clk_base = of_iomap(np, 1);
351 pr_err("%s: Unable to map clk base\n", __func__);
355 /* Populate base address for PLLs */
356 for (i = 0; i < ARRAY_SIZE(meson8b_clk_plls); i++)
357 meson8b_clk_plls[i]->base = clk_base;
359 /* Populate the base address for CPU clk */
360 meson8b_cpu_clk.base = clk_base;
364 * CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1
366 for (clkid = CLKID_XTAL; clkid < CLK_NR_CLKS; clkid++) {
367 /* array might be sparse */
368 if (!meson8b_hw_onecell_data.hws[clkid])
371 /* FIXME convert to devm_clk_register */
372 ret = clk_hw_register(NULL, meson8b_hw_onecell_data.hws[clkid]);
378 * Register CPU clk notifier
380 * FIXME this is wrong for a lot of reasons. First, the muxes should be
381 * struct clk_hw objects. Second, we shouldn't program the muxes in
382 * notifier handlers. The tricky programming sequence will be handled
383 * by the forthcoming coordinated clock rates mechanism once that
384 * feature is released.
386 * Furthermore, looking up the parent this way is terrible. At some
387 * point we will stop allocating a default struct clk when registering
388 * a new clk_hw, and this hack will no longer work. Releasing the ccr
389 * feature before that time solves the problem :-)
391 parent_hw = clk_hw_get_parent(&meson8b_cpu_clk.hw);
392 parent_clk = parent_hw->clk;
393 ret = clk_notifier_register(parent_clk, &meson8b_cpu_clk.clk_nb);
395 pr_err("%s: failed to register clock notifier for cpu_clk\n",
397 goto unregister_clk_nb;
400 meson_clk_register_clks(meson8b_clk_confs,
401 ARRAY_SIZE(meson8b_clk_confs),
405 /* FIXME remove after converting to platform_driver/devm_clk_register */
407 clk_notifier_unregister(parent_clk, &meson8b_a5_clk.clk_nb);
409 for (clkid = CLK_NR_CLKS - 1; clkid >= 0; clkid--)
410 clk_hw_unregister(meson8b_hw_onecell_data.hws[clkid]);
412 CLK_OF_DECLARE(meson8b_clock, "amlogic,meson8b-clkc", meson8b_clkc_init);