2 * Marvell Armada CP110 System Controller
4 * Copyright (C) 2016 Marvell
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
14 * CP110 has 5 core clocks:
17 * - PPv2 core (1/3 APLL)
21 * - NAND clock, which is either:
22 * - Equal to the core clock
25 * CP110 has 32 gatable clocks, for the various peripherals in the
26 * IP. They have fairly complicated parent/child relationships.
29 #define pr_fmt(fmt) "cp110-system-controller: " fmt
31 #include <linux/clk-provider.h>
32 #include <linux/mfd/syscon.h>
33 #include <linux/module.h>
35 #include <linux/of_address.h>
36 #include <linux/platform_device.h>
37 #include <linux/regmap.h>
38 #include <linux/slab.h>
40 #define CP110_PM_CLOCK_GATING_REG 0x220
41 #define CP110_NAND_FLASH_CLK_CTRL_REG 0x700
42 #define NF_CLOCK_SEL_400_MASK BIT(0)
46 CP110_CLK_TYPE_GATABLE,
49 #define CP110_MAX_CORE_CLOCKS 5
50 #define CP110_MAX_GATABLE_CLOCKS 32
52 #define CP110_CLK_NUM \
53 (CP110_MAX_CORE_CLOCKS + CP110_MAX_GATABLE_CLOCKS)
55 #define CP110_CORE_APLL 0
56 #define CP110_CORE_PPV2 1
57 #define CP110_CORE_EIP 2
58 #define CP110_CORE_CORE 3
59 #define CP110_CORE_NAND 4
61 /* A number of gatable clocks need special handling */
62 #define CP110_GATE_AUDIO 0
63 #define CP110_GATE_COMM_UNIT 1
64 #define CP110_GATE_NAND 2
65 #define CP110_GATE_PPV2 3
66 #define CP110_GATE_SDIO 4
67 #define CP110_GATE_XOR1 7
68 #define CP110_GATE_XOR0 8
69 #define CP110_GATE_PCIE_X1_0 11
70 #define CP110_GATE_PCIE_X1_1 12
71 #define CP110_GATE_PCIE_X4 13
72 #define CP110_GATE_PCIE_XOR 14
73 #define CP110_GATE_SATA 15
74 #define CP110_GATE_SATA_USB 16
75 #define CP110_GATE_MAIN 17
76 #define CP110_GATE_SDMMC 18
77 #define CP110_GATE_SLOW_IO 21
78 #define CP110_GATE_USB3H0 22
79 #define CP110_GATE_USB3H1 23
80 #define CP110_GATE_USB3DEV 24
81 #define CP110_GATE_EIP150 25
82 #define CP110_GATE_EIP197 26
84 struct cp110_gate_clk {
86 struct regmap *regmap;
90 #define to_cp110_gate_clk(clk) container_of(clk, struct cp110_gate_clk, hw)
92 static int cp110_gate_enable(struct clk_hw *hw)
94 struct cp110_gate_clk *gate = to_cp110_gate_clk(hw);
96 regmap_update_bits(gate->regmap, CP110_PM_CLOCK_GATING_REG,
97 BIT(gate->bit_idx), BIT(gate->bit_idx));
102 static void cp110_gate_disable(struct clk_hw *hw)
104 struct cp110_gate_clk *gate = to_cp110_gate_clk(hw);
106 regmap_update_bits(gate->regmap, CP110_PM_CLOCK_GATING_REG,
107 BIT(gate->bit_idx), 0);
110 static int cp110_gate_is_enabled(struct clk_hw *hw)
112 struct cp110_gate_clk *gate = to_cp110_gate_clk(hw);
115 regmap_read(gate->regmap, CP110_PM_CLOCK_GATING_REG, &val);
117 return val & BIT(gate->bit_idx);
120 static const struct clk_ops cp110_gate_ops = {
121 .enable = cp110_gate_enable,
122 .disable = cp110_gate_disable,
123 .is_enabled = cp110_gate_is_enabled,
126 static struct clk *cp110_register_gate(const char *name,
127 const char *parent_name,
128 struct regmap *regmap, u8 bit_idx)
130 struct cp110_gate_clk *gate;
132 struct clk_init_data init;
134 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
136 return ERR_PTR(-ENOMEM);
138 memset(&init, 0, sizeof(init));
141 init.ops = &cp110_gate_ops;
142 init.parent_names = &parent_name;
143 init.num_parents = 1;
145 gate->regmap = regmap;
146 gate->bit_idx = bit_idx;
147 gate->hw.init = &init;
149 clk = clk_register(NULL, &gate->hw);
156 static void cp110_unregister_gate(struct clk *clk)
160 hw = __clk_get_hw(clk);
165 kfree(to_cp110_gate_clk(hw));
168 static struct clk *cp110_of_clk_get(struct of_phandle_args *clkspec, void *data)
170 struct clk_onecell_data *clk_data = data;
171 unsigned int type = clkspec->args[0];
172 unsigned int idx = clkspec->args[1];
174 if (type == CP110_CLK_TYPE_CORE) {
175 if (idx > CP110_MAX_CORE_CLOCKS)
176 return ERR_PTR(-EINVAL);
177 return clk_data->clks[idx];
178 } else if (type == CP110_CLK_TYPE_GATABLE) {
179 if (idx > CP110_MAX_GATABLE_CLOCKS)
180 return ERR_PTR(-EINVAL);
181 return clk_data->clks[CP110_MAX_CORE_CLOCKS + idx];
184 return ERR_PTR(-EINVAL);
187 static int cp110_syscon_clk_probe(struct platform_device *pdev)
189 struct regmap *regmap;
190 struct device_node *np = pdev->dev.of_node;
191 const char *ppv2_name, *apll_name, *core_name, *eip_name, *nand_name;
192 struct clk_onecell_data *cp110_clk_data;
193 struct clk *clk, **cp110_clks;
197 regmap = syscon_node_to_regmap(np);
199 return PTR_ERR(regmap);
201 ret = regmap_read(regmap, CP110_NAND_FLASH_CLK_CTRL_REG,
206 cp110_clks = devm_kcalloc(&pdev->dev, sizeof(struct clk *),
207 CP110_CLK_NUM, GFP_KERNEL);
211 cp110_clk_data = devm_kzalloc(&pdev->dev,
212 sizeof(*cp110_clk_data),
217 cp110_clk_data->clks = cp110_clks;
218 cp110_clk_data->clk_num = CP110_CLK_NUM;
220 /* Register the APLL which is the root of the clk tree */
221 of_property_read_string_index(np, "core-clock-output-names",
222 CP110_CORE_APLL, &apll_name);
223 clk = clk_register_fixed_rate(NULL, apll_name, NULL, 0,
230 cp110_clks[CP110_CORE_APLL] = clk;
233 of_property_read_string_index(np, "core-clock-output-names",
234 CP110_CORE_PPV2, &ppv2_name);
235 clk = clk_register_fixed_factor(NULL, ppv2_name, apll_name, 0, 1, 3);
241 cp110_clks[CP110_CORE_PPV2] = clk;
243 /* EIP clock is APLL/2 */
244 of_property_read_string_index(np, "core-clock-output-names",
245 CP110_CORE_EIP, &eip_name);
246 clk = clk_register_fixed_factor(NULL, eip_name, apll_name, 0, 1, 2);
252 cp110_clks[CP110_CORE_EIP] = clk;
254 /* Core clock is EIP/2 */
255 of_property_read_string_index(np, "core-clock-output-names",
256 CP110_CORE_CORE, &core_name);
257 clk = clk_register_fixed_factor(NULL, core_name, eip_name, 0, 1, 2);
263 cp110_clks[CP110_CORE_CORE] = clk;
265 /* NAND can be either APLL/2.5 or core clock */
266 of_property_read_string_index(np, "core-clock-output-names",
267 CP110_CORE_NAND, &nand_name);
268 if (nand_clk_ctrl & NF_CLOCK_SEL_400_MASK)
269 clk = clk_register_fixed_factor(NULL, nand_name,
272 clk = clk_register_fixed_factor(NULL, nand_name,
279 cp110_clks[CP110_CORE_NAND] = clk;
281 for (i = 0; i < CP110_MAX_GATABLE_CLOCKS; i++) {
282 const char *parent, *name;
285 ret = of_property_read_string_index(np,
286 "gate-clock-output-names",
288 /* Reached the end of the list? */
292 if (!strcmp(name, "none"))
296 case CP110_GATE_AUDIO:
297 case CP110_GATE_COMM_UNIT:
298 case CP110_GATE_EIP150:
299 case CP110_GATE_EIP197:
300 case CP110_GATE_SLOW_IO:
301 of_property_read_string_index(np,
302 "gate-clock-output-names",
303 CP110_GATE_MAIN, &parent);
305 case CP110_GATE_NAND:
308 case CP110_GATE_PPV2:
311 case CP110_GATE_SDIO:
312 of_property_read_string_index(np,
313 "gate-clock-output-names",
314 CP110_GATE_SDMMC, &parent);
316 case CP110_GATE_XOR1:
317 case CP110_GATE_XOR0:
318 case CP110_GATE_PCIE_X1_0:
319 case CP110_GATE_PCIE_X1_1:
320 case CP110_GATE_PCIE_X4:
321 of_property_read_string_index(np,
322 "gate-clock-output-names",
323 CP110_GATE_PCIE_XOR, &parent);
325 case CP110_GATE_SATA:
326 case CP110_GATE_USB3H0:
327 case CP110_GATE_USB3H1:
328 case CP110_GATE_USB3DEV:
329 of_property_read_string_index(np,
330 "gate-clock-output-names",
331 CP110_GATE_SATA_USB, &parent);
338 clk = cp110_register_gate(name, parent, regmap, i);
344 cp110_clks[CP110_MAX_CORE_CLOCKS + i] = clk;
347 ret = of_clk_add_provider(np, cp110_of_clk_get, cp110_clk_data);
351 platform_set_drvdata(pdev, cp110_clks);
357 for (i = 0; i < CP110_MAX_GATABLE_CLOCKS; i++) {
358 clk = cp110_clks[CP110_MAX_CORE_CLOCKS + i];
361 cp110_unregister_gate(clk);
364 clk_unregister_fixed_factor(cp110_clks[CP110_CORE_NAND]);
366 clk_unregister_fixed_factor(cp110_clks[CP110_CORE_CORE]);
368 clk_unregister_fixed_factor(cp110_clks[CP110_CORE_EIP]);
370 clk_unregister_fixed_factor(cp110_clks[CP110_CORE_PPV2]);
372 clk_unregister_fixed_rate(cp110_clks[CP110_CORE_APLL]);
377 static int cp110_syscon_clk_remove(struct platform_device *pdev)
379 struct clk **cp110_clks = platform_get_drvdata(pdev);
382 of_clk_del_provider(pdev->dev.of_node);
384 for (i = 0; i < CP110_MAX_GATABLE_CLOCKS; i++) {
385 struct clk *clk = cp110_clks[CP110_MAX_CORE_CLOCKS + i];
388 cp110_unregister_gate(clk);
391 clk_unregister_fixed_factor(cp110_clks[CP110_CORE_NAND]);
392 clk_unregister_fixed_factor(cp110_clks[CP110_CORE_CORE]);
393 clk_unregister_fixed_factor(cp110_clks[CP110_CORE_EIP]);
394 clk_unregister_fixed_factor(cp110_clks[CP110_CORE_PPV2]);
395 clk_unregister_fixed_rate(cp110_clks[CP110_CORE_APLL]);
400 static const struct of_device_id cp110_syscon_of_match[] = {
401 { .compatible = "marvell,cp110-system-controller0", },
404 MODULE_DEVICE_TABLE(of, armada8k_pcie_of_match);
406 static struct platform_driver cp110_syscon_driver = {
407 .probe = cp110_syscon_clk_probe,
408 .remove = cp110_syscon_clk_remove,
410 .name = "marvell-cp110-system-controller0",
411 .of_match_table = cp110_syscon_of_match,
415 module_platform_driver(cp110_syscon_driver);
417 MODULE_DESCRIPTION("Marvell CP110 System Controller 0 driver");
418 MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
419 MODULE_LICENSE("GPL");