2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/bug.h>
18 #include <linux/delay.h>
19 #include <linux/export.h>
20 #include <linux/clk-provider.h>
21 #include <linux/regmap.h>
23 #include <asm/div64.h>
27 #define PLL_OUTCTRL BIT(0)
28 #define PLL_BYPASSNL BIT(1)
29 #define PLL_RESET_N BIT(2)
30 #define PLL_LOCK_COUNT_SHIFT 8
31 #define PLL_LOCK_COUNT_MASK 0x3f
32 #define PLL_BIAS_COUNT_SHIFT 14
33 #define PLL_BIAS_COUNT_MASK 0x3f
34 #define PLL_VOTE_FSM_ENA BIT(20)
35 #define PLL_VOTE_FSM_RESET BIT(21)
37 static int clk_pll_enable(struct clk_hw *hw)
39 struct clk_pll *pll = to_clk_pll(hw);
43 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
44 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val);
48 /* Skip if already enabled or in FSM mode */
49 if ((val & mask) == mask || val & PLL_VOTE_FSM_ENA)
52 /* Disable PLL bypass mode. */
53 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL,
59 * H/W requires a 5us delay between disabling the bypass and
60 * de-asserting the reset. Delay 10us just to be safe.
64 /* De-assert active-low PLL reset. */
65 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N,
70 /* Wait until PLL is locked. */
73 /* Enable PLL output. */
74 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL,
82 static void clk_pll_disable(struct clk_hw *hw)
84 struct clk_pll *pll = to_clk_pll(hw);
88 regmap_read(pll->clkr.regmap, pll->mode_reg, &val);
89 /* Skip if in FSM mode */
90 if (val & PLL_VOTE_FSM_ENA)
92 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
93 regmap_update_bits(pll->clkr.regmap, pll->mode_reg, mask, 0);
97 clk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
99 struct clk_pll *pll = to_clk_pll(hw);
104 regmap_read(pll->clkr.regmap, pll->l_reg, &l);
105 regmap_read(pll->clkr.regmap, pll->m_reg, &m);
106 regmap_read(pll->clkr.regmap, pll->n_reg, &n);
112 rate = parent_rate * l;
122 const struct clk_ops clk_pll_ops = {
123 .enable = clk_pll_enable,
124 .disable = clk_pll_disable,
125 .recalc_rate = clk_pll_recalc_rate,
127 EXPORT_SYMBOL_GPL(clk_pll_ops);
129 static int wait_for_pll(struct clk_pll *pll)
134 const char *name = __clk_get_name(pll->clkr.hw.clk);
136 /* Wait for pll to enable. */
137 for (count = 200; count > 0; count--) {
138 ret = regmap_read(pll->clkr.regmap, pll->status_reg, &val);
141 if (val & BIT(pll->status_bit))
146 WARN(1, "%s didn't enable after voting for it!\n", name);
150 static int clk_pll_vote_enable(struct clk_hw *hw)
153 struct clk_pll *p = to_clk_pll(__clk_get_hw(__clk_get_parent(hw->clk)));
155 ret = clk_enable_regmap(hw);
159 return wait_for_pll(p);
162 const struct clk_ops clk_pll_vote_ops = {
163 .enable = clk_pll_vote_enable,
164 .disable = clk_disable_regmap,
166 EXPORT_SYMBOL_GPL(clk_pll_vote_ops);
169 clk_pll_set_fsm_mode(struct clk_pll *pll, struct regmap *regmap)
174 /* De-assert reset to FSM */
175 regmap_update_bits(regmap, pll->mode_reg, PLL_VOTE_FSM_RESET, 0);
177 /* Program bias count and lock count */
178 val = 1 << PLL_BIAS_COUNT_SHIFT;
179 mask = PLL_BIAS_COUNT_MASK << PLL_BIAS_COUNT_SHIFT;
180 mask |= PLL_LOCK_COUNT_MASK << PLL_LOCK_COUNT_SHIFT;
181 regmap_update_bits(regmap, pll->mode_reg, mask, val);
183 /* Enable PLL FSM voting */
184 regmap_update_bits(regmap, pll->mode_reg, PLL_VOTE_FSM_ENA,
188 static void clk_pll_configure(struct clk_pll *pll, struct regmap *regmap,
189 const struct pll_config *config)
194 regmap_write(regmap, pll->l_reg, config->l);
195 regmap_write(regmap, pll->m_reg, config->m);
196 regmap_write(regmap, pll->n_reg, config->n);
198 val = config->vco_val;
199 val |= config->pre_div_val;
200 val |= config->post_div_val;
201 val |= config->mn_ena_mask;
202 val |= config->main_output_mask;
203 val |= config->aux_output_mask;
205 mask = config->vco_mask;
206 mask |= config->pre_div_mask;
207 mask |= config->post_div_mask;
208 mask |= config->mn_ena_mask;
209 mask |= config->main_output_mask;
210 mask |= config->aux_output_mask;
212 regmap_update_bits(regmap, pll->config_reg, mask, val);
215 void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,
216 const struct pll_config *config, bool fsm_mode)
218 clk_pll_configure(pll, regmap, config);
220 clk_pll_set_fsm_mode(pll, regmap);
222 EXPORT_SYMBOL_GPL(clk_pll_configure_sr_hpm_lp);