drivers/clk/qcom/gcc-msm8660.c

   1 /*
   2  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/bitops.h>
  16 #include <linux/err.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/clk-provider.h>
  22 #include <linux/regmap.h>
  23 #include <linux/reset-controller.h>
  24
  25 #include <dt-bindings/clock/qcom,gcc-msm8660.h>
  26 #include <dt-bindings/reset/qcom,gcc-msm8660.h>
  27
  28 #include "common.h"
  29 #include "clk-regmap.h"
  30 #include "clk-pll.h"
  31 #include "clk-rcg.h"
  32 #include "clk-branch.h"
  33 #include "reset.h"
  34
  35 static struct clk_pll pll8 = {
  36         .l_reg = 0x3144,
  37         .m_reg = 0x3148,
  38         .n_reg = 0x314c,
  39         .config_reg = 0x3154,
  40         .mode_reg = 0x3140,
  41         .status_reg = 0x3158,
  42         .status_bit = 16,
  43         .clkr.hw.init = &(struct clk_init_data){
  44                 .name = "pll8",
  45                 .parent_names = (const char *[]){ "pxo" },
  46                 .num_parents = 1,
  47                 .ops = &clk_pll_ops,
  48         },
  49 };
  50
  51 static struct clk_regmap pll8_vote = {
  52         .enable_reg = 0x34c0,
  53         .enable_mask = BIT(8),
  54         .hw.init = &(struct clk_init_data){
  55                 .name = "pll8_vote",
  56                 .parent_names = (const char *[]){ "pll8" },
  57                 .num_parents = 1,
  58                 .ops = &clk_pll_vote_ops,
  59         },
  60 };
  61
  62 #define P_PXO   0
  63 #define P_PLL8  1
  64 #define P_CXO   2
  65
  66 static const u8 gcc_pxo_pll8_map[] = {
  67         [P_PXO]         = 0,
  68         [P_PLL8]        = 3,
  69 };
  70
  71 static const char *gcc_pxo_pll8[] = {
  72         "pxo",
  73         "pll8_vote",
  74 };
  75
  76 static const u8 gcc_pxo_pll8_cxo_map[] = {
  77         [P_PXO]         = 0,
  78         [P_PLL8]        = 3,
  79         [P_CXO]         = 5,
  80 };
  81
  82 static const char *gcc_pxo_pll8_cxo[] = {
  83         "pxo",
  84         "pll8_vote",
  85         "cxo",
  86 };
  87
  88 static struct freq_tbl clk_tbl_gsbi_uart[] = {
  89         {  1843200, P_PLL8, 2,  6, 625 },
  90         {  3686400, P_PLL8, 2, 12, 625 },
  91         {  7372800, P_PLL8, 2, 24, 625 },
  92         { 14745600, P_PLL8, 2, 48, 625 },
  93         { 16000000, P_PLL8, 4,  1,   6 },
  94         { 24000000, P_PLL8, 4,  1,   4 },
  95         { 32000000, P_PLL8, 4,  1,   3 },
  96         { 40000000, P_PLL8, 1,  5,  48 },
  97         { 46400000, P_PLL8, 1, 29, 240 },
  98         { 48000000, P_PLL8, 4,  1,   2 },
  99         { 51200000, P_PLL8, 1,  2,  15 },
 100         { 56000000, P_PLL8, 1,  7,  48 },
 101         { 58982400, P_PLL8, 1, 96, 625 },
 102         { 64000000, P_PLL8, 2,  1,   3 },
 103         { }
 104 };
 105
 106 static struct clk_rcg gsbi1_uart_src = {
 107         .ns_reg = 0x29d4,
 108         .md_reg = 0x29d0,
 109         .mn = {
 110                 .mnctr_en_bit = 8,
 111                 .mnctr_reset_bit = 7,
 112                 .mnctr_mode_shift = 5,
 113                 .n_val_shift = 16,
 114                 .m_val_shift = 16,
 115                 .width = 16,
 116         },
 117         .p = {
 118                 .pre_div_shift = 3,
 119                 .pre_div_width = 2,
 120         },
 121         .s = {
 122                 .src_sel_shift = 0,
 123                 .parent_map = gcc_pxo_pll8_map,
 124         },
 125         .freq_tbl = clk_tbl_gsbi_uart,
 126         .clkr = {
 127                 .enable_reg = 0x29d4,
 128                 .enable_mask = BIT(11),
 129                 .hw.init = &(struct clk_init_data){
 130                         .name = "gsbi1_uart_src",
 131                         .parent_names = gcc_pxo_pll8,
 132                         .num_parents = 2,
 133                         .ops = &clk_rcg_ops,
 134                         .flags = CLK_SET_PARENT_GATE,
 135                 },
 136         },
 137 };
 138
 139 static struct clk_branch gsbi1_uart_clk = {
 140         .halt_reg = 0x2fcc,
 141         .halt_bit = 10,
 142         .clkr = {
 143                 .enable_reg = 0x29d4,
 144                 .enable_mask = BIT(9),
 145                 .hw.init = &(struct clk_init_data){
 146                         .name = "gsbi1_uart_clk",
 147                         .parent_names = (const char *[]){
 148                                 "gsbi1_uart_src",
 149                         },
 150                         .num_parents = 1,
 151                         .ops = &clk_branch_ops,
 152                         .flags = CLK_SET_RATE_PARENT,
 153                 },
 154         },
 155 };
 156
 157 static struct clk_rcg gsbi2_uart_src = {
 158         .ns_reg = 0x29f4,
 159         .md_reg = 0x29f0,
 160         .mn = {
 161                 .mnctr_en_bit = 8,
 162                 .mnctr_reset_bit = 7,
 163                 .mnctr_mode_shift = 5,
 164                 .n_val_shift = 16,
 165                 .m_val_shift = 16,
 166                 .width = 16,
 167         },
 168         .p = {
 169                 .pre_div_shift = 3,
 170                 .pre_div_width = 2,
 171         },
 172         .s = {
 173                 .src_sel_shift = 0,
 174                 .parent_map = gcc_pxo_pll8_map,
 175         },
 176         .freq_tbl = clk_tbl_gsbi_uart,
 177         .clkr = {
 178                 .enable_reg = 0x29f4,
 179                 .enable_mask = BIT(11),
 180                 .hw.init = &(struct clk_init_data){
 181                         .name = "gsbi2_uart_src",
 182                         .parent_names = gcc_pxo_pll8,
 183                         .num_parents = 2,
 184                         .ops = &clk_rcg_ops,
 185                         .flags = CLK_SET_PARENT_GATE,
 186                 },
 187         },
 188 };
 189
 190 static struct clk_branch gsbi2_uart_clk = {
 191         .halt_reg = 0x2fcc,
 192         .halt_bit = 6,
 193         .clkr = {
 194                 .enable_reg = 0x29f4,
 195                 .enable_mask = BIT(9),
 196                 .hw.init = &(struct clk_init_data){
 197                         .name = "gsbi2_uart_clk",
 198                         .parent_names = (const char *[]){
 199                                 "gsbi2_uart_src",
 200                         },
 201                         .num_parents = 1,
 202                         .ops = &clk_branch_ops,
 203                         .flags = CLK_SET_RATE_PARENT,
 204                 },
 205         },
 206 };
 207
 208 static struct clk_rcg gsbi3_uart_src = {
 209         .ns_reg = 0x2a14,
 210         .md_reg = 0x2a10,
 211         .mn = {
 212                 .mnctr_en_bit = 8,
 213                 .mnctr_reset_bit = 7,
 214                 .mnctr_mode_shift = 5,
 215                 .n_val_shift = 16,
 216                 .m_val_shift = 16,
 217                 .width = 16,
 218         },
 219         .p = {
 220                 .pre_div_shift = 3,
 221                 .pre_div_width = 2,
 222         },
 223         .s = {
 224                 .src_sel_shift = 0,
 225                 .parent_map = gcc_pxo_pll8_map,
 226         },
 227         .freq_tbl = clk_tbl_gsbi_uart,
 228         .clkr = {
 229                 .enable_reg = 0x2a14,
 230                 .enable_mask = BIT(11),
 231                 .hw.init = &(struct clk_init_data){
 232                         .name = "gsbi3_uart_src",
 233                         .parent_names = gcc_pxo_pll8,
 234                         .num_parents = 2,
 235                         .ops = &clk_rcg_ops,
 236                         .flags = CLK_SET_PARENT_GATE,
 237                 },
 238         },
 239 };
 240
 241 static struct clk_branch gsbi3_uart_clk = {
 242         .halt_reg = 0x2fcc,
 243         .halt_bit = 2,
 244         .clkr = {
 245                 .enable_reg = 0x2a14,
 246                 .enable_mask = BIT(9),
 247                 .hw.init = &(struct clk_init_data){
 248                         .name = "gsbi3_uart_clk",
 249                         .parent_names = (const char *[]){
 250                                 "gsbi3_uart_src",
 251                         },
 252                         .num_parents = 1,
 253                         .ops = &clk_branch_ops,
 254                         .flags = CLK_SET_RATE_PARENT,
 255                 },
 256         },
 257 };
 258
 259 static struct clk_rcg gsbi4_uart_src = {
 260         .ns_reg = 0x2a34,
 261         .md_reg = 0x2a30,
 262         .mn = {
 263                 .mnctr_en_bit = 8,
 264                 .mnctr_reset_bit = 7,
 265                 .mnctr_mode_shift = 5,
 266                 .n_val_shift = 16,
 267                 .m_val_shift = 16,
 268                 .width = 16,
 269         },
 270         .p = {
 271                 .pre_div_shift = 3,
 272                 .pre_div_width = 2,
 273         },
 274         .s = {
 275                 .src_sel_shift = 0,
 276                 .parent_map = gcc_pxo_pll8_map,
 277         },
 278         .freq_tbl = clk_tbl_gsbi_uart,
 279         .clkr = {
 280                 .enable_reg = 0x2a34,
 281                 .enable_mask = BIT(11),
 282                 .hw.init = &(struct clk_init_data){
 283                         .name = "gsbi4_uart_src",
 284                         .parent_names = gcc_pxo_pll8,
 285                         .num_parents = 2,
 286                         .ops = &clk_rcg_ops,
 287                         .flags = CLK_SET_PARENT_GATE,
 288                 },
 289         },
 290 };
 291
 292 static struct clk_branch gsbi4_uart_clk = {
 293         .halt_reg = 0x2fd0,
 294         .halt_bit = 26,
 295         .clkr = {
 296                 .enable_reg = 0x2a34,
 297                 .enable_mask = BIT(9),
 298                 .hw.init = &(struct clk_init_data){
 299                         .name = "gsbi4_uart_clk",
 300                         .parent_names = (const char *[]){
 301                                 "gsbi4_uart_src",
 302                         },
 303                         .num_parents = 1,
 304                         .ops = &clk_branch_ops,
 305                         .flags = CLK_SET_RATE_PARENT,
 306                 },
 307         },
 308 };
 309
 310 static struct clk_rcg gsbi5_uart_src = {
 311         .ns_reg = 0x2a54,
 312         .md_reg = 0x2a50,
 313         .mn = {
 314                 .mnctr_en_bit = 8,
 315                 .mnctr_reset_bit = 7,
 316                 .mnctr_mode_shift = 5,
 317                 .n_val_shift = 16,
 318                 .m_val_shift = 16,
 319                 .width = 16,
 320         },
 321         .p = {
 322                 .pre_div_shift = 3,
 323                 .pre_div_width = 2,
 324         },
 325         .s = {
 326                 .src_sel_shift = 0,
 327                 .parent_map = gcc_pxo_pll8_map,
 328         },
 329         .freq_tbl = clk_tbl_gsbi_uart,
 330         .clkr = {
 331                 .enable_reg = 0x2a54,
 332                 .enable_mask = BIT(11),
 333                 .hw.init = &(struct clk_init_data){
 334                         .name = "gsbi5_uart_src",
 335                         .parent_names = gcc_pxo_pll8,
 336                         .num_parents = 2,
 337                         .ops = &clk_rcg_ops,
 338                         .flags = CLK_SET_PARENT_GATE,
 339                 },
 340         },
 341 };
 342
 343 static struct clk_branch gsbi5_uart_clk = {
 344         .halt_reg = 0x2fd0,
 345         .halt_bit = 22,
 346         .clkr = {
 347                 .enable_reg = 0x2a54,
 348                 .enable_mask = BIT(9),
 349                 .hw.init = &(struct clk_init_data){
 350                         .name = "gsbi5_uart_clk",
 351                         .parent_names = (const char *[]){
 352                                 "gsbi5_uart_src",
 353                         },
 354                         .num_parents = 1,
 355                         .ops = &clk_branch_ops,
 356                         .flags = CLK_SET_RATE_PARENT,
 357                 },
 358         },
 359 };
 360
 361 static struct clk_rcg gsbi6_uart_src = {
 362         .ns_reg = 0x2a74,
 363         .md_reg = 0x2a70,
 364         .mn = {
 365                 .mnctr_en_bit = 8,
 366                 .mnctr_reset_bit = 7,
 367                 .mnctr_mode_shift = 5,
 368                 .n_val_shift = 16,
 369                 .m_val_shift = 16,
 370                 .width = 16,
 371         },
 372         .p = {
 373                 .pre_div_shift = 3,
 374                 .pre_div_width = 2,
 375         },
 376         .s = {
 377                 .src_sel_shift = 0,
 378                 .parent_map = gcc_pxo_pll8_map,
 379         },
 380         .freq_tbl = clk_tbl_gsbi_uart,
 381         .clkr = {
 382                 .enable_reg = 0x2a74,
 383                 .enable_mask = BIT(11),
 384                 .hw.init = &(struct clk_init_data){
 385                         .name = "gsbi6_uart_src",
 386                         .parent_names = gcc_pxo_pll8,
 387                         .num_parents = 2,
 388                         .ops = &clk_rcg_ops,
 389                         .flags = CLK_SET_PARENT_GATE,
 390                 },
 391         },
 392 };
 393
 394 static struct clk_branch gsbi6_uart_clk = {
 395         .halt_reg = 0x2fd0,
 396         .halt_bit = 18,
 397         .clkr = {
 398                 .enable_reg = 0x2a74,
 399                 .enable_mask = BIT(9),
 400                 .hw.init = &(struct clk_init_data){
 401                         .name = "gsbi6_uart_clk",
 402                         .parent_names = (const char *[]){
 403                                 "gsbi6_uart_src",
 404                         },
 405                         .num_parents = 1,
 406                         .ops = &clk_branch_ops,
 407                         .flags = CLK_SET_RATE_PARENT,
 408                 },
 409         },
 410 };
 411
 412 static struct clk_rcg gsbi7_uart_src = {
 413         .ns_reg = 0x2a94,
 414         .md_reg = 0x2a90,
 415         .mn = {
 416                 .mnctr_en_bit = 8,
 417                 .mnctr_reset_bit = 7,
 418                 .mnctr_mode_shift = 5,
 419                 .n_val_shift = 16,
 420                 .m_val_shift = 16,
 421                 .width = 16,
 422         },
 423         .p = {
 424                 .pre_div_shift = 3,
 425                 .pre_div_width = 2,
 426         },
 427         .s = {
 428                 .src_sel_shift = 0,
 429                 .parent_map = gcc_pxo_pll8_map,
 430         },
 431         .freq_tbl = clk_tbl_gsbi_uart,
 432         .clkr = {
 433                 .enable_reg = 0x2a94,
 434                 .enable_mask = BIT(11),
 435                 .hw.init = &(struct clk_init_data){
 436                         .name = "gsbi7_uart_src",
 437                         .parent_names = gcc_pxo_pll8,
 438                         .num_parents = 2,
 439                         .ops = &clk_rcg_ops,
 440                         .flags = CLK_SET_PARENT_GATE,
 441                 },
 442         },
 443 };
 444
 445 static struct clk_branch gsbi7_uart_clk = {
 446         .halt_reg = 0x2fd0,
 447         .halt_bit = 14,
 448         .clkr = {
 449                 .enable_reg = 0x2a94,
 450                 .enable_mask = BIT(9),
 451                 .hw.init = &(struct clk_init_data){
 452                         .name = "gsbi7_uart_clk",
 453                         .parent_names = (const char *[]){
 454                                 "gsbi7_uart_src",
 455                         },
 456                         .num_parents = 1,
 457                         .ops = &clk_branch_ops,
 458                         .flags = CLK_SET_RATE_PARENT,
 459                 },
 460         },
 461 };
 462
 463 static struct clk_rcg gsbi8_uart_src = {
 464         .ns_reg = 0x2ab4,
 465         .md_reg = 0x2ab0,
 466         .mn = {
 467                 .mnctr_en_bit = 8,
 468                 .mnctr_reset_bit = 7,
 469                 .mnctr_mode_shift = 5,
 470                 .n_val_shift = 16,
 471                 .m_val_shift = 16,
 472                 .width = 16,
 473         },
 474         .p = {
 475                 .pre_div_shift = 3,
 476                 .pre_div_width = 2,
 477         },
 478         .s = {
 479                 .src_sel_shift = 0,
 480                 .parent_map = gcc_pxo_pll8_map,
 481         },
 482         .freq_tbl = clk_tbl_gsbi_uart,
 483         .clkr = {
 484                 .enable_reg = 0x2ab4,
 485                 .enable_mask = BIT(11),
 486                 .hw.init = &(struct clk_init_data){
 487                         .name = "gsbi8_uart_src",
 488                         .parent_names = gcc_pxo_pll8,
 489                         .num_parents = 2,
 490                         .ops = &clk_rcg_ops,
 491                         .flags = CLK_SET_PARENT_GATE,
 492                 },
 493         },
 494 };
 495
 496 static struct clk_branch gsbi8_uart_clk = {
 497         .halt_reg = 0x2fd0,
 498         .halt_bit = 10,
 499         .clkr = {
 500                 .enable_reg = 0x2ab4,
 501                 .enable_mask = BIT(9),
 502                 .hw.init = &(struct clk_init_data){
 503                         .name = "gsbi8_uart_clk",
 504                         .parent_names = (const char *[]){ "gsbi8_uart_src" },
 505                         .num_parents = 1,
 506                         .ops = &clk_branch_ops,
 507                         .flags = CLK_SET_RATE_PARENT,
 508                 },
 509         },
 510 };
 511
 512 static struct clk_rcg gsbi9_uart_src = {
 513         .ns_reg = 0x2ad4,
 514         .md_reg = 0x2ad0,
 515         .mn = {
 516                 .mnctr_en_bit = 8,
 517                 .mnctr_reset_bit = 7,
 518                 .mnctr_mode_shift = 5,
 519                 .n_val_shift = 16,
 520                 .m_val_shift = 16,
 521                 .width = 16,
 522         },
 523         .p = {
 524                 .pre_div_shift = 3,
 525                 .pre_div_width = 2,
 526         },
 527         .s = {
 528                 .src_sel_shift = 0,
 529                 .parent_map = gcc_pxo_pll8_map,
 530         },
 531         .freq_tbl = clk_tbl_gsbi_uart,
 532         .clkr = {
 533                 .enable_reg = 0x2ad4,
 534                 .enable_mask = BIT(11),
 535                 .hw.init = &(struct clk_init_data){
 536                         .name = "gsbi9_uart_src",
 537                         .parent_names = gcc_pxo_pll8,
 538                         .num_parents = 2,
 539                         .ops = &clk_rcg_ops,
 540                         .flags = CLK_SET_PARENT_GATE,
 541                 },
 542         },
 543 };
 544
 545 static struct clk_branch gsbi9_uart_clk = {
 546         .halt_reg = 0x2fd0,
 547         .halt_bit = 6,
 548         .clkr = {
 549                 .enable_reg = 0x2ad4,
 550                 .enable_mask = BIT(9),
 551                 .hw.init = &(struct clk_init_data){
 552                         .name = "gsbi9_uart_clk",
 553                         .parent_names = (const char *[]){ "gsbi9_uart_src" },
 554                         .num_parents = 1,
 555                         .ops = &clk_branch_ops,
 556                         .flags = CLK_SET_RATE_PARENT,
 557                 },
 558         },
 559 };
 560
 561 static struct clk_rcg gsbi10_uart_src = {
 562         .ns_reg = 0x2af4,
 563         .md_reg = 0x2af0,
 564         .mn = {
 565                 .mnctr_en_bit = 8,
 566                 .mnctr_reset_bit = 7,
 567                 .mnctr_mode_shift = 5,
 568                 .n_val_shift = 16,
 569                 .m_val_shift = 16,
 570                 .width = 16,
 571         },
 572         .p = {
 573                 .pre_div_shift = 3,
 574                 .pre_div_width = 2,
 575         },
 576         .s = {
 577                 .src_sel_shift = 0,
 578                 .parent_map = gcc_pxo_pll8_map,
 579         },
 580         .freq_tbl = clk_tbl_gsbi_uart,
 581         .clkr = {
 582                 .enable_reg = 0x2af4,
 583                 .enable_mask = BIT(11),
 584                 .hw.init = &(struct clk_init_data){
 585                         .name = "gsbi10_uart_src",
 586                         .parent_names = gcc_pxo_pll8,
 587                         .num_parents = 2,
 588                         .ops = &clk_rcg_ops,
 589                         .flags = CLK_SET_PARENT_GATE,
 590                 },
 591         },
 592 };
 593
 594 static struct clk_branch gsbi10_uart_clk = {
 595         .halt_reg = 0x2fd0,
 596         .halt_bit = 2,
 597         .clkr = {
 598                 .enable_reg = 0x2af4,
 599                 .enable_mask = BIT(9),
 600                 .hw.init = &(struct clk_init_data){
 601                         .name = "gsbi10_uart_clk",
 602                         .parent_names = (const char *[]){ "gsbi10_uart_src" },
 603                         .num_parents = 1,
 604                         .ops = &clk_branch_ops,
 605                         .flags = CLK_SET_RATE_PARENT,
 606                 },
 607         },
 608 };
 609
 610 static struct clk_rcg gsbi11_uart_src = {
 611         .ns_reg = 0x2b14,
 612         .md_reg = 0x2b10,
 613         .mn = {
 614                 .mnctr_en_bit = 8,
 615                 .mnctr_reset_bit = 7,
 616                 .mnctr_mode_shift = 5,
 617                 .n_val_shift = 16,
 618                 .m_val_shift = 16,
 619                 .width = 16,
 620         },
 621         .p = {
 622                 .pre_div_shift = 3,
 623                 .pre_div_width = 2,
 624         },
 625         .s = {
 626                 .src_sel_shift = 0,
 627                 .parent_map = gcc_pxo_pll8_map,
 628         },
 629         .freq_tbl = clk_tbl_gsbi_uart,
 630         .clkr = {
 631                 .enable_reg = 0x2b14,
 632                 .enable_mask = BIT(11),
 633                 .hw.init = &(struct clk_init_data){
 634                         .name = "gsbi11_uart_src",
 635                         .parent_names = gcc_pxo_pll8,
 636                         .num_parents = 2,
 637                         .ops = &clk_rcg_ops,
 638                         .flags = CLK_SET_PARENT_GATE,
 639                 },
 640         },
 641 };
 642
 643 static struct clk_branch gsbi11_uart_clk = {
 644         .halt_reg = 0x2fd4,
 645         .halt_bit = 17,
 646         .clkr = {
 647                 .enable_reg = 0x2b14,
 648                 .enable_mask = BIT(9),
 649                 .hw.init = &(struct clk_init_data){
 650                         .name = "gsbi11_uart_clk",
 651                         .parent_names = (const char *[]){ "gsbi11_uart_src" },
 652                         .num_parents = 1,
 653                         .ops = &clk_branch_ops,
 654                         .flags = CLK_SET_RATE_PARENT,
 655                 },
 656         },
 657 };
 658
 659 static struct clk_rcg gsbi12_uart_src = {
 660         .ns_reg = 0x2b34,
 661         .md_reg = 0x2b30,
 662         .mn = {
 663                 .mnctr_en_bit = 8,
 664                 .mnctr_reset_bit = 7,
 665                 .mnctr_mode_shift = 5,
 666                 .n_val_shift = 16,
 667                 .m_val_shift = 16,
 668                 .width = 16,
 669         },
 670         .p = {
 671                 .pre_div_shift = 3,
 672                 .pre_div_width = 2,
 673         },
 674         .s = {
 675                 .src_sel_shift = 0,
 676                 .parent_map = gcc_pxo_pll8_map,
 677         },
 678         .freq_tbl = clk_tbl_gsbi_uart,
 679         .clkr = {
 680                 .enable_reg = 0x2b34,
 681                 .enable_mask = BIT(11),
 682                 .hw.init = &(struct clk_init_data){
 683                         .name = "gsbi12_uart_src",
 684                         .parent_names = gcc_pxo_pll8,
 685                         .num_parents = 2,
 686                         .ops = &clk_rcg_ops,
 687                         .flags = CLK_SET_PARENT_GATE,
 688                 },
 689         },
 690 };
 691
 692 static struct clk_branch gsbi12_uart_clk = {
 693         .halt_reg = 0x2fd4,
 694         .halt_bit = 13,
 695         .clkr = {
 696                 .enable_reg = 0x2b34,
 697                 .enable_mask = BIT(9),
 698                 .hw.init = &(struct clk_init_data){
 699                         .name = "gsbi12_uart_clk",
 700                         .parent_names = (const char *[]){ "gsbi12_uart_src" },
 701                         .num_parents = 1,
 702                         .ops = &clk_branch_ops,
 703                         .flags = CLK_SET_RATE_PARENT,
 704                 },
 705         },
 706 };
 707
 708 static struct freq_tbl clk_tbl_gsbi_qup[] = {
 709         {  1100000, P_PXO,  1, 2, 49 },
 710         {  5400000, P_PXO,  1, 1,  5 },
 711         { 10800000, P_PXO,  1, 2,  5 },
 712         { 15060000, P_PLL8, 1, 2, 51 },
 713         { 24000000, P_PLL8, 4, 1,  4 },
 714         { 25600000, P_PLL8, 1, 1, 15 },
 715         { 27000000, P_PXO,  1, 0,  0 },
 716         { 48000000, P_PLL8, 4, 1,  2 },
 717         { 51200000, P_PLL8, 1, 2, 15 },
 718         { }
 719 };
 720
 721 static struct clk_rcg gsbi1_qup_src = {
 722         .ns_reg = 0x29cc,
 723         .md_reg = 0x29c8,
 724         .mn = {
 725                 .mnctr_en_bit = 8,
 726                 .mnctr_reset_bit = 7,
 727                 .mnctr_mode_shift = 5,
 728                 .n_val_shift = 16,
 729                 .m_val_shift = 16,
 730                 .width = 8,
 731         },
 732         .p = {
 733                 .pre_div_shift = 3,
 734                 .pre_div_width = 2,
 735         },
 736         .s = {
 737                 .src_sel_shift = 0,
 738                 .parent_map = gcc_pxo_pll8_map,
 739         },
 740         .freq_tbl = clk_tbl_gsbi_qup,
 741         .clkr = {
 742                 .enable_reg = 0x29cc,
 743                 .enable_mask = BIT(11),
 744                 .hw.init = &(struct clk_init_data){
 745                         .name = "gsbi1_qup_src",
 746                         .parent_names = gcc_pxo_pll8,
 747                         .num_parents = 2,
 748                         .ops = &clk_rcg_ops,
 749                         .flags = CLK_SET_PARENT_GATE,
 750                 },
 751         },
 752 };
 753
 754 static struct clk_branch gsbi1_qup_clk = {
 755         .halt_reg = 0x2fcc,
 756         .halt_bit = 9,
 757         .clkr = {
 758                 .enable_reg = 0x29cc,
 759                 .enable_mask = BIT(9),
 760                 .hw.init = &(struct clk_init_data){
 761                         .name = "gsbi1_qup_clk",
 762                         .parent_names = (const char *[]){ "gsbi1_qup_src" },
 763                         .num_parents = 1,
 764                         .ops = &clk_branch_ops,
 765                         .flags = CLK_SET_RATE_PARENT,
 766                 },
 767         },
 768 };
 769
 770 static struct clk_rcg gsbi2_qup_src = {
 771         .ns_reg = 0x29ec,
 772         .md_reg = 0x29e8,
 773         .mn = {
 774                 .mnctr_en_bit = 8,
 775                 .mnctr_reset_bit = 7,
 776                 .mnctr_mode_shift = 5,
 777                 .n_val_shift = 16,
 778                 .m_val_shift = 16,
 779                 .width = 8,
 780         },
 781         .p = {
 782                 .pre_div_shift = 3,
 783                 .pre_div_width = 2,
 784         },
 785         .s = {
 786                 .src_sel_shift = 0,
 787                 .parent_map = gcc_pxo_pll8_map,
 788         },
 789         .freq_tbl = clk_tbl_gsbi_qup,
 790         .clkr = {
 791                 .enable_reg = 0x29ec,
 792                 .enable_mask = BIT(11),
 793                 .hw.init = &(struct clk_init_data){
 794                         .name = "gsbi2_qup_src",
 795                         .parent_names = gcc_pxo_pll8,
 796                         .num_parents = 2,
 797                         .ops = &clk_rcg_ops,
 798                         .flags = CLK_SET_PARENT_GATE,
 799                 },
 800         },
 801 };
 802
 803 static struct clk_branch gsbi2_qup_clk = {
 804         .halt_reg = 0x2fcc,
 805         .halt_bit = 4,
 806         .clkr = {
 807                 .enable_reg = 0x29ec,
 808                 .enable_mask = BIT(9),
 809                 .hw.init = &(struct clk_init_data){
 810                         .name = "gsbi2_qup_clk",
 811                         .parent_names = (const char *[]){ "gsbi2_qup_src" },
 812                         .num_parents = 1,
 813                         .ops = &clk_branch_ops,
 814                         .flags = CLK_SET_RATE_PARENT,
 815                 },
 816         },
 817 };
 818
 819 static struct clk_rcg gsbi3_qup_src = {
 820         .ns_reg = 0x2a0c,
 821         .md_reg = 0x2a08,
 822         .mn = {
 823                 .mnctr_en_bit = 8,
 824                 .mnctr_reset_bit = 7,
 825                 .mnctr_mode_shift = 5,
 826                 .n_val_shift = 16,
 827                 .m_val_shift = 16,
 828                 .width = 8,
 829         },
 830         .p = {
 831                 .pre_div_shift = 3,
 832                 .pre_div_width = 2,
 833         },
 834         .s = {
 835                 .src_sel_shift = 0,
 836                 .parent_map = gcc_pxo_pll8_map,
 837         },
 838         .freq_tbl = clk_tbl_gsbi_qup,
 839         .clkr = {
 840                 .enable_reg = 0x2a0c,
 841                 .enable_mask = BIT(11),
 842                 .hw.init = &(struct clk_init_data){
 843                         .name = "gsbi3_qup_src",
 844                         .parent_names = gcc_pxo_pll8,
 845                         .num_parents = 2,
 846                         .ops = &clk_rcg_ops,
 847                         .flags = CLK_SET_PARENT_GATE,
 848                 },
 849         },
 850 };
 851
 852 static struct clk_branch gsbi3_qup_clk = {
 853         .halt_reg = 0x2fcc,
 854         .halt_bit = 0,
 855         .clkr = {
 856                 .enable_reg = 0x2a0c,
 857                 .enable_mask = BIT(9),
 858                 .hw.init = &(struct clk_init_data){
 859                         .name = "gsbi3_qup_clk",
 860                         .parent_names = (const char *[]){ "gsbi3_qup_src" },
 861                         .num_parents = 1,
 862                         .ops = &clk_branch_ops,
 863                         .flags = CLK_SET_RATE_PARENT,
 864                 },
 865         },
 866 };
 867
 868 static struct clk_rcg gsbi4_qup_src = {
 869         .ns_reg = 0x2a2c,
 870         .md_reg = 0x2a28,
 871         .mn = {
 872                 .mnctr_en_bit = 8,
 873                 .mnctr_reset_bit = 7,
 874                 .mnctr_mode_shift = 5,
 875                 .n_val_shift = 16,
 876                 .m_val_shift = 16,
 877                 .width = 8,
 878         },
 879         .p = {
 880                 .pre_div_shift = 3,
 881                 .pre_div_width = 2,
 882         },
 883         .s = {
 884                 .src_sel_shift = 0,
 885                 .parent_map = gcc_pxo_pll8_map,
 886         },
 887         .freq_tbl = clk_tbl_gsbi_qup,
 888         .clkr = {
 889                 .enable_reg = 0x2a2c,
 890                 .enable_mask = BIT(11),
 891                 .hw.init = &(struct clk_init_data){
 892                         .name = "gsbi4_qup_src",
 893                         .parent_names = gcc_pxo_pll8,
 894                         .num_parents = 2,
 895                         .ops = &clk_rcg_ops,
 896                         .flags = CLK_SET_PARENT_GATE,
 897                 },
 898         },
 899 };
 900
 901 static struct clk_branch gsbi4_qup_clk = {
 902         .halt_reg = 0x2fd0,
 903         .halt_bit = 24,
 904         .clkr = {
 905                 .enable_reg = 0x2a2c,
 906                 .enable_mask = BIT(9),
 907                 .hw.init = &(struct clk_init_data){
 908                         .name = "gsbi4_qup_clk",
 909                         .parent_names = (const char *[]){ "gsbi4_qup_src" },
 910                         .num_parents = 1,
 911                         .ops = &clk_branch_ops,
 912                         .flags = CLK_SET_RATE_PARENT,
 913                 },
 914         },
 915 };
 916
 917 static struct clk_rcg gsbi5_qup_src = {
 918         .ns_reg = 0x2a4c,
 919         .md_reg = 0x2a48,
 920         .mn = {
 921                 .mnctr_en_bit = 8,
 922                 .mnctr_reset_bit = 7,
 923                 .mnctr_mode_shift = 5,
 924                 .n_val_shift = 16,
 925                 .m_val_shift = 16,
 926                 .width = 8,
 927         },
 928         .p = {
 929                 .pre_div_shift = 3,
 930                 .pre_div_width = 2,
 931         },
 932         .s = {
 933                 .src_sel_shift = 0,
 934                 .parent_map = gcc_pxo_pll8_map,
 935         },
 936         .freq_tbl = clk_tbl_gsbi_qup,
 937         .clkr = {
 938                 .enable_reg = 0x2a4c,
 939                 .enable_mask = BIT(11),
 940                 .hw.init = &(struct clk_init_data){
 941                         .name = "gsbi5_qup_src",
 942                         .parent_names = gcc_pxo_pll8,
 943                         .num_parents = 2,
 944                         .ops = &clk_rcg_ops,
 945                         .flags = CLK_SET_PARENT_GATE,
 946                 },
 947         },
 948 };
 949
 950 static struct clk_branch gsbi5_qup_clk = {
 951         .halt_reg = 0x2fd0,
 952         .halt_bit = 20,
 953         .clkr = {
 954                 .enable_reg = 0x2a4c,
 955                 .enable_mask = BIT(9),
 956                 .hw.init = &(struct clk_init_data){
 957                         .name = "gsbi5_qup_clk",
 958                         .parent_names = (const char *[]){ "gsbi5_qup_src" },
 959                         .num_parents = 1,
 960                         .ops = &clk_branch_ops,
 961                         .flags = CLK_SET_RATE_PARENT,
 962                 },
 963         },
 964 };
 965
 966 static struct clk_rcg gsbi6_qup_src = {
 967         .ns_reg = 0x2a6c,
 968         .md_reg = 0x2a68,
 969         .mn = {
 970                 .mnctr_en_bit = 8,
 971                 .mnctr_reset_bit = 7,
 972                 .mnctr_mode_shift = 5,
 973                 .n_val_shift = 16,
 974                 .m_val_shift = 16,
 975                 .width = 8,
 976         },
 977         .p = {
 978                 .pre_div_shift = 3,
 979                 .pre_div_width = 2,
 980         },
 981         .s = {
 982                 .src_sel_shift = 0,
 983                 .parent_map = gcc_pxo_pll8_map,
 984         },
 985         .freq_tbl = clk_tbl_gsbi_qup,
 986         .clkr = {
 987                 .enable_reg = 0x2a6c,
 988                 .enable_mask = BIT(11),
 989                 .hw.init = &(struct clk_init_data){
 990                         .name = "gsbi6_qup_src",
 991                         .parent_names = gcc_pxo_pll8,
 992                         .num_parents = 2,
 993                         .ops = &clk_rcg_ops,
 994                         .flags = CLK_SET_PARENT_GATE,
 995                 },
 996         },
 997 };
 998
 999 static struct clk_branch gsbi6_qup_clk = {
1000         .halt_reg = 0x2fd0,
1001         .halt_bit = 16,
1002         .clkr = {
1003                 .enable_reg = 0x2a6c,
1004                 .enable_mask = BIT(9),
1005                 .hw.init = &(struct clk_init_data){
1006                         .name = "gsbi6_qup_clk",
1007                         .parent_names = (const char *[]){ "gsbi6_qup_src" },
1008                         .num_parents = 1,
1009                         .ops = &clk_branch_ops,
1010                         .flags = CLK_SET_RATE_PARENT,
1011                 },
1012         },
1013 };
1014
1015 static struct clk_rcg gsbi7_qup_src = {
1016         .ns_reg = 0x2a8c,
1017         .md_reg = 0x2a88,
1018         .mn = {
1019                 .mnctr_en_bit = 8,
1020                 .mnctr_reset_bit = 7,
1021                 .mnctr_mode_shift = 5,
1022                 .n_val_shift = 16,
1023                 .m_val_shift = 16,
1024                 .width = 8,
1025         },
1026         .p = {
1027                 .pre_div_shift = 3,
1028                 .pre_div_width = 2,
1029         },
1030         .s = {
1031                 .src_sel_shift = 0,
1032                 .parent_map = gcc_pxo_pll8_map,
1033         },
1034         .freq_tbl = clk_tbl_gsbi_qup,
1035         .clkr = {
1036                 .enable_reg = 0x2a8c,
1037                 .enable_mask = BIT(11),
1038                 .hw.init = &(struct clk_init_data){
1039                         .name = "gsbi7_qup_src",
1040                         .parent_names = gcc_pxo_pll8,
1041                         .num_parents = 2,
1042                         .ops = &clk_rcg_ops,
1043                         .flags = CLK_SET_PARENT_GATE,
1044                 },
1045         },
1046 };
1047
1048 static struct clk_branch gsbi7_qup_clk = {
1049         .halt_reg = 0x2fd0,
1050         .halt_bit = 12,
1051         .clkr = {
1052                 .enable_reg = 0x2a8c,
1053                 .enable_mask = BIT(9),
1054                 .hw.init = &(struct clk_init_data){
1055                         .name = "gsbi7_qup_clk",
1056                         .parent_names = (const char *[]){ "gsbi7_qup_src" },
1057                         .num_parents = 1,
1058                         .ops = &clk_branch_ops,
1059                         .flags = CLK_SET_RATE_PARENT,
1060                 },
1061         },
1062 };
1063
1064 static struct clk_rcg gsbi8_qup_src = {
1065         .ns_reg = 0x2aac,
1066         .md_reg = 0x2aa8,
1067         .mn = {
1068                 .mnctr_en_bit = 8,
1069                 .mnctr_reset_bit = 7,
1070                 .mnctr_mode_shift = 5,
1071                 .n_val_shift = 16,
1072                 .m_val_shift = 16,
1073                 .width = 8,
1074         },
1075         .p = {
1076                 .pre_div_shift = 3,
1077                 .pre_div_width = 2,
1078         },
1079         .s = {
1080                 .src_sel_shift = 0,
1081                 .parent_map = gcc_pxo_pll8_map,
1082         },
1083         .freq_tbl = clk_tbl_gsbi_qup,
1084         .clkr = {
1085                 .enable_reg = 0x2aac,
1086                 .enable_mask = BIT(11),
1087                 .hw.init = &(struct clk_init_data){
1088                         .name = "gsbi8_qup_src",
1089                         .parent_names = gcc_pxo_pll8,
1090                         .num_parents = 2,
1091                         .ops = &clk_rcg_ops,
1092                         .flags = CLK_SET_PARENT_GATE,
1093                 },
1094         },
1095 };
1096
1097 static struct clk_branch gsbi8_qup_clk = {
1098         .halt_reg = 0x2fd0,
1099         .halt_bit = 8,
1100         .clkr = {
1101                 .enable_reg = 0x2aac,
1102                 .enable_mask = BIT(9),
1103                 .hw.init = &(struct clk_init_data){
1104                         .name = "gsbi8_qup_clk",
1105                         .parent_names = (const char *[]){ "gsbi8_qup_src" },
1106                         .num_parents = 1,
1107                         .ops = &clk_branch_ops,
1108                         .flags = CLK_SET_RATE_PARENT,
1109                 },
1110         },
1111 };
1112
1113 static struct clk_rcg gsbi9_qup_src = {
1114         .ns_reg = 0x2acc,
1115         .md_reg = 0x2ac8,
1116         .mn = {
1117                 .mnctr_en_bit = 8,
1118                 .mnctr_reset_bit = 7,
1119                 .mnctr_mode_shift = 5,
1120                 .n_val_shift = 16,
1121                 .m_val_shift = 16,
1122                 .width = 8,
1123         },
1124         .p = {
1125                 .pre_div_shift = 3,
1126                 .pre_div_width = 2,
1127         },
1128         .s = {
1129                 .src_sel_shift = 0,
1130                 .parent_map = gcc_pxo_pll8_map,
1131         },
1132         .freq_tbl = clk_tbl_gsbi_qup,
1133         .clkr = {
1134                 .enable_reg = 0x2acc,
1135                 .enable_mask = BIT(11),
1136                 .hw.init = &(struct clk_init_data){
1137                         .name = "gsbi9_qup_src",
1138                         .parent_names = gcc_pxo_pll8,
1139                         .num_parents = 2,
1140                         .ops = &clk_rcg_ops,
1141                         .flags = CLK_SET_PARENT_GATE,
1142                 },
1143         },
1144 };
1145
1146 static struct clk_branch gsbi9_qup_clk = {
1147         .halt_reg = 0x2fd0,
1148         .halt_bit = 4,
1149         .clkr = {
1150                 .enable_reg = 0x2acc,
1151                 .enable_mask = BIT(9),
1152                 .hw.init = &(struct clk_init_data){
1153                         .name = "gsbi9_qup_clk",
1154                         .parent_names = (const char *[]){ "gsbi9_qup_src" },
1155                         .num_parents = 1,
1156                         .ops = &clk_branch_ops,
1157                         .flags = CLK_SET_RATE_PARENT,
1158                 },
1159         },
1160 };
1161
1162 static struct clk_rcg gsbi10_qup_src = {
1163         .ns_reg = 0x2aec,
1164         .md_reg = 0x2ae8,
1165         .mn = {
1166                 .mnctr_en_bit = 8,
1167                 .mnctr_reset_bit = 7,
1168                 .mnctr_mode_shift = 5,
1169                 .n_val_shift = 16,
1170                 .m_val_shift = 16,
1171                 .width = 8,
1172         },
1173         .p = {
1174                 .pre_div_shift = 3,
1175                 .pre_div_width = 2,
1176         },
1177         .s = {
1178                 .src_sel_shift = 0,
1179                 .parent_map = gcc_pxo_pll8_map,
1180         },
1181         .freq_tbl = clk_tbl_gsbi_qup,
1182         .clkr = {
1183                 .enable_reg = 0x2aec,
1184                 .enable_mask = BIT(11),
1185                 .hw.init = &(struct clk_init_data){
1186                         .name = "gsbi10_qup_src",
1187                         .parent_names = gcc_pxo_pll8,
1188                         .num_parents = 2,
1189                         .ops = &clk_rcg_ops,
1190                         .flags = CLK_SET_PARENT_GATE,
1191                 },
1192         },
1193 };
1194
1195 static struct clk_branch gsbi10_qup_clk = {
1196         .halt_reg = 0x2fd0,
1197         .halt_bit = 0,
1198         .clkr = {
1199                 .enable_reg = 0x2aec,
1200                 .enable_mask = BIT(9),
1201                 .hw.init = &(struct clk_init_data){
1202                         .name = "gsbi10_qup_clk",
1203                         .parent_names = (const char *[]){ "gsbi10_qup_src" },
1204                         .num_parents = 1,
1205                         .ops = &clk_branch_ops,
1206                         .flags = CLK_SET_RATE_PARENT,
1207                 },
1208         },
1209 };
1210
1211 static struct clk_rcg gsbi11_qup_src = {
1212         .ns_reg = 0x2b0c,
1213         .md_reg = 0x2b08,
1214         .mn = {
1215                 .mnctr_en_bit = 8,
1216                 .mnctr_reset_bit = 7,
1217                 .mnctr_mode_shift = 5,
1218                 .n_val_shift = 16,
1219                 .m_val_shift = 16,
1220                 .width = 8,
1221         },
1222         .p = {
1223                 .pre_div_shift = 3,
1224                 .pre_div_width = 2,
1225         },
1226         .s = {
1227                 .src_sel_shift = 0,
1228                 .parent_map = gcc_pxo_pll8_map,
1229         },
1230         .freq_tbl = clk_tbl_gsbi_qup,
1231         .clkr = {
1232                 .enable_reg = 0x2b0c,
1233                 .enable_mask = BIT(11),
1234                 .hw.init = &(struct clk_init_data){
1235                         .name = "gsbi11_qup_src",
1236                         .parent_names = gcc_pxo_pll8,
1237                         .num_parents = 2,
1238                         .ops = &clk_rcg_ops,
1239                         .flags = CLK_SET_PARENT_GATE,
1240                 },
1241         },
1242 };
1243
1244 static struct clk_branch gsbi11_qup_clk = {
1245         .halt_reg = 0x2fd4,
1246         .halt_bit = 15,
1247         .clkr = {
1248                 .enable_reg = 0x2b0c,
1249                 .enable_mask = BIT(9),
1250                 .hw.init = &(struct clk_init_data){
1251                         .name = "gsbi11_qup_clk",
1252                         .parent_names = (const char *[]){ "gsbi11_qup_src" },
1253                         .num_parents = 1,
1254                         .ops = &clk_branch_ops,
1255                         .flags = CLK_SET_RATE_PARENT,
1256                 },
1257         },
1258 };
1259
1260 static struct clk_rcg gsbi12_qup_src = {
1261         .ns_reg = 0x2b2c,
1262         .md_reg = 0x2b28,
1263         .mn = {
1264                 .mnctr_en_bit = 8,
1265                 .mnctr_reset_bit = 7,
1266                 .mnctr_mode_shift = 5,
1267                 .n_val_shift = 16,
1268                 .m_val_shift = 16,
1269                 .width = 8,
1270         },
1271         .p = {
1272                 .pre_div_shift = 3,
1273                 .pre_div_width = 2,
1274         },
1275         .s = {
1276                 .src_sel_shift = 0,
1277                 .parent_map = gcc_pxo_pll8_map,
1278         },
1279         .freq_tbl = clk_tbl_gsbi_qup,
1280         .clkr = {
1281                 .enable_reg = 0x2b2c,
1282                 .enable_mask = BIT(11),
1283                 .hw.init = &(struct clk_init_data){
1284                         .name = "gsbi12_qup_src",
1285                         .parent_names = gcc_pxo_pll8,
1286                         .num_parents = 2,
1287                         .ops = &clk_rcg_ops,
1288                         .flags = CLK_SET_PARENT_GATE,
1289                 },
1290         },
1291 };
1292
1293 static struct clk_branch gsbi12_qup_clk = {
1294         .halt_reg = 0x2fd4,
1295         .halt_bit = 11,
1296         .clkr = {
1297                 .enable_reg = 0x2b2c,
1298                 .enable_mask = BIT(9),
1299                 .hw.init = &(struct clk_init_data){
1300                         .name = "gsbi12_qup_clk",
1301                         .parent_names = (const char *[]){ "gsbi12_qup_src" },
1302                         .num_parents = 1,
1303                         .ops = &clk_branch_ops,
1304                         .flags = CLK_SET_RATE_PARENT,
1305                 },
1306         },
1307 };
1308
1309 static const struct freq_tbl clk_tbl_gp[] = {
1310         { 9600000, P_CXO,  2, 0, 0 },
1311         { 13500000, P_PXO,  2, 0, 0 },
1312         { 19200000, P_CXO,  1, 0, 0 },
1313         { 27000000, P_PXO,  1, 0, 0 },
1314         { 64000000, P_PLL8, 2, 1, 3 },
1315         { 76800000, P_PLL8, 1, 1, 5 },
1316         { 96000000, P_PLL8, 4, 0, 0 },
1317         { 128000000, P_PLL8, 3, 0, 0 },
1318         { 192000000, P_PLL8, 2, 0, 0 },
1319         { }
1320 };
1321
1322 static struct clk_rcg gp0_src = {
1323         .ns_reg = 0x2d24,
1324         .md_reg = 0x2d00,
1325         .mn = {
1326                 .mnctr_en_bit = 8,
1327                 .mnctr_reset_bit = 7,
1328                 .mnctr_mode_shift = 5,
1329                 .n_val_shift = 16,
1330                 .m_val_shift = 16,
1331                 .width = 8,
1332         },
1333         .p = {
1334                 .pre_div_shift = 3,
1335                 .pre_div_width = 2,
1336         },
1337         .s = {
1338                 .src_sel_shift = 0,
1339                 .parent_map = gcc_pxo_pll8_cxo_map,
1340         },
1341         .freq_tbl = clk_tbl_gp,
1342         .clkr = {
1343                 .enable_reg = 0x2d24,
1344                 .enable_mask = BIT(11),
1345                 .hw.init = &(struct clk_init_data){
1346                         .name = "gp0_src",
1347                         .parent_names = gcc_pxo_pll8_cxo,
1348                         .num_parents = 3,
1349                         .ops = &clk_rcg_ops,
1350                         .flags = CLK_SET_PARENT_GATE,
1351                 },
1352         }
1353 };
1354
1355 static struct clk_branch gp0_clk = {
1356         .halt_reg = 0x2fd8,
1357         .halt_bit = 7,
1358         .clkr = {
1359                 .enable_reg = 0x2d24,
1360                 .enable_mask = BIT(9),
1361                 .hw.init = &(struct clk_init_data){
1362                         .name = "gp0_clk",
1363                         .parent_names = (const char *[]){ "gp0_src" },
1364                         .num_parents = 1,
1365                         .ops = &clk_branch_ops,
1366                         .flags = CLK_SET_RATE_PARENT,
1367                 },
1368         },
1369 };
1370
1371 static struct clk_rcg gp1_src = {
1372         .ns_reg = 0x2d44,
1373         .md_reg = 0x2d40,
1374         .mn = {
1375                 .mnctr_en_bit = 8,
1376                 .mnctr_reset_bit = 7,
1377                 .mnctr_mode_shift = 5,
1378                 .n_val_shift = 16,
1379                 .m_val_shift = 16,
1380                 .width = 8,
1381         },
1382         .p = {
1383                 .pre_div_shift = 3,
1384                 .pre_div_width = 2,
1385         },
1386         .s = {
1387                 .src_sel_shift = 0,
1388                 .parent_map = gcc_pxo_pll8_cxo_map,
1389         },
1390         .freq_tbl = clk_tbl_gp,
1391         .clkr = {
1392                 .enable_reg = 0x2d44,
1393                 .enable_mask = BIT(11),
1394                 .hw.init = &(struct clk_init_data){
1395                         .name = "gp1_src",
1396                         .parent_names = gcc_pxo_pll8_cxo,
1397                         .num_parents = 3,
1398                         .ops = &clk_rcg_ops,
1399                         .flags = CLK_SET_RATE_GATE,
1400                 },
1401         }
1402 };
1403
1404 static struct clk_branch gp1_clk = {
1405         .halt_reg = 0x2fd8,
1406         .halt_bit = 6,
1407         .clkr = {
1408                 .enable_reg = 0x2d44,
1409                 .enable_mask = BIT(9),
1410                 .hw.init = &(struct clk_init_data){
1411                         .name = "gp1_clk",
1412                         .parent_names = (const char *[]){ "gp1_src" },
1413                         .num_parents = 1,
1414                         .ops = &clk_branch_ops,
1415                         .flags = CLK_SET_RATE_PARENT,
1416                 },
1417         },
1418 };
1419
1420 static struct clk_rcg gp2_src = {
1421         .ns_reg = 0x2d64,
1422         .md_reg = 0x2d60,
1423         .mn = {
1424                 .mnctr_en_bit = 8,
1425                 .mnctr_reset_bit = 7,
1426                 .mnctr_mode_shift = 5,
1427                 .n_val_shift = 16,
1428                 .m_val_shift = 16,
1429                 .width = 8,
1430         },
1431         .p = {
1432                 .pre_div_shift = 3,
1433                 .pre_div_width = 2,
1434         },
1435         .s = {
1436                 .src_sel_shift = 0,
1437                 .parent_map = gcc_pxo_pll8_cxo_map,
1438         },
1439         .freq_tbl = clk_tbl_gp,
1440         .clkr = {
1441                 .enable_reg = 0x2d64,
1442                 .enable_mask = BIT(11),
1443                 .hw.init = &(struct clk_init_data){
1444                         .name = "gp2_src",
1445                         .parent_names = gcc_pxo_pll8_cxo,
1446                         .num_parents = 3,
1447                         .ops = &clk_rcg_ops,
1448                         .flags = CLK_SET_RATE_GATE,
1449                 },
1450         }
1451 };
1452
1453 static struct clk_branch gp2_clk = {
1454         .halt_reg = 0x2fd8,
1455         .halt_bit = 5,
1456         .clkr = {
1457                 .enable_reg = 0x2d64,
1458                 .enable_mask = BIT(9),
1459                 .hw.init = &(struct clk_init_data){
1460                         .name = "gp2_clk",
1461                         .parent_names = (const char *[]){ "gp2_src" },
1462                         .num_parents = 1,
1463                         .ops = &clk_branch_ops,
1464                         .flags = CLK_SET_RATE_PARENT,
1465                 },
1466         },
1467 };
1468
1469 static struct clk_branch pmem_clk = {
1470         .hwcg_reg = 0x25a0,
1471         .hwcg_bit = 6,
1472         .halt_reg = 0x2fc8,
1473         .halt_bit = 20,
1474         .clkr = {
1475                 .enable_reg = 0x25a0,
1476                 .enable_mask = BIT(4),
1477                 .hw.init = &(struct clk_init_data){
1478                         .name = "pmem_clk",
1479                         .ops = &clk_branch_ops,
1480                         .flags = CLK_IS_ROOT,
1481                 },
1482         },
1483 };
1484
1485 static struct clk_rcg prng_src = {
1486         .ns_reg = 0x2e80,
1487         .p = {
1488                 .pre_div_shift = 3,
1489                 .pre_div_width = 4,
1490         },
1491         .s = {
1492                 .src_sel_shift = 0,
1493                 .parent_map = gcc_pxo_pll8_map,
1494         },
1495         .clkr.hw = {
1496                 .init = &(struct clk_init_data){
1497                         .name = "prng_src",
1498                         .parent_names = gcc_pxo_pll8,
1499                         .num_parents = 2,
1500                         .ops = &clk_rcg_ops,
1501                 },
1502         },
1503 };
1504
1505 static struct clk_branch prng_clk = {
1506         .halt_reg = 0x2fd8,
1507         .halt_check = BRANCH_HALT_VOTED,
1508         .halt_bit = 10,
1509         .clkr = {
1510                 .enable_reg = 0x3080,
1511                 .enable_mask = BIT(10),
1512                 .hw.init = &(struct clk_init_data){
1513                         .name = "prng_clk",
1514                         .parent_names = (const char *[]){ "prng_src" },
1515                         .num_parents = 1,
1516                         .ops = &clk_branch_ops,
1517                 },
1518         },
1519 };
1520
1521 static const struct freq_tbl clk_tbl_sdc[] = {
1522         {    144000, P_PXO,   3, 2, 125 },
1523         {    400000, P_PLL8,  4, 1, 240 },
1524         {  16000000, P_PLL8,  4, 1,   6 },
1525         {  17070000, P_PLL8,  1, 2,  45 },
1526         {  20210000, P_PLL8,  1, 1,  19 },
1527         {  24000000, P_PLL8,  4, 1,   4 },
1528         {  48000000, P_PLL8,  4, 1,   2 },
1529         { }
1530 };
1531
1532 static struct clk_rcg sdc1_src = {
1533         .ns_reg = 0x282c,
1534         .md_reg = 0x2828,
1535         .mn = {
1536                 .mnctr_en_bit = 8,
1537                 .mnctr_reset_bit = 7,
1538                 .mnctr_mode_shift = 5,
1539                 .n_val_shift = 16,
1540                 .m_val_shift = 16,
1541                 .width = 8,
1542         },
1543         .p = {
1544                 .pre_div_shift = 3,
1545                 .pre_div_width = 2,
1546         },
1547         .s = {
1548                 .src_sel_shift = 0,
1549                 .parent_map = gcc_pxo_pll8_map,
1550         },
1551         .freq_tbl = clk_tbl_sdc,
1552         .clkr = {
1553                 .enable_reg = 0x282c,
1554                 .enable_mask = BIT(11),
1555                 .hw.init = &(struct clk_init_data){
1556                         .name = "sdc1_src",
1557                         .parent_names = gcc_pxo_pll8,
1558                         .num_parents = 2,
1559                         .ops = &clk_rcg_ops,
1560                         .flags = CLK_SET_RATE_GATE,
1561                 },
1562         }
1563 };
1564
1565 static struct clk_branch sdc1_clk = {
1566         .halt_reg = 0x2fc8,
1567         .halt_bit = 6,
1568         .clkr = {
1569                 .enable_reg = 0x282c,
1570                 .enable_mask = BIT(9),
1571                 .hw.init = &(struct clk_init_data){
1572                         .name = "sdc1_clk",
1573                         .parent_names = (const char *[]){ "sdc1_src" },
1574                         .num_parents = 1,
1575                         .ops = &clk_branch_ops,
1576                         .flags = CLK_SET_RATE_PARENT,
1577                 },
1578         },
1579 };
1580
1581 static struct clk_rcg sdc2_src = {
1582         .ns_reg = 0x284c,
1583         .md_reg = 0x2848,
1584         .mn = {
1585                 .mnctr_en_bit = 8,
1586                 .mnctr_reset_bit = 7,
1587                 .mnctr_mode_shift = 5,
1588                 .n_val_shift = 16,
1589                 .m_val_shift = 16,
1590                 .width = 8,
1591         },
1592         .p = {
1593                 .pre_div_shift = 3,
1594                 .pre_div_width = 2,
1595         },
1596         .s = {
1597                 .src_sel_shift = 0,
1598                 .parent_map = gcc_pxo_pll8_map,
1599         },
1600         .freq_tbl = clk_tbl_sdc,
1601         .clkr = {
1602                 .enable_reg = 0x284c,
1603                 .enable_mask = BIT(11),
1604                 .hw.init = &(struct clk_init_data){
1605                         .name = "sdc2_src",
1606                         .parent_names = gcc_pxo_pll8,
1607                         .num_parents = 2,
1608                         .ops = &clk_rcg_ops,
1609                         .flags = CLK_SET_RATE_GATE,
1610                 },
1611         }
1612 };
1613
1614 static struct clk_branch sdc2_clk = {
1615         .halt_reg = 0x2fc8,
1616         .halt_bit = 5,
1617         .clkr = {
1618                 .enable_reg = 0x284c,
1619                 .enable_mask = BIT(9),
1620                 .hw.init = &(struct clk_init_data){
1621                         .name = "sdc2_clk",
1622                         .parent_names = (const char *[]){ "sdc2_src" },
1623                         .num_parents = 1,
1624                         .ops = &clk_branch_ops,
1625                         .flags = CLK_SET_RATE_PARENT,
1626                 },
1627         },
1628 };
1629
1630 static struct clk_rcg sdc3_src = {
1631         .ns_reg = 0x286c,
1632         .md_reg = 0x2868,
1633         .mn = {
1634                 .mnctr_en_bit = 8,
1635                 .mnctr_reset_bit = 7,
1636                 .mnctr_mode_shift = 5,
1637                 .n_val_shift = 16,
1638                 .m_val_shift = 16,
1639                 .width = 8,
1640         },
1641         .p = {
1642                 .pre_div_shift = 3,
1643                 .pre_div_width = 2,
1644         },
1645         .s = {
1646                 .src_sel_shift = 0,
1647                 .parent_map = gcc_pxo_pll8_map,
1648         },
1649         .freq_tbl = clk_tbl_sdc,
1650         .clkr = {
1651                 .enable_reg = 0x286c,
1652                 .enable_mask = BIT(11),
1653                 .hw.init = &(struct clk_init_data){
1654                         .name = "sdc3_src",
1655                         .parent_names = gcc_pxo_pll8,
1656                         .num_parents = 2,
1657                         .ops = &clk_rcg_ops,
1658                         .flags = CLK_SET_RATE_GATE,
1659                 },
1660         }
1661 };
1662
1663 static struct clk_branch sdc3_clk = {
1664         .halt_reg = 0x2fc8,
1665         .halt_bit = 4,
1666         .clkr = {
1667                 .enable_reg = 0x286c,
1668                 .enable_mask = BIT(9),
1669                 .hw.init = &(struct clk_init_data){
1670                         .name = "sdc3_clk",
1671                         .parent_names = (const char *[]){ "sdc3_src" },
1672                         .num_parents = 1,
1673                         .ops = &clk_branch_ops,
1674                         .flags = CLK_SET_RATE_PARENT,
1675                 },
1676         },
1677 };
1678
1679 static struct clk_rcg sdc4_src = {
1680         .ns_reg = 0x288c,
1681         .md_reg = 0x2888,
1682         .mn = {
1683                 .mnctr_en_bit = 8,
1684                 .mnctr_reset_bit = 7,
1685                 .mnctr_mode_shift = 5,
1686                 .n_val_shift = 16,
1687                 .m_val_shift = 16,
1688                 .width = 8,
1689         },
1690         .p = {
1691                 .pre_div_shift = 3,
1692                 .pre_div_width = 2,
1693         },
1694         .s = {
1695                 .src_sel_shift = 0,
1696                 .parent_map = gcc_pxo_pll8_map,
1697         },
1698         .freq_tbl = clk_tbl_sdc,
1699         .clkr = {
1700                 .enable_reg = 0x288c,
1701                 .enable_mask = BIT(11),
1702                 .hw.init = &(struct clk_init_data){
1703                         .name = "sdc4_src",
1704                         .parent_names = gcc_pxo_pll8,
1705                         .num_parents = 2,
1706                         .ops = &clk_rcg_ops,
1707                         .flags = CLK_SET_RATE_GATE,
1708                 },
1709         }
1710 };
1711
1712 static struct clk_branch sdc4_clk = {
1713         .halt_reg = 0x2fc8,
1714         .halt_bit = 3,
1715         .clkr = {
1716                 .enable_reg = 0x288c,
1717                 .enable_mask = BIT(9),
1718                 .hw.init = &(struct clk_init_data){
1719                         .name = "sdc4_clk",
1720                         .parent_names = (const char *[]){ "sdc4_src" },
1721                         .num_parents = 1,
1722                         .ops = &clk_branch_ops,
1723                         .flags = CLK_SET_RATE_PARENT,
1724                 },
1725         },
1726 };
1727
1728 static struct clk_rcg sdc5_src = {
1729         .ns_reg = 0x28ac,
1730         .md_reg = 0x28a8,
1731         .mn = {
1732                 .mnctr_en_bit = 8,
1733                 .mnctr_reset_bit = 7,
1734                 .mnctr_mode_shift = 5,
1735                 .n_val_shift = 16,
1736                 .m_val_shift = 16,
1737                 .width = 8,
1738         },
1739         .p = {
1740                 .pre_div_shift = 3,
1741                 .pre_div_width = 2,
1742         },
1743         .s = {
1744                 .src_sel_shift = 0,
1745                 .parent_map = gcc_pxo_pll8_map,
1746         },
1747         .freq_tbl = clk_tbl_sdc,
1748         .clkr = {
1749                 .enable_reg = 0x28ac,
1750                 .enable_mask = BIT(11),
1751                 .hw.init = &(struct clk_init_data){
1752                         .name = "sdc5_src",
1753                         .parent_names = gcc_pxo_pll8,
1754                         .num_parents = 2,
1755                         .ops = &clk_rcg_ops,
1756                         .flags = CLK_SET_RATE_GATE,
1757                 },
1758         }
1759 };
1760
1761 static struct clk_branch sdc5_clk = {
1762         .halt_reg = 0x2fc8,
1763         .halt_bit = 2,
1764         .clkr = {
1765                 .enable_reg = 0x28ac,
1766                 .enable_mask = BIT(9),
1767                 .hw.init = &(struct clk_init_data){
1768                         .name = "sdc5_clk",
1769                         .parent_names = (const char *[]){ "sdc5_src" },
1770                         .num_parents = 1,
1771                         .ops = &clk_branch_ops,
1772                         .flags = CLK_SET_RATE_PARENT,
1773                 },
1774         },
1775 };
1776
1777 static const struct freq_tbl clk_tbl_tsif_ref[] = {
1778         { 105000, P_PXO,  1, 1, 256 },
1779         { }
1780 };
1781
1782 static struct clk_rcg tsif_ref_src = {
1783         .ns_reg = 0x2710,
1784         .md_reg = 0x270c,
1785         .mn = {
1786                 .mnctr_en_bit = 8,
1787                 .mnctr_reset_bit = 7,
1788                 .mnctr_mode_shift = 5,
1789                 .n_val_shift = 16,
1790                 .m_val_shift = 16,
1791                 .width = 16,
1792         },
1793         .p = {
1794                 .pre_div_shift = 3,
1795                 .pre_div_width = 2,
1796         },
1797         .s = {
1798                 .src_sel_shift = 0,
1799                 .parent_map = gcc_pxo_pll8_map,
1800         },
1801         .freq_tbl = clk_tbl_tsif_ref,
1802         .clkr = {
1803                 .enable_reg = 0x2710,
1804                 .enable_mask = BIT(11),
1805                 .hw.init = &(struct clk_init_data){
1806                         .name = "tsif_ref_src",
1807                         .parent_names = gcc_pxo_pll8,
1808                         .num_parents = 2,
1809                         .ops = &clk_rcg_ops,
1810                         .flags = CLK_SET_RATE_GATE,
1811                 },
1812         }
1813 };
1814
1815 static struct clk_branch tsif_ref_clk = {
1816         .halt_reg = 0x2fd4,
1817         .halt_bit = 5,
1818         .clkr = {
1819                 .enable_reg = 0x2710,
1820                 .enable_mask = BIT(9),
1821                 .hw.init = &(struct clk_init_data){
1822                         .name = "tsif_ref_clk",
1823                         .parent_names = (const char *[]){ "tsif_ref_src" },
1824                         .num_parents = 1,
1825                         .ops = &clk_branch_ops,
1826                         .flags = CLK_SET_RATE_PARENT,
1827                 },
1828         },
1829 };
1830
1831 static const struct freq_tbl clk_tbl_usb[] = {
1832         { 60000000, P_PLL8, 1, 5, 32 },
1833         { }
1834 };
1835
1836 static struct clk_rcg usb_hs1_xcvr_src = {
1837         .ns_reg = 0x290c,
1838         .md_reg = 0x2908,
1839         .mn = {
1840                 .mnctr_en_bit = 8,
1841                 .mnctr_reset_bit = 7,
1842                 .mnctr_mode_shift = 5,
1843                 .n_val_shift = 16,
1844                 .m_val_shift = 16,
1845                 .width = 8,
1846         },
1847         .p = {
1848                 .pre_div_shift = 3,
1849                 .pre_div_width = 2,
1850         },
1851         .s = {
1852                 .src_sel_shift = 0,
1853                 .parent_map = gcc_pxo_pll8_map,
1854         },
1855         .freq_tbl = clk_tbl_usb,
1856         .clkr = {
1857                 .enable_reg = 0x290c,
1858                 .enable_mask = BIT(11),
1859                 .hw.init = &(struct clk_init_data){
1860                         .name = "usb_hs1_xcvr_src",
1861                         .parent_names = gcc_pxo_pll8,
1862                         .num_parents = 2,
1863                         .ops = &clk_rcg_ops,
1864                         .flags = CLK_SET_RATE_GATE,
1865                 },
1866         }
1867 };
1868
1869 static struct clk_branch usb_hs1_xcvr_clk = {
1870         .halt_reg = 0x2fc8,
1871         .halt_bit = 0,
1872         .clkr = {
1873                 .enable_reg = 0x290c,
1874                 .enable_mask = BIT(9),
1875                 .hw.init = &(struct clk_init_data){
1876                         .name = "usb_hs1_xcvr_clk",
1877                         .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
1878                         .num_parents = 1,
1879                         .ops = &clk_branch_ops,
1880                         .flags = CLK_SET_RATE_PARENT,
1881                 },
1882         },
1883 };
1884
1885 static struct clk_rcg usb_fs1_xcvr_fs_src = {
1886         .ns_reg = 0x2968,
1887         .md_reg = 0x2964,
1888         .mn = {
1889                 .mnctr_en_bit = 8,
1890                 .mnctr_reset_bit = 7,
1891                 .mnctr_mode_shift = 5,
1892                 .n_val_shift = 16,
1893                 .m_val_shift = 16,
1894                 .width = 8,
1895         },
1896         .p = {
1897                 .pre_div_shift = 3,
1898                 .pre_div_width = 2,
1899         },
1900         .s = {
1901                 .src_sel_shift = 0,
1902                 .parent_map = gcc_pxo_pll8_map,
1903         },
1904         .freq_tbl = clk_tbl_usb,
1905         .clkr = {
1906                 .enable_reg = 0x2968,
1907                 .enable_mask = BIT(11),
1908                 .hw.init = &(struct clk_init_data){
1909                         .name = "usb_fs1_xcvr_fs_src",
1910                         .parent_names = gcc_pxo_pll8,
1911                         .num_parents = 2,
1912                         .ops = &clk_rcg_ops,
1913                         .flags = CLK_SET_RATE_GATE,
1914                 },
1915         }
1916 };
1917
1918 static const char *usb_fs1_xcvr_fs_src_p[] = { "usb_fs1_xcvr_fs_src" };
1919
1920 static struct clk_branch usb_fs1_xcvr_fs_clk = {
1921         .halt_reg = 0x2fcc,
1922         .halt_bit = 15,
1923         .clkr = {
1924                 .enable_reg = 0x2968,
1925                 .enable_mask = BIT(9),
1926                 .hw.init = &(struct clk_init_data){
1927                         .name = "usb_fs1_xcvr_fs_clk",
1928                         .parent_names = usb_fs1_xcvr_fs_src_p,
1929                         .num_parents = 1,
1930                         .ops = &clk_branch_ops,
1931                         .flags = CLK_SET_RATE_PARENT,
1932                 },
1933         },
1934 };
1935
1936 static struct clk_branch usb_fs1_system_clk = {
1937         .halt_reg = 0x2fcc,
1938         .halt_bit = 16,
1939         .clkr = {
1940                 .enable_reg = 0x296c,
1941                 .enable_mask = BIT(4),
1942                 .hw.init = &(struct clk_init_data){
1943                         .parent_names = usb_fs1_xcvr_fs_src_p,
1944                         .num_parents = 1,
1945                         .name = "usb_fs1_system_clk",
1946                         .ops = &clk_branch_ops,
1947                         .flags = CLK_SET_RATE_PARENT,
1948                 },
1949         },
1950 };
1951
1952 static struct clk_rcg usb_fs2_xcvr_fs_src = {
1953         .ns_reg = 0x2988,
1954         .md_reg = 0x2984,
1955         .mn = {
1956                 .mnctr_en_bit = 8,
1957                 .mnctr_reset_bit = 7,
1958                 .mnctr_mode_shift = 5,
1959                 .n_val_shift = 16,
1960                 .m_val_shift = 16,
1961                 .width = 8,
1962         },
1963         .p = {
1964                 .pre_div_shift = 3,
1965                 .pre_div_width = 2,
1966         },
1967         .s = {
1968                 .src_sel_shift = 0,
1969                 .parent_map = gcc_pxo_pll8_map,
1970         },
1971         .freq_tbl = clk_tbl_usb,
1972         .clkr = {
1973                 .enable_reg = 0x2988,
1974                 .enable_mask = BIT(11),
1975                 .hw.init = &(struct clk_init_data){
1976                         .name = "usb_fs2_xcvr_fs_src",
1977                         .parent_names = gcc_pxo_pll8,
1978                         .num_parents = 2,
1979                         .ops = &clk_rcg_ops,
1980                         .flags = CLK_SET_RATE_GATE,
1981                 },
1982         }
1983 };
1984
1985 static const char *usb_fs2_xcvr_fs_src_p[] = { "usb_fs2_xcvr_fs_src" };
1986
1987 static struct clk_branch usb_fs2_xcvr_fs_clk = {
1988         .halt_reg = 0x2fcc,
1989         .halt_bit = 12,
1990         .clkr = {
1991                 .enable_reg = 0x2988,
1992                 .enable_mask = BIT(9),
1993                 .hw.init = &(struct clk_init_data){
1994                         .name = "usb_fs2_xcvr_fs_clk",
1995                         .parent_names = usb_fs2_xcvr_fs_src_p,
1996                         .num_parents = 1,
1997                         .ops = &clk_branch_ops,
1998                         .flags = CLK_SET_RATE_PARENT,
1999                 },
2000         },
2001 };
2002
2003 static struct clk_branch usb_fs2_system_clk = {
2004         .halt_reg = 0x2fcc,
2005         .halt_bit = 13,
2006         .clkr = {
2007                 .enable_reg = 0x298c,
2008                 .enable_mask = BIT(4),
2009                 .hw.init = &(struct clk_init_data){
2010                         .name = "usb_fs2_system_clk",
2011                         .parent_names = usb_fs2_xcvr_fs_src_p,
2012                         .num_parents = 1,
2013                         .ops = &clk_branch_ops,
2014                         .flags = CLK_SET_RATE_PARENT,
2015                 },
2016         },
2017 };
2018
2019 static struct clk_branch gsbi1_h_clk = {
2020         .halt_reg = 0x2fcc,
2021         .halt_bit = 11,
2022         .clkr = {
2023                 .enable_reg = 0x29c0,
2024                 .enable_mask = BIT(4),
2025                 .hw.init = &(struct clk_init_data){
2026                         .name = "gsbi1_h_clk",
2027                         .ops = &clk_branch_ops,
2028                         .flags = CLK_IS_ROOT,
2029                 },
2030         },
2031 };
2032
2033 static struct clk_branch gsbi2_h_clk = {
2034         .halt_reg = 0x2fcc,
2035         .halt_bit = 7,
2036         .clkr = {
2037                 .enable_reg = 0x29e0,
2038                 .enable_mask = BIT(4),
2039                 .hw.init = &(struct clk_init_data){
2040                         .name = "gsbi2_h_clk",
2041                         .ops = &clk_branch_ops,
2042                         .flags = CLK_IS_ROOT,
2043                 },
2044         },
2045 };
2046
2047 static struct clk_branch gsbi3_h_clk = {
2048         .halt_reg = 0x2fcc,
2049         .halt_bit = 3,
2050         .clkr = {
2051                 .enable_reg = 0x2a00,
2052                 .enable_mask = BIT(4),
2053                 .hw.init = &(struct clk_init_data){
2054                         .name = "gsbi3_h_clk",
2055                         .ops = &clk_branch_ops,
2056                         .flags = CLK_IS_ROOT,
2057                 },
2058         },
2059 };
2060
2061 static struct clk_branch gsbi4_h_clk = {
2062         .halt_reg = 0x2fd0,
2063         .halt_bit = 27,
2064         .clkr = {
2065                 .enable_reg = 0x2a20,
2066                 .enable_mask = BIT(4),
2067                 .hw.init = &(struct clk_init_data){
2068                         .name = "gsbi4_h_clk",
2069                         .ops = &clk_branch_ops,
2070                         .flags = CLK_IS_ROOT,
2071                 },
2072         },
2073 };
2074
2075 static struct clk_branch gsbi5_h_clk = {
2076         .halt_reg = 0x2fd0,
2077         .halt_bit = 23,
2078         .clkr = {
2079                 .enable_reg = 0x2a40,
2080                 .enable_mask = BIT(4),
2081                 .hw.init = &(struct clk_init_data){
2082                         .name = "gsbi5_h_clk",
2083                         .ops = &clk_branch_ops,
2084                         .flags = CLK_IS_ROOT,
2085                 },
2086         },
2087 };
2088
2089 static struct clk_branch gsbi6_h_clk = {
2090         .halt_reg = 0x2fd0,
2091         .halt_bit = 19,
2092         .clkr = {
2093                 .enable_reg = 0x2a60,
2094                 .enable_mask = BIT(4),
2095                 .hw.init = &(struct clk_init_data){
2096                         .name = "gsbi6_h_clk",
2097                         .ops = &clk_branch_ops,
2098                         .flags = CLK_IS_ROOT,
2099                 },
2100         },
2101 };
2102
2103 static struct clk_branch gsbi7_h_clk = {
2104         .halt_reg = 0x2fd0,
2105         .halt_bit = 15,
2106         .clkr = {
2107                 .enable_reg = 0x2a80,
2108                 .enable_mask = BIT(4),
2109                 .hw.init = &(struct clk_init_data){
2110                         .name = "gsbi7_h_clk",
2111                         .ops = &clk_branch_ops,
2112                         .flags = CLK_IS_ROOT,
2113                 },
2114         },
2115 };
2116
2117 static struct clk_branch gsbi8_h_clk = {
2118         .halt_reg = 0x2fd0,
2119         .halt_bit = 11,
2120         .clkr = {
2121                 .enable_reg = 0x2aa0,
2122                 .enable_mask = BIT(4),
2123                 .hw.init = &(struct clk_init_data){
2124                         .name = "gsbi8_h_clk",
2125                         .ops = &clk_branch_ops,
2126                         .flags = CLK_IS_ROOT,
2127                 },
2128         },
2129 };
2130
2131 static struct clk_branch gsbi9_h_clk = {
2132         .halt_reg = 0x2fd0,
2133         .halt_bit = 7,
2134         .clkr = {
2135                 .enable_reg = 0x2ac0,
2136                 .enable_mask = BIT(4),
2137                 .hw.init = &(struct clk_init_data){
2138                         .name = "gsbi9_h_clk",
2139                         .ops = &clk_branch_ops,
2140                         .flags = CLK_IS_ROOT,
2141                 },
2142         },
2143 };
2144
2145 static struct clk_branch gsbi10_h_clk = {
2146         .halt_reg = 0x2fd0,
2147         .halt_bit = 3,
2148         .clkr = {
2149                 .enable_reg = 0x2ae0,
2150                 .enable_mask = BIT(4),
2151                 .hw.init = &(struct clk_init_data){
2152                         .name = "gsbi10_h_clk",
2153                         .ops = &clk_branch_ops,
2154                         .flags = CLK_IS_ROOT,
2155                 },
2156         },
2157 };
2158
2159 static struct clk_branch gsbi11_h_clk = {
2160         .halt_reg = 0x2fd4,
2161         .halt_bit = 18,
2162         .clkr = {
2163                 .enable_reg = 0x2b00,
2164                 .enable_mask = BIT(4),
2165                 .hw.init = &(struct clk_init_data){
2166                         .name = "gsbi11_h_clk",
2167                         .ops = &clk_branch_ops,
2168                         .flags = CLK_IS_ROOT,
2169                 },
2170         },
2171 };
2172
2173 static struct clk_branch gsbi12_h_clk = {
2174         .halt_reg = 0x2fd4,
2175         .halt_bit = 14,
2176         .clkr = {
2177                 .enable_reg = 0x2b20,
2178                 .enable_mask = BIT(4),
2179                 .hw.init = &(struct clk_init_data){
2180                         .name = "gsbi12_h_clk",
2181                         .ops = &clk_branch_ops,
2182                         .flags = CLK_IS_ROOT,
2183                 },
2184         },
2185 };
2186
2187 static struct clk_branch tsif_h_clk = {
2188         .halt_reg = 0x2fd4,
2189         .halt_bit = 7,
2190         .clkr = {
2191                 .enable_reg = 0x2700,
2192                 .enable_mask = BIT(4),
2193                 .hw.init = &(struct clk_init_data){
2194                         .name = "tsif_h_clk",
2195                         .ops = &clk_branch_ops,
2196                         .flags = CLK_IS_ROOT,
2197                 },
2198         },
2199 };
2200
2201 static struct clk_branch usb_fs1_h_clk = {
2202         .halt_reg = 0x2fcc,
2203         .halt_bit = 17,
2204         .clkr = {
2205                 .enable_reg = 0x2960,
2206                 .enable_mask = BIT(4),
2207                 .hw.init = &(struct clk_init_data){
2208                         .name = "usb_fs1_h_clk",
2209                         .ops = &clk_branch_ops,
2210                         .flags = CLK_IS_ROOT,
2211                 },
2212         },
2213 };
2214
2215 static struct clk_branch usb_fs2_h_clk = {
2216         .halt_reg = 0x2fcc,
2217         .halt_bit = 14,
2218         .clkr = {
2219                 .enable_reg = 0x2980,
2220                 .enable_mask = BIT(4),
2221                 .hw.init = &(struct clk_init_data){
2222                         .name = "usb_fs2_h_clk",
2223                         .ops = &clk_branch_ops,
2224                         .flags = CLK_IS_ROOT,
2225                 },
2226         },
2227 };
2228
2229 static struct clk_branch usb_hs1_h_clk = {
2230         .halt_reg = 0x2fc8,
2231         .halt_bit = 1,
2232         .clkr = {
2233                 .enable_reg = 0x2900,
2234                 .enable_mask = BIT(4),
2235                 .hw.init = &(struct clk_init_data){
2236                         .name = "usb_hs1_h_clk",
2237                         .ops = &clk_branch_ops,
2238                         .flags = CLK_IS_ROOT,
2239                 },
2240         },
2241 };
2242
2243 static struct clk_branch sdc1_h_clk = {
2244         .halt_reg = 0x2fc8,
2245         .halt_bit = 11,
2246         .clkr = {
2247                 .enable_reg = 0x2820,
2248                 .enable_mask = BIT(4),
2249                 .hw.init = &(struct clk_init_data){
2250                         .name = "sdc1_h_clk",
2251                         .ops = &clk_branch_ops,
2252                         .flags = CLK_IS_ROOT,
2253                 },
2254         },
2255 };
2256
2257 static struct clk_branch sdc2_h_clk = {
2258         .halt_reg = 0x2fc8,
2259         .halt_bit = 10,
2260         .clkr = {
2261                 .enable_reg = 0x2840,
2262                 .enable_mask = BIT(4),
2263                 .hw.init = &(struct clk_init_data){
2264                         .name = "sdc2_h_clk",
2265                         .ops = &clk_branch_ops,
2266                         .flags = CLK_IS_ROOT,
2267                 },
2268         },
2269 };
2270
2271 static struct clk_branch sdc3_h_clk = {
2272         .halt_reg = 0x2fc8,
2273         .halt_bit = 9,
2274         .clkr = {
2275                 .enable_reg = 0x2860,
2276                 .enable_mask = BIT(4),
2277                 .hw.init = &(struct clk_init_data){
2278                         .name = "sdc3_h_clk",
2279                         .ops = &clk_branch_ops,
2280                         .flags = CLK_IS_ROOT,
2281                 },
2282         },
2283 };
2284
2285 static struct clk_branch sdc4_h_clk = {
2286         .halt_reg = 0x2fc8,
2287         .halt_bit = 8,
2288         .clkr = {
2289                 .enable_reg = 0x2880,
2290                 .enable_mask = BIT(4),
2291                 .hw.init = &(struct clk_init_data){
2292                         .name = "sdc4_h_clk",
2293                         .ops = &clk_branch_ops,
2294                         .flags = CLK_IS_ROOT,
2295                 },
2296         },
2297 };
2298
2299 static struct clk_branch sdc5_h_clk = {
2300         .halt_reg = 0x2fc8,
2301         .halt_bit = 7,
2302         .clkr = {
2303                 .enable_reg = 0x28a0,
2304                 .enable_mask = BIT(4),
2305                 .hw.init = &(struct clk_init_data){
2306                         .name = "sdc5_h_clk",
2307                         .ops = &clk_branch_ops,
2308                         .flags = CLK_IS_ROOT,
2309                 },
2310         },
2311 };
2312
2313 static struct clk_branch adm0_clk = {
2314         .halt_reg = 0x2fdc,
2315         .halt_check = BRANCH_HALT_VOTED,
2316         .halt_bit = 14,
2317         .clkr = {
2318                 .enable_reg = 0x3080,
2319                 .enable_mask = BIT(2),
2320                 .hw.init = &(struct clk_init_data){
2321                         .name = "adm0_clk",
2322                         .ops = &clk_branch_ops,
2323                         .flags = CLK_IS_ROOT,
2324                 },
2325         },
2326 };
2327
2328 static struct clk_branch adm0_pbus_clk = {
2329         .halt_reg = 0x2fdc,
2330         .halt_check = BRANCH_HALT_VOTED,
2331         .halt_bit = 13,
2332         .clkr = {
2333                 .enable_reg = 0x3080,
2334                 .enable_mask = BIT(3),
2335                 .hw.init = &(struct clk_init_data){
2336                         .name = "adm0_pbus_clk",
2337                         .ops = &clk_branch_ops,
2338                         .flags = CLK_IS_ROOT,
2339                 },
2340         },
2341 };
2342
2343 static struct clk_branch adm1_clk = {
2344         .halt_reg = 0x2fdc,
2345         .halt_bit = 12,
2346         .halt_check = BRANCH_HALT_VOTED,
2347         .clkr = {
2348                 .enable_reg = 0x3080,
2349                 .enable_mask = BIT(4),
2350                 .hw.init = &(struct clk_init_data){
2351                         .name = "adm1_clk",
2352                         .ops = &clk_branch_ops,
2353                         .flags = CLK_IS_ROOT,
2354                 },
2355         },
2356 };
2357
2358 static struct clk_branch adm1_pbus_clk = {
2359         .halt_reg = 0x2fdc,
2360         .halt_bit = 11,
2361         .halt_check = BRANCH_HALT_VOTED,
2362         .clkr = {
2363                 .enable_reg = 0x3080,
2364                 .enable_mask = BIT(5),
2365                 .hw.init = &(struct clk_init_data){
2366                         .name = "adm1_pbus_clk",
2367                         .ops = &clk_branch_ops,
2368                         .flags = CLK_IS_ROOT,
2369                 },
2370         },
2371 };
2372
2373 static struct clk_branch modem_ahb1_h_clk = {
2374         .halt_reg = 0x2fdc,
2375         .halt_bit = 8,
2376         .halt_check = BRANCH_HALT_VOTED,
2377         .clkr = {
2378                 .enable_reg = 0x3080,
2379                 .enable_mask = BIT(0),
2380                 .hw.init = &(struct clk_init_data){
2381                         .name = "modem_ahb1_h_clk",
2382                         .ops = &clk_branch_ops,
2383                         .flags = CLK_IS_ROOT,
2384                 },
2385         },
2386 };
2387
2388 static struct clk_branch modem_ahb2_h_clk = {
2389         .halt_reg = 0x2fdc,
2390         .halt_bit = 7,
2391         .halt_check = BRANCH_HALT_VOTED,
2392         .clkr = {
2393                 .enable_reg = 0x3080,
2394                 .enable_mask = BIT(1),
2395                 .hw.init = &(struct clk_init_data){
2396                         .name = "modem_ahb2_h_clk",
2397                         .ops = &clk_branch_ops,
2398                         .flags = CLK_IS_ROOT,
2399                 },
2400         },
2401 };
2402
2403 static struct clk_branch pmic_arb0_h_clk = {
2404         .halt_reg = 0x2fd8,
2405         .halt_check = BRANCH_HALT_VOTED,
2406         .halt_bit = 22,
2407         .clkr = {
2408                 .enable_reg = 0x3080,
2409                 .enable_mask = BIT(8),
2410                 .hw.init = &(struct clk_init_data){
2411                         .name = "pmic_arb0_h_clk",
2412                         .ops = &clk_branch_ops,
2413                         .flags = CLK_IS_ROOT,
2414                 },
2415         },
2416 };
2417
2418 static struct clk_branch pmic_arb1_h_clk = {
2419         .halt_reg = 0x2fd8,
2420         .halt_check = BRANCH_HALT_VOTED,
2421         .halt_bit = 21,
2422         .clkr = {
2423                 .enable_reg = 0x3080,
2424                 .enable_mask = BIT(9),
2425                 .hw.init = &(struct clk_init_data){
2426                         .name = "pmic_arb1_h_clk",
2427                         .ops = &clk_branch_ops,
2428                         .flags = CLK_IS_ROOT,
2429                 },
2430         },
2431 };
2432
2433 static struct clk_branch pmic_ssbi2_clk = {
2434         .halt_reg = 0x2fd8,
2435         .halt_check = BRANCH_HALT_VOTED,
2436         .halt_bit = 23,
2437         .clkr = {
2438                 .enable_reg = 0x3080,
2439                 .enable_mask = BIT(7),
2440                 .hw.init = &(struct clk_init_data){
2441                         .name = "pmic_ssbi2_clk",
2442                         .ops = &clk_branch_ops,
2443                         .flags = CLK_IS_ROOT,
2444                 },
2445         },
2446 };
2447
2448 static struct clk_branch rpm_msg_ram_h_clk = {
2449         .hwcg_reg = 0x27e0,
2450         .hwcg_bit = 6,
2451         .halt_reg = 0x2fd8,
2452         .halt_check = BRANCH_HALT_VOTED,
2453         .halt_bit = 12,
2454         .clkr = {
2455                 .enable_reg = 0x3080,
2456                 .enable_mask = BIT(6),
2457                 .hw.init = &(struct clk_init_data){
2458                         .name = "rpm_msg_ram_h_clk",
2459                         .ops = &clk_branch_ops,
2460                         .flags = CLK_IS_ROOT,
2461                 },
2462         },
2463 };
2464
2465 static struct clk_regmap *gcc_msm8660_clks[] = {
2466         [PLL8] = &pll8.clkr,
2467         [PLL8_VOTE] = &pll8_vote,
2468         [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
2469         [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
2470         [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
2471         [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
2472         [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
2473         [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
2474         [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
2475         [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
2476         [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
2477         [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
2478         [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
2479         [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
2480         [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
2481         [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
2482         [GSBI8_UART_SRC] = &gsbi8_uart_src.clkr,
2483         [GSBI8_UART_CLK] = &gsbi8_uart_clk.clkr,
2484         [GSBI9_UART_SRC] = &gsbi9_uart_src.clkr,
2485         [GSBI9_UART_CLK] = &gsbi9_uart_clk.clkr,
2486         [GSBI10_UART_SRC] = &gsbi10_uart_src.clkr,
2487         [GSBI10_UART_CLK] = &gsbi10_uart_clk.clkr,
2488         [GSBI11_UART_SRC] = &gsbi11_uart_src.clkr,
2489         [GSBI11_UART_CLK] = &gsbi11_uart_clk.clkr,
2490         [GSBI12_UART_SRC] = &gsbi12_uart_src.clkr,
2491         [GSBI12_UART_CLK] = &gsbi12_uart_clk.clkr,
2492         [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
2493         [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
2494         [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
2495         [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
2496         [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
2497         [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
2498         [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
2499         [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
2500         [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
2501         [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
2502         [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
2503         [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
2504         [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
2505         [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
2506         [GSBI8_QUP_SRC] = &gsbi8_qup_src.clkr,
2507         [GSBI8_QUP_CLK] = &gsbi8_qup_clk.clkr,
2508         [GSBI9_QUP_SRC] = &gsbi9_qup_src.clkr,
2509         [GSBI9_QUP_CLK] = &gsbi9_qup_clk.clkr,
2510         [GSBI10_QUP_SRC] = &gsbi10_qup_src.clkr,
2511         [GSBI10_QUP_CLK] = &gsbi10_qup_clk.clkr,
2512         [GSBI11_QUP_SRC] = &gsbi11_qup_src.clkr,
2513         [GSBI11_QUP_CLK] = &gsbi11_qup_clk.clkr,
2514         [GSBI12_QUP_SRC] = &gsbi12_qup_src.clkr,
2515         [GSBI12_QUP_CLK] = &gsbi12_qup_clk.clkr,
2516         [GP0_SRC] = &gp0_src.clkr,
2517         [GP0_CLK] = &gp0_clk.clkr,
2518         [GP1_SRC] = &gp1_src.clkr,
2519         [GP1_CLK] = &gp1_clk.clkr,
2520         [GP2_SRC] = &gp2_src.clkr,
2521         [GP2_CLK] = &gp2_clk.clkr,
2522         [PMEM_CLK] = &pmem_clk.clkr,
2523         [PRNG_SRC] = &prng_src.clkr,
2524         [PRNG_CLK] = &prng_clk.clkr,
2525         [SDC1_SRC] = &sdc1_src.clkr,
2526         [SDC1_CLK] = &sdc1_clk.clkr,
2527         [SDC2_SRC] = &sdc2_src.clkr,
2528         [SDC2_CLK] = &sdc2_clk.clkr,
2529         [SDC3_SRC] = &sdc3_src.clkr,
2530         [SDC3_CLK] = &sdc3_clk.clkr,
2531         [SDC4_SRC] = &sdc4_src.clkr,
2532         [SDC4_CLK] = &sdc4_clk.clkr,
2533         [SDC5_SRC] = &sdc5_src.clkr,
2534         [SDC5_CLK] = &sdc5_clk.clkr,
2535         [TSIF_REF_SRC] = &tsif_ref_src.clkr,
2536         [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
2537         [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
2538         [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
2539         [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
2540         [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
2541         [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
2542         [USB_FS2_XCVR_FS_SRC] = &usb_fs2_xcvr_fs_src.clkr,
2543         [USB_FS2_XCVR_FS_CLK] = &usb_fs2_xcvr_fs_clk.clkr,
2544         [USB_FS2_SYSTEM_CLK] = &usb_fs2_system_clk.clkr,
2545         [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
2546         [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
2547         [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
2548         [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
2549         [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
2550         [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
2551         [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
2552         [GSBI8_H_CLK] = &gsbi8_h_clk.clkr,
2553         [GSBI9_H_CLK] = &gsbi9_h_clk.clkr,
2554         [GSBI10_H_CLK] = &gsbi10_h_clk.clkr,
2555         [GSBI11_H_CLK] = &gsbi11_h_clk.clkr,
2556         [GSBI12_H_CLK] = &gsbi12_h_clk.clkr,
2557         [TSIF_H_CLK] = &tsif_h_clk.clkr,
2558         [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
2559         [USB_FS2_H_CLK] = &usb_fs2_h_clk.clkr,
2560         [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
2561         [SDC1_H_CLK] = &sdc1_h_clk.clkr,
2562         [SDC2_H_CLK] = &sdc2_h_clk.clkr,
2563         [SDC3_H_CLK] = &sdc3_h_clk.clkr,
2564         [SDC4_H_CLK] = &sdc4_h_clk.clkr,
2565         [SDC5_H_CLK] = &sdc5_h_clk.clkr,
2566         [ADM0_CLK] = &adm0_clk.clkr,
2567         [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
2568         [ADM1_CLK] = &adm1_clk.clkr,
2569         [ADM1_PBUS_CLK] = &adm1_pbus_clk.clkr,
2570         [MODEM_AHB1_H_CLK] = &modem_ahb1_h_clk.clkr,
2571         [MODEM_AHB2_H_CLK] = &modem_ahb2_h_clk.clkr,
2572         [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
2573         [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
2574         [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
2575         [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
2576 };
2577
2578 static const struct qcom_reset_map gcc_msm8660_resets[] = {
2579         [AFAB_CORE_RESET] = { 0x2080, 7 },
2580         [SCSS_SYS_RESET] = { 0x20b4, 1 },
2581         [SCSS_SYS_POR_RESET] = { 0x20b4 },
2582         [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
2583         [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
2584         [AFAB_SMPSS_M0_RESET] = { 0x20b8 },
2585         [AFAB_EBI1_S_RESET] = { 0x20c0, 7 },
2586         [SFAB_CORE_RESET] = { 0x2120, 7 },
2587         [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
2588         [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
2589         [SFAB_ADM0_M2_RESET] = { 0x21e4, 7 },
2590         [ADM0_C2_RESET] = { 0x220c, 4 },
2591         [ADM0_C1_RESET] = { 0x220c, 3 },
2592         [ADM0_C0_RESET] = { 0x220c, 2 },
2593         [ADM0_PBUS_RESET] = { 0x220c, 1 },
2594         [ADM0_RESET] = { 0x220c },
2595         [SFAB_ADM1_M0_RESET] = { 0x2220, 7 },
2596         [SFAB_ADM1_M1_RESET] = { 0x2224, 7 },
2597         [SFAB_ADM1_M2_RESET] = { 0x2228, 7 },
2598         [MMFAB_ADM1_M3_RESET] = { 0x2240, 7 },
2599         [ADM1_C3_RESET] = { 0x226c, 5 },
2600         [ADM1_C2_RESET] = { 0x226c, 4 },
2601         [ADM1_C1_RESET] = { 0x226c, 3 },
2602         [ADM1_C0_RESET] = { 0x226c, 2 },
2603         [ADM1_PBUS_RESET] = { 0x226c, 1 },
2604         [ADM1_RESET] = { 0x226c },
2605         [IMEM0_RESET] = { 0x2280, 7 },
2606         [SFAB_LPASS_Q6_RESET] = { 0x23a0, 7 },
2607         [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
2608         [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
2609         [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
2610         [DFAB_CORE_RESET] = { 0x24ac, 7 },
2611         [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
2612         [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
2613         [DFAB_SWAY0_RESET] = { 0x2540, 7 },
2614         [DFAB_SWAY1_RESET] = { 0x2544, 7 },
2615         [DFAB_ARB0_RESET] = { 0x2560, 7 },
2616         [DFAB_ARB1_RESET] = { 0x2564, 7 },
2617         [PPSS_PROC_RESET] = { 0x2594, 1 },
2618         [PPSS_RESET] = { 0x2594 },
2619         [PMEM_RESET] = { 0x25a0, 7 },
2620         [DMA_BAM_RESET] = { 0x25c0, 7 },
2621         [SIC_RESET] = { 0x25e0, 7 },
2622         [SPS_TIC_RESET] = { 0x2600, 7 },
2623         [CFBP0_RESET] = { 0x2650, 7 },
2624         [CFBP1_RESET] = { 0x2654, 7 },
2625         [CFBP2_RESET] = { 0x2658, 7 },
2626         [EBI2_RESET] = { 0x2664, 7 },
2627         [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
2628         [CFPB_MASTER_RESET] = { 0x26a0, 7 },
2629         [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
2630         [CFPB_SPLITTER_RESET] = { 0x26e0, 7 },
2631         [TSIF_RESET] = { 0x2700, 7 },
2632         [CE1_RESET] = { 0x2720, 7 },
2633         [CE2_RESET] = { 0x2740, 7 },
2634         [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
2635         [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
2636         [RPM_PROC_RESET] = { 0x27c0, 7 },
2637         [RPM_BUS_RESET] = { 0x27c4, 7 },
2638         [RPM_MSG_RAM_RESET] = { 0x27e0, 7 },
2639         [PMIC_ARB0_RESET] = { 0x2800, 7 },
2640         [PMIC_ARB1_RESET] = { 0x2804, 7 },
2641         [PMIC_SSBI2_RESET] = { 0x280c, 12 },
2642         [SDC1_RESET] = { 0x2830 },
2643         [SDC2_RESET] = { 0x2850 },
2644         [SDC3_RESET] = { 0x2870 },
2645         [SDC4_RESET] = { 0x2890 },
2646         [SDC5_RESET] = { 0x28b0 },
2647         [USB_HS1_RESET] = { 0x2910 },
2648         [USB_HS2_XCVR_RESET] = { 0x2934, 1 },
2649         [USB_HS2_RESET] = { 0x2934 },
2650         [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
2651         [USB_FS1_RESET] = { 0x2974 },
2652         [USB_FS2_XCVR_RESET] = { 0x2994, 1 },
2653         [USB_FS2_RESET] = { 0x2994 },
2654         [GSBI1_RESET] = { 0x29dc },
2655         [GSBI2_RESET] = { 0x29fc },
2656         [GSBI3_RESET] = { 0x2a1c },
2657         [GSBI4_RESET] = { 0x2a3c },
2658         [GSBI5_RESET] = { 0x2a5c },
2659         [GSBI6_RESET] = { 0x2a7c },
2660         [GSBI7_RESET] = { 0x2a9c },
2661         [GSBI8_RESET] = { 0x2abc },
2662         [GSBI9_RESET] = { 0x2adc },
2663         [GSBI10_RESET] = { 0x2afc },
2664         [GSBI11_RESET] = { 0x2b1c },
2665         [GSBI12_RESET] = { 0x2b3c },
2666         [SPDM_RESET] = { 0x2b6c },
2667         [SEC_CTRL_RESET] = { 0x2b80, 7 },
2668         [TLMM_H_RESET] = { 0x2ba0, 7 },
2669         [TLMM_RESET] = { 0x2ba4, 7 },
2670         [MARRM_PWRON_RESET] = { 0x2bd4, 1 },
2671         [MARM_RESET] = { 0x2bd4 },
2672         [MAHB1_RESET] = { 0x2be4, 7 },
2673         [SFAB_MSS_S_RESET] = { 0x2c00, 7 },
2674         [MAHB2_RESET] = { 0x2c20, 7 },
2675         [MODEM_SW_AHB_RESET] = { 0x2c48, 1 },
2676         [MODEM_RESET] = { 0x2c48 },
2677         [SFAB_MSS_MDM1_RESET] = { 0x2c4c, 1 },
2678         [SFAB_MSS_MDM0_RESET] = { 0x2c4c },
2679         [MSS_SLP_RESET] = { 0x2c60, 7 },
2680         [MSS_MARM_SAW_RESET] = { 0x2c68, 1 },
2681         [MSS_WDOG_RESET] = { 0x2c68 },
2682         [TSSC_RESET] = { 0x2ca0, 7 },
2683         [PDM_RESET] = { 0x2cc0, 12 },
2684         [SCSS_CORE0_RESET] = { 0x2d60, 1 },
2685         [SCSS_CORE0_POR_RESET] = { 0x2d60 },
2686         [SCSS_CORE1_RESET] = { 0x2d80, 1 },
2687         [SCSS_CORE1_POR_RESET] = { 0x2d80 },
2688         [MPM_RESET] = { 0x2da4, 1 },
2689         [EBI1_1X_DIV_RESET] = { 0x2dec, 9 },
2690         [EBI1_RESET] = { 0x2dec, 7 },
2691         [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
2692         [USB_PHY0_RESET] = { 0x2e20 },
2693         [USB_PHY1_RESET] = { 0x2e40 },
2694         [PRNG_RESET] = { 0x2e80, 12 },
2695 };
2696
2697 static const struct regmap_config gcc_msm8660_regmap_config = {
2698         .reg_bits       = 32,
2699         .reg_stride     = 4,
2700         .val_bits       = 32,
2701         .max_register   = 0x363c,
2702         .fast_io        = true,
2703 };
2704
2705 static const struct qcom_cc_desc gcc_msm8660_desc = {
2706         .config = &gcc_msm8660_regmap_config,
2707         .clks = gcc_msm8660_clks,
2708         .num_clks = ARRAY_SIZE(gcc_msm8660_clks),
2709         .resets = gcc_msm8660_resets,
2710         .num_resets = ARRAY_SIZE(gcc_msm8660_resets),
2711 };
2712
2713 static const struct of_device_id gcc_msm8660_match_table[] = {
2714         { .compatible = "qcom,gcc-msm8660" },
2715         { }
2716 };
2717 MODULE_DEVICE_TABLE(of, gcc_msm8660_match_table);
2718
2719 static int gcc_msm8660_probe(struct platform_device *pdev)
2720 {
2721         struct clk *clk;
2722         struct device *dev = &pdev->dev;
2723
2724         /* Temporary until RPM clocks supported */
2725         clk = clk_register_fixed_rate(dev, "cxo", NULL, CLK_IS_ROOT, 19200000);
2726         if (IS_ERR(clk))
2727                 return PTR_ERR(clk);
2728
2729         clk = clk_register_fixed_rate(dev, "pxo", NULL, CLK_IS_ROOT, 27000000);
2730         if (IS_ERR(clk))
2731                 return PTR_ERR(clk);
2732
2733         return qcom_cc_probe(pdev, &gcc_msm8660_desc);
2734 }
2735
2736 static int gcc_msm8660_remove(struct platform_device *pdev)
2737 {
2738         qcom_cc_remove(pdev);
2739         return 0;
2740 }
2741
2742 static struct platform_driver gcc_msm8660_driver = {
2743         .probe          = gcc_msm8660_probe,
2744         .remove         = gcc_msm8660_remove,
2745         .driver         = {
2746                 .name   = "gcc-msm8660",
2747                 .owner  = THIS_MODULE,
2748                 .of_match_table = gcc_msm8660_match_table,
2749         },
2750 };
2751
2752 static int __init gcc_msm8660_init(void)
2753 {
2754         return platform_driver_register(&gcc_msm8660_driver);
2755 }
2756 core_initcall(gcc_msm8660_init);
2757
2758 static void __exit gcc_msm8660_exit(void)
2759 {
2760         platform_driver_unregister(&gcc_msm8660_driver);
2761 }
2762 module_exit(gcc_msm8660_exit);
2763
2764 MODULE_DESCRIPTION("GCC MSM 8660 Driver");
2765 MODULE_LICENSE("GPL v2");
2766 MODULE_ALIAS("platform:gcc-msm8660");