2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Author: Padmavathi Venna <padma.v@samsung.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * Common Clock Framework support for Audio Subsystem Clock Controller.
12 #include <linux/slab.h>
14 #include <linux/clk.h>
15 #include <linux/clk-provider.h>
16 #include <linux/of_address.h>
17 #include <linux/of_device.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
22 #include <dt-bindings/clock/exynos-audss-clk.h>
24 static DEFINE_SPINLOCK(lock);
25 static struct clk **clk_table;
26 static void __iomem *reg_base;
27 static struct clk_onecell_data clk_data;
29 * On Exynos5420 this will be a clock which has to be enabled before any
30 * access to audss registers. Typically a child of EPLL.
32 * On other platforms this will be -ENODEV.
34 static struct clk *epll;
36 #define ASS_CLK_SRC 0x0
37 #define ASS_CLK_DIV 0x4
38 #define ASS_CLK_GATE 0x8
40 #ifdef CONFIG_PM_SLEEP
41 static unsigned long reg_save[][2] = {
47 static int exynos_audss_clk_suspend(void)
51 for (i = 0; i < ARRAY_SIZE(reg_save); i++)
52 reg_save[i][1] = readl(reg_base + reg_save[i][0]);
57 static void exynos_audss_clk_resume(void)
61 for (i = 0; i < ARRAY_SIZE(reg_save); i++)
62 writel(reg_save[i][1], reg_base + reg_save[i][0]);
65 static struct syscore_ops exynos_audss_clk_syscore_ops = {
66 .suspend = exynos_audss_clk_suspend,
67 .resume = exynos_audss_clk_resume,
69 #endif /* CONFIG_PM_SLEEP */
71 struct exynos_audss_clk_drvdata {
72 unsigned int has_adma_clk:1;
73 unsigned int has_mst_clk:1;
74 unsigned int enable_epll:1;
75 unsigned int num_clks;
78 static const struct exynos_audss_clk_drvdata exynos4210_drvdata = {
79 .num_clks = EXYNOS_AUDSS_MAX_CLKS - 1,
82 static const struct exynos_audss_clk_drvdata exynos5410_drvdata = {
83 .num_clks = EXYNOS_AUDSS_MAX_CLKS - 1,
87 static const struct exynos_audss_clk_drvdata exynos5420_drvdata = {
88 .num_clks = EXYNOS_AUDSS_MAX_CLKS,
93 static const struct of_device_id exynos_audss_clk_of_match[] = {
95 .compatible = "samsung,exynos4210-audss-clock",
96 .data = &exynos4210_drvdata,
98 .compatible = "samsung,exynos5250-audss-clock",
99 .data = &exynos4210_drvdata,
101 .compatible = "samsung,exynos5410-audss-clock",
102 .data = &exynos5410_drvdata,
104 .compatible = "samsung,exynos5420-audss-clock",
105 .data = &exynos5420_drvdata,
110 static void exynos_audss_clk_teardown(void)
114 for (i = EXYNOS_MOUT_AUDSS; i < EXYNOS_DOUT_SRP; i++) {
115 if (!IS_ERR(clk_table[i]))
116 clk_unregister_mux(clk_table[i]);
119 for (; i < EXYNOS_SRP_CLK; i++) {
120 if (!IS_ERR(clk_table[i]))
121 clk_unregister_divider(clk_table[i]);
124 for (; i < clk_data.clk_num; i++) {
125 if (!IS_ERR(clk_table[i]))
126 clk_unregister_gate(clk_table[i]);
130 /* register exynos_audss clocks */
131 static int exynos_audss_clk_probe(struct platform_device *pdev)
133 const char *mout_audss_p[] = {"fin_pll", "fout_epll"};
134 const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"};
135 const char *sclk_pcm_p = "sclk_pcm0";
136 struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in;
137 const struct exynos_audss_clk_drvdata *variant;
138 struct resource *res;
141 variant = of_device_get_match_data(&pdev->dev);
145 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
146 reg_base = devm_ioremap_resource(&pdev->dev, res);
147 if (IS_ERR(reg_base)) {
148 dev_err(&pdev->dev, "failed to map audss registers\n");
149 return PTR_ERR(reg_base);
152 epll = ERR_PTR(-ENODEV);
154 clk_table = devm_kzalloc(&pdev->dev,
155 sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
160 clk_data.clks = clk_table;
161 clk_data.clk_num = variant->num_clks;
163 pll_ref = devm_clk_get(&pdev->dev, "pll_ref");
164 pll_in = devm_clk_get(&pdev->dev, "pll_in");
165 if (!IS_ERR(pll_ref))
166 mout_audss_p[0] = __clk_get_name(pll_ref);
167 if (!IS_ERR(pll_in)) {
168 mout_audss_p[1] = __clk_get_name(pll_in);
170 if (variant->enable_epll) {
173 ret = clk_prepare_enable(epll);
176 "failed to prepare the epll clock\n");
181 clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
182 mout_audss_p, ARRAY_SIZE(mout_audss_p),
183 CLK_SET_RATE_NO_REPARENT,
184 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
186 cdclk = devm_clk_get(&pdev->dev, "cdclk");
187 sclk_audio = devm_clk_get(&pdev->dev, "sclk_audio");
189 mout_i2s_p[1] = __clk_get_name(cdclk);
190 if (!IS_ERR(sclk_audio))
191 mout_i2s_p[2] = __clk_get_name(sclk_audio);
192 clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s",
193 mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
194 CLK_SET_RATE_NO_REPARENT,
195 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
197 clk_table[EXYNOS_DOUT_SRP] = clk_register_divider(NULL, "dout_srp",
198 "mout_audss", 0, reg_base + ASS_CLK_DIV, 0, 4,
201 clk_table[EXYNOS_DOUT_AUD_BUS] = clk_register_divider(NULL,
202 "dout_aud_bus", "dout_srp", 0,
203 reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
205 clk_table[EXYNOS_DOUT_I2S] = clk_register_divider(NULL, "dout_i2s",
206 "mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0,
209 clk_table[EXYNOS_SRP_CLK] = clk_register_gate(NULL, "srp_clk",
210 "dout_srp", CLK_SET_RATE_PARENT,
211 reg_base + ASS_CLK_GATE, 0, 0, &lock);
213 clk_table[EXYNOS_I2S_BUS] = clk_register_gate(NULL, "i2s_bus",
214 "dout_aud_bus", CLK_SET_RATE_PARENT,
215 reg_base + ASS_CLK_GATE, 2, 0, &lock);
217 clk_table[EXYNOS_SCLK_I2S] = clk_register_gate(NULL, "sclk_i2s",
218 "dout_i2s", CLK_SET_RATE_PARENT,
219 reg_base + ASS_CLK_GATE, 3, 0, &lock);
221 clk_table[EXYNOS_PCM_BUS] = clk_register_gate(NULL, "pcm_bus",
222 "sclk_pcm", CLK_SET_RATE_PARENT,
223 reg_base + ASS_CLK_GATE, 4, 0, &lock);
225 sclk_pcm_in = devm_clk_get(&pdev->dev, "sclk_pcm_in");
226 if (!IS_ERR(sclk_pcm_in))
227 sclk_pcm_p = __clk_get_name(sclk_pcm_in);
228 clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm",
229 sclk_pcm_p, CLK_SET_RATE_PARENT,
230 reg_base + ASS_CLK_GATE, 5, 0, &lock);
232 if (variant->has_adma_clk) {
233 clk_table[EXYNOS_ADMA] = clk_register_gate(NULL, "adma",
234 "dout_srp", CLK_SET_RATE_PARENT,
235 reg_base + ASS_CLK_GATE, 9, 0, &lock);
238 for (i = 0; i < clk_data.clk_num; i++) {
239 if (IS_ERR(clk_table[i])) {
240 dev_err(&pdev->dev, "failed to register clock %d\n", i);
241 ret = PTR_ERR(clk_table[i]);
246 ret = of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get,
249 dev_err(&pdev->dev, "failed to add clock provider\n");
253 #ifdef CONFIG_PM_SLEEP
254 register_syscore_ops(&exynos_audss_clk_syscore_ops);
259 exynos_audss_clk_teardown();
262 clk_disable_unprepare(epll);
267 static int exynos_audss_clk_remove(struct platform_device *pdev)
269 #ifdef CONFIG_PM_SLEEP
270 unregister_syscore_ops(&exynos_audss_clk_syscore_ops);
273 of_clk_del_provider(pdev->dev.of_node);
275 exynos_audss_clk_teardown();
278 clk_disable_unprepare(epll);
283 static struct platform_driver exynos_audss_clk_driver = {
285 .name = "exynos-audss-clk",
286 .of_match_table = exynos_audss_clk_of_match,
288 .probe = exynos_audss_clk_probe,
289 .remove = exynos_audss_clk_remove,
292 module_platform_driver(exynos_audss_clk_driver);
294 MODULE_AUTHOR("Padmavathi Venna <padma.v@samsung.com>");
295 MODULE_DESCRIPTION("Exynos Audio Subsystem Clock Controller");
296 MODULE_LICENSE("GPL v2");
297 MODULE_ALIAS("platform:exynos-audss-clk");