2 * clkgen-mux.c: ST GEN-MUX Clock driver
4 * Copyright (C) 2014 STMicroelectronics (R&D) Limited
6 * Authors: Stephen Gallimore <stephen.gallimore@st.com>
7 * Pankaj Dev <pankaj.dev@st.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
16 #include <linux/slab.h>
17 #include <linux/of_address.h>
18 #include <linux/clk.h>
19 #include <linux/clk-provider.h>
21 static DEFINE_SPINLOCK(clkgena_divmux_lock);
22 static DEFINE_SPINLOCK(clkgenf_lock);
24 static const char ** __init clkgen_mux_get_parents(struct device_node *np,
30 nparents = of_clk_get_parent_count(np);
31 if (WARN_ON(nparents <= 0))
32 return ERR_PTR(-EINVAL);
34 parents = kcalloc(nparents, sizeof(const char *), GFP_KERNEL);
36 return ERR_PTR(-ENOMEM);
38 *num_parents = of_clk_parent_fill(np, parents, nparents);
43 * DOC: Clock mux with a programmable divider on each of its three inputs.
44 * The mux has an input setting which effectively gates its output.
46 * Traits of this clock:
47 * prepare - clk_(un)prepare only ensures parent is (un)prepared
48 * enable - clk_enable and clk_disable are functional & control gating
49 * rate - set rate is supported
50 * parent - set/get parent
55 struct clkgena_divmux {
57 /* Subclassed mux and divider structures */
59 struct clk_divider div[NUM_INPUTS];
60 /* Enable/running feedback register bits for each input */
61 void __iomem *feedback_reg[NUM_INPUTS];
67 #define to_clkgena_divmux(_hw) container_of(_hw, struct clkgena_divmux, hw)
69 struct clkgena_divmux_data {
74 int div_offsets[NUM_INPUTS];
75 int fb_offsets[NUM_INPUTS];
79 #define CKGAX_CLKOPSRC_SWITCH_OFF 0x3
81 static int clkgena_divmux_is_running(struct clkgena_divmux *mux)
83 u32 regval = readl(mux->feedback_reg[mux->muxsel]);
84 u32 running = regval & BIT(mux->feedback_bit_idx);
88 static int clkgena_divmux_enable(struct clk_hw *hw)
90 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
91 struct clk_hw *mux_hw = &genamux->mux.hw;
92 unsigned long timeout;
95 __clk_hw_set_clk(mux_hw, hw);
97 ret = clk_mux_ops.set_parent(mux_hw, genamux->muxsel);
101 timeout = jiffies + msecs_to_jiffies(10);
103 while (!clkgena_divmux_is_running(genamux)) {
104 if (time_after(jiffies, timeout))
112 static void clkgena_divmux_disable(struct clk_hw *hw)
114 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
115 struct clk_hw *mux_hw = &genamux->mux.hw;
117 __clk_hw_set_clk(mux_hw, hw);
119 clk_mux_ops.set_parent(mux_hw, CKGAX_CLKOPSRC_SWITCH_OFF);
122 static int clkgena_divmux_is_enabled(struct clk_hw *hw)
124 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
125 struct clk_hw *mux_hw = &genamux->mux.hw;
127 __clk_hw_set_clk(mux_hw, hw);
129 return (s8)clk_mux_ops.get_parent(mux_hw) > 0;
132 static u8 clkgena_divmux_get_parent(struct clk_hw *hw)
134 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
135 struct clk_hw *mux_hw = &genamux->mux.hw;
137 __clk_hw_set_clk(mux_hw, hw);
139 genamux->muxsel = clk_mux_ops.get_parent(mux_hw);
140 if ((s8)genamux->muxsel < 0) {
141 pr_debug("%s: %s: Invalid parent, setting to default.\n",
142 __func__, clk_hw_get_name(hw));
146 return genamux->muxsel;
149 static int clkgena_divmux_set_parent(struct clk_hw *hw, u8 index)
151 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
153 if (index >= CKGAX_CLKOPSRC_SWITCH_OFF)
156 genamux->muxsel = index;
159 * If the mux is already enabled, call enable directly to set the
160 * new mux position and wait for it to start running again. Otherwise
163 if (clkgena_divmux_is_enabled(hw))
164 clkgena_divmux_enable(hw);
169 static unsigned long clkgena_divmux_recalc_rate(struct clk_hw *hw,
170 unsigned long parent_rate)
172 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
173 struct clk_hw *div_hw = &genamux->div[genamux->muxsel].hw;
175 __clk_hw_set_clk(div_hw, hw);
177 return clk_divider_ops.recalc_rate(div_hw, parent_rate);
180 static int clkgena_divmux_set_rate(struct clk_hw *hw, unsigned long rate,
181 unsigned long parent_rate)
183 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
184 struct clk_hw *div_hw = &genamux->div[genamux->muxsel].hw;
186 __clk_hw_set_clk(div_hw, hw);
188 return clk_divider_ops.set_rate(div_hw, rate, parent_rate);
191 static long clkgena_divmux_round_rate(struct clk_hw *hw, unsigned long rate,
192 unsigned long *prate)
194 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
195 struct clk_hw *div_hw = &genamux->div[genamux->muxsel].hw;
197 __clk_hw_set_clk(div_hw, hw);
199 return clk_divider_ops.round_rate(div_hw, rate, prate);
202 static const struct clk_ops clkgena_divmux_ops = {
203 .enable = clkgena_divmux_enable,
204 .disable = clkgena_divmux_disable,
205 .is_enabled = clkgena_divmux_is_enabled,
206 .get_parent = clkgena_divmux_get_parent,
207 .set_parent = clkgena_divmux_set_parent,
208 .round_rate = clkgena_divmux_round_rate,
209 .recalc_rate = clkgena_divmux_recalc_rate,
210 .set_rate = clkgena_divmux_set_rate,
214 * clk_register_genamux - register a genamux clock with the clock framework
216 static struct clk * __init clk_register_genamux(const char *name,
217 const char **parent_names, u8 num_parents,
219 const struct clkgena_divmux_data *muxdata,
223 * Fixed constants across all ClockgenA variants
225 const int mux_width = 2;
226 const int divider_width = 5;
227 struct clkgena_divmux *genamux;
229 struct clk_init_data init;
232 genamux = kzalloc(sizeof(*genamux), GFP_KERNEL);
234 return ERR_PTR(-ENOMEM);
237 init.ops = &clkgena_divmux_ops;
238 init.flags = CLK_IS_BASIC | CLK_GET_RATE_NOCACHE;
239 init.parent_names = parent_names;
240 init.num_parents = num_parents;
242 genamux->mux.lock = &clkgena_divmux_lock;
243 genamux->mux.mask = BIT(mux_width) - 1;
244 genamux->mux.shift = muxdata->mux_start_bit + (idx * mux_width);
245 if (genamux->mux.shift > 31) {
247 * We have spilled into the second mux register so
248 * adjust the register address and the bit shift accordingly
250 genamux->mux.reg = reg + muxdata->mux_offset2;
251 genamux->mux.shift -= 32;
253 genamux->mux.reg = reg + muxdata->mux_offset;
256 for (i = 0; i < NUM_INPUTS; i++) {
258 * Divider config for each input
260 void __iomem *divbase = reg + muxdata->div_offsets[i];
261 genamux->div[i].width = divider_width;
262 genamux->div[i].reg = divbase + (idx * sizeof(u32));
265 * Mux enabled/running feedback register for each input.
267 genamux->feedback_reg[i] = reg + muxdata->fb_offsets[i];
270 genamux->feedback_bit_idx = muxdata->fb_start_bit_idx + idx;
271 genamux->hw.init = &init;
273 clk = clk_register(NULL, &genamux->hw);
279 pr_debug("%s: parent %s rate %lu\n",
281 __clk_get_name(clk_get_parent(clk)),
287 static struct clkgena_divmux_data st_divmux_c65hs = {
291 .div_offsets = { 0x800, 0x900, 0xb00 },
292 .fb_offsets = { 0x18, 0x1c, 0x20 },
293 .fb_start_bit_idx = 0,
296 static struct clkgena_divmux_data st_divmux_c65ls = {
301 .div_offsets = { 0x810, 0xa10, 0xb10 },
302 .fb_offsets = { 0x18, 0x1c, 0x20 },
303 .fb_start_bit_idx = 4,
306 static struct clkgena_divmux_data st_divmux_c32odf0 = {
310 .div_offsets = { 0x800, 0x900, 0xa60 },
311 .fb_offsets = { 0x2c, 0x24, 0x28 },
312 .fb_start_bit_idx = 0,
315 static struct clkgena_divmux_data st_divmux_c32odf1 = {
319 .div_offsets = { 0x820, 0x980, 0xa80 },
320 .fb_offsets = { 0x2c, 0x24, 0x28 },
321 .fb_start_bit_idx = 8,
324 static struct clkgena_divmux_data st_divmux_c32odf2 = {
328 .div_offsets = { 0x840, 0xa20, 0xb10 },
329 .fb_offsets = { 0x2c, 0x24, 0x28 },
330 .fb_start_bit_idx = 16,
333 static struct clkgena_divmux_data st_divmux_c32odf3 = {
337 .div_offsets = { 0x860, 0xa40, 0xb30 },
338 .fb_offsets = { 0x2c, 0x24, 0x28 },
339 .fb_start_bit_idx = 24,
342 static const struct of_device_id clkgena_divmux_of_match[] = {
344 .compatible = "st,clkgena-divmux-c65-hs",
345 .data = &st_divmux_c65hs,
348 .compatible = "st,clkgena-divmux-c65-ls",
349 .data = &st_divmux_c65ls,
352 .compatible = "st,clkgena-divmux-c32-odf0",
353 .data = &st_divmux_c32odf0,
356 .compatible = "st,clkgena-divmux-c32-odf1",
357 .data = &st_divmux_c32odf1,
360 .compatible = "st,clkgena-divmux-c32-odf2",
361 .data = &st_divmux_c32odf2,
364 .compatible = "st,clkgena-divmux-c32-odf3",
365 .data = &st_divmux_c32odf3,
370 static void __iomem * __init clkgen_get_register_base(struct device_node *np)
372 struct device_node *pnode;
375 pnode = of_get_parent(np);
379 reg = of_iomap(pnode, 0);
385 static void __init st_of_clkgena_divmux_setup(struct device_node *np)
387 const struct of_device_id *match;
388 const struct clkgena_divmux_data *data;
389 struct clk_onecell_data *clk_data;
391 const char **parents;
392 int num_parents = 0, i;
394 match = of_match_node(clkgena_divmux_of_match, np);
400 reg = clkgen_get_register_base(np);
404 parents = clkgen_mux_get_parents(np, &num_parents);
408 clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
412 clk_data->clk_num = data->num_outputs;
413 clk_data->clks = kcalloc(clk_data->clk_num, sizeof(struct clk *),
419 for (i = 0; i < clk_data->clk_num; i++) {
421 const char *clk_name;
423 if (of_property_read_string_index(np, "clock-output-names",
428 * If we read an empty clock name then the output is unused
430 if (*clk_name == '\0')
433 clk = clk_register_genamux(clk_name, parents, num_parents,
439 clk_data->clks[i] = clk;
444 of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
447 kfree(clk_data->clks);
455 CLK_OF_DECLARE(clkgenadivmux, "st,clkgena-divmux", st_of_clkgena_divmux_setup);
457 struct clkgena_prediv_data {
460 struct clk_div_table *table;
463 static struct clk_div_table prediv_table16[] = {
464 { .val = 0, .div = 1 },
465 { .val = 1, .div = 16 },
469 static struct clkgena_prediv_data prediv_c65_data = {
472 .table = prediv_table16,
475 static struct clkgena_prediv_data prediv_c32_data = {
478 .table = prediv_table16,
481 static const struct of_device_id clkgena_prediv_of_match[] = {
482 { .compatible = "st,clkgena-prediv-c65", .data = &prediv_c65_data },
483 { .compatible = "st,clkgena-prediv-c32", .data = &prediv_c32_data },
487 static void __init st_of_clkgena_prediv_setup(struct device_node *np)
489 const struct of_device_id *match;
491 const char *parent_name, *clk_name;
493 const struct clkgena_prediv_data *data;
495 match = of_match_node(clkgena_prediv_of_match, np);
497 pr_err("%s: No matching data\n", __func__);
503 reg = clkgen_get_register_base(np);
507 parent_name = of_clk_get_parent_name(np, 0);
511 if (of_property_read_string_index(np, "clock-output-names",
515 clk = clk_register_divider_table(NULL, clk_name, parent_name,
516 CLK_GET_RATE_NOCACHE,
517 reg + data->offset, data->shift, 1,
518 0, data->table, NULL);
522 of_clk_add_provider(np, of_clk_src_simple_get, clk);
523 pr_debug("%s: parent %s rate %u\n",
525 __clk_get_name(clk_get_parent(clk)),
526 (unsigned int)clk_get_rate(clk));
532 CLK_OF_DECLARE(clkgenaprediv, "st,clkgena-prediv", st_of_clkgena_prediv_setup);
534 struct clkgen_mux_data {
539 unsigned long clk_flags;
543 static struct clkgen_mux_data clkgen_mux_c_vcc_hd_416 = {
549 static struct clkgen_mux_data clkgen_mux_f_vcc_fvdp_416 = {
555 static struct clkgen_mux_data clkgen_mux_f_vcc_hva_416 = {
561 static struct clkgen_mux_data clkgen_mux_f_vcc_hd_416 = {
565 .lock = &clkgenf_lock,
568 static struct clkgen_mux_data clkgen_mux_c_vcc_sd_416 = {
572 .lock = &clkgenf_lock,
575 static struct clkgen_mux_data stih415_a9_mux_data = {
580 static struct clkgen_mux_data stih416_a9_mux_data = {
585 static struct clkgen_mux_data stih407_a9_mux_data = {
591 static const struct of_device_id mux_of_match[] = {
593 .compatible = "st,stih416-clkgenc-vcc-hd",
594 .data = &clkgen_mux_c_vcc_hd_416,
597 .compatible = "st,stih416-clkgenf-vcc-fvdp",
598 .data = &clkgen_mux_f_vcc_fvdp_416,
601 .compatible = "st,stih416-clkgenf-vcc-hva",
602 .data = &clkgen_mux_f_vcc_hva_416,
605 .compatible = "st,stih416-clkgenf-vcc-hd",
606 .data = &clkgen_mux_f_vcc_hd_416,
609 .compatible = "st,stih416-clkgenf-vcc-sd",
610 .data = &clkgen_mux_c_vcc_sd_416,
613 .compatible = "st,stih415-clkgen-a9-mux",
614 .data = &stih415_a9_mux_data,
617 .compatible = "st,stih416-clkgen-a9-mux",
618 .data = &stih416_a9_mux_data,
621 .compatible = "st,stih407-clkgen-a9-mux",
622 .data = &stih407_a9_mux_data,
627 static void __init st_of_clkgen_mux_setup(struct device_node *np)
629 const struct of_device_id *match;
632 const char **parents;
634 const struct clkgen_mux_data *data;
636 match = of_match_node(mux_of_match, np);
638 pr_err("%s: No matching data\n", __func__);
644 reg = of_iomap(np, 0);
646 pr_err("%s: Failed to get base address\n", __func__);
650 parents = clkgen_mux_get_parents(np, &num_parents);
651 if (IS_ERR(parents)) {
652 pr_err("%s: Failed to get parents (%ld)\n",
653 __func__, PTR_ERR(parents));
657 clk = clk_register_mux(NULL, np->name, parents, num_parents,
658 data->clk_flags | CLK_SET_RATE_PARENT,
660 data->shift, data->width, data->mux_flags,
665 pr_debug("%s: parent %s rate %u\n",
667 __clk_get_name(clk_get_parent(clk)),
668 (unsigned int)clk_get_rate(clk));
671 of_clk_add_provider(np, of_clk_src_simple_get, clk);
679 CLK_OF_DECLARE(clkgen_mux, "st,clkgen-mux", st_of_clkgen_mux_setup);
681 #define VCC_MAX_CHANNELS 16
683 #define VCC_GATE_OFFSET 0x0
684 #define VCC_MUX_OFFSET 0x4
685 #define VCC_DIV_OFFSET 0x8
687 struct clkgen_vcc_data {
689 unsigned long clk_flags;
692 static struct clkgen_vcc_data st_clkgenc_vcc_416 = {
693 .clk_flags = CLK_SET_RATE_PARENT,
696 static struct clkgen_vcc_data st_clkgenf_vcc_416 = {
697 .lock = &clkgenf_lock,
700 static const struct of_device_id vcc_of_match[] = {
701 { .compatible = "st,stih416-clkgenc", .data = &st_clkgenc_vcc_416 },
702 { .compatible = "st,stih416-clkgenf", .data = &st_clkgenf_vcc_416 },
706 static void __init st_of_clkgen_vcc_setup(struct device_node *np)
708 const struct of_device_id *match;
710 const char **parents;
712 struct clk_onecell_data *clk_data;
713 const struct clkgen_vcc_data *data;
715 match = of_match_node(vcc_of_match, np);
720 reg = of_iomap(np, 0);
724 parents = clkgen_mux_get_parents(np, &num_parents);
728 clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
732 clk_data->clk_num = VCC_MAX_CHANNELS;
733 clk_data->clks = kcalloc(clk_data->clk_num, sizeof(struct clk *),
739 for (i = 0; i < clk_data->clk_num; i++) {
741 const char *clk_name;
742 struct clk_gate *gate;
743 struct clk_divider *div;
746 if (of_property_read_string_index(np, "clock-output-names",
751 * If we read an empty clock name then the output is unused
753 if (*clk_name == '\0')
756 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
760 div = kzalloc(sizeof(*div), GFP_KERNEL);
766 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
773 gate->reg = reg + VCC_GATE_OFFSET;
775 gate->flags = CLK_GATE_SET_TO_DISABLE;
776 gate->lock = data->lock;
778 div->reg = reg + VCC_DIV_OFFSET;
781 div->flags = CLK_DIVIDER_POWER_OF_TWO |
782 CLK_DIVIDER_ROUND_CLOSEST;
784 mux->reg = reg + VCC_MUX_OFFSET;
788 clk = clk_register_composite(NULL, clk_name, parents,
790 &mux->hw, &clk_mux_ops,
791 &div->hw, &clk_divider_ops,
792 &gate->hw, &clk_gate_ops,
794 CLK_GET_RATE_NOCACHE);
802 pr_debug("%s: parent %s rate %u\n",
804 __clk_get_name(clk_get_parent(clk)),
805 (unsigned int)clk_get_rate(clk));
807 clk_data->clks[i] = clk;
812 of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
816 for (i = 0; i < clk_data->clk_num; i++) {
817 struct clk_composite *composite;
819 if (!clk_data->clks[i])
822 composite = container_of(__clk_get_hw(clk_data->clks[i]),
823 struct clk_composite, hw);
824 kfree(container_of(composite->gate_hw, struct clk_gate, hw));
825 kfree(container_of(composite->rate_hw, struct clk_divider, hw));
826 kfree(container_of(composite->mux_hw, struct clk_mux, hw));
829 kfree(clk_data->clks);
837 CLK_OF_DECLARE(clkgen_vcc, "st,clkgen-vcc", st_of_clkgen_vcc_setup);