2 * Copyright (C) 2013 Emilio López <emilio@elopez.com.ar>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * Adjustable factor-based clock implementation
11 #include <linux/clk-provider.h>
12 #include <linux/delay.h>
13 #include <linux/err.h>
15 #include <linux/module.h>
16 #include <linux/of_address.h>
17 #include <linux/slab.h>
18 #include <linux/string.h>
20 #include "clk-factors.h"
23 * DOC: basic adjustable factor-based clock
25 * Traits of this clock:
26 * prepare - clk_prepare only ensures that parents are prepared
27 * enable - clk_enable only ensures that parents are enabled
28 * rate - rate is adjustable.
29 * clk->rate = (parent->rate * N * (K + 1) >> P) / (M + 1)
30 * parent - fixed parent. No clk_set_parent support
33 #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
35 #define FACTORS_MAX_PARENTS 5
37 #define SETMASK(len, pos) (((1U << (len)) - 1) << (pos))
38 #define CLRMASK(len, pos) (~(SETMASK(len, pos)))
39 #define FACTOR_GET(bit, len, reg) (((reg) & SETMASK(len, bit)) >> (bit))
41 #define FACTOR_SET(bit, len, reg, val) \
42 (((reg) & CLRMASK(len, bit)) | (val << (bit)))
44 static unsigned long clk_factors_recalc_rate(struct clk_hw *hw,
45 unsigned long parent_rate)
47 u8 n = 1, k = 0, p = 0, m = 0;
50 struct clk_factors *factors = to_clk_factors(hw);
51 const struct clk_factors_config *config = factors->config;
53 /* Fetch the register value */
54 reg = readl(factors->reg);
56 /* Get each individual factor if applicable */
57 if (config->nwidth != SUNXI_FACTORS_NOT_APPLICABLE)
58 n = FACTOR_GET(config->nshift, config->nwidth, reg);
59 if (config->kwidth != SUNXI_FACTORS_NOT_APPLICABLE)
60 k = FACTOR_GET(config->kshift, config->kwidth, reg);
61 if (config->mwidth != SUNXI_FACTORS_NOT_APPLICABLE)
62 m = FACTOR_GET(config->mshift, config->mwidth, reg);
63 if (config->pwidth != SUNXI_FACTORS_NOT_APPLICABLE)
64 p = FACTOR_GET(config->pshift, config->pwidth, reg);
66 if (factors->recalc) {
67 struct factors_request factors_req = {
68 .parent_rate = parent_rate,
75 /* get mux details from mux clk structure */
77 factors_req.parent_index =
78 (reg >> factors->mux->shift) &
81 factors->recalc(&factors_req);
83 return factors_req.rate;
86 /* Calculate the rate */
87 rate = (parent_rate * (n + config->n_start) * (k + 1) >> p) / (m + 1);
92 static long clk_factors_round_rate(struct clk_hw *hw, unsigned long rate,
93 unsigned long *parent_rate)
95 struct clk_factors *factors = to_clk_factors(hw);
96 struct factors_request req = {
98 .parent_rate = *parent_rate,
101 factors->get_factors(&req);
107 static int clk_factors_determine_rate(struct clk_hw *hw,
108 struct clk_rate_request *req)
110 struct clk_factors *factors = to_clk_factors(hw);
111 struct clk_hw *parent, *best_parent = NULL;
113 unsigned long parent_rate, best = 0, child_rate, best_child_rate = 0;
115 /* find the parent that can help provide the fastest rate <= rate */
116 num_parents = clk_hw_get_num_parents(hw);
117 for (i = 0; i < num_parents; i++) {
118 struct factors_request factors_req = {
122 parent = clk_hw_get_parent_by_index(hw, i);
125 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)
126 parent_rate = clk_hw_round_rate(parent, req->rate);
128 parent_rate = clk_hw_get_rate(parent);
130 factors_req.parent_rate = parent_rate;
131 factors->get_factors(&factors_req);
132 child_rate = factors_req.rate;
134 if (child_rate <= req->rate && child_rate > best_child_rate) {
135 best_parent = parent;
137 best_child_rate = child_rate;
144 req->best_parent_hw = best_parent;
145 req->best_parent_rate = best;
146 req->rate = best_child_rate;
151 static int clk_factors_set_rate(struct clk_hw *hw, unsigned long rate,
152 unsigned long parent_rate)
154 struct factors_request req = {
156 .parent_rate = parent_rate,
159 struct clk_factors *factors = to_clk_factors(hw);
160 const struct clk_factors_config *config = factors->config;
161 unsigned long flags = 0;
163 factors->get_factors(&req);
166 spin_lock_irqsave(factors->lock, flags);
168 /* Fetch the register value */
169 reg = readl(factors->reg);
171 /* Set up the new factors - macros do not do anything if width is 0 */
172 reg = FACTOR_SET(config->nshift, config->nwidth, reg, req.n);
173 reg = FACTOR_SET(config->kshift, config->kwidth, reg, req.k);
174 reg = FACTOR_SET(config->mshift, config->mwidth, reg, req.m);
175 reg = FACTOR_SET(config->pshift, config->pwidth, reg, req.p);
178 writel(reg, factors->reg);
180 /* delay 500us so pll stabilizes */
181 __delay((rate >> 20) * 500 / 2);
184 spin_unlock_irqrestore(factors->lock, flags);
189 static const struct clk_ops clk_factors_ops = {
190 .determine_rate = clk_factors_determine_rate,
191 .recalc_rate = clk_factors_recalc_rate,
192 .round_rate = clk_factors_round_rate,
193 .set_rate = clk_factors_set_rate,
196 struct clk *sunxi_factors_register(struct device_node *node,
197 const struct factors_data *data,
202 struct clk_factors *factors;
203 struct clk_gate *gate = NULL;
204 struct clk_mux *mux = NULL;
205 struct clk_hw *gate_hw = NULL;
206 struct clk_hw *mux_hw = NULL;
207 const char *clk_name = node->name;
208 const char *parents[FACTORS_MAX_PARENTS];
211 /* if we have a mux, we will have >1 parents */
212 i = of_clk_parent_fill(node, parents, FACTORS_MAX_PARENTS);
215 * some factor clocks, such as pll5 and pll6, may have multiple
216 * outputs, and have their name designated in factors_data
219 clk_name = data->name;
221 of_property_read_string(node, "clock-output-names", &clk_name);
223 factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL);
227 /* set up factors properties */
229 factors->config = data->table;
230 factors->get_factors = data->getter;
231 factors->recalc = data->recalc;
232 factors->lock = lock;
234 /* Add a gate if this factor clock can be gated */
236 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
240 factors->gate = gate;
242 /* set up gate properties */
244 gate->bit_idx = data->enable;
245 gate->lock = factors->lock;
249 /* Add a mux if this factor clock can be muxed */
251 mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
257 /* set up gate properties */
259 mux->shift = data->mux;
260 mux->mask = data->muxmask;
261 mux->lock = factors->lock;
265 clk = clk_register_composite(NULL, clk_name,
267 mux_hw, &clk_mux_ops,
268 &factors->hw, &clk_factors_ops,
269 gate_hw, &clk_gate_ops, 0);
273 ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
277 ret = clk_register_clkdev(clk, clk_name, NULL);
284 of_clk_del_provider(node);
286 /* TODO: The composite clock stuff will leak a bit here. */
298 void sunxi_factors_unregister(struct device_node *node, struct clk *clk)
300 struct clk_hw *hw = __clk_get_hw(clk);
301 struct clk_factors *factors;
307 factors = to_clk_factors(hw);
308 name = clk_hw_get_name(hw);
310 /* No unregister call for clkdev_* */
311 of_clk_del_provider(node);
312 /* TODO: The composite clock stuff will leak a bit here. */
315 kfree(factors->gate);