drivers/clk/ux500/u8540_clk.c

   1 /*
   2  * Clock definitions for u8540 platform.
   3  *
   4  * Copyright (C) 2012 ST-Ericsson SA
   5  * Author: Ulf Hansson <ulf.hansson@linaro.org>
   6  *
   7  * License terms: GNU General Public License (GPL) version 2
   8  */
   9
  10 #include <linux/of.h>
  11 #include <linux/of_address.h>
  12 #include <linux/clkdev.h>
  13 #include <linux/clk-provider.h>
  14 #include <linux/mfd/dbx500-prcmu.h>
  15 #include <linux/platform_data/clk-ux500.h>
  16 #include "clk.h"
  17
  18 static const struct of_device_id u8540_clk_of_match[] = {
  19         { .compatible = "stericsson,u8540-clks", },
  20         { }
  21 };
  22
  23 /* CLKRST4 is missing making it hard to index things */
  24 enum clkrst_index {
  25         CLKRST1_INDEX = 0,
  26         CLKRST2_INDEX,
  27         CLKRST3_INDEX,
  28         CLKRST5_INDEX,
  29         CLKRST6_INDEX,
  30         CLKRST_MAX,
  31 };
  32
  33 void u8540_clk_init(void)
  34 {
  35         struct clk *clk;
  36         struct device_node *np = NULL;
  37         u32 bases[CLKRST_MAX];
  38         int i;
  39
  40         if (of_have_populated_dt())
  41                 np = of_find_matching_node(NULL, u8540_clk_of_match);
  42         if (!np) {
  43                 pr_err("Either DT or U8540 Clock node not found\n");
  44                 return;
  45         }
  46         for (i = 0; i < ARRAY_SIZE(bases); i++) {
  47                 struct resource r;
  48
  49                 if (of_address_to_resource(np, i, &r))
  50                         /* Not much choice but to continue */
  51                         pr_err("failed to get CLKRST %d base address\n",
  52                                i + 1);
  53                 bases[i] = r.start;
  54         }
  55
  56         /* Clock sources. */
  57         /* Fixed ClockGen */
  58         clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0,
  59                                 CLK_IGNORE_UNUSED);
  60         clk_register_clkdev(clk, "soc0_pll", NULL);
  61
  62         clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1,
  63                                 CLK_IGNORE_UNUSED);
  64         clk_register_clkdev(clk, "soc1_pll", NULL);
  65
  66         clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR,
  67                                 CLK_IGNORE_UNUSED);
  68         clk_register_clkdev(clk, "ddr_pll", NULL);
  69
  70         clk = clk_register_fixed_rate(NULL, "rtc32k", NULL,
  71                                 CLK_IGNORE_UNUSED,
  72                                 32768);
  73         clk_register_clkdev(clk, "clk32k", NULL);
  74         clk_register_clkdev(clk, "apb_pclk", "rtc-pl031");
  75
  76         clk = clk_register_fixed_rate(NULL, "ulp38m4", NULL,
  77                                 CLK_IGNORE_UNUSED,
  78                                 38400000);
  79
  80         clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, 0);
  81         clk_register_clkdev(clk, NULL, "UART");
  82
  83         /* msp02clk needs a abx500 clk as parent. Handle by abx500 clk driver */
  84         clk = clk_reg_prcmu_gate("msp02clk", "ab9540_sysclk12_b1",
  85                         PRCMU_MSP02CLK, 0);
  86         clk_register_clkdev(clk, NULL, "MSP02");
  87
  88         clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, 0);
  89         clk_register_clkdev(clk, NULL, "MSP1");
  90
  91         clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, 0);
  92         clk_register_clkdev(clk, NULL, "I2C");
  93
  94         clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, 0);
  95         clk_register_clkdev(clk, NULL, "slim");
  96
  97         clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, 0);
  98         clk_register_clkdev(clk, NULL, "PERIPH1");
  99
 100         clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, 0);
 101         clk_register_clkdev(clk, NULL, "PERIPH2");
 102
 103         clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, 0);
 104         clk_register_clkdev(clk, NULL, "PERIPH3");
 105
 106         clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, 0);
 107         clk_register_clkdev(clk, NULL, "PERIPH5");
 108
 109         clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, 0);
 110         clk_register_clkdev(clk, NULL, "PERIPH6");
 111
 112         clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, 0);
 113         clk_register_clkdev(clk, NULL, "PERIPH7");
 114
 115         clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0,
 116                                 CLK_SET_RATE_GATE);
 117         clk_register_clkdev(clk, NULL, "lcd");
 118         clk_register_clkdev(clk, "lcd", "mcde");
 119
 120         clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, 0);
 121         clk_register_clkdev(clk, NULL, "bml");
 122
 123         clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0,
 124                                      CLK_SET_RATE_GATE);
 125
 126         clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0,
 127                                      CLK_SET_RATE_GATE);
 128
 129         clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0,
 130                                      CLK_SET_RATE_GATE);
 131         clk_register_clkdev(clk, NULL, "hdmi");
 132         clk_register_clkdev(clk, "hdmi", "mcde");
 133
 134         clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, 0);
 135         clk_register_clkdev(clk, NULL, "apeat");
 136
 137         clk = clk_reg_prcmu_gate("apetraceclk", NULL, PRCMU_APETRACECLK, 0);
 138         clk_register_clkdev(clk, NULL, "apetrace");
 139
 140         clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, 0);
 141         clk_register_clkdev(clk, NULL, "mcde");
 142         clk_register_clkdev(clk, "mcde", "mcde");
 143         clk_register_clkdev(clk, NULL, "dsilink.0");
 144         clk_register_clkdev(clk, NULL, "dsilink.1");
 145         clk_register_clkdev(clk, NULL, "dsilink.2");
 146
 147         clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK, 0);
 148         clk_register_clkdev(clk, NULL, "ipi2");
 149
 150         clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK, 0);
 151         clk_register_clkdev(clk, NULL, "dsialt");
 152
 153         clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, 0);
 154         clk_register_clkdev(clk, NULL, "dma40.0");
 155
 156         clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, 0);
 157         clk_register_clkdev(clk, NULL, "b2r2");
 158         clk_register_clkdev(clk, NULL, "b2r2_core");
 159         clk_register_clkdev(clk, NULL, "U8500-B2R2.0");
 160         clk_register_clkdev(clk, NULL, "b2r2_1_core");
 161
 162         clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0,
 163                                      CLK_SET_RATE_GATE);
 164         clk_register_clkdev(clk, NULL, "tv");
 165         clk_register_clkdev(clk, "tv", "mcde");
 166
 167         clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, 0);
 168         clk_register_clkdev(clk, NULL, "SSP");
 169
 170         clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, 0);
 171         clk_register_clkdev(clk, NULL, "rngclk");
 172
 173         clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, 0);
 174         clk_register_clkdev(clk, NULL, "uicc");
 175
 176         clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, 0);
 177         clk_register_clkdev(clk, NULL, "mtu0");
 178         clk_register_clkdev(clk, NULL, "mtu1");
 179
 180         clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL,
 181                                         PRCMU_SDMMCCLK, 100000000,
 182                                         CLK_SET_RATE_GATE);
 183         clk_register_clkdev(clk, NULL, "sdmmc");
 184
 185         clk = clk_reg_prcmu_opp_volt_scalable("sdmmchclk", NULL,
 186                                         PRCMU_SDMMCHCLK, 400000000,
 187                                         CLK_SET_RATE_GATE);
 188         clk_register_clkdev(clk, NULL, "sdmmchclk");
 189
 190         clk = clk_reg_prcmu_gate("hvaclk", NULL, PRCMU_HVACLK, 0);
 191         clk_register_clkdev(clk, NULL, "hva");
 192
 193         clk = clk_reg_prcmu_gate("g1clk", NULL, PRCMU_G1CLK, 0);
 194         clk_register_clkdev(clk, NULL, "g1");
 195
 196         clk = clk_reg_prcmu_scalable("spare1clk", NULL, PRCMU_SPARE1CLK, 0,
 197                                      CLK_SET_RATE_GATE);
 198         clk_register_clkdev(clk, "dsilcd", "mcde");
 199
 200         clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk",
 201                                 PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE);
 202         clk_register_clkdev(clk, "dsihs2", "mcde");
 203         clk_register_clkdev(clk, "hs_clk", "dsilink.2");
 204
 205         clk = clk_reg_prcmu_scalable("dsilcd_pll", "spare1clk",
 206                                 PRCMU_PLLDSI_LCD, 0, CLK_SET_RATE_GATE);
 207         clk_register_clkdev(clk, "dsilcd_pll", "mcde");
 208
 209         clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll",
 210                                 PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE);
 211         clk_register_clkdev(clk, "dsihs0", "mcde");
 212
 213         clk = clk_reg_prcmu_scalable("dsi0lcdclk", "dsilcd_pll",
 214                                 PRCMU_DSI0CLK_LCD, 0, CLK_SET_RATE_GATE);
 215         clk_register_clkdev(clk, "dsihs0", "mcde");
 216         clk_register_clkdev(clk, "hs_clk", "dsilink.0");
 217
 218         clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll",
 219                                 PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE);
 220         clk_register_clkdev(clk, "dsihs1", "mcde");
 221
 222         clk = clk_reg_prcmu_scalable("dsi1lcdclk", "dsilcd_pll",
 223                                 PRCMU_DSI1CLK_LCD, 0, CLK_SET_RATE_GATE);
 224         clk_register_clkdev(clk, "dsihs1", "mcde");
 225         clk_register_clkdev(clk, "hs_clk", "dsilink.1");
 226
 227         clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk",
 228                                 PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE);
 229         clk_register_clkdev(clk, "lp_clk", "dsilink.0");
 230         clk_register_clkdev(clk, "dsilp0", "mcde");
 231
 232         clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk",
 233                                 PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE);
 234         clk_register_clkdev(clk, "lp_clk", "dsilink.1");
 235         clk_register_clkdev(clk, "dsilp1", "mcde");
 236
 237         clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk",
 238                                 PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE);
 239         clk_register_clkdev(clk, "lp_clk", "dsilink.2");
 240         clk_register_clkdev(clk, "dsilp2", "mcde");
 241
 242         clk = clk_reg_prcmu_scalable_rate("armss", NULL,
 243                                 PRCMU_ARMSS, 0, CLK_IGNORE_UNUSED);
 244         clk_register_clkdev(clk, "armss", NULL);
 245
 246         clk = clk_register_fixed_factor(NULL, "smp_twd", "armss",
 247                                 CLK_IGNORE_UNUSED, 1, 2);
 248         clk_register_clkdev(clk, NULL, "smp_twd");
 249
 250         /* PRCC P-clocks */
 251         /* Peripheral 1 : PRCC P-clocks */
 252         clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", bases[CLKRST1_INDEX],
 253                                 BIT(0), 0);
 254         clk_register_clkdev(clk, "apb_pclk", "uart0");
 255
 256         clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", bases[CLKRST1_INDEX],
 257                                 BIT(1), 0);
 258         clk_register_clkdev(clk, "apb_pclk", "uart1");
 259
 260         clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", bases[CLKRST1_INDEX],
 261                                 BIT(2), 0);
 262         clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.1");
 263
 264         clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", bases[CLKRST1_INDEX],
 265                                 BIT(3), 0);
 266         clk_register_clkdev(clk, "apb_pclk", "msp0");
 267         clk_register_clkdev(clk, "apb_pclk", "dbx5x0-msp-i2s.0");
 268
 269         clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", bases[CLKRST1_INDEX],
 270                                 BIT(4), 0);
 271         clk_register_clkdev(clk, "apb_pclk", "msp1");
 272         clk_register_clkdev(clk, "apb_pclk", "dbx5x0-msp-i2s.1");
 273
 274         clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", bases[CLKRST1_INDEX],
 275                                 BIT(5), 0);
 276         clk_register_clkdev(clk, "apb_pclk", "sdi0");
 277
 278         clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", bases[CLKRST1_INDEX],
 279                                 BIT(6), 0);
 280         clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.2");
 281
 282         clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", bases[CLKRST1_INDEX],
 283                                 BIT(7), 0);
 284         clk_register_clkdev(clk, NULL, "spi3");
 285
 286         clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", bases[CLKRST1_INDEX],
 287                                 BIT(8), 0);
 288         clk_register_clkdev(clk, "apb_pclk", "slimbus0");
 289
 290         clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", bases[CLKRST1_INDEX],
 291                                 BIT(9), 0);
 292         clk_register_clkdev(clk, NULL, "gpio.0");
 293         clk_register_clkdev(clk, NULL, "gpio.1");
 294         clk_register_clkdev(clk, NULL, "gpioblock0");
 295         clk_register_clkdev(clk, "apb_pclk", "ab85xx-codec.0");
 296
 297         clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", bases[CLKRST1_INDEX],
 298                                 BIT(10), 0);
 299         clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.4");
 300
 301         clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", bases[CLKRST1_INDEX],
 302                                 BIT(11), 0);
 303         clk_register_clkdev(clk, "apb_pclk", "msp3");
 304         clk_register_clkdev(clk, "apb_pclk", "dbx5x0-msp-i2s.3");
 305
 306         /* Peripheral 2 : PRCC P-clocks */
 307         clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", bases[CLKRST2_INDEX],
 308                                 BIT(0), 0);
 309         clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.3");
 310
 311         clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", bases[CLKRST2_INDEX],
 312                                 BIT(1), 0);
 313         clk_register_clkdev(clk, NULL, "spi2");
 314
 315         clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", bases[CLKRST2_INDEX],
 316                                 BIT(2), 0);
 317         clk_register_clkdev(clk, NULL, "spi1");
 318
 319         clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", bases[CLKRST2_INDEX],
 320                                 BIT(3), 0);
 321         clk_register_clkdev(clk, NULL, "pwl");
 322
 323         clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", bases[CLKRST2_INDEX],
 324                                 BIT(4), 0);
 325         clk_register_clkdev(clk, "apb_pclk", "sdi4");
 326
 327         clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", bases[CLKRST2_INDEX],
 328                                 BIT(5), 0);
 329         clk_register_clkdev(clk, "apb_pclk", "msp2");
 330         clk_register_clkdev(clk, "apb_pclk", "dbx5x0-msp-i2s.2");
 331
 332         clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", bases[CLKRST2_INDEX],
 333                                 BIT(6), 0);
 334         clk_register_clkdev(clk, "apb_pclk", "sdi1");
 335
 336         clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", bases[CLKRST2_INDEX],
 337                                 BIT(7), 0);
 338         clk_register_clkdev(clk, "apb_pclk", "sdi3");
 339
 340         clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", bases[CLKRST2_INDEX],
 341                                 BIT(8), 0);
 342         clk_register_clkdev(clk, NULL, "spi0");
 343
 344         clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", bases[CLKRST2_INDEX],
 345                                 BIT(9), 0);
 346         clk_register_clkdev(clk, "hsir_hclk", "ste_hsi.0");
 347
 348         clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", bases[CLKRST2_INDEX],
 349                                 BIT(10), 0);
 350         clk_register_clkdev(clk, "hsit_hclk", "ste_hsi.0");
 351
 352         clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", bases[CLKRST2_INDEX],
 353                                 BIT(11), 0);
 354         clk_register_clkdev(clk, NULL, "gpio.6");
 355         clk_register_clkdev(clk, NULL, "gpio.7");
 356         clk_register_clkdev(clk, NULL, "gpioblock1");
 357
 358         clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", bases[CLKRST2_INDEX],
 359                                 BIT(12), 0);
 360         clk_register_clkdev(clk, "msp4-pclk", "ab85xx-codec.0");
 361
 362         /* Peripheral 3 : PRCC P-clocks */
 363         clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", bases[CLKRST3_INDEX],
 364                                 BIT(0), 0);
 365         clk_register_clkdev(clk, NULL, "fsmc");
 366
 367         clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", bases[CLKRST3_INDEX],
 368                                 BIT(1), 0);
 369         clk_register_clkdev(clk, "apb_pclk", "ssp0");
 370
 371         clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", bases[CLKRST3_INDEX],
 372                                 BIT(2), 0);
 373         clk_register_clkdev(clk, "apb_pclk", "ssp1");
 374
 375         clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", bases[CLKRST3_INDEX],
 376                                 BIT(3), 0);
 377         clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.0");
 378
 379         clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", bases[CLKRST3_INDEX],
 380                                 BIT(4), 0);
 381         clk_register_clkdev(clk, "apb_pclk", "sdi2");
 382
 383         clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", bases[CLKRST3_INDEX],
 384                                 BIT(5), 0);
 385         clk_register_clkdev(clk, "apb_pclk", "ske");
 386         clk_register_clkdev(clk, "apb_pclk", "nmk-ske-keypad");
 387
 388         clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", bases[CLKRST3_INDEX],
 389                                 BIT(6), 0);
 390         clk_register_clkdev(clk, "apb_pclk", "uart2");
 391
 392         clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", bases[CLKRST3_INDEX],
 393                                 BIT(7), 0);
 394         clk_register_clkdev(clk, "apb_pclk", "sdi5");
 395
 396         clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", bases[CLKRST3_INDEX],
 397                                 BIT(8), 0);
 398         clk_register_clkdev(clk, NULL, "gpio.2");
 399         clk_register_clkdev(clk, NULL, "gpio.3");
 400         clk_register_clkdev(clk, NULL, "gpio.4");
 401         clk_register_clkdev(clk, NULL, "gpio.5");
 402         clk_register_clkdev(clk, NULL, "gpioblock2");
 403
 404         clk = clk_reg_prcc_pclk("p3_pclk9", "per3clk", bases[CLKRST3_INDEX],
 405                                 BIT(9), 0);
 406         clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.5");
 407
 408         clk = clk_reg_prcc_pclk("p3_pclk10", "per3clk", bases[CLKRST3_INDEX],
 409                                 BIT(10), 0);
 410         clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.6");
 411
 412         clk = clk_reg_prcc_pclk("p3_pclk11", "per3clk", bases[CLKRST3_INDEX],
 413                                 BIT(11), 0);
 414         clk_register_clkdev(clk, "apb_pclk", "uart3");
 415
 416         clk = clk_reg_prcc_pclk("p3_pclk12", "per3clk", bases[CLKRST3_INDEX],
 417                                 BIT(12), 0);
 418         clk_register_clkdev(clk, "apb_pclk", "uart4");
 419
 420         /* Peripheral 5 : PRCC P-clocks */
 421         clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", bases[CLKRST5_INDEX],
 422                                 BIT(0), 0);
 423         clk_register_clkdev(clk, "usb", "musb-ux500.0");
 424         clk_register_clkdev(clk, "usbclk", "ab-iddet.0");
 425
 426         clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", bases[CLKRST5_INDEX],
 427                                 BIT(1), 0);
 428         clk_register_clkdev(clk, NULL, "gpio.8");
 429         clk_register_clkdev(clk, NULL, "gpioblock3");
 430
 431         /* Peripheral 6 : PRCC P-clocks */
 432         clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", bases[CLKRST6_INDEX],
 433                                 BIT(0), 0);
 434         clk_register_clkdev(clk, "apb_pclk", "rng");
 435
 436         clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", bases[CLKRST6_INDEX],
 437                                 BIT(1), 0);
 438         clk_register_clkdev(clk, NULL, "cryp0");
 439         clk_register_clkdev(clk, NULL, "cryp1");
 440
 441         clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", bases[CLKRST6_INDEX],
 442                                 BIT(2), 0);
 443         clk_register_clkdev(clk, NULL, "hash0");
 444
 445         clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", bases[CLKRST6_INDEX],
 446                                 BIT(3), 0);
 447         clk_register_clkdev(clk, NULL, "pka");
 448
 449         clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", bases[CLKRST6_INDEX],
 450                                 BIT(4), 0);
 451         clk_register_clkdev(clk, NULL, "db8540-hash1");
 452
 453         clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", bases[CLKRST6_INDEX],
 454                                 BIT(5), 0);
 455         clk_register_clkdev(clk, NULL, "cfgreg");
 456
 457         clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", bases[CLKRST6_INDEX],
 458                                 BIT(6), 0);
 459         clk_register_clkdev(clk, "apb_pclk", "mtu0");
 460
 461         clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", bases[CLKRST6_INDEX],
 462                                 BIT(7), 0);
 463         clk_register_clkdev(clk, "apb_pclk", "mtu1");
 464
 465         /*
 466          * PRCC K-clocks  ==> see table PRCC_PCKEN/PRCC_KCKEN
 467          * This differs from the internal implementation:
 468          * We don't use the PERPIH[n| clock as parent, since those _should_
 469          * only be used as parents for the P-clocks.
 470          * TODO: "parentjoin" with corresponding P-clocks for all K-clocks.
 471          */
 472
 473         /* Peripheral 1 : PRCC K-clocks */
 474         clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk",
 475                         bases[CLKRST1_INDEX], BIT(0), CLK_SET_RATE_GATE);
 476         clk_register_clkdev(clk, NULL, "uart0");
 477
 478         clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk",
 479                         bases[CLKRST1_INDEX], BIT(1), CLK_SET_RATE_GATE);
 480         clk_register_clkdev(clk, NULL, "uart1");
 481
 482         clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk",
 483                         bases[CLKRST1_INDEX], BIT(2), CLK_SET_RATE_GATE);
 484         clk_register_clkdev(clk, NULL, "nmk-i2c.1");
 485
 486         clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk",
 487                         bases[CLKRST1_INDEX], BIT(3), CLK_SET_RATE_GATE);
 488         clk_register_clkdev(clk, NULL, "msp0");
 489         clk_register_clkdev(clk, NULL, "dbx5x0-msp-i2s.0");
 490
 491         clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk",
 492                         bases[CLKRST1_INDEX], BIT(4), CLK_SET_RATE_GATE);
 493         clk_register_clkdev(clk, NULL, "msp1");
 494         clk_register_clkdev(clk, NULL, "dbx5x0-msp-i2s.1");
 495
 496         clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmchclk",
 497                         bases[CLKRST1_INDEX], BIT(5), CLK_SET_RATE_GATE);
 498         clk_register_clkdev(clk, NULL, "sdi0");
 499
 500         clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk",
 501                         bases[CLKRST1_INDEX], BIT(6), CLK_SET_RATE_GATE);
 502         clk_register_clkdev(clk, NULL, "nmk-i2c.2");
 503
 504         clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk",
 505                         bases[CLKRST1_INDEX], BIT(8), CLK_SET_RATE_GATE);
 506         clk_register_clkdev(clk, NULL, "slimbus0");
 507
 508         clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk",
 509                         bases[CLKRST1_INDEX], BIT(9), CLK_SET_RATE_GATE);
 510         clk_register_clkdev(clk, NULL, "nmk-i2c.4");
 511
 512         clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk",
 513                         bases[CLKRST1_INDEX], BIT(10), CLK_SET_RATE_GATE);
 514         clk_register_clkdev(clk, NULL, "msp3");
 515         clk_register_clkdev(clk, NULL, "dbx5x0-msp-i2s.3");
 516
 517         /* Peripheral 2 : PRCC K-clocks */
 518         clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk",
 519                         bases[CLKRST2_INDEX], BIT(0), CLK_SET_RATE_GATE);
 520         clk_register_clkdev(clk, NULL, "nmk-i2c.3");
 521
 522         clk = clk_reg_prcc_kclk("p2_pwl_kclk", "rtc32k",
 523                         bases[CLKRST2_INDEX], BIT(1), CLK_SET_RATE_GATE);
 524         clk_register_clkdev(clk, NULL, "pwl");
 525
 526         clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmchclk",
 527                         bases[CLKRST2_INDEX], BIT(2), CLK_SET_RATE_GATE);
 528         clk_register_clkdev(clk, NULL, "sdi4");
 529
 530         clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk",
 531                         bases[CLKRST2_INDEX], BIT(3), CLK_SET_RATE_GATE);
 532         clk_register_clkdev(clk, NULL, "msp2");
 533         clk_register_clkdev(clk, NULL, "dbx5x0-msp-i2s.2");
 534
 535         clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmchclk",
 536                         bases[CLKRST2_INDEX], BIT(4), CLK_SET_RATE_GATE);
 537         clk_register_clkdev(clk, NULL, "sdi1");
 538
 539         clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk",
 540                         bases[CLKRST2_INDEX], BIT(5), CLK_SET_RATE_GATE);
 541         clk_register_clkdev(clk, NULL, "sdi3");
 542
 543         clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk",
 544                         bases[CLKRST2_INDEX], BIT(6),
 545                         CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
 546         clk_register_clkdev(clk, "hsir_hsirxclk", "ste_hsi.0");
 547
 548         clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk",
 549                         bases[CLKRST2_INDEX], BIT(7),
 550                         CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
 551         clk_register_clkdev(clk, "hsit_hsitxclk", "ste_hsi.0");
 552
 553         /* Should only be 9540, but might be added for 85xx as well */
 554         clk = clk_reg_prcc_kclk("p2_msp4_kclk", "msp02clk",
 555                         bases[CLKRST2_INDEX], BIT(9), CLK_SET_RATE_GATE);
 556         clk_register_clkdev(clk, NULL, "msp4");
 557         clk_register_clkdev(clk, "msp4", "ab85xx-codec.0");
 558
 559         /* Peripheral 3 : PRCC K-clocks */
 560         clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk",
 561                         bases[CLKRST3_INDEX], BIT(1), CLK_SET_RATE_GATE);
 562         clk_register_clkdev(clk, NULL, "ssp0");
 563
 564         clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk",
 565                         bases[CLKRST3_INDEX], BIT(2), CLK_SET_RATE_GATE);
 566         clk_register_clkdev(clk, NULL, "ssp1");
 567
 568         clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk",
 569                         bases[CLKRST3_INDEX], BIT(3), CLK_SET_RATE_GATE);
 570         clk_register_clkdev(clk, NULL, "nmk-i2c.0");
 571
 572         clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmchclk",
 573                         bases[CLKRST3_INDEX], BIT(4), CLK_SET_RATE_GATE);
 574         clk_register_clkdev(clk, NULL, "sdi2");
 575
 576         clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k",
 577                         bases[CLKRST3_INDEX], BIT(5), CLK_SET_RATE_GATE);
 578         clk_register_clkdev(clk, NULL, "ske");
 579         clk_register_clkdev(clk, NULL, "nmk-ske-keypad");
 580
 581         clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk",
 582                         bases[CLKRST3_INDEX], BIT(6), CLK_SET_RATE_GATE);
 583         clk_register_clkdev(clk, NULL, "uart2");
 584
 585         clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk",
 586                         bases[CLKRST3_INDEX], BIT(7), CLK_SET_RATE_GATE);
 587         clk_register_clkdev(clk, NULL, "sdi5");
 588
 589         clk = clk_reg_prcc_kclk("p3_i2c5_kclk", "i2cclk",
 590                         bases[CLKRST3_INDEX], BIT(8), CLK_SET_RATE_GATE);
 591         clk_register_clkdev(clk, NULL, "nmk-i2c.5");
 592
 593         clk = clk_reg_prcc_kclk("p3_i2c6_kclk", "i2cclk",
 594                         bases[CLKRST3_INDEX], BIT(9), CLK_SET_RATE_GATE);
 595         clk_register_clkdev(clk, NULL, "nmk-i2c.6");
 596
 597         clk = clk_reg_prcc_kclk("p3_uart3_kclk", "uartclk",
 598                         bases[CLKRST3_INDEX], BIT(10), CLK_SET_RATE_GATE);
 599         clk_register_clkdev(clk, NULL, "uart3");
 600
 601         clk = clk_reg_prcc_kclk("p3_uart4_kclk", "uartclk",
 602                         bases[CLKRST3_INDEX], BIT(11), CLK_SET_RATE_GATE);
 603         clk_register_clkdev(clk, NULL, "uart4");
 604
 605         /* Peripheral 6 : PRCC K-clocks */
 606         clk = clk_reg_prcc_kclk("p6_rng_kclk", "rngclk",
 607                         bases[CLKRST6_INDEX], BIT(0), CLK_SET_RATE_GATE);
 608         clk_register_clkdev(clk, NULL, "rng");
 609 }