drivers/crypto/picoxcell_crypto.c

   1 /*
   2  * Copyright (c) 2010-2011 Picochip Ltd., Jamie Iles
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  17  */
  18 #include <crypto/internal/aead.h>
  19 #include <crypto/aes.h>
  20 #include <crypto/algapi.h>
  21 #include <crypto/authenc.h>
  22 #include <crypto/des.h>
  23 #include <crypto/md5.h>
  24 #include <crypto/sha.h>
  25 #include <crypto/internal/skcipher.h>
  26 #include <linux/clk.h>
  27 #include <linux/crypto.h>
  28 #include <linux/delay.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/dmapool.h>
  31 #include <linux/err.h>
  32 #include <linux/init.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/io.h>
  35 #include <linux/list.h>
  36 #include <linux/module.h>
  37 #include <linux/of.h>
  38 #include <linux/platform_device.h>
  39 #include <linux/pm.h>
  40 #include <linux/rtnetlink.h>
  41 #include <linux/scatterlist.h>
  42 #include <linux/sched.h>
  43 #include <linux/sizes.h>
  44 #include <linux/slab.h>
  45 #include <linux/timer.h>
  46
  47 #include "picoxcell_crypto_regs.h"
  48
  49 /*
  50  * The threshold for the number of entries in the CMD FIFO available before
  51  * the CMD0_CNT interrupt is raised. Increasing this value will reduce the
  52  * number of interrupts raised to the CPU.
  53  */
  54 #define CMD0_IRQ_THRESHOLD   1
  55
  56 /*
  57  * The timeout period (in jiffies) for a PDU. When the the number of PDUs in
  58  * flight is greater than the STAT_IRQ_THRESHOLD or 0 the timer is disabled.
  59  * When there are packets in flight but lower than the threshold, we enable
  60  * the timer and at expiry, attempt to remove any processed packets from the
  61  * queue and if there are still packets left, schedule the timer again.
  62  */
  63 #define PACKET_TIMEOUT      1
  64
  65 /* The priority to register each algorithm with. */
  66 #define SPACC_CRYPTO_ALG_PRIORITY       10000
  67
  68 #define SPACC_CRYPTO_KASUMI_F8_KEY_LEN  16
  69 #define SPACC_CRYPTO_IPSEC_CIPHER_PG_SZ 64
  70 #define SPACC_CRYPTO_IPSEC_HASH_PG_SZ   64
  71 #define SPACC_CRYPTO_IPSEC_MAX_CTXS     32
  72 #define SPACC_CRYPTO_IPSEC_FIFO_SZ      32
  73 #define SPACC_CRYPTO_L2_CIPHER_PG_SZ    64
  74 #define SPACC_CRYPTO_L2_HASH_PG_SZ      64
  75 #define SPACC_CRYPTO_L2_MAX_CTXS        128
  76 #define SPACC_CRYPTO_L2_FIFO_SZ         128
  77
  78 #define MAX_DDT_LEN                     16
  79
  80 /* DDT format. This must match the hardware DDT format exactly. */
  81 struct spacc_ddt {
  82         dma_addr_t      p;
  83         u32             len;
  84 };
  85
  86 /*
  87  * Asynchronous crypto request structure.
  88  *
  89  * This structure defines a request that is either queued for processing or
  90  * being processed.
  91  */
  92 struct spacc_req {
  93         struct list_head                list;
  94         struct spacc_engine             *engine;
  95         struct crypto_async_request     *req;
  96         int                             result;
  97         bool                            is_encrypt;
  98         unsigned                        ctx_id;
  99         dma_addr_t                      src_addr, dst_addr;
 100         struct spacc_ddt                *src_ddt, *dst_ddt;
 101         void                            (*complete)(struct spacc_req *req);
 102
 103         /* AEAD specific bits. */
 104         u8                              *giv;
 105         size_t                          giv_len;
 106         dma_addr_t                      giv_pa;
 107 };
 108
 109 struct spacc_engine {
 110         void __iomem                    *regs;
 111         struct list_head                pending;
 112         int                             next_ctx;
 113         spinlock_t                      hw_lock;
 114         int                             in_flight;
 115         struct list_head                completed;
 116         struct list_head                in_progress;
 117         struct tasklet_struct           complete;
 118         unsigned long                   fifo_sz;
 119         void __iomem                    *cipher_ctx_base;
 120         void __iomem                    *hash_key_base;
 121         struct spacc_alg                *algs;
 122         unsigned                        num_algs;
 123         struct list_head                registered_algs;
 124         size_t                          cipher_pg_sz;
 125         size_t                          hash_pg_sz;
 126         const char                      *name;
 127         struct clk                      *clk;
 128         struct device                   *dev;
 129         unsigned                        max_ctxs;
 130         struct timer_list               packet_timeout;
 131         unsigned                        stat_irq_thresh;
 132         struct dma_pool                 *req_pool;
 133 };
 134
 135 /* Algorithm type mask. */
 136 #define SPACC_CRYPTO_ALG_MASK           0x7
 137
 138 /* SPACC definition of a crypto algorithm. */
 139 struct spacc_alg {
 140         unsigned long                   ctrl_default;
 141         unsigned long                   type;
 142         struct crypto_alg               alg;
 143         struct spacc_engine             *engine;
 144         struct list_head                entry;
 145         int                             key_offs;
 146         int                             iv_offs;
 147 };
 148
 149 /* Generic context structure for any algorithm type. */
 150 struct spacc_generic_ctx {
 151         struct spacc_engine             *engine;
 152         int                             flags;
 153         int                             key_offs;
 154         int                             iv_offs;
 155 };
 156
 157 /* Block cipher context. */
 158 struct spacc_ablk_ctx {
 159         struct spacc_generic_ctx        generic;
 160         u8                              key[AES_MAX_KEY_SIZE];
 161         u8                              key_len;
 162         /*
 163          * The fallback cipher. If the operation can't be done in hardware,
 164          * fallback to a software version.
 165          */
 166         struct crypto_ablkcipher        *sw_cipher;
 167 };
 168
 169 /* AEAD cipher context. */
 170 struct spacc_aead_ctx {
 171         struct spacc_generic_ctx        generic;
 172         u8                              cipher_key[AES_MAX_KEY_SIZE];
 173         u8                              hash_ctx[SPACC_CRYPTO_IPSEC_HASH_PG_SZ];
 174         u8                              cipher_key_len;
 175         u8                              hash_key_len;
 176         struct crypto_aead              *sw_cipher;
 177         size_t                          auth_size;
 178         u8                              salt[AES_BLOCK_SIZE];
 179 };
 180
 181 static int spacc_ablk_submit(struct spacc_req *req);
 182
 183 static inline struct spacc_alg *to_spacc_alg(struct crypto_alg *alg)
 184 {
 185         return alg ? container_of(alg, struct spacc_alg, alg) : NULL;
 186 }
 187
 188 static inline int spacc_fifo_cmd_full(struct spacc_engine *engine)
 189 {
 190         u32 fifo_stat = readl(engine->regs + SPA_FIFO_STAT_REG_OFFSET);
 191
 192         return fifo_stat & SPA_FIFO_CMD_FULL;
 193 }
 194
 195 /*
 196  * Given a cipher context, and a context number, get the base address of the
 197  * context page.
 198  *
 199  * Returns the address of the context page where the key/context may
 200  * be written.
 201  */
 202 static inline void __iomem *spacc_ctx_page_addr(struct spacc_generic_ctx *ctx,
 203                                                 unsigned indx,
 204                                                 bool is_cipher_ctx)
 205 {
 206         return is_cipher_ctx ? ctx->engine->cipher_ctx_base +
 207                         (indx * ctx->engine->cipher_pg_sz) :
 208                 ctx->engine->hash_key_base + (indx * ctx->engine->hash_pg_sz);
 209 }
 210
 211 /* The context pages can only be written with 32-bit accesses. */
 212 static inline void memcpy_toio32(u32 __iomem *dst, const void *src,
 213                                  unsigned count)
 214 {
 215         const u32 *src32 = (const u32 *) src;
 216
 217         while (count--)
 218                 writel(*src32++, dst++);
 219 }
 220
 221 static void spacc_cipher_write_ctx(struct spacc_generic_ctx *ctx,
 222                                    void __iomem *page_addr, const u8 *key,
 223                                    size_t key_len, const u8 *iv, size_t iv_len)
 224 {
 225         void __iomem *key_ptr = page_addr + ctx->key_offs;
 226         void __iomem *iv_ptr = page_addr + ctx->iv_offs;
 227
 228         memcpy_toio32(key_ptr, key, key_len / 4);
 229         memcpy_toio32(iv_ptr, iv, iv_len / 4);
 230 }
 231
 232 /*
 233  * Load a context into the engines context memory.
 234  *
 235  * Returns the index of the context page where the context was loaded.
 236  */
 237 static unsigned spacc_load_ctx(struct spacc_generic_ctx *ctx,
 238                                const u8 *ciph_key, size_t ciph_len,
 239                                const u8 *iv, size_t ivlen, const u8 *hash_key,
 240                                size_t hash_len)
 241 {
 242         unsigned indx = ctx->engine->next_ctx++;
 243         void __iomem *ciph_page_addr, *hash_page_addr;
 244
 245         ciph_page_addr = spacc_ctx_page_addr(ctx, indx, 1);
 246         hash_page_addr = spacc_ctx_page_addr(ctx, indx, 0);
 247
 248         ctx->engine->next_ctx &= ctx->engine->fifo_sz - 1;
 249         spacc_cipher_write_ctx(ctx, ciph_page_addr, ciph_key, ciph_len, iv,
 250                                ivlen);
 251         writel(ciph_len | (indx << SPA_KEY_SZ_CTX_INDEX_OFFSET) |
 252                (1 << SPA_KEY_SZ_CIPHER_OFFSET),
 253                ctx->engine->regs + SPA_KEY_SZ_REG_OFFSET);
 254
 255         if (hash_key) {
 256                 memcpy_toio32(hash_page_addr, hash_key, hash_len / 4);
 257                 writel(hash_len | (indx << SPA_KEY_SZ_CTX_INDEX_OFFSET),
 258                        ctx->engine->regs + SPA_KEY_SZ_REG_OFFSET);
 259         }
 260
 261         return indx;
 262 }
 263
 264 /* Count the number of scatterlist entries in a scatterlist. */
 265 static inline int sg_count(struct scatterlist *sg_list, int nbytes)
 266 {
 267         return sg_nents_for_len(sg_list, nbytes);
 268 }
 269
 270 static inline void ddt_set(struct spacc_ddt *ddt, dma_addr_t phys, size_t len)
 271 {
 272         ddt->p = phys;
 273         ddt->len = len;
 274 }
 275
 276 /*
 277  * Take a crypto request and scatterlists for the data and turn them into DDTs
 278  * for passing to the crypto engines. This also DMA maps the data so that the
 279  * crypto engines can DMA to/from them.
 280  */
 281 static struct spacc_ddt *spacc_sg_to_ddt(struct spacc_engine *engine,
 282                                          struct scatterlist *payload,
 283                                          unsigned nbytes,
 284                                          enum dma_data_direction dir,
 285                                          dma_addr_t *ddt_phys)
 286 {
 287         unsigned nents, mapped_ents;
 288         struct scatterlist *cur;
 289         struct spacc_ddt *ddt;
 290         int i;
 291
 292         nents = sg_count(payload, nbytes);
 293         mapped_ents = dma_map_sg(engine->dev, payload, nents, dir);
 294
 295         if (mapped_ents + 1 > MAX_DDT_LEN)
 296                 goto out;
 297
 298         ddt = dma_pool_alloc(engine->req_pool, GFP_ATOMIC, ddt_phys);
 299         if (!ddt)
 300                 goto out;
 301
 302         for_each_sg(payload, cur, mapped_ents, i)
 303                 ddt_set(&ddt[i], sg_dma_address(cur), sg_dma_len(cur));
 304         ddt_set(&ddt[mapped_ents], 0, 0);
 305
 306         return ddt;
 307
 308 out:
 309         dma_unmap_sg(engine->dev, payload, nents, dir);
 310         return NULL;
 311 }
 312
 313 static int spacc_aead_make_ddts(struct spacc_req *req, u8 *giv)
 314 {
 315         struct aead_request *areq = container_of(req->req, struct aead_request,
 316                                                  base);
 317         struct spacc_engine *engine = req->engine;
 318         struct spacc_ddt *src_ddt, *dst_ddt;
 319         unsigned ivsize = crypto_aead_ivsize(crypto_aead_reqtfm(areq));
 320         unsigned nents = sg_count(areq->src, areq->cryptlen);
 321         dma_addr_t iv_addr;
 322         struct scatterlist *cur;
 323         int i, dst_ents, src_ents, assoc_ents;
 324         u8 *iv = giv ? giv : areq->iv;
 325
 326         src_ddt = dma_pool_alloc(engine->req_pool, GFP_ATOMIC, &req->src_addr);
 327         if (!src_ddt)
 328                 return -ENOMEM;
 329
 330         dst_ddt = dma_pool_alloc(engine->req_pool, GFP_ATOMIC, &req->dst_addr);
 331         if (!dst_ddt) {
 332                 dma_pool_free(engine->req_pool, src_ddt, req->src_addr);
 333                 return -ENOMEM;
 334         }
 335
 336         req->src_ddt = src_ddt;
 337         req->dst_ddt = dst_ddt;
 338
 339         assoc_ents = dma_map_sg(engine->dev, areq->assoc,
 340                 sg_count(areq->assoc, areq->assoclen), DMA_TO_DEVICE);
 341         if (areq->src != areq->dst) {
 342                 src_ents = dma_map_sg(engine->dev, areq->src, nents,
 343                                       DMA_TO_DEVICE);
 344                 dst_ents = dma_map_sg(engine->dev, areq->dst, nents,
 345                                       DMA_FROM_DEVICE);
 346         } else {
 347                 src_ents = dma_map_sg(engine->dev, areq->src, nents,
 348                                       DMA_BIDIRECTIONAL);
 349                 dst_ents = 0;
 350         }
 351
 352         /*
 353          * Map the IV/GIV. For the GIV it needs to be bidirectional as it is
 354          * formed by the crypto block and sent as the ESP IV for IPSEC.
 355          */
 356         iv_addr = dma_map_single(engine->dev, iv, ivsize,
 357                                  giv ? DMA_BIDIRECTIONAL : DMA_TO_DEVICE);
 358         req->giv_pa = iv_addr;
 359
 360         /*
 361          * Map the associated data. For decryption we don't copy the
 362          * associated data.
 363          */
 364         for_each_sg(areq->assoc, cur, assoc_ents, i) {
 365                 ddt_set(src_ddt++, sg_dma_address(cur), sg_dma_len(cur));
 366                 if (req->is_encrypt)
 367                         ddt_set(dst_ddt++, sg_dma_address(cur),
 368                                 sg_dma_len(cur));
 369         }
 370         ddt_set(src_ddt++, iv_addr, ivsize);
 371
 372         if (giv || req->is_encrypt)
 373                 ddt_set(dst_ddt++, iv_addr, ivsize);
 374
 375         /*
 376          * Now map in the payload for the source and destination and terminate
 377          * with the NULL pointers.
 378          */
 379         for_each_sg(areq->src, cur, src_ents, i) {
 380                 ddt_set(src_ddt++, sg_dma_address(cur), sg_dma_len(cur));
 381                 if (areq->src == areq->dst)
 382                         ddt_set(dst_ddt++, sg_dma_address(cur),
 383                                 sg_dma_len(cur));
 384         }
 385
 386         for_each_sg(areq->dst, cur, dst_ents, i)
 387                 ddt_set(dst_ddt++, sg_dma_address(cur),
 388                         sg_dma_len(cur));
 389
 390         ddt_set(src_ddt, 0, 0);
 391         ddt_set(dst_ddt, 0, 0);
 392
 393         return 0;
 394 }
 395
 396 static void spacc_aead_free_ddts(struct spacc_req *req)
 397 {
 398         struct aead_request *areq = container_of(req->req, struct aead_request,
 399                                                  base);
 400         struct spacc_alg *alg = to_spacc_alg(req->req->tfm->__crt_alg);
 401         struct spacc_ablk_ctx *aead_ctx = crypto_tfm_ctx(req->req->tfm);
 402         struct spacc_engine *engine = aead_ctx->generic.engine;
 403         unsigned ivsize = alg->alg.cra_aead.ivsize;
 404         unsigned nents = sg_count(areq->src, areq->cryptlen);
 405
 406         if (areq->src != areq->dst) {
 407                 dma_unmap_sg(engine->dev, areq->src, nents, DMA_TO_DEVICE);
 408                 dma_unmap_sg(engine->dev, areq->dst,
 409                              sg_count(areq->dst, areq->cryptlen),
 410                              DMA_FROM_DEVICE);
 411         } else
 412                 dma_unmap_sg(engine->dev, areq->src, nents, DMA_BIDIRECTIONAL);
 413
 414         dma_unmap_sg(engine->dev, areq->assoc,
 415                      sg_count(areq->assoc, areq->assoclen), DMA_TO_DEVICE);
 416
 417         dma_unmap_single(engine->dev, req->giv_pa, ivsize, DMA_BIDIRECTIONAL);
 418
 419         dma_pool_free(engine->req_pool, req->src_ddt, req->src_addr);
 420         dma_pool_free(engine->req_pool, req->dst_ddt, req->dst_addr);
 421 }
 422
 423 static void spacc_free_ddt(struct spacc_req *req, struct spacc_ddt *ddt,
 424                            dma_addr_t ddt_addr, struct scatterlist *payload,
 425                            unsigned nbytes, enum dma_data_direction dir)
 426 {
 427         unsigned nents = sg_count(payload, nbytes);
 428
 429         dma_unmap_sg(req->engine->dev, payload, nents, dir);
 430         dma_pool_free(req->engine->req_pool, ddt, ddt_addr);
 431 }
 432
 433 /*
 434  * Set key for a DES operation in an AEAD cipher. This also performs weak key
 435  * checking if required.
 436  */
 437 static int spacc_aead_des_setkey(struct crypto_aead *aead, const u8 *key,
 438                                  unsigned int len)
 439 {
 440         struct crypto_tfm *tfm = crypto_aead_tfm(aead);
 441         struct spacc_aead_ctx *ctx = crypto_tfm_ctx(tfm);
 442         u32 tmp[DES_EXPKEY_WORDS];
 443
 444         if (unlikely(!des_ekey(tmp, key)) &&
 445             (crypto_aead_get_flags(aead)) & CRYPTO_TFM_REQ_WEAK_KEY) {
 446                 tfm->crt_flags |= CRYPTO_TFM_RES_WEAK_KEY;
 447                 return -EINVAL;
 448         }
 449
 450         memcpy(ctx->cipher_key, key, len);
 451         ctx->cipher_key_len = len;
 452
 453         return 0;
 454 }
 455
 456 /* Set the key for the AES block cipher component of the AEAD transform. */
 457 static int spacc_aead_aes_setkey(struct crypto_aead *aead, const u8 *key,
 458                                  unsigned int len)
 459 {
 460         struct crypto_tfm *tfm = crypto_aead_tfm(aead);
 461         struct spacc_aead_ctx *ctx = crypto_tfm_ctx(tfm);
 462
 463         /*
 464          * IPSec engine only supports 128 and 256 bit AES keys. If we get a
 465          * request for any other size (192 bits) then we need to do a software
 466          * fallback.
 467          */
 468         if (len != AES_KEYSIZE_128 && len != AES_KEYSIZE_256) {
 469                 /*
 470                  * Set the fallback transform to use the same request flags as
 471                  * the hardware transform.
 472                  */
 473                 ctx->sw_cipher->base.crt_flags &= ~CRYPTO_TFM_REQ_MASK;
 474                 ctx->sw_cipher->base.crt_flags |=
 475                         tfm->crt_flags & CRYPTO_TFM_REQ_MASK;
 476                 return crypto_aead_setkey(ctx->sw_cipher, key, len);
 477         }
 478
 479         memcpy(ctx->cipher_key, key, len);
 480         ctx->cipher_key_len = len;
 481
 482         return 0;
 483 }
 484
 485 static int spacc_aead_setkey(struct crypto_aead *tfm, const u8 *key,
 486                              unsigned int keylen)
 487 {
 488         struct spacc_aead_ctx *ctx = crypto_aead_ctx(tfm);
 489         struct spacc_alg *alg = to_spacc_alg(tfm->base.__crt_alg);
 490         struct crypto_authenc_keys keys;
 491         int err = -EINVAL;
 492
 493         if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
 494                 goto badkey;
 495
 496         if (keys.enckeylen > AES_MAX_KEY_SIZE)
 497                 goto badkey;
 498
 499         if (keys.authkeylen > sizeof(ctx->hash_ctx))
 500                 goto badkey;
 501
 502         if ((alg->ctrl_default & SPACC_CRYPTO_ALG_MASK) ==
 503             SPA_CTRL_CIPH_ALG_AES)
 504                 err = spacc_aead_aes_setkey(tfm, keys.enckey, keys.enckeylen);
 505         else
 506                 err = spacc_aead_des_setkey(tfm, keys.enckey, keys.enckeylen);
 507
 508         if (err)
 509                 goto badkey;
 510
 511         memcpy(ctx->hash_ctx, keys.authkey, keys.authkeylen);
 512         ctx->hash_key_len = keys.authkeylen;
 513
 514         return 0;
 515
 516 badkey:
 517         crypto_aead_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
 518         return -EINVAL;
 519 }
 520
 521 static int spacc_aead_setauthsize(struct crypto_aead *tfm,
 522                                   unsigned int authsize)
 523 {
 524         struct spacc_aead_ctx *ctx = crypto_tfm_ctx(crypto_aead_tfm(tfm));
 525
 526         ctx->auth_size = authsize;
 527
 528         return 0;
 529 }
 530
 531 /*
 532  * Check if an AEAD request requires a fallback operation. Some requests can't
 533  * be completed in hardware because the hardware may not support certain key
 534  * sizes. In these cases we need to complete the request in software.
 535  */
 536 static int spacc_aead_need_fallback(struct spacc_req *req)
 537 {
 538         struct aead_request *aead_req;
 539         struct crypto_tfm *tfm = req->req->tfm;
 540         struct crypto_alg *alg = req->req->tfm->__crt_alg;
 541         struct spacc_alg *spacc_alg = to_spacc_alg(alg);
 542         struct spacc_aead_ctx *ctx = crypto_tfm_ctx(tfm);
 543
 544         aead_req = container_of(req->req, struct aead_request, base);
 545         /*
 546          * If we have a non-supported key-length, then we need to do a
 547          * software fallback.
 548          */
 549         if ((spacc_alg->ctrl_default & SPACC_CRYPTO_ALG_MASK) ==
 550             SPA_CTRL_CIPH_ALG_AES &&
 551             ctx->cipher_key_len != AES_KEYSIZE_128 &&
 552             ctx->cipher_key_len != AES_KEYSIZE_256)
 553                 return 1;
 554
 555         return 0;
 556 }
 557
 558 static int spacc_aead_do_fallback(struct aead_request *req, unsigned alg_type,
 559                                   bool is_encrypt)
 560 {
 561         struct crypto_tfm *old_tfm = crypto_aead_tfm(crypto_aead_reqtfm(req));
 562         struct spacc_aead_ctx *ctx = crypto_tfm_ctx(old_tfm);
 563         int err;
 564
 565         if (ctx->sw_cipher) {
 566                 /*
 567                  * Change the request to use the software fallback transform,
 568                  * and once the ciphering has completed, put the old transform
 569                  * back into the request.
 570                  */
 571                 aead_request_set_tfm(req, ctx->sw_cipher);
 572                 err = is_encrypt ? crypto_aead_encrypt(req) :
 573                     crypto_aead_decrypt(req);
 574                 aead_request_set_tfm(req, __crypto_aead_cast(old_tfm));
 575         } else
 576                 err = -EINVAL;
 577
 578         return err;
 579 }
 580
 581 static void spacc_aead_complete(struct spacc_req *req)
 582 {
 583         spacc_aead_free_ddts(req);
 584         req->req->complete(req->req, req->result);
 585 }
 586
 587 static int spacc_aead_submit(struct spacc_req *req)
 588 {
 589         struct crypto_tfm *tfm = req->req->tfm;
 590         struct spacc_aead_ctx *ctx = crypto_tfm_ctx(tfm);
 591         struct crypto_alg *alg = req->req->tfm->__crt_alg;
 592         struct spacc_alg *spacc_alg = to_spacc_alg(alg);
 593         struct spacc_engine *engine = ctx->generic.engine;
 594         u32 ctrl, proc_len, assoc_len;
 595         struct aead_request *aead_req =
 596                 container_of(req->req, struct aead_request, base);
 597
 598         req->result = -EINPROGRESS;
 599         req->ctx_id = spacc_load_ctx(&ctx->generic, ctx->cipher_key,
 600                 ctx->cipher_key_len, aead_req->iv, alg->cra_aead.ivsize,
 601                 ctx->hash_ctx, ctx->hash_key_len);
 602
 603         /* Set the source and destination DDT pointers. */
 604         writel(req->src_addr, engine->regs + SPA_SRC_PTR_REG_OFFSET);
 605         writel(req->dst_addr, engine->regs + SPA_DST_PTR_REG_OFFSET);
 606         writel(0, engine->regs + SPA_OFFSET_REG_OFFSET);
 607
 608         assoc_len = aead_req->assoclen;
 609         proc_len = aead_req->cryptlen + assoc_len;
 610
 611         /*
 612          * If we aren't generating an IV, then we need to include the IV in the
 613          * associated data so that it is included in the hash.
 614          */
 615         if (!req->giv) {
 616                 assoc_len += crypto_aead_ivsize(crypto_aead_reqtfm(aead_req));
 617                 proc_len += crypto_aead_ivsize(crypto_aead_reqtfm(aead_req));
 618         } else
 619                 proc_len += req->giv_len;
 620
 621         /*
 622          * If we are decrypting, we need to take the length of the ICV out of
 623          * the processing length.
 624          */
 625         if (!req->is_encrypt)
 626                 proc_len -= ctx->auth_size;
 627
 628         writel(proc_len, engine->regs + SPA_PROC_LEN_REG_OFFSET);
 629         writel(assoc_len, engine->regs + SPA_AAD_LEN_REG_OFFSET);
 630         writel(ctx->auth_size, engine->regs + SPA_ICV_LEN_REG_OFFSET);
 631         writel(0, engine->regs + SPA_ICV_OFFSET_REG_OFFSET);
 632         writel(0, engine->regs + SPA_AUX_INFO_REG_OFFSET);
 633
 634         ctrl = spacc_alg->ctrl_default | (req->ctx_id << SPA_CTRL_CTX_IDX) |
 635                 (1 << SPA_CTRL_ICV_APPEND);
 636         if (req->is_encrypt)
 637                 ctrl |= (1 << SPA_CTRL_ENCRYPT_IDX) | (1 << SPA_CTRL_AAD_COPY);
 638         else
 639                 ctrl |= (1 << SPA_CTRL_KEY_EXP);
 640
 641         mod_timer(&engine->packet_timeout, jiffies + PACKET_TIMEOUT);
 642
 643         writel(ctrl, engine->regs + SPA_CTRL_REG_OFFSET);
 644
 645         return -EINPROGRESS;
 646 }
 647
 648 static int spacc_req_submit(struct spacc_req *req);
 649
 650 static void spacc_push(struct spacc_engine *engine)
 651 {
 652         struct spacc_req *req;
 653
 654         while (!list_empty(&engine->pending) &&
 655                engine->in_flight + 1 <= engine->fifo_sz) {
 656
 657                 ++engine->in_flight;
 658                 req = list_first_entry(&engine->pending, struct spacc_req,
 659                                        list);
 660                 list_move_tail(&req->list, &engine->in_progress);
 661
 662                 req->result = spacc_req_submit(req);
 663         }
 664 }
 665
 666 /*
 667  * Setup an AEAD request for processing. This will configure the engine, load
 668  * the context and then start the packet processing.
 669  *
 670  * @giv Pointer to destination address for a generated IV. If the
 671  *      request does not need to generate an IV then this should be set to NULL.
 672  */
 673 static int spacc_aead_setup(struct aead_request *req, u8 *giv,
 674                             unsigned alg_type, bool is_encrypt)
 675 {
 676         struct crypto_alg *alg = req->base.tfm->__crt_alg;
 677         struct spacc_engine *engine = to_spacc_alg(alg)->engine;
 678         struct spacc_req *dev_req = aead_request_ctx(req);
 679         int err = -EINPROGRESS;
 680         unsigned long flags;
 681         unsigned ivsize = crypto_aead_ivsize(crypto_aead_reqtfm(req));
 682
 683         dev_req->giv            = giv;
 684         dev_req->giv_len        = ivsize;
 685         dev_req->req            = &req->base;
 686         dev_req->is_encrypt     = is_encrypt;
 687         dev_req->result         = -EBUSY;
 688         dev_req->engine         = engine;
 689         dev_req->complete       = spacc_aead_complete;
 690
 691         if (unlikely(spacc_aead_need_fallback(dev_req)))
 692                 return spacc_aead_do_fallback(req, alg_type, is_encrypt);
 693
 694         spacc_aead_make_ddts(dev_req, dev_req->giv);
 695
 696         err = -EINPROGRESS;
 697         spin_lock_irqsave(&engine->hw_lock, flags);
 698         if (unlikely(spacc_fifo_cmd_full(engine)) ||
 699             engine->in_flight + 1 > engine->fifo_sz) {
 700                 if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) {
 701                         err = -EBUSY;
 702                         spin_unlock_irqrestore(&engine->hw_lock, flags);
 703                         goto out_free_ddts;
 704                 }
 705                 list_add_tail(&dev_req->list, &engine->pending);
 706         } else {
 707                 list_add_tail(&dev_req->list, &engine->pending);
 708                 spacc_push(engine);
 709         }
 710         spin_unlock_irqrestore(&engine->hw_lock, flags);
 711
 712         goto out;
 713
 714 out_free_ddts:
 715         spacc_aead_free_ddts(dev_req);
 716 out:
 717         return err;
 718 }
 719
 720 static int spacc_aead_encrypt(struct aead_request *req)
 721 {
 722         struct crypto_aead *aead = crypto_aead_reqtfm(req);
 723         struct crypto_tfm *tfm = crypto_aead_tfm(aead);
 724         struct spacc_alg *alg = to_spacc_alg(tfm->__crt_alg);
 725
 726         return spacc_aead_setup(req, NULL, alg->type, 1);
 727 }
 728
 729 static int spacc_aead_givencrypt(struct aead_givcrypt_request *req)
 730 {
 731         struct crypto_aead *tfm = aead_givcrypt_reqtfm(req);
 732         struct spacc_aead_ctx *ctx = crypto_aead_ctx(tfm);
 733         size_t ivsize = crypto_aead_ivsize(tfm);
 734         struct spacc_alg *alg = to_spacc_alg(tfm->base.__crt_alg);
 735         unsigned len;
 736         __be64 seq;
 737
 738         memcpy(req->areq.iv, ctx->salt, ivsize);
 739         len = ivsize;
 740         if (ivsize > sizeof(u64)) {
 741                 memset(req->giv, 0, ivsize - sizeof(u64));
 742                 len = sizeof(u64);
 743         }
 744         seq = cpu_to_be64(req->seq);
 745         memcpy(req->giv + ivsize - len, &seq, len);
 746
 747         return spacc_aead_setup(&req->areq, req->giv, alg->type, 1);
 748 }
 749
 750 static int spacc_aead_decrypt(struct aead_request *req)
 751 {
 752         struct crypto_aead *aead = crypto_aead_reqtfm(req);
 753         struct crypto_tfm *tfm = crypto_aead_tfm(aead);
 754         struct spacc_alg *alg = to_spacc_alg(tfm->__crt_alg);
 755
 756         return spacc_aead_setup(req, NULL, alg->type, 0);
 757 }
 758
 759 /*
 760  * Initialise a new AEAD context. This is responsible for allocating the
 761  * fallback cipher and initialising the context.
 762  */
 763 static int spacc_aead_cra_init(struct crypto_tfm *tfm)
 764 {
 765         struct spacc_aead_ctx *ctx = crypto_tfm_ctx(tfm);
 766         struct crypto_alg *alg = tfm->__crt_alg;
 767         struct spacc_alg *spacc_alg = to_spacc_alg(alg);
 768         struct spacc_engine *engine = spacc_alg->engine;
 769
 770         ctx->generic.flags = spacc_alg->type;
 771         ctx->generic.engine = engine;
 772         ctx->sw_cipher = crypto_alloc_aead(alg->cra_name, 0,
 773                                            CRYPTO_ALG_ASYNC |
 774                                            CRYPTO_ALG_NEED_FALLBACK);
 775         if (IS_ERR(ctx->sw_cipher)) {
 776                 dev_warn(engine->dev, "failed to allocate fallback for %s\n",
 777                          alg->cra_name);
 778                 ctx->sw_cipher = NULL;
 779         }
 780         ctx->generic.key_offs = spacc_alg->key_offs;
 781         ctx->generic.iv_offs = spacc_alg->iv_offs;
 782
 783         get_random_bytes(ctx->salt, sizeof(ctx->salt));
 784
 785         crypto_aead_set_reqsize(__crypto_aead_cast(tfm),
 786                                 sizeof(struct spacc_req));
 787
 788         return 0;
 789 }
 790
 791 /*
 792  * Destructor for an AEAD context. This is called when the transform is freed
 793  * and must free the fallback cipher.
 794  */
 795 static void spacc_aead_cra_exit(struct crypto_tfm *tfm)
 796 {
 797         struct spacc_aead_ctx *ctx = crypto_tfm_ctx(tfm);
 798
 799         if (ctx->sw_cipher)
 800                 crypto_free_aead(ctx->sw_cipher);
 801         ctx->sw_cipher = NULL;
 802 }
 803
 804 /*
 805  * Set the DES key for a block cipher transform. This also performs weak key
 806  * checking if the transform has requested it.
 807  */
 808 static int spacc_des_setkey(struct crypto_ablkcipher *cipher, const u8 *key,
 809                             unsigned int len)
 810 {
 811         struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
 812         struct spacc_ablk_ctx *ctx = crypto_tfm_ctx(tfm);
 813         u32 tmp[DES_EXPKEY_WORDS];
 814
 815         if (len > DES3_EDE_KEY_SIZE) {
 816                 crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
 817                 return -EINVAL;
 818         }
 819
 820         if (unlikely(!des_ekey(tmp, key)) &&
 821             (crypto_ablkcipher_get_flags(cipher) & CRYPTO_TFM_REQ_WEAK_KEY)) {
 822                 tfm->crt_flags |= CRYPTO_TFM_RES_WEAK_KEY;
 823                 return -EINVAL;
 824         }
 825
 826         memcpy(ctx->key, key, len);
 827         ctx->key_len = len;
 828
 829         return 0;
 830 }
 831
 832 /*
 833  * Set the key for an AES block cipher. Some key lengths are not supported in
 834  * hardware so this must also check whether a fallback is needed.
 835  */
 836 static int spacc_aes_setkey(struct crypto_ablkcipher *cipher, const u8 *key,
 837                             unsigned int len)
 838 {
 839         struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
 840         struct spacc_ablk_ctx *ctx = crypto_tfm_ctx(tfm);
 841         int err = 0;
 842
 843         if (len > AES_MAX_KEY_SIZE) {
 844                 crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
 845                 return -EINVAL;
 846         }
 847
 848         /*
 849          * IPSec engine only supports 128 and 256 bit AES keys. If we get a
 850          * request for any other size (192 bits) then we need to do a software
 851          * fallback.
 852          */
 853         if (len != AES_KEYSIZE_128 && len != AES_KEYSIZE_256 &&
 854             ctx->sw_cipher) {
 855                 /*
 856                  * Set the fallback transform to use the same request flags as
 857                  * the hardware transform.
 858                  */
 859                 ctx->sw_cipher->base.crt_flags &= ~CRYPTO_TFM_REQ_MASK;
 860                 ctx->sw_cipher->base.crt_flags |=
 861                         cipher->base.crt_flags & CRYPTO_TFM_REQ_MASK;
 862
 863                 err = crypto_ablkcipher_setkey(ctx->sw_cipher, key, len);
 864                 if (err)
 865                         goto sw_setkey_failed;
 866         } else if (len != AES_KEYSIZE_128 && len != AES_KEYSIZE_256 &&
 867                    !ctx->sw_cipher)
 868                 err = -EINVAL;
 869
 870         memcpy(ctx->key, key, len);
 871         ctx->key_len = len;
 872
 873 sw_setkey_failed:
 874         if (err && ctx->sw_cipher) {
 875                 tfm->crt_flags &= ~CRYPTO_TFM_RES_MASK;
 876                 tfm->crt_flags |=
 877                         ctx->sw_cipher->base.crt_flags & CRYPTO_TFM_RES_MASK;
 878         }
 879
 880         return err;
 881 }
 882
 883 static int spacc_kasumi_f8_setkey(struct crypto_ablkcipher *cipher,
 884                                   const u8 *key, unsigned int len)
 885 {
 886         struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
 887         struct spacc_ablk_ctx *ctx = crypto_tfm_ctx(tfm);
 888         int err = 0;
 889
 890         if (len > AES_MAX_KEY_SIZE) {
 891                 crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
 892                 err = -EINVAL;
 893                 goto out;
 894         }
 895
 896         memcpy(ctx->key, key, len);
 897         ctx->key_len = len;
 898
 899 out:
 900         return err;
 901 }
 902
 903 static int spacc_ablk_need_fallback(struct spacc_req *req)
 904 {
 905         struct spacc_ablk_ctx *ctx;
 906         struct crypto_tfm *tfm = req->req->tfm;
 907         struct crypto_alg *alg = req->req->tfm->__crt_alg;
 908         struct spacc_alg *spacc_alg = to_spacc_alg(alg);
 909
 910         ctx = crypto_tfm_ctx(tfm);
 911
 912         return (spacc_alg->ctrl_default & SPACC_CRYPTO_ALG_MASK) ==
 913                         SPA_CTRL_CIPH_ALG_AES &&
 914                         ctx->key_len != AES_KEYSIZE_128 &&
 915                         ctx->key_len != AES_KEYSIZE_256;
 916 }
 917
 918 static void spacc_ablk_complete(struct spacc_req *req)
 919 {
 920         struct ablkcipher_request *ablk_req =
 921                 container_of(req->req, struct ablkcipher_request, base);
 922
 923         if (ablk_req->src != ablk_req->dst) {
 924                 spacc_free_ddt(req, req->src_ddt, req->src_addr, ablk_req->src,
 925                                ablk_req->nbytes, DMA_TO_DEVICE);
 926                 spacc_free_ddt(req, req->dst_ddt, req->dst_addr, ablk_req->dst,
 927                                ablk_req->nbytes, DMA_FROM_DEVICE);
 928         } else
 929                 spacc_free_ddt(req, req->dst_ddt, req->dst_addr, ablk_req->dst,
 930                                ablk_req->nbytes, DMA_BIDIRECTIONAL);
 931
 932         req->req->complete(req->req, req->result);
 933 }
 934
 935 static int spacc_ablk_submit(struct spacc_req *req)
 936 {
 937         struct crypto_tfm *tfm = req->req->tfm;
 938         struct spacc_ablk_ctx *ctx = crypto_tfm_ctx(tfm);
 939         struct ablkcipher_request *ablk_req = ablkcipher_request_cast(req->req);
 940         struct crypto_alg *alg = req->req->tfm->__crt_alg;
 941         struct spacc_alg *spacc_alg = to_spacc_alg(alg);
 942         struct spacc_engine *engine = ctx->generic.engine;
 943         u32 ctrl;
 944
 945         req->ctx_id = spacc_load_ctx(&ctx->generic, ctx->key,
 946                 ctx->key_len, ablk_req->info, alg->cra_ablkcipher.ivsize,
 947                 NULL, 0);
 948
 949         writel(req->src_addr, engine->regs + SPA_SRC_PTR_REG_OFFSET);
 950         writel(req->dst_addr, engine->regs + SPA_DST_PTR_REG_OFFSET);
 951         writel(0, engine->regs + SPA_OFFSET_REG_OFFSET);
 952
 953         writel(ablk_req->nbytes, engine->regs + SPA_PROC_LEN_REG_OFFSET);
 954         writel(0, engine->regs + SPA_ICV_OFFSET_REG_OFFSET);
 955         writel(0, engine->regs + SPA_AUX_INFO_REG_OFFSET);
 956         writel(0, engine->regs + SPA_AAD_LEN_REG_OFFSET);
 957
 958         ctrl = spacc_alg->ctrl_default | (req->ctx_id << SPA_CTRL_CTX_IDX) |
 959                 (req->is_encrypt ? (1 << SPA_CTRL_ENCRYPT_IDX) :
 960                  (1 << SPA_CTRL_KEY_EXP));
 961
 962         mod_timer(&engine->packet_timeout, jiffies + PACKET_TIMEOUT);
 963
 964         writel(ctrl, engine->regs + SPA_CTRL_REG_OFFSET);
 965
 966         return -EINPROGRESS;
 967 }
 968
 969 static int spacc_ablk_do_fallback(struct ablkcipher_request *req,
 970                                   unsigned alg_type, bool is_encrypt)
 971 {
 972         struct crypto_tfm *old_tfm =
 973             crypto_ablkcipher_tfm(crypto_ablkcipher_reqtfm(req));
 974         struct spacc_ablk_ctx *ctx = crypto_tfm_ctx(old_tfm);
 975         int err;
 976
 977         if (!ctx->sw_cipher)
 978                 return -EINVAL;
 979
 980         /*
 981          * Change the request to use the software fallback transform, and once
 982          * the ciphering has completed, put the old transform back into the
 983          * request.
 984          */
 985         ablkcipher_request_set_tfm(req, ctx->sw_cipher);
 986         err = is_encrypt ? crypto_ablkcipher_encrypt(req) :
 987                 crypto_ablkcipher_decrypt(req);
 988         ablkcipher_request_set_tfm(req, __crypto_ablkcipher_cast(old_tfm));
 989
 990         return err;
 991 }
 992
 993 static int spacc_ablk_setup(struct ablkcipher_request *req, unsigned alg_type,
 994                             bool is_encrypt)
 995 {
 996         struct crypto_alg *alg = req->base.tfm->__crt_alg;
 997         struct spacc_engine *engine = to_spacc_alg(alg)->engine;
 998         struct spacc_req *dev_req = ablkcipher_request_ctx(req);
 999         unsigned long flags;
1000         int err = -ENOMEM;
1001
1002         dev_req->req            = &req->base;
1003         dev_req->is_encrypt     = is_encrypt;
1004         dev_req->engine         = engine;
1005         dev_req->complete       = spacc_ablk_complete;
1006         dev_req->result         = -EINPROGRESS;
1007
1008         if (unlikely(spacc_ablk_need_fallback(dev_req)))
1009                 return spacc_ablk_do_fallback(req, alg_type, is_encrypt);
1010
1011         /*
1012          * Create the DDT's for the engine. If we share the same source and
1013          * destination then we can optimize by reusing the DDT's.
1014          */
1015         if (req->src != req->dst) {
1016                 dev_req->src_ddt = spacc_sg_to_ddt(engine, req->src,
1017                         req->nbytes, DMA_TO_DEVICE, &dev_req->src_addr);
1018                 if (!dev_req->src_ddt)
1019                         goto out;
1020
1021                 dev_req->dst_ddt = spacc_sg_to_ddt(engine, req->dst,
1022                         req->nbytes, DMA_FROM_DEVICE, &dev_req->dst_addr);
1023                 if (!dev_req->dst_ddt)
1024                         goto out_free_src;
1025         } else {
1026                 dev_req->dst_ddt = spacc_sg_to_ddt(engine, req->dst,
1027                         req->nbytes, DMA_BIDIRECTIONAL, &dev_req->dst_addr);
1028                 if (!dev_req->dst_ddt)
1029                         goto out;
1030
1031                 dev_req->src_ddt = NULL;
1032                 dev_req->src_addr = dev_req->dst_addr;
1033         }
1034
1035         err = -EINPROGRESS;
1036         spin_lock_irqsave(&engine->hw_lock, flags);
1037         /*
1038          * Check if the engine will accept the operation now. If it won't then
1039          * we either stick it on the end of a pending list if we can backlog,
1040          * or bailout with an error if not.
1041          */
1042         if (unlikely(spacc_fifo_cmd_full(engine)) ||
1043             engine->in_flight + 1 > engine->fifo_sz) {
1044                 if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) {
1045                         err = -EBUSY;
1046                         spin_unlock_irqrestore(&engine->hw_lock, flags);
1047                         goto out_free_ddts;
1048                 }
1049                 list_add_tail(&dev_req->list, &engine->pending);
1050         } else {
1051                 list_add_tail(&dev_req->list, &engine->pending);
1052                 spacc_push(engine);
1053         }
1054         spin_unlock_irqrestore(&engine->hw_lock, flags);
1055
1056         goto out;
1057
1058 out_free_ddts:
1059         spacc_free_ddt(dev_req, dev_req->dst_ddt, dev_req->dst_addr, req->dst,
1060                        req->nbytes, req->src == req->dst ?
1061                        DMA_BIDIRECTIONAL : DMA_FROM_DEVICE);
1062 out_free_src:
1063         if (req->src != req->dst)
1064                 spacc_free_ddt(dev_req, dev_req->src_ddt, dev_req->src_addr,
1065                                req->src, req->nbytes, DMA_TO_DEVICE);
1066 out:
1067         return err;
1068 }
1069
1070 static int spacc_ablk_cra_init(struct crypto_tfm *tfm)
1071 {
1072         struct spacc_ablk_ctx *ctx = crypto_tfm_ctx(tfm);
1073         struct crypto_alg *alg = tfm->__crt_alg;
1074         struct spacc_alg *spacc_alg = to_spacc_alg(alg);
1075         struct spacc_engine *engine = spacc_alg->engine;
1076
1077         ctx->generic.flags = spacc_alg->type;
1078         ctx->generic.engine = engine;
1079         if (alg->cra_flags & CRYPTO_ALG_NEED_FALLBACK) {
1080                 ctx->sw_cipher = crypto_alloc_ablkcipher(alg->cra_name, 0,
1081                                 CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK);
1082                 if (IS_ERR(ctx->sw_cipher)) {
1083                         dev_warn(engine->dev, "failed to allocate fallback for %s\n",
1084                                  alg->cra_name);
1085                         ctx->sw_cipher = NULL;
1086                 }
1087         }
1088         ctx->generic.key_offs = spacc_alg->key_offs;
1089         ctx->generic.iv_offs = spacc_alg->iv_offs;
1090
1091         tfm->crt_ablkcipher.reqsize = sizeof(struct spacc_req);
1092
1093         return 0;
1094 }
1095
1096 static void spacc_ablk_cra_exit(struct crypto_tfm *tfm)
1097 {
1098         struct spacc_ablk_ctx *ctx = crypto_tfm_ctx(tfm);
1099
1100         if (ctx->sw_cipher)
1101                 crypto_free_ablkcipher(ctx->sw_cipher);
1102         ctx->sw_cipher = NULL;
1103 }
1104
1105 static int spacc_ablk_encrypt(struct ablkcipher_request *req)
1106 {
1107         struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(req);
1108         struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
1109         struct spacc_alg *alg = to_spacc_alg(tfm->__crt_alg);
1110
1111         return spacc_ablk_setup(req, alg->type, 1);
1112 }
1113
1114 static int spacc_ablk_decrypt(struct ablkcipher_request *req)
1115 {
1116         struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(req);
1117         struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
1118         struct spacc_alg *alg = to_spacc_alg(tfm->__crt_alg);
1119
1120         return spacc_ablk_setup(req, alg->type, 0);
1121 }
1122
1123 static inline int spacc_fifo_stat_empty(struct spacc_engine *engine)
1124 {
1125         return readl(engine->regs + SPA_FIFO_STAT_REG_OFFSET) &
1126                 SPA_FIFO_STAT_EMPTY;
1127 }
1128
1129 static void spacc_process_done(struct spacc_engine *engine)
1130 {
1131         struct spacc_req *req;
1132         unsigned long flags;
1133
1134         spin_lock_irqsave(&engine->hw_lock, flags);
1135
1136         while (!spacc_fifo_stat_empty(engine)) {
1137                 req = list_first_entry(&engine->in_progress, struct spacc_req,
1138                                        list);
1139                 list_move_tail(&req->list, &engine->completed);
1140                 --engine->in_flight;
1141
1142                 /* POP the status register. */
1143                 writel(~0, engine->regs + SPA_STAT_POP_REG_OFFSET);
1144                 req->result = (readl(engine->regs + SPA_STATUS_REG_OFFSET) &
1145                      SPA_STATUS_RES_CODE_MASK) >> SPA_STATUS_RES_CODE_OFFSET;
1146
1147                 /*
1148                  * Convert the SPAcc error status into the standard POSIX error
1149                  * codes.
1150                  */
1151                 if (unlikely(req->result)) {
1152                         switch (req->result) {
1153                         case SPA_STATUS_ICV_FAIL:
1154                                 req->result = -EBADMSG;
1155                                 break;
1156
1157                         case SPA_STATUS_MEMORY_ERROR:
1158                                 dev_warn(engine->dev,
1159                                          "memory error triggered\n");
1160                                 req->result = -EFAULT;
1161                                 break;
1162
1163                         case SPA_STATUS_BLOCK_ERROR:
1164                                 dev_warn(engine->dev,
1165                                          "block error triggered\n");
1166                                 req->result = -EIO;
1167                                 break;
1168                         }
1169                 }
1170         }
1171
1172         tasklet_schedule(&engine->complete);
1173
1174         spin_unlock_irqrestore(&engine->hw_lock, flags);
1175 }
1176
1177 static irqreturn_t spacc_spacc_irq(int irq, void *dev)
1178 {
1179         struct spacc_engine *engine = (struct spacc_engine *)dev;
1180         u32 spacc_irq_stat = readl(engine->regs + SPA_IRQ_STAT_REG_OFFSET);
1181
1182         writel(spacc_irq_stat, engine->regs + SPA_IRQ_STAT_REG_OFFSET);
1183         spacc_process_done(engine);
1184
1185         return IRQ_HANDLED;
1186 }
1187
1188 static void spacc_packet_timeout(unsigned long data)
1189 {
1190         struct spacc_engine *engine = (struct spacc_engine *)data;
1191
1192         spacc_process_done(engine);
1193 }
1194
1195 static int spacc_req_submit(struct spacc_req *req)
1196 {
1197         struct crypto_alg *alg = req->req->tfm->__crt_alg;
1198
1199         if (CRYPTO_ALG_TYPE_AEAD == (CRYPTO_ALG_TYPE_MASK & alg->cra_flags))
1200                 return spacc_aead_submit(req);
1201         else
1202                 return spacc_ablk_submit(req);
1203 }
1204
1205 static void spacc_spacc_complete(unsigned long data)
1206 {
1207         struct spacc_engine *engine = (struct spacc_engine *)data;
1208         struct spacc_req *req, *tmp;
1209         unsigned long flags;
1210         LIST_HEAD(completed);
1211
1212         spin_lock_irqsave(&engine->hw_lock, flags);
1213
1214         list_splice_init(&engine->completed, &completed);
1215         spacc_push(engine);
1216         if (engine->in_flight)
1217                 mod_timer(&engine->packet_timeout, jiffies + PACKET_TIMEOUT);
1218
1219         spin_unlock_irqrestore(&engine->hw_lock, flags);
1220
1221         list_for_each_entry_safe(req, tmp, &completed, list) {
1222                 list_del(&req->list);
1223                 req->complete(req);
1224         }
1225 }
1226
1227 #ifdef CONFIG_PM
1228 static int spacc_suspend(struct device *dev)
1229 {
1230         struct platform_device *pdev = to_platform_device(dev);
1231         struct spacc_engine *engine = platform_get_drvdata(pdev);
1232
1233         /*
1234          * We only support standby mode. All we have to do is gate the clock to
1235          * the spacc. The hardware will preserve state until we turn it back
1236          * on again.
1237          */
1238         clk_disable(engine->clk);
1239
1240         return 0;
1241 }
1242
1243 static int spacc_resume(struct device *dev)
1244 {
1245         struct platform_device *pdev = to_platform_device(dev);
1246         struct spacc_engine *engine = platform_get_drvdata(pdev);
1247
1248         return clk_enable(engine->clk);
1249 }
1250
1251 static const struct dev_pm_ops spacc_pm_ops = {
1252         .suspend        = spacc_suspend,
1253         .resume         = spacc_resume,
1254 };
1255 #endif /* CONFIG_PM */
1256
1257 static inline struct spacc_engine *spacc_dev_to_engine(struct device *dev)
1258 {
1259         return dev ? platform_get_drvdata(to_platform_device(dev)) : NULL;
1260 }
1261
1262 static ssize_t spacc_stat_irq_thresh_show(struct device *dev,
1263                                           struct device_attribute *attr,
1264                                           char *buf)
1265 {
1266         struct spacc_engine *engine = spacc_dev_to_engine(dev);
1267
1268         return snprintf(buf, PAGE_SIZE, "%u\n", engine->stat_irq_thresh);
1269 }
1270
1271 static ssize_t spacc_stat_irq_thresh_store(struct device *dev,
1272                                            struct device_attribute *attr,
1273                                            const char *buf, size_t len)
1274 {
1275         struct spacc_engine *engine = spacc_dev_to_engine(dev);
1276         unsigned long thresh;
1277
1278         if (kstrtoul(buf, 0, &thresh))
1279                 return -EINVAL;
1280
1281         thresh = clamp(thresh, 1UL, engine->fifo_sz - 1);
1282
1283         engine->stat_irq_thresh = thresh;
1284         writel(engine->stat_irq_thresh << SPA_IRQ_CTRL_STAT_CNT_OFFSET,
1285                engine->regs + SPA_IRQ_CTRL_REG_OFFSET);
1286
1287         return len;
1288 }
1289 static DEVICE_ATTR(stat_irq_thresh, 0644, spacc_stat_irq_thresh_show,
1290                    spacc_stat_irq_thresh_store);
1291
1292 static struct spacc_alg ipsec_engine_algs[] = {
1293         {
1294                 .ctrl_default = SPA_CTRL_CIPH_ALG_AES | SPA_CTRL_CIPH_MODE_CBC,
1295                 .key_offs = 0,
1296                 .iv_offs = AES_MAX_KEY_SIZE,
1297                 .alg = {
1298                         .cra_name = "cbc(aes)",
1299                         .cra_driver_name = "cbc-aes-picoxcell",
1300                         .cra_priority = SPACC_CRYPTO_ALG_PRIORITY,
1301                         .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
1302                                      CRYPTO_ALG_KERN_DRIVER_ONLY |
1303                                      CRYPTO_ALG_ASYNC |
1304                                      CRYPTO_ALG_NEED_FALLBACK,
1305                         .cra_blocksize = AES_BLOCK_SIZE,
1306                         .cra_ctxsize = sizeof(struct spacc_ablk_ctx),
1307                         .cra_type = &crypto_ablkcipher_type,
1308                         .cra_module = THIS_MODULE,
1309                         .cra_ablkcipher = {
1310                                 .setkey = spacc_aes_setkey,
1311                                 .encrypt = spacc_ablk_encrypt,
1312                                 .decrypt = spacc_ablk_decrypt,
1313                                 .min_keysize = AES_MIN_KEY_SIZE,
1314                                 .max_keysize = AES_MAX_KEY_SIZE,
1315                                 .ivsize = AES_BLOCK_SIZE,
1316                         },
1317                         .cra_init = spacc_ablk_cra_init,
1318                         .cra_exit = spacc_ablk_cra_exit,
1319                 },
1320         },
1321         {
1322                 .key_offs = 0,
1323                 .iv_offs = AES_MAX_KEY_SIZE,
1324                 .ctrl_default = SPA_CTRL_CIPH_ALG_AES | SPA_CTRL_CIPH_MODE_ECB,
1325                 .alg = {
1326                         .cra_name = "ecb(aes)",
1327                         .cra_driver_name = "ecb-aes-picoxcell",
1328                         .cra_priority = SPACC_CRYPTO_ALG_PRIORITY,
1329                         .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
1330                                 CRYPTO_ALG_KERN_DRIVER_ONLY |
1331                                 CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
1332                         .cra_blocksize = AES_BLOCK_SIZE,
1333                         .cra_ctxsize = sizeof(struct spacc_ablk_ctx),
1334                         .cra_type = &crypto_ablkcipher_type,
1335                         .cra_module = THIS_MODULE,
1336                         .cra_ablkcipher = {
1337                                 .setkey = spacc_aes_setkey,
1338                                 .encrypt = spacc_ablk_encrypt,
1339                                 .decrypt = spacc_ablk_decrypt,
1340                                 .min_keysize = AES_MIN_KEY_SIZE,
1341                                 .max_keysize = AES_MAX_KEY_SIZE,
1342                         },
1343                         .cra_init = spacc_ablk_cra_init,
1344                         .cra_exit = spacc_ablk_cra_exit,
1345                 },
1346         },
1347         {
1348                 .key_offs = DES_BLOCK_SIZE,
1349                 .iv_offs = 0,
1350                 .ctrl_default = SPA_CTRL_CIPH_ALG_DES | SPA_CTRL_CIPH_MODE_CBC,
1351                 .alg = {
1352                         .cra_name = "cbc(des)",
1353                         .cra_driver_name = "cbc-des-picoxcell",
1354                         .cra_priority = SPACC_CRYPTO_ALG_PRIORITY,
1355                         .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
1356                                         CRYPTO_ALG_ASYNC |
1357                                         CRYPTO_ALG_KERN_DRIVER_ONLY,
1358                         .cra_blocksize = DES_BLOCK_SIZE,
1359                         .cra_ctxsize = sizeof(struct spacc_ablk_ctx),
1360                         .cra_type = &crypto_ablkcipher_type,
1361                         .cra_module = THIS_MODULE,
1362                         .cra_ablkcipher = {
1363                                 .setkey = spacc_des_setkey,
1364                                 .encrypt = spacc_ablk_encrypt,
1365                                 .decrypt = spacc_ablk_decrypt,
1366                                 .min_keysize = DES_KEY_SIZE,
1367                                 .max_keysize = DES_KEY_SIZE,
1368                                 .ivsize = DES_BLOCK_SIZE,
1369                         },
1370                         .cra_init = spacc_ablk_cra_init,
1371                         .cra_exit = spacc_ablk_cra_exit,
1372                 },
1373         },
1374         {
1375                 .key_offs = DES_BLOCK_SIZE,
1376                 .iv_offs = 0,
1377                 .ctrl_default = SPA_CTRL_CIPH_ALG_DES | SPA_CTRL_CIPH_MODE_ECB,
1378                 .alg = {
1379                         .cra_name = "ecb(des)",
1380                         .cra_driver_name = "ecb-des-picoxcell",
1381                         .cra_priority = SPACC_CRYPTO_ALG_PRIORITY,
1382                         .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
1383                                         CRYPTO_ALG_ASYNC |
1384                                         CRYPTO_ALG_KERN_DRIVER_ONLY,
1385                         .cra_blocksize = DES_BLOCK_SIZE,
1386                         .cra_ctxsize = sizeof(struct spacc_ablk_ctx),
1387                         .cra_type = &crypto_ablkcipher_type,
1388                         .cra_module = THIS_MODULE,
1389                         .cra_ablkcipher = {
1390                                 .setkey = spacc_des_setkey,
1391                                 .encrypt = spacc_ablk_encrypt,
1392                                 .decrypt = spacc_ablk_decrypt,
1393                                 .min_keysize = DES_KEY_SIZE,
1394                                 .max_keysize = DES_KEY_SIZE,
1395                         },
1396                         .cra_init = spacc_ablk_cra_init,
1397                         .cra_exit = spacc_ablk_cra_exit,
1398                 },
1399         },
1400         {
1401                 .key_offs = DES_BLOCK_SIZE,
1402                 .iv_offs = 0,
1403                 .ctrl_default = SPA_CTRL_CIPH_ALG_DES | SPA_CTRL_CIPH_MODE_CBC,
1404                 .alg = {
1405                         .cra_name = "cbc(des3_ede)",
1406                         .cra_driver_name = "cbc-des3-ede-picoxcell",
1407                         .cra_priority = SPACC_CRYPTO_ALG_PRIORITY,
1408                         .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
1409                                         CRYPTO_ALG_ASYNC |
1410                                         CRYPTO_ALG_KERN_DRIVER_ONLY,
1411                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1412                         .cra_ctxsize = sizeof(struct spacc_ablk_ctx),
1413                         .cra_type = &crypto_ablkcipher_type,
1414                         .cra_module = THIS_MODULE,
1415                         .cra_ablkcipher = {
1416                                 .setkey = spacc_des_setkey,
1417                                 .encrypt = spacc_ablk_encrypt,
1418                                 .decrypt = spacc_ablk_decrypt,
1419                                 .min_keysize = DES3_EDE_KEY_SIZE,
1420                                 .max_keysize = DES3_EDE_KEY_SIZE,
1421                                 .ivsize = DES3_EDE_BLOCK_SIZE,
1422                         },
1423                         .cra_init = spacc_ablk_cra_init,
1424                         .cra_exit = spacc_ablk_cra_exit,
1425                 },
1426         },
1427         {
1428                 .key_offs = DES_BLOCK_SIZE,
1429                 .iv_offs = 0,
1430                 .ctrl_default = SPA_CTRL_CIPH_ALG_DES | SPA_CTRL_CIPH_MODE_ECB,
1431                 .alg = {
1432                         .cra_name = "ecb(des3_ede)",
1433                         .cra_driver_name = "ecb-des3-ede-picoxcell",
1434                         .cra_priority = SPACC_CRYPTO_ALG_PRIORITY,
1435                         .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
1436                                         CRYPTO_ALG_ASYNC |
1437                                         CRYPTO_ALG_KERN_DRIVER_ONLY,
1438                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1439                         .cra_ctxsize = sizeof(struct spacc_ablk_ctx),
1440                         .cra_type = &crypto_ablkcipher_type,
1441                         .cra_module = THIS_MODULE,
1442                         .cra_ablkcipher = {
1443                                 .setkey = spacc_des_setkey,
1444                                 .encrypt = spacc_ablk_encrypt,
1445                                 .decrypt = spacc_ablk_decrypt,
1446                                 .min_keysize = DES3_EDE_KEY_SIZE,
1447                                 .max_keysize = DES3_EDE_KEY_SIZE,
1448                         },
1449                         .cra_init = spacc_ablk_cra_init,
1450                         .cra_exit = spacc_ablk_cra_exit,
1451                 },
1452         },
1453         {
1454                 .ctrl_default = SPA_CTRL_CIPH_ALG_AES | SPA_CTRL_CIPH_MODE_CBC |
1455                                 SPA_CTRL_HASH_ALG_SHA | SPA_CTRL_HASH_MODE_HMAC,
1456                 .key_offs = 0,
1457                 .iv_offs = AES_MAX_KEY_SIZE,
1458                 .alg = {
1459                         .cra_name = "authenc(hmac(sha1),cbc(aes))",
1460                         .cra_driver_name = "authenc-hmac-sha1-cbc-aes-picoxcell",
1461                         .cra_priority = SPACC_CRYPTO_ALG_PRIORITY,
1462                         .cra_flags = CRYPTO_ALG_TYPE_AEAD |
1463                                         CRYPTO_ALG_ASYNC |
1464                                         CRYPTO_ALG_KERN_DRIVER_ONLY,
1465                         .cra_blocksize = AES_BLOCK_SIZE,
1466                         .cra_ctxsize = sizeof(struct spacc_aead_ctx),
1467                         .cra_type = &crypto_aead_type,
1468                         .cra_module = THIS_MODULE,
1469                         .cra_aead = {
1470                                 .setkey = spacc_aead_setkey,
1471                                 .setauthsize = spacc_aead_setauthsize,
1472                                 .encrypt = spacc_aead_encrypt,
1473                                 .decrypt = spacc_aead_decrypt,
1474                                 .givencrypt = spacc_aead_givencrypt,
1475                                 .ivsize = AES_BLOCK_SIZE,
1476                                 .maxauthsize = SHA1_DIGEST_SIZE,
1477                         },
1478                         .cra_init = spacc_aead_cra_init,
1479                         .cra_exit = spacc_aead_cra_exit,
1480                 },
1481         },
1482         {
1483                 .ctrl_default = SPA_CTRL_CIPH_ALG_AES | SPA_CTRL_CIPH_MODE_CBC |
1484                                 SPA_CTRL_HASH_ALG_SHA256 |
1485                                 SPA_CTRL_HASH_MODE_HMAC,
1486                 .key_offs = 0,
1487                 .iv_offs = AES_MAX_KEY_SIZE,
1488                 .alg = {
1489                         .cra_name = "authenc(hmac(sha256),cbc(aes))",
1490                         .cra_driver_name = "authenc-hmac-sha256-cbc-aes-picoxcell",
1491                         .cra_priority = SPACC_CRYPTO_ALG_PRIORITY,
1492                         .cra_flags = CRYPTO_ALG_TYPE_AEAD |
1493                                         CRYPTO_ALG_ASYNC |
1494                                         CRYPTO_ALG_KERN_DRIVER_ONLY,
1495                         .cra_blocksize = AES_BLOCK_SIZE,
1496                         .cra_ctxsize = sizeof(struct spacc_aead_ctx),
1497                         .cra_type = &crypto_aead_type,
1498                         .cra_module = THIS_MODULE,
1499                         .cra_aead = {
1500                                 .setkey = spacc_aead_setkey,
1501                                 .setauthsize = spacc_aead_setauthsize,
1502                                 .encrypt = spacc_aead_encrypt,
1503                                 .decrypt = spacc_aead_decrypt,
1504                                 .givencrypt = spacc_aead_givencrypt,
1505                                 .ivsize = AES_BLOCK_SIZE,
1506                                 .maxauthsize = SHA256_DIGEST_SIZE,
1507                         },
1508                         .cra_init = spacc_aead_cra_init,
1509                         .cra_exit = spacc_aead_cra_exit,
1510                 },
1511         },
1512         {
1513                 .key_offs = 0,
1514                 .iv_offs = AES_MAX_KEY_SIZE,
1515                 .ctrl_default = SPA_CTRL_CIPH_ALG_AES | SPA_CTRL_CIPH_MODE_CBC |
1516                                 SPA_CTRL_HASH_ALG_MD5 | SPA_CTRL_HASH_MODE_HMAC,
1517                 .alg = {
1518                         .cra_name = "authenc(hmac(md5),cbc(aes))",
1519                         .cra_driver_name = "authenc-hmac-md5-cbc-aes-picoxcell",
1520                         .cra_priority = SPACC_CRYPTO_ALG_PRIORITY,
1521                         .cra_flags = CRYPTO_ALG_TYPE_AEAD |
1522                                         CRYPTO_ALG_ASYNC |
1523                                         CRYPTO_ALG_KERN_DRIVER_ONLY,
1524                         .cra_blocksize = AES_BLOCK_SIZE,
1525                         .cra_ctxsize = sizeof(struct spacc_aead_ctx),
1526                         .cra_type = &crypto_aead_type,
1527                         .cra_module = THIS_MODULE,
1528                         .cra_aead = {
1529                                 .setkey = spacc_aead_setkey,
1530                                 .setauthsize = spacc_aead_setauthsize,
1531                                 .encrypt = spacc_aead_encrypt,
1532                                 .decrypt = spacc_aead_decrypt,
1533                                 .givencrypt = spacc_aead_givencrypt,
1534                                 .ivsize = AES_BLOCK_SIZE,
1535                                 .maxauthsize = MD5_DIGEST_SIZE,
1536                         },
1537                         .cra_init = spacc_aead_cra_init,
1538                         .cra_exit = spacc_aead_cra_exit,
1539                 },
1540         },
1541         {
1542                 .key_offs = DES_BLOCK_SIZE,
1543                 .iv_offs = 0,
1544                 .ctrl_default = SPA_CTRL_CIPH_ALG_DES | SPA_CTRL_CIPH_MODE_CBC |
1545                                 SPA_CTRL_HASH_ALG_SHA | SPA_CTRL_HASH_MODE_HMAC,
1546                 .alg = {
1547                         .cra_name = "authenc(hmac(sha1),cbc(des3_ede))",
1548                         .cra_driver_name = "authenc-hmac-sha1-cbc-3des-picoxcell",
1549                         .cra_priority = SPACC_CRYPTO_ALG_PRIORITY,
1550                         .cra_flags = CRYPTO_ALG_TYPE_AEAD |
1551                                         CRYPTO_ALG_ASYNC |
1552                                         CRYPTO_ALG_KERN_DRIVER_ONLY,
1553                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1554                         .cra_ctxsize = sizeof(struct spacc_aead_ctx),
1555                         .cra_type = &crypto_aead_type,
1556                         .cra_module = THIS_MODULE,
1557                         .cra_aead = {
1558                                 .setkey = spacc_aead_setkey,
1559                                 .setauthsize = spacc_aead_setauthsize,
1560                                 .encrypt = spacc_aead_encrypt,
1561                                 .decrypt = spacc_aead_decrypt,
1562                                 .givencrypt = spacc_aead_givencrypt,
1563                                 .ivsize = DES3_EDE_BLOCK_SIZE,
1564                                 .maxauthsize = SHA1_DIGEST_SIZE,
1565                         },
1566                         .cra_init = spacc_aead_cra_init,
1567                         .cra_exit = spacc_aead_cra_exit,
1568                 },
1569         },
1570         {
1571                 .key_offs = DES_BLOCK_SIZE,
1572                 .iv_offs = 0,
1573                 .ctrl_default = SPA_CTRL_CIPH_ALG_AES | SPA_CTRL_CIPH_MODE_CBC |
1574                                 SPA_CTRL_HASH_ALG_SHA256 |
1575                                 SPA_CTRL_HASH_MODE_HMAC,
1576                 .alg = {
1577                         .cra_name = "authenc(hmac(sha256),cbc(des3_ede))",
1578                         .cra_driver_name = "authenc-hmac-sha256-cbc-3des-picoxcell",
1579                         .cra_priority = SPACC_CRYPTO_ALG_PRIORITY,
1580                         .cra_flags = CRYPTO_ALG_TYPE_AEAD |
1581                                         CRYPTO_ALG_ASYNC |
1582                                         CRYPTO_ALG_KERN_DRIVER_ONLY,
1583                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1584                         .cra_ctxsize = sizeof(struct spacc_aead_ctx),
1585                         .cra_type = &crypto_aead_type,
1586                         .cra_module = THIS_MODULE,
1587                         .cra_aead = {
1588                                 .setkey = spacc_aead_setkey,
1589                                 .setauthsize = spacc_aead_setauthsize,
1590                                 .encrypt = spacc_aead_encrypt,
1591                                 .decrypt = spacc_aead_decrypt,
1592                                 .givencrypt = spacc_aead_givencrypt,
1593                                 .ivsize = DES3_EDE_BLOCK_SIZE,
1594                                 .maxauthsize = SHA256_DIGEST_SIZE,
1595                         },
1596                         .cra_init = spacc_aead_cra_init,
1597                         .cra_exit = spacc_aead_cra_exit,
1598                 },
1599         },
1600         {
1601                 .key_offs = DES_BLOCK_SIZE,
1602                 .iv_offs = 0,
1603                 .ctrl_default = SPA_CTRL_CIPH_ALG_DES | SPA_CTRL_CIPH_MODE_CBC |
1604                                 SPA_CTRL_HASH_ALG_MD5 | SPA_CTRL_HASH_MODE_HMAC,
1605                 .alg = {
1606                         .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
1607                         .cra_driver_name = "authenc-hmac-md5-cbc-3des-picoxcell",
1608                         .cra_priority = SPACC_CRYPTO_ALG_PRIORITY,
1609                         .cra_flags = CRYPTO_ALG_TYPE_AEAD |
1610                                         CRYPTO_ALG_ASYNC |
1611                                         CRYPTO_ALG_KERN_DRIVER_ONLY,
1612                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1613                         .cra_ctxsize = sizeof(struct spacc_aead_ctx),
1614                         .cra_type = &crypto_aead_type,
1615                         .cra_module = THIS_MODULE,
1616                         .cra_aead = {
1617                                 .setkey = spacc_aead_setkey,
1618                                 .setauthsize = spacc_aead_setauthsize,
1619                                 .encrypt = spacc_aead_encrypt,
1620                                 .decrypt = spacc_aead_decrypt,
1621                                 .givencrypt = spacc_aead_givencrypt,
1622                                 .ivsize = DES3_EDE_BLOCK_SIZE,
1623                                 .maxauthsize = MD5_DIGEST_SIZE,
1624                         },
1625                         .cra_init = spacc_aead_cra_init,
1626                         .cra_exit = spacc_aead_cra_exit,
1627                 },
1628         },
1629 };
1630
1631 static struct spacc_alg l2_engine_algs[] = {
1632         {
1633                 .key_offs = 0,
1634                 .iv_offs = SPACC_CRYPTO_KASUMI_F8_KEY_LEN,
1635                 .ctrl_default = SPA_CTRL_CIPH_ALG_KASUMI |
1636                                 SPA_CTRL_CIPH_MODE_F8,
1637                 .alg = {
1638                         .cra_name = "f8(kasumi)",
1639                         .cra_driver_name = "f8-kasumi-picoxcell",
1640                         .cra_priority = SPACC_CRYPTO_ALG_PRIORITY,
1641                         .cra_flags = CRYPTO_ALG_TYPE_GIVCIPHER |
1642                                         CRYPTO_ALG_ASYNC |
1643                                         CRYPTO_ALG_KERN_DRIVER_ONLY,
1644                         .cra_blocksize = 8,
1645                         .cra_ctxsize = sizeof(struct spacc_ablk_ctx),
1646                         .cra_type = &crypto_ablkcipher_type,
1647                         .cra_module = THIS_MODULE,
1648                         .cra_ablkcipher = {
1649                                 .setkey = spacc_kasumi_f8_setkey,
1650                                 .encrypt = spacc_ablk_encrypt,
1651                                 .decrypt = spacc_ablk_decrypt,
1652                                 .min_keysize = 16,
1653                                 .max_keysize = 16,
1654                                 .ivsize = 8,
1655                         },
1656                         .cra_init = spacc_ablk_cra_init,
1657                         .cra_exit = spacc_ablk_cra_exit,
1658                 },
1659         },
1660 };
1661
1662 #ifdef CONFIG_OF
1663 static const struct of_device_id spacc_of_id_table[] = {
1664         { .compatible = "picochip,spacc-ipsec" },
1665         { .compatible = "picochip,spacc-l2" },
1666         {}
1667 };
1668 #endif /* CONFIG_OF */
1669
1670 static bool spacc_is_compatible(struct platform_device *pdev,
1671                                 const char *spacc_type)
1672 {
1673         const struct platform_device_id *platid = platform_get_device_id(pdev);
1674
1675         if (platid && !strcmp(platid->name, spacc_type))
1676                 return true;
1677
1678 #ifdef CONFIG_OF
1679         if (of_device_is_compatible(pdev->dev.of_node, spacc_type))
1680                 return true;
1681 #endif /* CONFIG_OF */
1682
1683         return false;
1684 }
1685
1686 static int spacc_probe(struct platform_device *pdev)
1687 {
1688         int i, err, ret = -EINVAL;
1689         struct resource *mem, *irq;
1690         struct spacc_engine *engine = devm_kzalloc(&pdev->dev, sizeof(*engine),
1691                                                    GFP_KERNEL);
1692         if (!engine)
1693                 return -ENOMEM;
1694
1695         if (spacc_is_compatible(pdev, "picochip,spacc-ipsec")) {
1696                 engine->max_ctxs        = SPACC_CRYPTO_IPSEC_MAX_CTXS;
1697                 engine->cipher_pg_sz    = SPACC_CRYPTO_IPSEC_CIPHER_PG_SZ;
1698                 engine->hash_pg_sz      = SPACC_CRYPTO_IPSEC_HASH_PG_SZ;
1699                 engine->fifo_sz         = SPACC_CRYPTO_IPSEC_FIFO_SZ;
1700                 engine->algs            = ipsec_engine_algs;
1701                 engine->num_algs        = ARRAY_SIZE(ipsec_engine_algs);
1702         } else if (spacc_is_compatible(pdev, "picochip,spacc-l2")) {
1703                 engine->max_ctxs        = SPACC_CRYPTO_L2_MAX_CTXS;
1704                 engine->cipher_pg_sz    = SPACC_CRYPTO_L2_CIPHER_PG_SZ;
1705                 engine->hash_pg_sz      = SPACC_CRYPTO_L2_HASH_PG_SZ;
1706                 engine->fifo_sz         = SPACC_CRYPTO_L2_FIFO_SZ;
1707                 engine->algs            = l2_engine_algs;
1708                 engine->num_algs        = ARRAY_SIZE(l2_engine_algs);
1709         } else {
1710                 return -EINVAL;
1711         }
1712
1713         engine->name = dev_name(&pdev->dev);
1714
1715         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1716         engine->regs = devm_ioremap_resource(&pdev->dev, mem);
1717         if (IS_ERR(engine->regs))
1718                 return PTR_ERR(engine->regs);
1719
1720         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1721         if (!irq) {
1722                 dev_err(&pdev->dev, "no memory/irq resource for engine\n");
1723                 return -ENXIO;
1724         }
1725
1726         if (devm_request_irq(&pdev->dev, irq->start, spacc_spacc_irq, 0,
1727                              engine->name, engine)) {
1728                 dev_err(engine->dev, "failed to request IRQ\n");
1729                 return -EBUSY;
1730         }
1731
1732         engine->dev             = &pdev->dev;
1733         engine->cipher_ctx_base = engine->regs + SPA_CIPH_KEY_BASE_REG_OFFSET;
1734         engine->hash_key_base   = engine->regs + SPA_HASH_KEY_BASE_REG_OFFSET;
1735
1736         engine->req_pool = dmam_pool_create(engine->name, engine->dev,
1737                 MAX_DDT_LEN * sizeof(struct spacc_ddt), 8, SZ_64K);
1738         if (!engine->req_pool)
1739                 return -ENOMEM;
1740
1741         spin_lock_init(&engine->hw_lock);
1742
1743         engine->clk = clk_get(&pdev->dev, "ref");
1744         if (IS_ERR(engine->clk)) {
1745                 dev_info(&pdev->dev, "clk unavailable\n");
1746                 device_remove_file(&pdev->dev, &dev_attr_stat_irq_thresh);
1747                 return PTR_ERR(engine->clk);
1748         }
1749
1750         if (clk_enable(engine->clk)) {
1751                 dev_info(&pdev->dev, "unable to enable clk\n");
1752                 clk_put(engine->clk);
1753                 return -EIO;
1754         }
1755
1756         err = device_create_file(&pdev->dev, &dev_attr_stat_irq_thresh);
1757         if (err) {
1758                 clk_disable(engine->clk);
1759                 clk_put(engine->clk);
1760                 return err;
1761         }
1762
1763
1764         /*
1765          * Use an IRQ threshold of 50% as a default. This seems to be a
1766          * reasonable trade off of latency against throughput but can be
1767          * changed at runtime.
1768          */
1769         engine->stat_irq_thresh = (engine->fifo_sz / 2);
1770
1771         /*
1772          * Configure the interrupts. We only use the STAT_CNT interrupt as we
1773          * only submit a new packet for processing when we complete another in
1774          * the queue. This minimizes time spent in the interrupt handler.
1775          */
1776         writel(engine->stat_irq_thresh << SPA_IRQ_CTRL_STAT_CNT_OFFSET,
1777                engine->regs + SPA_IRQ_CTRL_REG_OFFSET);
1778         writel(SPA_IRQ_EN_STAT_EN | SPA_IRQ_EN_GLBL_EN,
1779                engine->regs + SPA_IRQ_EN_REG_OFFSET);
1780
1781         setup_timer(&engine->packet_timeout, spacc_packet_timeout,
1782                     (unsigned long)engine);
1783
1784         INIT_LIST_HEAD(&engine->pending);
1785         INIT_LIST_HEAD(&engine->completed);
1786         INIT_LIST_HEAD(&engine->in_progress);
1787         engine->in_flight = 0;
1788         tasklet_init(&engine->complete, spacc_spacc_complete,
1789                      (unsigned long)engine);
1790
1791         platform_set_drvdata(pdev, engine);
1792
1793         INIT_LIST_HEAD(&engine->registered_algs);
1794         for (i = 0; i < engine->num_algs; ++i) {
1795                 engine->algs[i].engine = engine;
1796                 err = crypto_register_alg(&engine->algs[i].alg);
1797                 if (!err) {
1798                         list_add_tail(&engine->algs[i].entry,
1799                                       &engine->registered_algs);
1800                         ret = 0;
1801                 }
1802                 if (err)
1803                         dev_err(engine->dev, "failed to register alg \"%s\"\n",
1804                                 engine->algs[i].alg.cra_name);
1805                 else
1806                         dev_dbg(engine->dev, "registered alg \"%s\"\n",
1807                                 engine->algs[i].alg.cra_name);
1808         }
1809
1810         return ret;
1811 }
1812
1813 static int spacc_remove(struct platform_device *pdev)
1814 {
1815         struct spacc_alg *alg, *next;
1816         struct spacc_engine *engine = platform_get_drvdata(pdev);
1817
1818         del_timer_sync(&engine->packet_timeout);
1819         device_remove_file(&pdev->dev, &dev_attr_stat_irq_thresh);
1820
1821         list_for_each_entry_safe(alg, next, &engine->registered_algs, entry) {
1822                 list_del(&alg->entry);
1823                 crypto_unregister_alg(&alg->alg);
1824         }
1825
1826         clk_disable(engine->clk);
1827         clk_put(engine->clk);
1828
1829         return 0;
1830 }
1831
1832 static const struct platform_device_id spacc_id_table[] = {
1833         { "picochip,spacc-ipsec", },
1834         { "picochip,spacc-l2", },
1835         { }
1836 };
1837
1838 static struct platform_driver spacc_driver = {
1839         .probe          = spacc_probe,
1840         .remove         = spacc_remove,
1841         .driver         = {
1842                 .name   = "picochip,spacc",
1843 #ifdef CONFIG_PM
1844                 .pm     = &spacc_pm_ops,
1845 #endif /* CONFIG_PM */
1846                 .of_match_table = of_match_ptr(spacc_of_id_table),
1847         },
1848         .id_table       = spacc_id_table,
1849 };
1850
1851 module_platform_driver(spacc_driver);
1852
1853 MODULE_LICENSE("GPL");
1854 MODULE_AUTHOR("Jamie Iles");