2 * Copyright (C) ST-Ericsson SA 2010
3 * Author: Shujuan Chen (shujuan.chen@stericsson.com)
4 * Author: Joakim Bech (joakim.xx.bech@stericsson.com)
5 * Author: Berne Hebark (berne.hebark@stericsson.com))
6 * License terms: GNU General Public License (GPL) version 2
11 #include <linux/bitops.h>
13 #define HASH_BLOCK_SIZE 64
14 #define HASH_DMA_ALIGN_SIZE 4
15 #define HASH_DMA_PERFORMANCE_MIN_SIZE 1024
16 #define HASH_BYTES_PER_WORD 4
18 /* Maximum value of the length's high word */
19 #define HASH_HIGH_WORD_MAX_VAL 0xFFFFFFFFUL
21 /* Power on Reset values HASH registers */
22 #define HASH_RESET_CR_VALUE 0x0
23 #define HASH_RESET_STR_VALUE 0x0
25 /* Number of context swap registers */
26 #define HASH_CSR_COUNT 52
28 #define HASH_RESET_CSRX_REG_VALUE 0x0
29 #define HASH_RESET_CSFULL_REG_VALUE 0x0
30 #define HASH_RESET_CSDATAIN_REG_VALUE 0x0
32 #define HASH_RESET_INDEX_VAL 0x0
33 #define HASH_RESET_BIT_INDEX_VAL 0x0
34 #define HASH_RESET_BUFFER_VAL 0x0
35 #define HASH_RESET_LEN_HIGH_VAL 0x0
36 #define HASH_RESET_LEN_LOW_VAL 0x0
38 /* Control register bitfields */
39 #define HASH_CR_RESUME_MASK 0x11FCF
41 #define HASH_CR_SWITCHON_POS 31
42 #define HASH_CR_SWITCHON_MASK BIT(31)
44 #define HASH_CR_EMPTYMSG_POS 20
45 #define HASH_CR_EMPTYMSG_MASK BIT(20)
47 #define HASH_CR_DINF_POS 12
48 #define HASH_CR_DINF_MASK BIT(12)
50 #define HASH_CR_NBW_POS 8
51 #define HASH_CR_NBW_MASK 0x00000F00UL
53 #define HASH_CR_LKEY_POS 16
54 #define HASH_CR_LKEY_MASK BIT(16)
56 #define HASH_CR_ALGO_POS 7
57 #define HASH_CR_ALGO_MASK BIT(7)
59 #define HASH_CR_MODE_POS 6
60 #define HASH_CR_MODE_MASK BIT(6)
62 #define HASH_CR_DATAFORM_POS 4
63 #define HASH_CR_DATAFORM_MASK (BIT(4) | BIT(5))
65 #define HASH_CR_DMAE_POS 3
66 #define HASH_CR_DMAE_MASK BIT(3)
68 #define HASH_CR_INIT_POS 2
69 #define HASH_CR_INIT_MASK BIT(2)
71 #define HASH_CR_PRIVN_POS 1
72 #define HASH_CR_PRIVN_MASK BIT(1)
74 #define HASH_CR_SECN_POS 0
75 #define HASH_CR_SECN_MASK BIT(0)
77 /* Start register bitfields */
78 #define HASH_STR_DCAL_POS 8
79 #define HASH_STR_DCAL_MASK BIT(8)
80 #define HASH_STR_DEFAULT 0x0
82 #define HASH_STR_NBLW_POS 0
83 #define HASH_STR_NBLW_MASK 0x0000001FUL
85 #define HASH_NBLW_MAX_VAL 0x1F
88 #define HASH_P_ID0 0xE0
89 #define HASH_P_ID1 0x05
90 #define HASH_P_ID2 0x38
91 #define HASH_P_ID3 0x00
92 #define HASH_CELL_ID0 0x0D
93 #define HASH_CELL_ID1 0xF0
94 #define HASH_CELL_ID2 0x05
95 #define HASH_CELL_ID3 0xB1
97 #define HASH_SET_BITS(reg_name, mask) \
98 writel_relaxed((readl_relaxed(reg_name) | mask), reg_name)
100 #define HASH_CLEAR_BITS(reg_name, mask) \
101 writel_relaxed((readl_relaxed(reg_name) & ~mask), reg_name)
103 #define HASH_PUT_BITS(reg, val, shift, mask) \
104 writel_relaxed(((readl(reg) & ~(mask)) | \
105 (((u32)val << shift) & (mask))), reg)
107 #define HASH_SET_DIN(val, len) writesl(&device_data->base->din, (val), (len))
109 #define HASH_INITIALIZE \
111 &device_data->base->cr, \
112 0x01, HASH_CR_INIT_POS, \
115 #define HASH_SET_DATA_FORMAT(data_format) \
117 &device_data->base->cr, \
118 (u32) (data_format), HASH_CR_DATAFORM_POS, \
119 HASH_CR_DATAFORM_MASK)
120 #define HASH_SET_NBLW(val) \
122 &device_data->base->str, \
123 (u32) (val), HASH_STR_NBLW_POS, \
125 #define HASH_SET_DCAL \
127 &device_data->base->str, \
128 0x01, HASH_STR_DCAL_POS, \
131 /* Hardware access method */
138 * struct uint64 - Structure to handle 64 bits integers.
139 * @high_word: Most significant bits.
140 * @low_word: Least significant bits.
142 * Used to handle 64 bits integers.
150 * struct hash_register - Contains all registers in ux500 hash hardware.
151 * @cr: HASH control register (0x000).
152 * @din: HASH data input register (0x004).
153 * @str: HASH start register (0x008).
154 * @hx: HASH digest register 0..7 (0x00c-0x01C).
155 * @padding0: Reserved (0x02C).
156 * @itcr: Integration test control register (0x080).
157 * @itip: Integration test input register (0x084).
158 * @itop: Integration test output register (0x088).
159 * @padding1: Reserved (0x08C).
160 * @csfull: HASH context full register (0x0F8).
161 * @csdatain: HASH context swap data input register (0x0FC).
162 * @csrx: HASH context swap register 0..51 (0x100-0x1CC).
163 * @padding2: Reserved (0x1D0).
164 * @periphid0: HASH peripheral identification register 0 (0xFE0).
165 * @periphid1: HASH peripheral identification register 1 (0xFE4).
166 * @periphid2: HASH peripheral identification register 2 (0xFE8).
167 * @periphid3: HASH peripheral identification register 3 (0xFEC).
168 * @cellid0: HASH PCell identification register 0 (0xFF0).
169 * @cellid1: HASH PCell identification register 1 (0xFF4).
170 * @cellid2: HASH PCell identification register 2 (0xFF8).
171 * @cellid3: HASH PCell identification register 3 (0xFFC).
173 * The device communicates to the HASH via 32-bit-wide control registers
174 * accessible via the 32-bit width AMBA rev. 2.0 AHB Bus. Below is a structure
175 * with the registers used.
177 struct hash_register {
183 u32 padding0[(0x080 - 0x02C) / sizeof(u32)];
189 u32 padding1[(0x0F8 - 0x08C) / sizeof(u32)];
193 u32 csrx[HASH_CSR_COUNT];
195 u32 padding2[(0xFE0 - 0x1D0) / sizeof(u32)];
209 * struct hash_state - Hash context state.
210 * @temp_cr: Temporary HASH Control Register.
211 * @str_reg: HASH Start Register.
212 * @din_reg: HASH Data Input Register.
213 * @csr[52]: HASH Context Swap Registers 0-39.
214 * @csfull: HASH Context Swap Registers 40 ie Status flags.
215 * @csdatain: HASH Context Swap Registers 41 ie Input data.
216 * @buffer: Working buffer for messages going to the hardware.
217 * @length: Length of the part of message hashed so far (floor(N/64) * 64).
218 * @index: Valid number of bytes in buffer (N % 64).
219 * @bit_index: Valid number of bits in buffer (N % 8).
221 * This structure is used between context switches, i.e. when ongoing jobs are
222 * interupted with new jobs. When this happens we need to store intermediate
223 * results in software.
225 * WARNING: "index" is the member of the structure, to be sure that "buffer"
226 * is aligned on a 4-bytes boundary. This is highly implementation dependent
227 * and MUST be checked whenever this code is ported on new platforms.
236 u32 buffer[HASH_BLOCK_SIZE / sizeof(u32)];
237 struct uint64 length;
243 * enum hash_device_id - HASH device ID.
244 * @HASH_DEVICE_ID_0: Hash hardware with ID 0
245 * @HASH_DEVICE_ID_1: Hash hardware with ID 1
247 enum hash_device_id {
248 HASH_DEVICE_ID_0 = 0,
253 * enum hash_data_format - HASH data format.
254 * @HASH_DATA_32_BITS: 32 bits data format
255 * @HASH_DATA_16_BITS: 16 bits data format
256 * @HASH_DATA_8_BITS: 8 bits data format.
257 * @HASH_DATA_1_BITS: 1 bit data format.
259 enum hash_data_format {
260 HASH_DATA_32_BITS = 0x0,
261 HASH_DATA_16_BITS = 0x1,
262 HASH_DATA_8_BITS = 0x2,
263 HASH_DATA_1_BIT = 0x3
267 * enum hash_algo - Enumeration for selecting between SHA1 or SHA2 algorithm.
268 * @HASH_ALGO_SHA1: Indicates that SHA1 is used.
269 * @HASH_ALGO_SHA2: Indicates that SHA2 (SHA256) is used.
272 HASH_ALGO_SHA1 = 0x0,
273 HASH_ALGO_SHA256 = 0x1
277 * enum hash_op - Enumeration for selecting between HASH or HMAC mode.
278 * @HASH_OPER_MODE_HASH: Indicates usage of normal HASH mode.
279 * @HASH_OPER_MODE_HMAC: Indicates usage of HMAC.
282 HASH_OPER_MODE_HASH = 0x0,
283 HASH_OPER_MODE_HMAC = 0x1
287 * struct hash_config - Configuration data for the hardware.
288 * @data_format: Format of data entered into the hash data in register.
289 * @algorithm: Algorithm selection bit.
290 * @oper_mode: Operating mode selection bit.
299 * struct hash_dma - Structure used for dma.
300 * @mask: DMA capabilities bitmap mask.
301 * @complete: Used to maintain state for a "completion".
302 * @chan_mem2hash: DMA channel.
303 * @cfg_mem2hash: DMA channel configuration.
304 * @sg_len: Scatterlist length.
306 * @nents: Number of sg entries.
310 struct completion complete;
311 struct dma_chan *chan_mem2hash;
314 struct scatterlist *sg;
319 * struct hash_ctx - The context used for hash calculations.
320 * @key: The key used in the operation.
321 * @keylen: The length of the key.
322 * @state: The state of the current calculations.
323 * @config: The current configuration.
324 * @digestsize: The size of current digest.
325 * @device: Pointer to the device structure.
330 struct hash_config config;
332 struct hash_device_data *device;
336 * struct hash_ctx - The request context used for hash calculations.
337 * @state: The state of the current calculations.
338 * @dma_mode: Used in special cases (workaround), e.g. need to change to
339 * cpu mode, if not supported/working in dma mode.
340 * @updated: Indicates if hardware is initialized for new operations.
342 struct hash_req_ctx {
343 struct hash_state state;
349 * struct hash_device_data - structure for a hash device.
350 * @base: Pointer to the hardware base address.
351 * @list_node: For inclusion in klist.
352 * @dev: Pointer to the device dev structure.
353 * @ctx_lock: Spinlock for current_ctx.
354 * @current_ctx: Pointer to the currently allocated context.
355 * @power_state: TRUE = power state on, FALSE = power state off.
356 * @power_state_lock: Spinlock for power_state.
357 * @regulator: Pointer to the device's power control.
358 * @clk: Pointer to the device's clock control.
359 * @restore_dev_state: TRUE = saved state, FALSE = no saved state.
360 * @dma: Structure used for dma.
362 struct hash_device_data {
363 struct hash_register __iomem *base;
364 struct klist_node list_node;
366 struct spinlock ctx_lock;
367 struct hash_ctx *current_ctx;
369 struct spinlock power_state_lock;
370 struct regulator *regulator;
372 bool restore_dev_state;
373 struct hash_state state; /* Used for saving and resuming state */
377 int hash_check_hw(struct hash_device_data *device_data);
379 int hash_setconfiguration(struct hash_device_data *device_data,
380 struct hash_config *config);
382 void hash_begin(struct hash_device_data *device_data, struct hash_ctx *ctx);
384 void hash_get_digest(struct hash_device_data *device_data,
385 u8 *digest, int algorithm);
387 int hash_hw_update(struct ahash_request *req);
389 int hash_save_state(struct hash_device_data *device_data,
390 struct hash_state *state);
392 int hash_resume_state(struct hash_device_data *device_data,
393 const struct hash_state *state);