drivers/dma/imx-sdma.c

   1 /*
   2  * drivers/dma/imx-sdma.c
   3  *
   4  * This file contains a driver for the Freescale Smart DMA engine
   5  *
   6  * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
   7  *
   8  * Based on code from Freescale:
   9  *
  10  * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
  11  *
  12  * The code contained herein is licensed under the GNU General Public
  13  * License. You may obtain a copy of the GNU General Public License
  14  * Version 2 or later at the following locations:
  15  *
  16  * http://www.opensource.org/licenses/gpl-license.html
  17  * http://www.gnu.org/copyleft/gpl.html
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/module.h>
  22 #include <linux/types.h>
  23 #include <linux/bitops.h>
  24 #include <linux/mm.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/clk.h>
  27 #include <linux/delay.h>
  28 #include <linux/sched.h>
  29 #include <linux/semaphore.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/device.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/firmware.h>
  34 #include <linux/slab.h>
  35 #include <linux/platform_device.h>
  36 #include <linux/dmaengine.h>
  37 #include <linux/of.h>
  38 #include <linux/of_device.h>
  39 #include <linux/of_dma.h>
  40
  41 #include <asm/irq.h>
  42 #include <linux/platform_data/dma-imx-sdma.h>
  43 #include <linux/platform_data/dma-imx.h>
  44
  45 #include "dmaengine.h"
  46
  47 /* SDMA registers */
  48 #define SDMA_H_C0PTR            0x000
  49 #define SDMA_H_INTR             0x004
  50 #define SDMA_H_STATSTOP         0x008
  51 #define SDMA_H_START            0x00c
  52 #define SDMA_H_EVTOVR           0x010
  53 #define SDMA_H_DSPOVR           0x014
  54 #define SDMA_H_HOSTOVR          0x018
  55 #define SDMA_H_EVTPEND          0x01c
  56 #define SDMA_H_DSPENBL          0x020
  57 #define SDMA_H_RESET            0x024
  58 #define SDMA_H_EVTERR           0x028
  59 #define SDMA_H_INTRMSK          0x02c
  60 #define SDMA_H_PSW              0x030
  61 #define SDMA_H_EVTERRDBG        0x034
  62 #define SDMA_H_CONFIG           0x038
  63 #define SDMA_ONCE_ENB           0x040
  64 #define SDMA_ONCE_DATA          0x044
  65 #define SDMA_ONCE_INSTR         0x048
  66 #define SDMA_ONCE_STAT          0x04c
  67 #define SDMA_ONCE_CMD           0x050
  68 #define SDMA_EVT_MIRROR         0x054
  69 #define SDMA_ILLINSTADDR        0x058
  70 #define SDMA_CHN0ADDR           0x05c
  71 #define SDMA_ONCE_RTB           0x060
  72 #define SDMA_XTRIG_CONF1        0x070
  73 #define SDMA_XTRIG_CONF2        0x074
  74 #define SDMA_CHNENBL0_IMX35     0x200
  75 #define SDMA_CHNENBL0_IMX31     0x080
  76 #define SDMA_CHNPRI_0           0x100
  77
  78 /*
  79  * Buffer descriptor status values.
  80  */
  81 #define BD_DONE  0x01
  82 #define BD_WRAP  0x02
  83 #define BD_CONT  0x04
  84 #define BD_INTR  0x08
  85 #define BD_RROR  0x10
  86 #define BD_LAST  0x20
  87 #define BD_EXTD  0x80
  88
  89 /*
  90  * Data Node descriptor status values.
  91  */
  92 #define DND_END_OF_FRAME  0x80
  93 #define DND_END_OF_XFER   0x40
  94 #define DND_DONE          0x20
  95 #define DND_UNUSED        0x01
  96
  97 /*
  98  * IPCV2 descriptor status values.
  99  */
 100 #define BD_IPCV2_END_OF_FRAME  0x40
 101
 102 #define IPCV2_MAX_NODES        50
 103 /*
 104  * Error bit set in the CCB status field by the SDMA,
 105  * in setbd routine, in case of a transfer error
 106  */
 107 #define DATA_ERROR  0x10000000
 108
 109 /*
 110  * Buffer descriptor commands.
 111  */
 112 #define C0_ADDR             0x01
 113 #define C0_LOAD             0x02
 114 #define C0_DUMP             0x03
 115 #define C0_SETCTX           0x07
 116 #define C0_GETCTX           0x03
 117 #define C0_SETDM            0x01
 118 #define C0_SETPM            0x04
 119 #define C0_GETDM            0x02
 120 #define C0_GETPM            0x08
 121 /*
 122  * Change endianness indicator in the BD command field
 123  */
 124 #define CHANGE_ENDIANNESS   0x80
 125
 126 /*
 127  * Mode/Count of data node descriptors - IPCv2
 128  */
 129 struct sdma_mode_count {
 130         u32 count   : 16; /* size of the buffer pointed by this BD */
 131         u32 status  :  8; /* E,R,I,C,W,D status bits stored here */
 132         u32 command :  8; /* command mostlky used for channel 0 */
 133 };
 134
 135 /*
 136  * Buffer descriptor
 137  */
 138 struct sdma_buffer_descriptor {
 139         struct sdma_mode_count  mode;
 140         u32 buffer_addr;        /* address of the buffer described */
 141         u32 ext_buffer_addr;    /* extended buffer address */
 142 } __attribute__ ((packed));
 143
 144 /**
 145  * struct sdma_channel_control - Channel control Block
 146  *
 147  * @current_bd_ptr      current buffer descriptor processed
 148  * @base_bd_ptr         first element of buffer descriptor array
 149  * @unused              padding. The SDMA engine expects an array of 128 byte
 150  *                      control blocks
 151  */
 152 struct sdma_channel_control {
 153         u32 current_bd_ptr;
 154         u32 base_bd_ptr;
 155         u32 unused[2];
 156 } __attribute__ ((packed));
 157
 158 /**
 159  * struct sdma_state_registers - SDMA context for a channel
 160  *
 161  * @pc:         program counter
 162  * @t:          test bit: status of arithmetic & test instruction
 163  * @rpc:        return program counter
 164  * @sf:         source fault while loading data
 165  * @spc:        loop start program counter
 166  * @df:         destination fault while storing data
 167  * @epc:        loop end program counter
 168  * @lm:         loop mode
 169  */
 170 struct sdma_state_registers {
 171         u32 pc     :14;
 172         u32 unused1: 1;
 173         u32 t      : 1;
 174         u32 rpc    :14;
 175         u32 unused0: 1;
 176         u32 sf     : 1;
 177         u32 spc    :14;
 178         u32 unused2: 1;
 179         u32 df     : 1;
 180         u32 epc    :14;
 181         u32 lm     : 2;
 182 } __attribute__ ((packed));
 183
 184 /**
 185  * struct sdma_context_data - sdma context specific to a channel
 186  *
 187  * @channel_state:      channel state bits
 188  * @gReg:               general registers
 189  * @mda:                burst dma destination address register
 190  * @msa:                burst dma source address register
 191  * @ms:                 burst dma status register
 192  * @md:                 burst dma data register
 193  * @pda:                peripheral dma destination address register
 194  * @psa:                peripheral dma source address register
 195  * @ps:                 peripheral dma status register
 196  * @pd:                 peripheral dma data register
 197  * @ca:                 CRC polynomial register
 198  * @cs:                 CRC accumulator register
 199  * @dda:                dedicated core destination address register
 200  * @dsa:                dedicated core source address register
 201  * @ds:                 dedicated core status register
 202  * @dd:                 dedicated core data register
 203  */
 204 struct sdma_context_data {
 205         struct sdma_state_registers  channel_state;
 206         u32  gReg[8];
 207         u32  mda;
 208         u32  msa;
 209         u32  ms;
 210         u32  md;
 211         u32  pda;
 212         u32  psa;
 213         u32  ps;
 214         u32  pd;
 215         u32  ca;
 216         u32  cs;
 217         u32  dda;
 218         u32  dsa;
 219         u32  ds;
 220         u32  dd;
 221         u32  scratch0;
 222         u32  scratch1;
 223         u32  scratch2;
 224         u32  scratch3;
 225         u32  scratch4;
 226         u32  scratch5;
 227         u32  scratch6;
 228         u32  scratch7;
 229 } __attribute__ ((packed));
 230
 231 #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
 232
 233 struct sdma_engine;
 234
 235 /**
 236  * struct sdma_channel - housekeeping for a SDMA channel
 237  *
 238  * @sdma                pointer to the SDMA engine for this channel
 239  * @channel             the channel number, matches dmaengine chan_id + 1
 240  * @direction           transfer type. Needed for setting SDMA script
 241  * @peripheral_type     Peripheral type. Needed for setting SDMA script
 242  * @event_id0           aka dma request line
 243  * @event_id1           for channels that use 2 events
 244  * @word_size           peripheral access size
 245  * @buf_tail            ID of the buffer that was processed
 246  * @num_bd              max NUM_BD. number of descriptors currently handling
 247  */
 248 struct sdma_channel {
 249         struct sdma_engine              *sdma;
 250         unsigned int                    channel;
 251         enum dma_transfer_direction             direction;
 252         enum sdma_peripheral_type       peripheral_type;
 253         unsigned int                    event_id0;
 254         unsigned int                    event_id1;
 255         enum dma_slave_buswidth         word_size;
 256         unsigned int                    buf_tail;
 257         unsigned int                    num_bd;
 258         struct sdma_buffer_descriptor   *bd;
 259         dma_addr_t                      bd_phys;
 260         unsigned int                    pc_from_device, pc_to_device;
 261         unsigned long                   flags;
 262         dma_addr_t                      per_address;
 263         unsigned long                   event_mask[2];
 264         unsigned long                   watermark_level;
 265         u32                             shp_addr, per_addr;
 266         struct dma_chan                 chan;
 267         spinlock_t                      lock;
 268         struct dma_async_tx_descriptor  desc;
 269         enum dma_status                 status;
 270         unsigned int                    chn_count;
 271         unsigned int                    chn_real_count;
 272         struct tasklet_struct           tasklet;
 273 };
 274
 275 #define IMX_DMA_SG_LOOP         BIT(0)
 276
 277 #define MAX_DMA_CHANNELS 32
 278 #define MXC_SDMA_DEFAULT_PRIORITY 1
 279 #define MXC_SDMA_MIN_PRIORITY 1
 280 #define MXC_SDMA_MAX_PRIORITY 7
 281
 282 #define SDMA_FIRMWARE_MAGIC 0x414d4453
 283
 284 /**
 285  * struct sdma_firmware_header - Layout of the firmware image
 286  *
 287  * @magic               "SDMA"
 288  * @version_major       increased whenever layout of struct sdma_script_start_addrs
 289  *                      changes.
 290  * @version_minor       firmware minor version (for binary compatible changes)
 291  * @script_addrs_start  offset of struct sdma_script_start_addrs in this image
 292  * @num_script_addrs    Number of script addresses in this image
 293  * @ram_code_start      offset of SDMA ram image in this firmware image
 294  * @ram_code_size       size of SDMA ram image
 295  * @script_addrs        Stores the start address of the SDMA scripts
 296  *                      (in SDMA memory space)
 297  */
 298 struct sdma_firmware_header {
 299         u32     magic;
 300         u32     version_major;
 301         u32     version_minor;
 302         u32     script_addrs_start;
 303         u32     num_script_addrs;
 304         u32     ram_code_start;
 305         u32     ram_code_size;
 306 };
 307
 308 enum sdma_devtype {
 309         IMX31_SDMA,     /* runs on i.mx31 */
 310         IMX35_SDMA,     /* runs on i.mx35 and later */
 311 };
 312
 313 struct sdma_engine {
 314         struct device                   *dev;
 315         struct device_dma_parameters    dma_parms;
 316         struct sdma_channel             channel[MAX_DMA_CHANNELS];
 317         struct sdma_channel_control     *channel_control;
 318         void __iomem                    *regs;
 319         enum sdma_devtype               devtype;
 320         unsigned int                    num_events;
 321         struct sdma_context_data        *context;
 322         dma_addr_t                      context_phys;
 323         struct dma_device               dma_device;
 324         struct clk                      *clk_ipg;
 325         struct clk                      *clk_ahb;
 326         spinlock_t                      channel_0_lock;
 327         struct sdma_script_start_addrs  *script_addrs;
 328 };
 329
 330 static struct platform_device_id sdma_devtypes[] = {
 331         {
 332                 .name = "imx31-sdma",
 333                 .driver_data = IMX31_SDMA,
 334         }, {
 335                 .name = "imx35-sdma",
 336                 .driver_data = IMX35_SDMA,
 337         }, {
 338                 /* sentinel */
 339         }
 340 };
 341 MODULE_DEVICE_TABLE(platform, sdma_devtypes);
 342
 343 static const struct of_device_id sdma_dt_ids[] = {
 344         { .compatible = "fsl,imx31-sdma", .data = &sdma_devtypes[IMX31_SDMA], },
 345         { .compatible = "fsl,imx35-sdma", .data = &sdma_devtypes[IMX35_SDMA], },
 346         { /* sentinel */ }
 347 };
 348 MODULE_DEVICE_TABLE(of, sdma_dt_ids);
 349
 350 #define SDMA_H_CONFIG_DSPDMA    BIT(12) /* indicates if the DSPDMA is used */
 351 #define SDMA_H_CONFIG_RTD_PINS  BIT(11) /* indicates if Real-Time Debug pins are enabled */
 352 #define SDMA_H_CONFIG_ACR       BIT(4)  /* indicates if AHB freq /core freq = 2 or 1 */
 353 #define SDMA_H_CONFIG_CSM       (3)       /* indicates which context switch mode is selected*/
 354
 355 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
 356 {
 357         u32 chnenbl0 = (sdma->devtype == IMX31_SDMA ? SDMA_CHNENBL0_IMX31 :
 358                                                       SDMA_CHNENBL0_IMX35);
 359         return chnenbl0 + event * 4;
 360 }
 361
 362 static int sdma_config_ownership(struct sdma_channel *sdmac,
 363                 bool event_override, bool mcu_override, bool dsp_override)
 364 {
 365         struct sdma_engine *sdma = sdmac->sdma;
 366         int channel = sdmac->channel;
 367         unsigned long evt, mcu, dsp;
 368
 369         if (event_override && mcu_override && dsp_override)
 370                 return -EINVAL;
 371
 372         evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR);
 373         mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR);
 374         dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR);
 375
 376         if (dsp_override)
 377                 __clear_bit(channel, &dsp);
 378         else
 379                 __set_bit(channel, &dsp);
 380
 381         if (event_override)
 382                 __clear_bit(channel, &evt);
 383         else
 384                 __set_bit(channel, &evt);
 385
 386         if (mcu_override)
 387                 __clear_bit(channel, &mcu);
 388         else
 389                 __set_bit(channel, &mcu);
 390
 391         writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR);
 392         writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR);
 393         writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR);
 394
 395         return 0;
 396 }
 397
 398 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
 399 {
 400         writel(BIT(channel), sdma->regs + SDMA_H_START);
 401 }
 402
 403 /*
 404  * sdma_run_channel0 - run a channel and wait till it's done
 405  */
 406 static int sdma_run_channel0(struct sdma_engine *sdma)
 407 {
 408         int ret;
 409         unsigned long timeout = 500;
 410
 411         sdma_enable_channel(sdma, 0);
 412
 413         while (!(ret = readl_relaxed(sdma->regs + SDMA_H_INTR) & 1)) {
 414                 if (timeout-- <= 0)
 415                         break;
 416                 udelay(1);
 417         }
 418
 419         if (ret) {
 420                 /* Clear the interrupt status */
 421                 writel_relaxed(ret, sdma->regs + SDMA_H_INTR);
 422         } else {
 423                 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
 424         }
 425
 426         return ret ? 0 : -ETIMEDOUT;
 427 }
 428
 429 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
 430                 u32 address)
 431 {
 432         struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
 433         void *buf_virt;
 434         dma_addr_t buf_phys;
 435         int ret;
 436         unsigned long flags;
 437
 438         buf_virt = dma_alloc_coherent(NULL,
 439                         size,
 440                         &buf_phys, GFP_KERNEL);
 441         if (!buf_virt) {
 442                 return -ENOMEM;
 443         }
 444
 445         spin_lock_irqsave(&sdma->channel_0_lock, flags);
 446
 447         bd0->mode.command = C0_SETPM;
 448         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
 449         bd0->mode.count = size / 2;
 450         bd0->buffer_addr = buf_phys;
 451         bd0->ext_buffer_addr = address;
 452
 453         memcpy(buf_virt, buf, size);
 454
 455         ret = sdma_run_channel0(sdma);
 456
 457         spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
 458
 459         dma_free_coherent(NULL, size, buf_virt, buf_phys);
 460
 461         return ret;
 462 }
 463
 464 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
 465 {
 466         struct sdma_engine *sdma = sdmac->sdma;
 467         int channel = sdmac->channel;
 468         unsigned long val;
 469         u32 chnenbl = chnenbl_ofs(sdma, event);
 470
 471         val = readl_relaxed(sdma->regs + chnenbl);
 472         __set_bit(channel, &val);
 473         writel_relaxed(val, sdma->regs + chnenbl);
 474 }
 475
 476 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
 477 {
 478         struct sdma_engine *sdma = sdmac->sdma;
 479         int channel = sdmac->channel;
 480         u32 chnenbl = chnenbl_ofs(sdma, event);
 481         unsigned long val;
 482
 483         val = readl_relaxed(sdma->regs + chnenbl);
 484         __clear_bit(channel, &val);
 485         writel_relaxed(val, sdma->regs + chnenbl);
 486 }
 487
 488 static void sdma_handle_channel_loop(struct sdma_channel *sdmac)
 489 {
 490         struct sdma_buffer_descriptor *bd;
 491
 492         /*
 493          * loop mode. Iterate over descriptors, re-setup them and
 494          * call callback function.
 495          */
 496         while (1) {
 497                 bd = &sdmac->bd[sdmac->buf_tail];
 498
 499                 if (bd->mode.status & BD_DONE)
 500                         break;
 501
 502                 if (bd->mode.status & BD_RROR)
 503                         sdmac->status = DMA_ERROR;
 504                 else
 505                         sdmac->status = DMA_IN_PROGRESS;
 506
 507                 bd->mode.status |= BD_DONE;
 508                 sdmac->buf_tail++;
 509                 sdmac->buf_tail %= sdmac->num_bd;
 510
 511                 if (sdmac->desc.callback)
 512                         sdmac->desc.callback(sdmac->desc.callback_param);
 513         }
 514 }
 515
 516 static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac)
 517 {
 518         struct sdma_buffer_descriptor *bd;
 519         int i, error = 0;
 520
 521         sdmac->chn_real_count = 0;
 522         /*
 523          * non loop mode. Iterate over all descriptors, collect
 524          * errors and call callback function
 525          */
 526         for (i = 0; i < sdmac->num_bd; i++) {
 527                 bd = &sdmac->bd[i];
 528
 529                  if (bd->mode.status & (BD_DONE | BD_RROR))
 530                         error = -EIO;
 531                  sdmac->chn_real_count += bd->mode.count;
 532         }
 533
 534         if (error)
 535                 sdmac->status = DMA_ERROR;
 536         else
 537                 sdmac->status = DMA_SUCCESS;
 538
 539         dma_cookie_complete(&sdmac->desc);
 540         if (sdmac->desc.callback)
 541                 sdmac->desc.callback(sdmac->desc.callback_param);
 542 }
 543
 544 static void sdma_tasklet(unsigned long data)
 545 {
 546         struct sdma_channel *sdmac = (struct sdma_channel *) data;
 547
 548         if (sdmac->flags & IMX_DMA_SG_LOOP)
 549                 sdma_handle_channel_loop(sdmac);
 550         else
 551                 mxc_sdma_handle_channel_normal(sdmac);
 552 }
 553
 554 static irqreturn_t sdma_int_handler(int irq, void *dev_id)
 555 {
 556         struct sdma_engine *sdma = dev_id;
 557         unsigned long stat;
 558
 559         stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
 560         /* not interested in channel 0 interrupts */
 561         stat &= ~1;
 562         writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
 563
 564         while (stat) {
 565                 int channel = fls(stat) - 1;
 566                 struct sdma_channel *sdmac = &sdma->channel[channel];
 567
 568                 tasklet_schedule(&sdmac->tasklet);
 569
 570                 __clear_bit(channel, &stat);
 571         }
 572
 573         return IRQ_HANDLED;
 574 }
 575
 576 /*
 577  * sets the pc of SDMA script according to the peripheral type
 578  */
 579 static void sdma_get_pc(struct sdma_channel *sdmac,
 580                 enum sdma_peripheral_type peripheral_type)
 581 {
 582         struct sdma_engine *sdma = sdmac->sdma;
 583         int per_2_emi = 0, emi_2_per = 0;
 584         /*
 585          * These are needed once we start to support transfers between
 586          * two peripherals or memory-to-memory transfers
 587          */
 588         int per_2_per = 0, emi_2_emi = 0;
 589
 590         sdmac->pc_from_device = 0;
 591         sdmac->pc_to_device = 0;
 592
 593         switch (peripheral_type) {
 594         case IMX_DMATYPE_MEMORY:
 595                 emi_2_emi = sdma->script_addrs->ap_2_ap_addr;
 596                 break;
 597         case IMX_DMATYPE_DSP:
 598                 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
 599                 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
 600                 break;
 601         case IMX_DMATYPE_FIRI:
 602                 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
 603                 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
 604                 break;
 605         case IMX_DMATYPE_UART:
 606                 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
 607                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
 608                 break;
 609         case IMX_DMATYPE_UART_SP:
 610                 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
 611                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 612                 break;
 613         case IMX_DMATYPE_ATA:
 614                 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
 615                 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
 616                 break;
 617         case IMX_DMATYPE_CSPI:
 618         case IMX_DMATYPE_EXT:
 619         case IMX_DMATYPE_SSI:
 620                 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
 621                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
 622                 break;
 623         case IMX_DMATYPE_SSI_SP:
 624         case IMX_DMATYPE_MMC:
 625         case IMX_DMATYPE_SDHC:
 626         case IMX_DMATYPE_CSPI_SP:
 627         case IMX_DMATYPE_ESAI:
 628         case IMX_DMATYPE_MSHC_SP:
 629                 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
 630                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 631                 break;
 632         case IMX_DMATYPE_ASRC:
 633                 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
 634                 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
 635                 per_2_per = sdma->script_addrs->per_2_per_addr;
 636                 break;
 637         case IMX_DMATYPE_MSHC:
 638                 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
 639                 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
 640                 break;
 641         case IMX_DMATYPE_CCM:
 642                 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
 643                 break;
 644         case IMX_DMATYPE_SPDIF:
 645                 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
 646                 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
 647                 break;
 648         case IMX_DMATYPE_IPU_MEMORY:
 649                 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
 650                 break;
 651         default:
 652                 break;
 653         }
 654
 655         sdmac->pc_from_device = per_2_emi;
 656         sdmac->pc_to_device = emi_2_per;
 657 }
 658
 659 static int sdma_load_context(struct sdma_channel *sdmac)
 660 {
 661         struct sdma_engine *sdma = sdmac->sdma;
 662         int channel = sdmac->channel;
 663         int load_address;
 664         struct sdma_context_data *context = sdma->context;
 665         struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
 666         int ret;
 667         unsigned long flags;
 668
 669         if (sdmac->direction == DMA_DEV_TO_MEM) {
 670                 load_address = sdmac->pc_from_device;
 671         } else {
 672                 load_address = sdmac->pc_to_device;
 673         }
 674
 675         if (load_address < 0)
 676                 return load_address;
 677
 678         dev_dbg(sdma->dev, "load_address = %d\n", load_address);
 679         dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level);
 680         dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
 681         dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
 682         dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]);
 683         dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]);
 684
 685         spin_lock_irqsave(&sdma->channel_0_lock, flags);
 686
 687         memset(context, 0, sizeof(*context));
 688         context->channel_state.pc = load_address;
 689
 690         /* Send by context the event mask,base address for peripheral
 691          * and watermark level
 692          */
 693         context->gReg[0] = sdmac->event_mask[1];
 694         context->gReg[1] = sdmac->event_mask[0];
 695         context->gReg[2] = sdmac->per_addr;
 696         context->gReg[6] = sdmac->shp_addr;
 697         context->gReg[7] = sdmac->watermark_level;
 698
 699         bd0->mode.command = C0_SETDM;
 700         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
 701         bd0->mode.count = sizeof(*context) / 4;
 702         bd0->buffer_addr = sdma->context_phys;
 703         bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
 704         ret = sdma_run_channel0(sdma);
 705
 706         spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
 707
 708         return ret;
 709 }
 710
 711 static void sdma_disable_channel(struct sdma_channel *sdmac)
 712 {
 713         struct sdma_engine *sdma = sdmac->sdma;
 714         int channel = sdmac->channel;
 715
 716         writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
 717         sdmac->status = DMA_ERROR;
 718 }
 719
 720 static int sdma_config_channel(struct sdma_channel *sdmac)
 721 {
 722         int ret;
 723
 724         sdma_disable_channel(sdmac);
 725
 726         sdmac->event_mask[0] = 0;
 727         sdmac->event_mask[1] = 0;
 728         sdmac->shp_addr = 0;
 729         sdmac->per_addr = 0;
 730
 731         if (sdmac->event_id0) {
 732                 if (sdmac->event_id0 >= sdmac->sdma->num_events)
 733                         return -EINVAL;
 734                 sdma_event_enable(sdmac, sdmac->event_id0);
 735         }
 736
 737         switch (sdmac->peripheral_type) {
 738         case IMX_DMATYPE_DSP:
 739                 sdma_config_ownership(sdmac, false, true, true);
 740                 break;
 741         case IMX_DMATYPE_MEMORY:
 742                 sdma_config_ownership(sdmac, false, true, false);
 743                 break;
 744         default:
 745                 sdma_config_ownership(sdmac, true, true, false);
 746                 break;
 747         }
 748
 749         sdma_get_pc(sdmac, sdmac->peripheral_type);
 750
 751         if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
 752                         (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
 753                 /* Handle multiple event channels differently */
 754                 if (sdmac->event_id1) {
 755                         sdmac->event_mask[1] = BIT(sdmac->event_id1 % 32);
 756                         if (sdmac->event_id1 > 31)
 757                                 __set_bit(31, &sdmac->watermark_level);
 758                         sdmac->event_mask[0] = BIT(sdmac->event_id0 % 32);
 759                         if (sdmac->event_id0 > 31)
 760                                 __set_bit(30, &sdmac->watermark_level);
 761                 } else {
 762                         __set_bit(sdmac->event_id0, sdmac->event_mask);
 763                 }
 764                 /* Watermark Level */
 765                 sdmac->watermark_level |= sdmac->watermark_level;
 766                 /* Address */
 767                 sdmac->shp_addr = sdmac->per_address;
 768         } else {
 769                 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
 770         }
 771
 772         ret = sdma_load_context(sdmac);
 773
 774         return ret;
 775 }
 776
 777 static int sdma_set_channel_priority(struct sdma_channel *sdmac,
 778                 unsigned int priority)
 779 {
 780         struct sdma_engine *sdma = sdmac->sdma;
 781         int channel = sdmac->channel;
 782
 783         if (priority < MXC_SDMA_MIN_PRIORITY
 784             || priority > MXC_SDMA_MAX_PRIORITY) {
 785                 return -EINVAL;
 786         }
 787
 788         writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
 789
 790         return 0;
 791 }
 792
 793 static int sdma_request_channel(struct sdma_channel *sdmac)
 794 {
 795         struct sdma_engine *sdma = sdmac->sdma;
 796         int channel = sdmac->channel;
 797         int ret = -EBUSY;
 798
 799         sdmac->bd = dma_alloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys, GFP_KERNEL);
 800         if (!sdmac->bd) {
 801                 ret = -ENOMEM;
 802                 goto out;
 803         }
 804
 805         memset(sdmac->bd, 0, PAGE_SIZE);
 806
 807         sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys;
 808         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
 809
 810         sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY);
 811         return 0;
 812 out:
 813
 814         return ret;
 815 }
 816
 817 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
 818 {
 819         return container_of(chan, struct sdma_channel, chan);
 820 }
 821
 822 static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx)
 823 {
 824         unsigned long flags;
 825         struct sdma_channel *sdmac = to_sdma_chan(tx->chan);
 826         dma_cookie_t cookie;
 827
 828         spin_lock_irqsave(&sdmac->lock, flags);
 829
 830         cookie = dma_cookie_assign(tx);
 831
 832         spin_unlock_irqrestore(&sdmac->lock, flags);
 833
 834         return cookie;
 835 }
 836
 837 static int sdma_alloc_chan_resources(struct dma_chan *chan)
 838 {
 839         struct sdma_channel *sdmac = to_sdma_chan(chan);
 840         struct imx_dma_data *data = chan->private;
 841         int prio, ret;
 842
 843         if (!data)
 844                 return -EINVAL;
 845
 846         switch (data->priority) {
 847         case DMA_PRIO_HIGH:
 848                 prio = 3;
 849                 break;
 850         case DMA_PRIO_MEDIUM:
 851                 prio = 2;
 852                 break;
 853         case DMA_PRIO_LOW:
 854         default:
 855                 prio = 1;
 856                 break;
 857         }
 858
 859         sdmac->peripheral_type = data->peripheral_type;
 860         sdmac->event_id0 = data->dma_request;
 861
 862         clk_enable(sdmac->sdma->clk_ipg);
 863         clk_enable(sdmac->sdma->clk_ahb);
 864
 865         ret = sdma_request_channel(sdmac);
 866         if (ret)
 867                 return ret;
 868
 869         ret = sdma_set_channel_priority(sdmac, prio);
 870         if (ret)
 871                 return ret;
 872
 873         dma_async_tx_descriptor_init(&sdmac->desc, chan);
 874         sdmac->desc.tx_submit = sdma_tx_submit;
 875         /* txd.flags will be overwritten in prep funcs */
 876         sdmac->desc.flags = DMA_CTRL_ACK;
 877
 878         return 0;
 879 }
 880
 881 static void sdma_free_chan_resources(struct dma_chan *chan)
 882 {
 883         struct sdma_channel *sdmac = to_sdma_chan(chan);
 884         struct sdma_engine *sdma = sdmac->sdma;
 885
 886         sdma_disable_channel(sdmac);
 887
 888         if (sdmac->event_id0)
 889                 sdma_event_disable(sdmac, sdmac->event_id0);
 890         if (sdmac->event_id1)
 891                 sdma_event_disable(sdmac, sdmac->event_id1);
 892
 893         sdmac->event_id0 = 0;
 894         sdmac->event_id1 = 0;
 895
 896         sdma_set_channel_priority(sdmac, 0);
 897
 898         dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);
 899
 900         clk_disable(sdma->clk_ipg);
 901         clk_disable(sdma->clk_ahb);
 902 }
 903
 904 static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
 905                 struct dma_chan *chan, struct scatterlist *sgl,
 906                 unsigned int sg_len, enum dma_transfer_direction direction,
 907                 unsigned long flags, void *context)
 908 {
 909         struct sdma_channel *sdmac = to_sdma_chan(chan);
 910         struct sdma_engine *sdma = sdmac->sdma;
 911         int ret, i, count;
 912         int channel = sdmac->channel;
 913         struct scatterlist *sg;
 914
 915         if (sdmac->status == DMA_IN_PROGRESS)
 916                 return NULL;
 917         sdmac->status = DMA_IN_PROGRESS;
 918
 919         sdmac->flags = 0;
 920
 921         sdmac->buf_tail = 0;
 922
 923         dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
 924                         sg_len, channel);
 925
 926         sdmac->direction = direction;
 927         ret = sdma_load_context(sdmac);
 928         if (ret)
 929                 goto err_out;
 930
 931         if (sg_len > NUM_BD) {
 932                 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
 933                                 channel, sg_len, NUM_BD);
 934                 ret = -EINVAL;
 935                 goto err_out;
 936         }
 937
 938         sdmac->chn_count = 0;
 939         for_each_sg(sgl, sg, sg_len, i) {
 940                 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
 941                 int param;
 942
 943                 bd->buffer_addr = sg->dma_address;
 944
 945                 count = sg_dma_len(sg);
 946
 947                 if (count > 0xffff) {
 948                         dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
 949                                         channel, count, 0xffff);
 950                         ret = -EINVAL;
 951                         goto err_out;
 952                 }
 953
 954                 bd->mode.count = count;
 955                 sdmac->chn_count += count;
 956
 957                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) {
 958                         ret =  -EINVAL;
 959                         goto err_out;
 960                 }
 961
 962                 switch (sdmac->word_size) {
 963                 case DMA_SLAVE_BUSWIDTH_4_BYTES:
 964                         bd->mode.command = 0;
 965                         if (count & 3 || sg->dma_address & 3)
 966                                 return NULL;
 967                         break;
 968                 case DMA_SLAVE_BUSWIDTH_2_BYTES:
 969                         bd->mode.command = 2;
 970                         if (count & 1 || sg->dma_address & 1)
 971                                 return NULL;
 972                         break;
 973                 case DMA_SLAVE_BUSWIDTH_1_BYTE:
 974                         bd->mode.command = 1;
 975                         break;
 976                 default:
 977                         return NULL;
 978                 }
 979
 980                 param = BD_DONE | BD_EXTD | BD_CONT;
 981
 982                 if (i + 1 == sg_len) {
 983                         param |= BD_INTR;
 984                         param |= BD_LAST;
 985                         param &= ~BD_CONT;
 986                 }
 987
 988                 dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n",
 989                                 i, count, sg->dma_address,
 990                                 param & BD_WRAP ? "wrap" : "",
 991                                 param & BD_INTR ? " intr" : "");
 992
 993                 bd->mode.status = param;
 994         }
 995
 996         sdmac->num_bd = sg_len;
 997         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
 998
 999         return &sdmac->desc;
1000 err_out:
1001         sdmac->status = DMA_ERROR;
1002         return NULL;
1003 }
1004
1005 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
1006                 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
1007                 size_t period_len, enum dma_transfer_direction direction,
1008                 unsigned long flags, void *context)
1009 {
1010         struct sdma_channel *sdmac = to_sdma_chan(chan);
1011         struct sdma_engine *sdma = sdmac->sdma;
1012         int num_periods = buf_len / period_len;
1013         int channel = sdmac->channel;
1014         int ret, i = 0, buf = 0;
1015
1016         dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1017
1018         if (sdmac->status == DMA_IN_PROGRESS)
1019                 return NULL;
1020
1021         sdmac->status = DMA_IN_PROGRESS;
1022
1023         sdmac->buf_tail = 0;
1024
1025         sdmac->flags |= IMX_DMA_SG_LOOP;
1026         sdmac->direction = direction;
1027         ret = sdma_load_context(sdmac);
1028         if (ret)
1029                 goto err_out;
1030
1031         if (num_periods > NUM_BD) {
1032                 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1033                                 channel, num_periods, NUM_BD);
1034                 goto err_out;
1035         }
1036
1037         if (period_len > 0xffff) {
1038                 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %d > %d\n",
1039                                 channel, period_len, 0xffff);
1040                 goto err_out;
1041         }
1042
1043         while (buf < buf_len) {
1044                 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1045                 int param;
1046
1047                 bd->buffer_addr = dma_addr;
1048
1049                 bd->mode.count = period_len;
1050
1051                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1052                         goto err_out;
1053                 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1054                         bd->mode.command = 0;
1055                 else
1056                         bd->mode.command = sdmac->word_size;
1057
1058                 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1059                 if (i + 1 == num_periods)
1060                         param |= BD_WRAP;
1061
1062                 dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n",
1063                                 i, period_len, dma_addr,
1064                                 param & BD_WRAP ? "wrap" : "",
1065                                 param & BD_INTR ? " intr" : "");
1066
1067                 bd->mode.status = param;
1068
1069                 dma_addr += period_len;
1070                 buf += period_len;
1071
1072                 i++;
1073         }
1074
1075         sdmac->num_bd = num_periods;
1076         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1077
1078         return &sdmac->desc;
1079 err_out:
1080         sdmac->status = DMA_ERROR;
1081         return NULL;
1082 }
1083
1084 static int sdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1085                 unsigned long arg)
1086 {
1087         struct sdma_channel *sdmac = to_sdma_chan(chan);
1088         struct dma_slave_config *dmaengine_cfg = (void *)arg;
1089
1090         switch (cmd) {
1091         case DMA_TERMINATE_ALL:
1092                 sdma_disable_channel(sdmac);
1093                 return 0;
1094         case DMA_SLAVE_CONFIG:
1095                 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
1096                         sdmac->per_address = dmaengine_cfg->src_addr;
1097                         sdmac->watermark_level = dmaengine_cfg->src_maxburst *
1098                                                 dmaengine_cfg->src_addr_width;
1099                         sdmac->word_size = dmaengine_cfg->src_addr_width;
1100                 } else {
1101                         sdmac->per_address = dmaengine_cfg->dst_addr;
1102                         sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
1103                                                 dmaengine_cfg->dst_addr_width;
1104                         sdmac->word_size = dmaengine_cfg->dst_addr_width;
1105                 }
1106                 sdmac->direction = dmaengine_cfg->direction;
1107                 return sdma_config_channel(sdmac);
1108         default:
1109                 return -ENOSYS;
1110         }
1111
1112         return -EINVAL;
1113 }
1114
1115 static enum dma_status sdma_tx_status(struct dma_chan *chan,
1116                                       dma_cookie_t cookie,
1117                                       struct dma_tx_state *txstate)
1118 {
1119         struct sdma_channel *sdmac = to_sdma_chan(chan);
1120
1121         dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
1122                         sdmac->chn_count - sdmac->chn_real_count);
1123
1124         return sdmac->status;
1125 }
1126
1127 static void sdma_issue_pending(struct dma_chan *chan)
1128 {
1129         struct sdma_channel *sdmac = to_sdma_chan(chan);
1130         struct sdma_engine *sdma = sdmac->sdma;
1131
1132         if (sdmac->status == DMA_IN_PROGRESS)
1133                 sdma_enable_channel(sdma, sdmac->channel);
1134 }
1135
1136 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1137
1138 static void sdma_add_scripts(struct sdma_engine *sdma,
1139                 const struct sdma_script_start_addrs *addr)
1140 {
1141         s32 *addr_arr = (u32 *)addr;
1142         s32 *saddr_arr = (u32 *)sdma->script_addrs;
1143         int i;
1144
1145         for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1146                 if (addr_arr[i] > 0)
1147                         saddr_arr[i] = addr_arr[i];
1148 }
1149
1150 static void sdma_load_firmware(const struct firmware *fw, void *context)
1151 {
1152         struct sdma_engine *sdma = context;
1153         const struct sdma_firmware_header *header;
1154         const struct sdma_script_start_addrs *addr;
1155         unsigned short *ram_code;
1156
1157         if (!fw) {
1158                 dev_err(sdma->dev, "firmware not found\n");
1159                 return;
1160         }
1161
1162         if (fw->size < sizeof(*header))
1163                 goto err_firmware;
1164
1165         header = (struct sdma_firmware_header *)fw->data;
1166
1167         if (header->magic != SDMA_FIRMWARE_MAGIC)
1168                 goto err_firmware;
1169         if (header->ram_code_start + header->ram_code_size > fw->size)
1170                 goto err_firmware;
1171
1172         addr = (void *)header + header->script_addrs_start;
1173         ram_code = (void *)header + header->ram_code_start;
1174
1175         clk_enable(sdma->clk_ipg);
1176         clk_enable(sdma->clk_ahb);
1177         /* download the RAM image for SDMA */
1178         sdma_load_script(sdma, ram_code,
1179                         header->ram_code_size,
1180                         addr->ram_code_start_addr);
1181         clk_disable(sdma->clk_ipg);
1182         clk_disable(sdma->clk_ahb);
1183
1184         sdma_add_scripts(sdma, addr);
1185
1186         dev_info(sdma->dev, "loaded firmware %d.%d\n",
1187                         header->version_major,
1188                         header->version_minor);
1189
1190 err_firmware:
1191         release_firmware(fw);
1192 }
1193
1194 static int __init sdma_get_firmware(struct sdma_engine *sdma,
1195                 const char *fw_name)
1196 {
1197         int ret;
1198
1199         ret = request_firmware_nowait(THIS_MODULE,
1200                         FW_ACTION_HOTPLUG, fw_name, sdma->dev,
1201                         GFP_KERNEL, sdma, sdma_load_firmware);
1202
1203         return ret;
1204 }
1205
1206 static int __init sdma_init(struct sdma_engine *sdma)
1207 {
1208         int i, ret;
1209         dma_addr_t ccb_phys;
1210
1211         switch (sdma->devtype) {
1212         case IMX31_SDMA:
1213                 sdma->num_events = 32;
1214                 break;
1215         case IMX35_SDMA:
1216                 sdma->num_events = 48;
1217                 break;
1218         default:
1219                 dev_err(sdma->dev, "Unknown sdma type %d. aborting\n",
1220                         sdma->devtype);
1221                 return -ENODEV;
1222         }
1223
1224         clk_enable(sdma->clk_ipg);
1225         clk_enable(sdma->clk_ahb);
1226
1227         /* Be sure SDMA has not started yet */
1228         writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
1229
1230         sdma->channel_control = dma_alloc_coherent(NULL,
1231                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
1232                         sizeof(struct sdma_context_data),
1233                         &ccb_phys, GFP_KERNEL);
1234
1235         if (!sdma->channel_control) {
1236                 ret = -ENOMEM;
1237                 goto err_dma_alloc;
1238         }
1239
1240         sdma->context = (void *)sdma->channel_control +
1241                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1242         sdma->context_phys = ccb_phys +
1243                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1244
1245         /* Zero-out the CCB structures array just allocated */
1246         memset(sdma->channel_control, 0,
1247                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control));
1248
1249         /* disable all channels */
1250         for (i = 0; i < sdma->num_events; i++)
1251                 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i));
1252
1253         /* All channels have priority 0 */
1254         for (i = 0; i < MAX_DMA_CHANNELS; i++)
1255                 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1256
1257         ret = sdma_request_channel(&sdma->channel[0]);
1258         if (ret)
1259                 goto err_dma_alloc;
1260
1261         sdma_config_ownership(&sdma->channel[0], false, true, false);
1262
1263         /* Set Command Channel (Channel Zero) */
1264         writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
1265
1266         /* Set bits of CONFIG register but with static context switching */
1267         /* FIXME: Check whether to set ACR bit depending on clock ratios */
1268         writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
1269
1270         writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1271
1272         /* Set bits of CONFIG register with given context switching mode */
1273         writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
1274
1275         /* Initializes channel's priorities */
1276         sdma_set_channel_priority(&sdma->channel[0], 7);
1277
1278         clk_disable(sdma->clk_ipg);
1279         clk_disable(sdma->clk_ahb);
1280
1281         return 0;
1282
1283 err_dma_alloc:
1284         clk_disable(sdma->clk_ipg);
1285         clk_disable(sdma->clk_ahb);
1286         dev_err(sdma->dev, "initialisation failed with %d\n", ret);
1287         return ret;
1288 }
1289
1290 static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param)
1291 {
1292         struct imx_dma_data *data = fn_param;
1293
1294         if (!imx_dma_is_general_purpose(chan))
1295                 return false;
1296
1297         chan->private = data;
1298
1299         return true;
1300 }
1301
1302 static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec,
1303                                    struct of_dma *ofdma)
1304 {
1305         struct sdma_engine *sdma = ofdma->of_dma_data;
1306         dma_cap_mask_t mask = sdma->dma_device.cap_mask;
1307         struct imx_dma_data data;
1308
1309         if (dma_spec->args_count != 3)
1310                 return NULL;
1311
1312         data.dma_request = dma_spec->args[0];
1313         data.peripheral_type = dma_spec->args[1];
1314         data.priority = dma_spec->args[2];
1315
1316         return dma_request_channel(mask, sdma_filter_fn, &data);
1317 }
1318
1319 static int __init sdma_probe(struct platform_device *pdev)
1320 {
1321         const struct of_device_id *of_id =
1322                         of_match_device(sdma_dt_ids, &pdev->dev);
1323         struct device_node *np = pdev->dev.of_node;
1324         const char *fw_name;
1325         int ret;
1326         int irq;
1327         struct resource *iores;
1328         struct sdma_platform_data *pdata = dev_get_platdata(&pdev->dev);
1329         int i;
1330         struct sdma_engine *sdma;
1331         s32 *saddr_arr;
1332
1333         sdma = kzalloc(sizeof(*sdma), GFP_KERNEL);
1334         if (!sdma)
1335                 return -ENOMEM;
1336
1337         spin_lock_init(&sdma->channel_0_lock);
1338
1339         sdma->dev = &pdev->dev;
1340
1341         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1342         irq = platform_get_irq(pdev, 0);
1343         if (!iores || irq < 0) {
1344                 ret = -EINVAL;
1345                 goto err_irq;
1346         }
1347
1348         if (!request_mem_region(iores->start, resource_size(iores), pdev->name)) {
1349                 ret = -EBUSY;
1350                 goto err_request_region;
1351         }
1352
1353         sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1354         if (IS_ERR(sdma->clk_ipg)) {
1355                 ret = PTR_ERR(sdma->clk_ipg);
1356                 goto err_clk;
1357         }
1358
1359         sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1360         if (IS_ERR(sdma->clk_ahb)) {
1361                 ret = PTR_ERR(sdma->clk_ahb);
1362                 goto err_clk;
1363         }
1364
1365         clk_prepare(sdma->clk_ipg);
1366         clk_prepare(sdma->clk_ahb);
1367
1368         sdma->regs = ioremap(iores->start, resource_size(iores));
1369         if (!sdma->regs) {
1370                 ret = -ENOMEM;
1371                 goto err_ioremap;
1372         }
1373
1374         ret = request_irq(irq, sdma_int_handler, 0, "sdma", sdma);
1375         if (ret)
1376                 goto err_request_irq;
1377
1378         sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
1379         if (!sdma->script_addrs) {
1380                 ret = -ENOMEM;
1381                 goto err_alloc;
1382         }
1383
1384         /* initially no scripts available */
1385         saddr_arr = (s32 *)sdma->script_addrs;
1386         for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1387                 saddr_arr[i] = -EINVAL;
1388
1389         if (of_id)
1390                 pdev->id_entry = of_id->data;
1391         sdma->devtype = pdev->id_entry->driver_data;
1392
1393         dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
1394         dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
1395
1396         INIT_LIST_HEAD(&sdma->dma_device.channels);
1397         /* Initialize channel parameters */
1398         for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1399                 struct sdma_channel *sdmac = &sdma->channel[i];
1400
1401                 sdmac->sdma = sdma;
1402                 spin_lock_init(&sdmac->lock);
1403
1404                 sdmac->chan.device = &sdma->dma_device;
1405                 dma_cookie_init(&sdmac->chan);
1406                 sdmac->channel = i;
1407
1408                 tasklet_init(&sdmac->tasklet, sdma_tasklet,
1409                              (unsigned long) sdmac);
1410                 /*
1411                  * Add the channel to the DMAC list. Do not add channel 0 though
1412                  * because we need it internally in the SDMA driver. This also means
1413                  * that channel 0 in dmaengine counting matches sdma channel 1.
1414                  */
1415                 if (i)
1416                         list_add_tail(&sdmac->chan.device_node,
1417                                         &sdma->dma_device.channels);
1418         }
1419
1420         ret = sdma_init(sdma);
1421         if (ret)
1422                 goto err_init;
1423
1424         if (pdata && pdata->script_addrs)
1425                 sdma_add_scripts(sdma, pdata->script_addrs);
1426
1427         if (pdata) {
1428                 ret = sdma_get_firmware(sdma, pdata->fw_name);
1429                 if (ret)
1430                         dev_warn(&pdev->dev, "failed to get firmware from platform data\n");
1431         } else {
1432                 /*
1433                  * Because that device tree does not encode ROM script address,
1434                  * the RAM script in firmware is mandatory for device tree
1435                  * probe, otherwise it fails.
1436                  */
1437                 ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
1438                                               &fw_name);
1439                 if (ret)
1440                         dev_warn(&pdev->dev, "failed to get firmware name\n");
1441                 else {
1442                         ret = sdma_get_firmware(sdma, fw_name);
1443                         if (ret)
1444                                 dev_warn(&pdev->dev, "failed to get firmware from device tree\n");
1445                 }
1446         }
1447
1448         sdma->dma_device.dev = &pdev->dev;
1449
1450         sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
1451         sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
1452         sdma->dma_device.device_tx_status = sdma_tx_status;
1453         sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
1454         sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
1455         sdma->dma_device.device_control = sdma_control;
1456         sdma->dma_device.device_issue_pending = sdma_issue_pending;
1457         sdma->dma_device.dev->dma_parms = &sdma->dma_parms;
1458         dma_set_max_seg_size(sdma->dma_device.dev, 65535);
1459
1460         ret = dma_async_device_register(&sdma->dma_device);
1461         if (ret) {
1462                 dev_err(&pdev->dev, "unable to register\n");
1463                 goto err_init;
1464         }
1465
1466         if (np) {
1467                 ret = of_dma_controller_register(np, sdma_xlate, sdma);
1468                 if (ret) {
1469                         dev_err(&pdev->dev, "failed to register controller\n");
1470                         goto err_register;
1471                 }
1472         }
1473
1474         dev_info(sdma->dev, "initialized\n");
1475
1476         return 0;
1477
1478 err_register:
1479         dma_async_device_unregister(&sdma->dma_device);
1480 err_init:
1481         kfree(sdma->script_addrs);
1482 err_alloc:
1483         free_irq(irq, sdma);
1484 err_request_irq:
1485         iounmap(sdma->regs);
1486 err_ioremap:
1487 err_clk:
1488         release_mem_region(iores->start, resource_size(iores));
1489 err_request_region:
1490 err_irq:
1491         kfree(sdma);
1492         return ret;
1493 }
1494
1495 static int sdma_remove(struct platform_device *pdev)
1496 {
1497         return -EBUSY;
1498 }
1499
1500 static struct platform_driver sdma_driver = {
1501         .driver         = {
1502                 .name   = "imx-sdma",
1503                 .of_match_table = sdma_dt_ids,
1504         },
1505         .id_table       = sdma_devtypes,
1506         .remove         = sdma_remove,
1507 };
1508
1509 static int __init sdma_module_init(void)
1510 {
1511         return platform_driver_probe(&sdma_driver, sdma_probe);
1512 }
1513 module_init(sdma_module_init);
1514
1515 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1516 MODULE_DESCRIPTION("i.MX SDMA driver");
1517 MODULE_LICENSE("GPL");