drivers/dma/imx-sdma.c

   1 /*
   2  * drivers/dma/imx-sdma.c
   3  *
   4  * This file contains a driver for the Freescale Smart DMA engine
   5  *
   6  * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
   7  *
   8  * Based on code from Freescale:
   9  *
  10  * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
  11  *
  12  * The code contained herein is licensed under the GNU General Public
  13  * License. You may obtain a copy of the GNU General Public License
  14  * Version 2 or later at the following locations:
  15  *
  16  * http://www.opensource.org/licenses/gpl-license.html
  17  * http://www.gnu.org/copyleft/gpl.html
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/module.h>
  22 #include <linux/types.h>
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/clk.h>
  26 #include <linux/wait.h>
  27 #include <linux/sched.h>
  28 #include <linux/semaphore.h>
  29 #include <linux/spinlock.h>
  30 #include <linux/device.h>
  31 #include <linux/dma-mapping.h>
  32 #include <linux/firmware.h>
  33 #include <linux/slab.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/dmaengine.h>
  36 #include <linux/of.h>
  37 #include <linux/of_device.h>
  38
  39 #include <asm/irq.h>
  40 #include <mach/sdma.h>
  41 #include <mach/dma.h>
  42 #include <mach/hardware.h>
  43
  44 /* SDMA registers */
  45 #define SDMA_H_C0PTR            0x000
  46 #define SDMA_H_INTR             0x004
  47 #define SDMA_H_STATSTOP         0x008
  48 #define SDMA_H_START            0x00c
  49 #define SDMA_H_EVTOVR           0x010
  50 #define SDMA_H_DSPOVR           0x014
  51 #define SDMA_H_HOSTOVR          0x018
  52 #define SDMA_H_EVTPEND          0x01c
  53 #define SDMA_H_DSPENBL          0x020
  54 #define SDMA_H_RESET            0x024
  55 #define SDMA_H_EVTERR           0x028
  56 #define SDMA_H_INTRMSK          0x02c
  57 #define SDMA_H_PSW              0x030
  58 #define SDMA_H_EVTERRDBG        0x034
  59 #define SDMA_H_CONFIG           0x038
  60 #define SDMA_ONCE_ENB           0x040
  61 #define SDMA_ONCE_DATA          0x044
  62 #define SDMA_ONCE_INSTR         0x048
  63 #define SDMA_ONCE_STAT          0x04c
  64 #define SDMA_ONCE_CMD           0x050
  65 #define SDMA_EVT_MIRROR         0x054
  66 #define SDMA_ILLINSTADDR        0x058
  67 #define SDMA_CHN0ADDR           0x05c
  68 #define SDMA_ONCE_RTB           0x060
  69 #define SDMA_XTRIG_CONF1        0x070
  70 #define SDMA_XTRIG_CONF2        0x074
  71 #define SDMA_CHNENBL0_IMX35     0x200
  72 #define SDMA_CHNENBL0_IMX31     0x080
  73 #define SDMA_CHNPRI_0           0x100
  74
  75 /*
  76  * Buffer descriptor status values.
  77  */
  78 #define BD_DONE  0x01
  79 #define BD_WRAP  0x02
  80 #define BD_CONT  0x04
  81 #define BD_INTR  0x08
  82 #define BD_RROR  0x10
  83 #define BD_LAST  0x20
  84 #define BD_EXTD  0x80
  85
  86 /*
  87  * Data Node descriptor status values.
  88  */
  89 #define DND_END_OF_FRAME  0x80
  90 #define DND_END_OF_XFER   0x40
  91 #define DND_DONE          0x20
  92 #define DND_UNUSED        0x01
  93
  94 /*
  95  * IPCV2 descriptor status values.
  96  */
  97 #define BD_IPCV2_END_OF_FRAME  0x40
  98
  99 #define IPCV2_MAX_NODES        50
 100 /*
 101  * Error bit set in the CCB status field by the SDMA,
 102  * in setbd routine, in case of a transfer error
 103  */
 104 #define DATA_ERROR  0x10000000
 105
 106 /*
 107  * Buffer descriptor commands.
 108  */
 109 #define C0_ADDR             0x01
 110 #define C0_LOAD             0x02
 111 #define C0_DUMP             0x03
 112 #define C0_SETCTX           0x07
 113 #define C0_GETCTX           0x03
 114 #define C0_SETDM            0x01
 115 #define C0_SETPM            0x04
 116 #define C0_GETDM            0x02
 117 #define C0_GETPM            0x08
 118 /*
 119  * Change endianness indicator in the BD command field
 120  */
 121 #define CHANGE_ENDIANNESS   0x80
 122
 123 /*
 124  * Mode/Count of data node descriptors - IPCv2
 125  */
 126 struct sdma_mode_count {
 127         u32 count   : 16; /* size of the buffer pointed by this BD */
 128         u32 status  :  8; /* E,R,I,C,W,D status bits stored here */
 129         u32 command :  8; /* command mostlky used for channel 0 */
 130 };
 131
 132 /*
 133  * Buffer descriptor
 134  */
 135 struct sdma_buffer_descriptor {
 136         struct sdma_mode_count  mode;
 137         u32 buffer_addr;        /* address of the buffer described */
 138         u32 ext_buffer_addr;    /* extended buffer address */
 139 } __attribute__ ((packed));
 140
 141 /**
 142  * struct sdma_channel_control - Channel control Block
 143  *
 144  * @current_bd_ptr      current buffer descriptor processed
 145  * @base_bd_ptr         first element of buffer descriptor array
 146  * @unused              padding. The SDMA engine expects an array of 128 byte
 147  *                      control blocks
 148  */
 149 struct sdma_channel_control {
 150         u32 current_bd_ptr;
 151         u32 base_bd_ptr;
 152         u32 unused[2];
 153 } __attribute__ ((packed));
 154
 155 /**
 156  * struct sdma_state_registers - SDMA context for a channel
 157  *
 158  * @pc:         program counter
 159  * @t:          test bit: status of arithmetic & test instruction
 160  * @rpc:        return program counter
 161  * @sf:         source fault while loading data
 162  * @spc:        loop start program counter
 163  * @df:         destination fault while storing data
 164  * @epc:        loop end program counter
 165  * @lm:         loop mode
 166  */
 167 struct sdma_state_registers {
 168         u32 pc     :14;
 169         u32 unused1: 1;
 170         u32 t      : 1;
 171         u32 rpc    :14;
 172         u32 unused0: 1;
 173         u32 sf     : 1;
 174         u32 spc    :14;
 175         u32 unused2: 1;
 176         u32 df     : 1;
 177         u32 epc    :14;
 178         u32 lm     : 2;
 179 } __attribute__ ((packed));
 180
 181 /**
 182  * struct sdma_context_data - sdma context specific to a channel
 183  *
 184  * @channel_state:      channel state bits
 185  * @gReg:               general registers
 186  * @mda:                burst dma destination address register
 187  * @msa:                burst dma source address register
 188  * @ms:                 burst dma status register
 189  * @md:                 burst dma data register
 190  * @pda:                peripheral dma destination address register
 191  * @psa:                peripheral dma source address register
 192  * @ps:                 peripheral dma status register
 193  * @pd:                 peripheral dma data register
 194  * @ca:                 CRC polynomial register
 195  * @cs:                 CRC accumulator register
 196  * @dda:                dedicated core destination address register
 197  * @dsa:                dedicated core source address register
 198  * @ds:                 dedicated core status register
 199  * @dd:                 dedicated core data register
 200  */
 201 struct sdma_context_data {
 202         struct sdma_state_registers  channel_state;
 203         u32  gReg[8];
 204         u32  mda;
 205         u32  msa;
 206         u32  ms;
 207         u32  md;
 208         u32  pda;
 209         u32  psa;
 210         u32  ps;
 211         u32  pd;
 212         u32  ca;
 213         u32  cs;
 214         u32  dda;
 215         u32  dsa;
 216         u32  ds;
 217         u32  dd;
 218         u32  scratch0;
 219         u32  scratch1;
 220         u32  scratch2;
 221         u32  scratch3;
 222         u32  scratch4;
 223         u32  scratch5;
 224         u32  scratch6;
 225         u32  scratch7;
 226 } __attribute__ ((packed));
 227
 228 #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
 229
 230 struct sdma_engine;
 231
 232 /**
 233  * struct sdma_channel - housekeeping for a SDMA channel
 234  *
 235  * @sdma                pointer to the SDMA engine for this channel
 236  * @channel             the channel number, matches dmaengine chan_id + 1
 237  * @direction           transfer type. Needed for setting SDMA script
 238  * @peripheral_type     Peripheral type. Needed for setting SDMA script
 239  * @event_id0           aka dma request line
 240  * @event_id1           for channels that use 2 events
 241  * @word_size           peripheral access size
 242  * @buf_tail            ID of the buffer that was processed
 243  * @done                channel completion
 244  * @num_bd              max NUM_BD. number of descriptors currently handling
 245  */
 246 struct sdma_channel {
 247         struct sdma_engine              *sdma;
 248         unsigned int                    channel;
 249         enum dma_transfer_direction             direction;
 250         enum sdma_peripheral_type       peripheral_type;
 251         unsigned int                    event_id0;
 252         unsigned int                    event_id1;
 253         enum dma_slave_buswidth         word_size;
 254         unsigned int                    buf_tail;
 255         struct completion               done;
 256         unsigned int                    num_bd;
 257         struct sdma_buffer_descriptor   *bd;
 258         dma_addr_t                      bd_phys;
 259         unsigned int                    pc_from_device, pc_to_device;
 260         unsigned long                   flags;
 261         dma_addr_t                      per_address;
 262         u32                             event_mask0, event_mask1;
 263         u32                             watermark_level;
 264         u32                             shp_addr, per_addr;
 265         struct dma_chan                 chan;
 266         spinlock_t                      lock;
 267         struct dma_async_tx_descriptor  desc;
 268         dma_cookie_t                    last_completed;
 269         enum dma_status                 status;
 270         unsigned int                    chn_count;
 271         unsigned int                    chn_real_count;
 272 };
 273
 274 #define IMX_DMA_SG_LOOP         (1 << 0)
 275
 276 #define MAX_DMA_CHANNELS 32
 277 #define MXC_SDMA_DEFAULT_PRIORITY 1
 278 #define MXC_SDMA_MIN_PRIORITY 1
 279 #define MXC_SDMA_MAX_PRIORITY 7
 280
 281 #define SDMA_FIRMWARE_MAGIC 0x414d4453
 282
 283 /**
 284  * struct sdma_firmware_header - Layout of the firmware image
 285  *
 286  * @magic               "SDMA"
 287  * @version_major       increased whenever layout of struct sdma_script_start_addrs
 288  *                      changes.
 289  * @version_minor       firmware minor version (for binary compatible changes)
 290  * @script_addrs_start  offset of struct sdma_script_start_addrs in this image
 291  * @num_script_addrs    Number of script addresses in this image
 292  * @ram_code_start      offset of SDMA ram image in this firmware image
 293  * @ram_code_size       size of SDMA ram image
 294  * @script_addrs        Stores the start address of the SDMA scripts
 295  *                      (in SDMA memory space)
 296  */
 297 struct sdma_firmware_header {
 298         u32     magic;
 299         u32     version_major;
 300         u32     version_minor;
 301         u32     script_addrs_start;
 302         u32     num_script_addrs;
 303         u32     ram_code_start;
 304         u32     ram_code_size;
 305 };
 306
 307 enum sdma_devtype {
 308         IMX31_SDMA,     /* runs on i.mx31 */
 309         IMX35_SDMA,     /* runs on i.mx35 and later */
 310 };
 311
 312 struct sdma_engine {
 313         struct device                   *dev;
 314         struct device_dma_parameters    dma_parms;
 315         struct sdma_channel             channel[MAX_DMA_CHANNELS];
 316         struct sdma_channel_control     *channel_control;
 317         void __iomem                    *regs;
 318         enum sdma_devtype               devtype;
 319         unsigned int                    num_events;
 320         struct sdma_context_data        *context;
 321         dma_addr_t                      context_phys;
 322         struct dma_device               dma_device;
 323         struct clk                      *clk;
 324         struct mutex                    channel_0_lock;
 325         struct sdma_script_start_addrs  *script_addrs;
 326 };
 327
 328 static struct platform_device_id sdma_devtypes[] = {
 329         {
 330                 .name = "imx31-sdma",
 331                 .driver_data = IMX31_SDMA,
 332         }, {
 333                 .name = "imx35-sdma",
 334                 .driver_data = IMX35_SDMA,
 335         }, {
 336                 /* sentinel */
 337         }
 338 };
 339 MODULE_DEVICE_TABLE(platform, sdma_devtypes);
 340
 341 static const struct of_device_id sdma_dt_ids[] = {
 342         { .compatible = "fsl,imx31-sdma", .data = &sdma_devtypes[IMX31_SDMA], },
 343         { .compatible = "fsl,imx35-sdma", .data = &sdma_devtypes[IMX35_SDMA], },
 344         { /* sentinel */ }
 345 };
 346 MODULE_DEVICE_TABLE(of, sdma_dt_ids);
 347
 348 #define SDMA_H_CONFIG_DSPDMA    (1 << 12) /* indicates if the DSPDMA is used */
 349 #define SDMA_H_CONFIG_RTD_PINS  (1 << 11) /* indicates if Real-Time Debug pins are enabled */
 350 #define SDMA_H_CONFIG_ACR       (1 << 4)  /* indicates if AHB freq /core freq = 2 or 1 */
 351 #define SDMA_H_CONFIG_CSM       (3)       /* indicates which context switch mode is selected*/
 352
 353 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
 354 {
 355         u32 chnenbl0 = (sdma->devtype == IMX31_SDMA ? SDMA_CHNENBL0_IMX31 :
 356                                                       SDMA_CHNENBL0_IMX35);
 357         return chnenbl0 + event * 4;
 358 }
 359
 360 static int sdma_config_ownership(struct sdma_channel *sdmac,
 361                 bool event_override, bool mcu_override, bool dsp_override)
 362 {
 363         struct sdma_engine *sdma = sdmac->sdma;
 364         int channel = sdmac->channel;
 365         u32 evt, mcu, dsp;
 366
 367         if (event_override && mcu_override && dsp_override)
 368                 return -EINVAL;
 369
 370         evt = __raw_readl(sdma->regs + SDMA_H_EVTOVR);
 371         mcu = __raw_readl(sdma->regs + SDMA_H_HOSTOVR);
 372         dsp = __raw_readl(sdma->regs + SDMA_H_DSPOVR);
 373
 374         if (dsp_override)
 375                 dsp &= ~(1 << channel);
 376         else
 377                 dsp |= (1 << channel);
 378
 379         if (event_override)
 380                 evt &= ~(1 << channel);
 381         else
 382                 evt |= (1 << channel);
 383
 384         if (mcu_override)
 385                 mcu &= ~(1 << channel);
 386         else
 387                 mcu |= (1 << channel);
 388
 389         __raw_writel(evt, sdma->regs + SDMA_H_EVTOVR);
 390         __raw_writel(mcu, sdma->regs + SDMA_H_HOSTOVR);
 391         __raw_writel(dsp, sdma->regs + SDMA_H_DSPOVR);
 392
 393         return 0;
 394 }
 395
 396 /*
 397  * sdma_run_channel - run a channel and wait till it's done
 398  */
 399 static int sdma_run_channel(struct sdma_channel *sdmac)
 400 {
 401         struct sdma_engine *sdma = sdmac->sdma;
 402         int channel = sdmac->channel;
 403         int ret;
 404
 405         init_completion(&sdmac->done);
 406
 407         __raw_writel(1 << channel, sdma->regs + SDMA_H_START);
 408
 409         ret = wait_for_completion_timeout(&sdmac->done, HZ);
 410
 411         return ret ? 0 : -ETIMEDOUT;
 412 }
 413
 414 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
 415                 u32 address)
 416 {
 417         struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
 418         void *buf_virt;
 419         dma_addr_t buf_phys;
 420         int ret;
 421
 422         mutex_lock(&sdma->channel_0_lock);
 423
 424         buf_virt = dma_alloc_coherent(NULL,
 425                         size,
 426                         &buf_phys, GFP_KERNEL);
 427         if (!buf_virt) {
 428                 ret = -ENOMEM;
 429                 goto err_out;
 430         }
 431
 432         bd0->mode.command = C0_SETPM;
 433         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
 434         bd0->mode.count = size / 2;
 435         bd0->buffer_addr = buf_phys;
 436         bd0->ext_buffer_addr = address;
 437
 438         memcpy(buf_virt, buf, size);
 439
 440         ret = sdma_run_channel(&sdma->channel[0]);
 441
 442         dma_free_coherent(NULL, size, buf_virt, buf_phys);
 443
 444 err_out:
 445         mutex_unlock(&sdma->channel_0_lock);
 446
 447         return ret;
 448 }
 449
 450 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
 451 {
 452         struct sdma_engine *sdma = sdmac->sdma;
 453         int channel = sdmac->channel;
 454         u32 val;
 455         u32 chnenbl = chnenbl_ofs(sdma, event);
 456
 457         val = __raw_readl(sdma->regs + chnenbl);
 458         val |= (1 << channel);
 459         __raw_writel(val, sdma->regs + chnenbl);
 460 }
 461
 462 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
 463 {
 464         struct sdma_engine *sdma = sdmac->sdma;
 465         int channel = sdmac->channel;
 466         u32 chnenbl = chnenbl_ofs(sdma, event);
 467         u32 val;
 468
 469         val = __raw_readl(sdma->regs + chnenbl);
 470         val &= ~(1 << channel);
 471         __raw_writel(val, sdma->regs + chnenbl);
 472 }
 473
 474 static void sdma_handle_channel_loop(struct sdma_channel *sdmac)
 475 {
 476         struct sdma_buffer_descriptor *bd;
 477
 478         /*
 479          * loop mode. Iterate over descriptors, re-setup them and
 480          * call callback function.
 481          */
 482         while (1) {
 483                 bd = &sdmac->bd[sdmac->buf_tail];
 484
 485                 if (bd->mode.status & BD_DONE)
 486                         break;
 487
 488                 if (bd->mode.status & BD_RROR)
 489                         sdmac->status = DMA_ERROR;
 490                 else
 491                         sdmac->status = DMA_IN_PROGRESS;
 492
 493                 bd->mode.status |= BD_DONE;
 494                 sdmac->buf_tail++;
 495                 sdmac->buf_tail %= sdmac->num_bd;
 496
 497                 if (sdmac->desc.callback)
 498                         sdmac->desc.callback(sdmac->desc.callback_param);
 499         }
 500 }
 501
 502 static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac)
 503 {
 504         struct sdma_buffer_descriptor *bd;
 505         int i, error = 0;
 506
 507         sdmac->chn_real_count = 0;
 508         /*
 509          * non loop mode. Iterate over all descriptors, collect
 510          * errors and call callback function
 511          */
 512         for (i = 0; i < sdmac->num_bd; i++) {
 513                 bd = &sdmac->bd[i];
 514
 515                  if (bd->mode.status & (BD_DONE | BD_RROR))
 516                         error = -EIO;
 517                  sdmac->chn_real_count += bd->mode.count;
 518         }
 519
 520         if (error)
 521                 sdmac->status = DMA_ERROR;
 522         else
 523                 sdmac->status = DMA_SUCCESS;
 524
 525         sdmac->last_completed = sdmac->desc.cookie;
 526         if (sdmac->desc.callback)
 527                 sdmac->desc.callback(sdmac->desc.callback_param);
 528 }
 529
 530 static void mxc_sdma_handle_channel(struct sdma_channel *sdmac)
 531 {
 532         complete(&sdmac->done);
 533
 534         /* not interested in channel 0 interrupts */
 535         if (sdmac->channel == 0)
 536                 return;
 537
 538         if (sdmac->flags & IMX_DMA_SG_LOOP)
 539                 sdma_handle_channel_loop(sdmac);
 540         else
 541                 mxc_sdma_handle_channel_normal(sdmac);
 542 }
 543
 544 static irqreturn_t sdma_int_handler(int irq, void *dev_id)
 545 {
 546         struct sdma_engine *sdma = dev_id;
 547         u32 stat;
 548
 549         stat = __raw_readl(sdma->regs + SDMA_H_INTR);
 550         __raw_writel(stat, sdma->regs + SDMA_H_INTR);
 551
 552         while (stat) {
 553                 int channel = fls(stat) - 1;
 554                 struct sdma_channel *sdmac = &sdma->channel[channel];
 555
 556                 mxc_sdma_handle_channel(sdmac);
 557
 558                 stat &= ~(1 << channel);
 559         }
 560
 561         return IRQ_HANDLED;
 562 }
 563
 564 /*
 565  * sets the pc of SDMA script according to the peripheral type
 566  */
 567 static void sdma_get_pc(struct sdma_channel *sdmac,
 568                 enum sdma_peripheral_type peripheral_type)
 569 {
 570         struct sdma_engine *sdma = sdmac->sdma;
 571         int per_2_emi = 0, emi_2_per = 0;
 572         /*
 573          * These are needed once we start to support transfers between
 574          * two peripherals or memory-to-memory transfers
 575          */
 576         int per_2_per = 0, emi_2_emi = 0;
 577
 578         sdmac->pc_from_device = 0;
 579         sdmac->pc_to_device = 0;
 580
 581         switch (peripheral_type) {
 582         case IMX_DMATYPE_MEMORY:
 583                 emi_2_emi = sdma->script_addrs->ap_2_ap_addr;
 584                 break;
 585         case IMX_DMATYPE_DSP:
 586                 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
 587                 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
 588                 break;
 589         case IMX_DMATYPE_FIRI:
 590                 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
 591                 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
 592                 break;
 593         case IMX_DMATYPE_UART:
 594                 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
 595                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
 596                 break;
 597         case IMX_DMATYPE_UART_SP:
 598                 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
 599                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 600                 break;
 601         case IMX_DMATYPE_ATA:
 602                 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
 603                 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
 604                 break;
 605         case IMX_DMATYPE_CSPI:
 606         case IMX_DMATYPE_EXT:
 607         case IMX_DMATYPE_SSI:
 608                 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
 609                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
 610                 break;
 611         case IMX_DMATYPE_SSI_SP:
 612         case IMX_DMATYPE_MMC:
 613         case IMX_DMATYPE_SDHC:
 614         case IMX_DMATYPE_CSPI_SP:
 615         case IMX_DMATYPE_ESAI:
 616         case IMX_DMATYPE_MSHC_SP:
 617                 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
 618                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 619                 break;
 620         case IMX_DMATYPE_ASRC:
 621                 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
 622                 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
 623                 per_2_per = sdma->script_addrs->per_2_per_addr;
 624                 break;
 625         case IMX_DMATYPE_MSHC:
 626                 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
 627                 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
 628                 break;
 629         case IMX_DMATYPE_CCM:
 630                 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
 631                 break;
 632         case IMX_DMATYPE_SPDIF:
 633                 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
 634                 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
 635                 break;
 636         case IMX_DMATYPE_IPU_MEMORY:
 637                 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
 638                 break;
 639         default:
 640                 break;
 641         }
 642
 643         sdmac->pc_from_device = per_2_emi;
 644         sdmac->pc_to_device = emi_2_per;
 645 }
 646
 647 static int sdma_load_context(struct sdma_channel *sdmac)
 648 {
 649         struct sdma_engine *sdma = sdmac->sdma;
 650         int channel = sdmac->channel;
 651         int load_address;
 652         struct sdma_context_data *context = sdma->context;
 653         struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
 654         int ret;
 655
 656         if (sdmac->direction == DMA_DEV_TO_MEM) {
 657                 load_address = sdmac->pc_from_device;
 658         } else {
 659                 load_address = sdmac->pc_to_device;
 660         }
 661
 662         if (load_address < 0)
 663                 return load_address;
 664
 665         dev_dbg(sdma->dev, "load_address = %d\n", load_address);
 666         dev_dbg(sdma->dev, "wml = 0x%08x\n", sdmac->watermark_level);
 667         dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
 668         dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
 669         dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", sdmac->event_mask0);
 670         dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", sdmac->event_mask1);
 671
 672         mutex_lock(&sdma->channel_0_lock);
 673
 674         memset(context, 0, sizeof(*context));
 675         context->channel_state.pc = load_address;
 676
 677         /* Send by context the event mask,base address for peripheral
 678          * and watermark level
 679          */
 680         context->gReg[0] = sdmac->event_mask1;
 681         context->gReg[1] = sdmac->event_mask0;
 682         context->gReg[2] = sdmac->per_addr;
 683         context->gReg[6] = sdmac->shp_addr;
 684         context->gReg[7] = sdmac->watermark_level;
 685
 686         bd0->mode.command = C0_SETDM;
 687         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
 688         bd0->mode.count = sizeof(*context) / 4;
 689         bd0->buffer_addr = sdma->context_phys;
 690         bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
 691
 692         ret = sdma_run_channel(&sdma->channel[0]);
 693
 694         mutex_unlock(&sdma->channel_0_lock);
 695
 696         return ret;
 697 }
 698
 699 static void sdma_disable_channel(struct sdma_channel *sdmac)
 700 {
 701         struct sdma_engine *sdma = sdmac->sdma;
 702         int channel = sdmac->channel;
 703
 704         __raw_writel(1 << channel, sdma->regs + SDMA_H_STATSTOP);
 705         sdmac->status = DMA_ERROR;
 706 }
 707
 708 static int sdma_config_channel(struct sdma_channel *sdmac)
 709 {
 710         int ret;
 711
 712         sdma_disable_channel(sdmac);
 713
 714         sdmac->event_mask0 = 0;
 715         sdmac->event_mask1 = 0;
 716         sdmac->shp_addr = 0;
 717         sdmac->per_addr = 0;
 718
 719         if (sdmac->event_id0) {
 720                 if (sdmac->event_id0 > 32)
 721                         return -EINVAL;
 722                 sdma_event_enable(sdmac, sdmac->event_id0);
 723         }
 724
 725         switch (sdmac->peripheral_type) {
 726         case IMX_DMATYPE_DSP:
 727                 sdma_config_ownership(sdmac, false, true, true);
 728                 break;
 729         case IMX_DMATYPE_MEMORY:
 730                 sdma_config_ownership(sdmac, false, true, false);
 731                 break;
 732         default:
 733                 sdma_config_ownership(sdmac, true, true, false);
 734                 break;
 735         }
 736
 737         sdma_get_pc(sdmac, sdmac->peripheral_type);
 738
 739         if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
 740                         (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
 741                 /* Handle multiple event channels differently */
 742                 if (sdmac->event_id1) {
 743                         sdmac->event_mask1 = 1 << (sdmac->event_id1 % 32);
 744                         if (sdmac->event_id1 > 31)
 745                                 sdmac->watermark_level |= 1 << 31;
 746                         sdmac->event_mask0 = 1 << (sdmac->event_id0 % 32);
 747                         if (sdmac->event_id0 > 31)
 748                                 sdmac->watermark_level |= 1 << 30;
 749                 } else {
 750                         sdmac->event_mask0 = 1 << sdmac->event_id0;
 751                         sdmac->event_mask1 = 1 << (sdmac->event_id0 - 32);
 752                 }
 753                 /* Watermark Level */
 754                 sdmac->watermark_level |= sdmac->watermark_level;
 755                 /* Address */
 756                 sdmac->shp_addr = sdmac->per_address;
 757         } else {
 758                 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
 759         }
 760
 761         ret = sdma_load_context(sdmac);
 762
 763         return ret;
 764 }
 765
 766 static int sdma_set_channel_priority(struct sdma_channel *sdmac,
 767                 unsigned int priority)
 768 {
 769         struct sdma_engine *sdma = sdmac->sdma;
 770         int channel = sdmac->channel;
 771
 772         if (priority < MXC_SDMA_MIN_PRIORITY
 773             || priority > MXC_SDMA_MAX_PRIORITY) {
 774                 return -EINVAL;
 775         }
 776
 777         __raw_writel(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
 778
 779         return 0;
 780 }
 781
 782 static int sdma_request_channel(struct sdma_channel *sdmac)
 783 {
 784         struct sdma_engine *sdma = sdmac->sdma;
 785         int channel = sdmac->channel;
 786         int ret = -EBUSY;
 787
 788         sdmac->bd = dma_alloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys, GFP_KERNEL);
 789         if (!sdmac->bd) {
 790                 ret = -ENOMEM;
 791                 goto out;
 792         }
 793
 794         memset(sdmac->bd, 0, PAGE_SIZE);
 795
 796         sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys;
 797         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
 798
 799         clk_enable(sdma->clk);
 800
 801         sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY);
 802
 803         init_completion(&sdmac->done);
 804
 805         sdmac->buf_tail = 0;
 806
 807         return 0;
 808 out:
 809
 810         return ret;
 811 }
 812
 813 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
 814 {
 815         __raw_writel(1 << channel, sdma->regs + SDMA_H_START);
 816 }
 817
 818 static dma_cookie_t sdma_assign_cookie(struct sdma_channel *sdmac)
 819 {
 820         dma_cookie_t cookie = sdmac->chan.cookie;
 821
 822         if (++cookie < 0)
 823                 cookie = 1;
 824
 825         sdmac->chan.cookie = cookie;
 826         sdmac->desc.cookie = cookie;
 827
 828         return cookie;
 829 }
 830
 831 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
 832 {
 833         return container_of(chan, struct sdma_channel, chan);
 834 }
 835
 836 static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx)
 837 {
 838         unsigned long flags;
 839         struct sdma_channel *sdmac = to_sdma_chan(tx->chan);
 840         struct sdma_engine *sdma = sdmac->sdma;
 841         dma_cookie_t cookie;
 842
 843         spin_lock_irqsave(&sdmac->lock, flags);
 844
 845         cookie = sdma_assign_cookie(sdmac);
 846
 847         sdma_enable_channel(sdma, sdmac->channel);
 848
 849         spin_unlock_irqrestore(&sdmac->lock, flags);
 850
 851         return cookie;
 852 }
 853
 854 static int sdma_alloc_chan_resources(struct dma_chan *chan)
 855 {
 856         struct sdma_channel *sdmac = to_sdma_chan(chan);
 857         struct imx_dma_data *data = chan->private;
 858         int prio, ret;
 859
 860         if (!data)
 861                 return -EINVAL;
 862
 863         switch (data->priority) {
 864         case DMA_PRIO_HIGH:
 865                 prio = 3;
 866                 break;
 867         case DMA_PRIO_MEDIUM:
 868                 prio = 2;
 869                 break;
 870         case DMA_PRIO_LOW:
 871         default:
 872                 prio = 1;
 873                 break;
 874         }
 875
 876         sdmac->peripheral_type = data->peripheral_type;
 877         sdmac->event_id0 = data->dma_request;
 878         ret = sdma_set_channel_priority(sdmac, prio);
 879         if (ret)
 880                 return ret;
 881
 882         ret = sdma_request_channel(sdmac);
 883         if (ret)
 884                 return ret;
 885
 886         dma_async_tx_descriptor_init(&sdmac->desc, chan);
 887         sdmac->desc.tx_submit = sdma_tx_submit;
 888         /* txd.flags will be overwritten in prep funcs */
 889         sdmac->desc.flags = DMA_CTRL_ACK;
 890
 891         return 0;
 892 }
 893
 894 static void sdma_free_chan_resources(struct dma_chan *chan)
 895 {
 896         struct sdma_channel *sdmac = to_sdma_chan(chan);
 897         struct sdma_engine *sdma = sdmac->sdma;
 898
 899         sdma_disable_channel(sdmac);
 900
 901         if (sdmac->event_id0)
 902                 sdma_event_disable(sdmac, sdmac->event_id0);
 903         if (sdmac->event_id1)
 904                 sdma_event_disable(sdmac, sdmac->event_id1);
 905
 906         sdmac->event_id0 = 0;
 907         sdmac->event_id1 = 0;
 908
 909         sdma_set_channel_priority(sdmac, 0);
 910
 911         dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);
 912
 913         clk_disable(sdma->clk);
 914 }
 915
 916 static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
 917                 struct dma_chan *chan, struct scatterlist *sgl,
 918                 unsigned int sg_len, enum dma_transfer_direction direction,
 919                 unsigned long flags)
 920 {
 921         struct sdma_channel *sdmac = to_sdma_chan(chan);
 922         struct sdma_engine *sdma = sdmac->sdma;
 923         int ret, i, count;
 924         int channel = sdmac->channel;
 925         struct scatterlist *sg;
 926
 927         if (sdmac->status == DMA_IN_PROGRESS)
 928                 return NULL;
 929         sdmac->status = DMA_IN_PROGRESS;
 930
 931         sdmac->flags = 0;
 932
 933         dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
 934                         sg_len, channel);
 935
 936         sdmac->direction = direction;
 937         ret = sdma_load_context(sdmac);
 938         if (ret)
 939                 goto err_out;
 940
 941         if (sg_len > NUM_BD) {
 942                 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
 943                                 channel, sg_len, NUM_BD);
 944                 ret = -EINVAL;
 945                 goto err_out;
 946         }
 947
 948         sdmac->chn_count = 0;
 949         for_each_sg(sgl, sg, sg_len, i) {
 950                 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
 951                 int param;
 952
 953                 bd->buffer_addr = sg->dma_address;
 954
 955                 count = sg->length;
 956
 957                 if (count > 0xffff) {
 958                         dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
 959                                         channel, count, 0xffff);
 960                         ret = -EINVAL;
 961                         goto err_out;
 962                 }
 963
 964                 bd->mode.count = count;
 965                 sdmac->chn_count += count;
 966
 967                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) {
 968                         ret =  -EINVAL;
 969                         goto err_out;
 970                 }
 971
 972                 switch (sdmac->word_size) {
 973                 case DMA_SLAVE_BUSWIDTH_4_BYTES:
 974                         bd->mode.command = 0;
 975                         if (count & 3 || sg->dma_address & 3)
 976                                 return NULL;
 977                         break;
 978                 case DMA_SLAVE_BUSWIDTH_2_BYTES:
 979                         bd->mode.command = 2;
 980                         if (count & 1 || sg->dma_address & 1)
 981                                 return NULL;
 982                         break;
 983                 case DMA_SLAVE_BUSWIDTH_1_BYTE:
 984                         bd->mode.command = 1;
 985                         break;
 986                 default:
 987                         return NULL;
 988                 }
 989
 990                 param = BD_DONE | BD_EXTD | BD_CONT;
 991
 992                 if (i + 1 == sg_len) {
 993                         param |= BD_INTR;
 994                         param |= BD_LAST;
 995                         param &= ~BD_CONT;
 996                 }
 997
 998                 dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n",
 999                                 i, count, sg->dma_address,
1000                                 param & BD_WRAP ? "wrap" : "",
1001                                 param & BD_INTR ? " intr" : "");
1002
1003                 bd->mode.status = param;
1004         }
1005
1006         sdmac->num_bd = sg_len;
1007         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1008
1009         return &sdmac->desc;
1010 err_out:
1011         sdmac->status = DMA_ERROR;
1012         return NULL;
1013 }
1014
1015 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
1016                 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
1017                 size_t period_len, enum dma_transfer_direction direction)
1018 {
1019         struct sdma_channel *sdmac = to_sdma_chan(chan);
1020         struct sdma_engine *sdma = sdmac->sdma;
1021         int num_periods = buf_len / period_len;
1022         int channel = sdmac->channel;
1023         int ret, i = 0, buf = 0;
1024
1025         dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1026
1027         if (sdmac->status == DMA_IN_PROGRESS)
1028                 return NULL;
1029
1030         sdmac->status = DMA_IN_PROGRESS;
1031
1032         sdmac->flags |= IMX_DMA_SG_LOOP;
1033         sdmac->direction = direction;
1034         ret = sdma_load_context(sdmac);
1035         if (ret)
1036                 goto err_out;
1037
1038         if (num_periods > NUM_BD) {
1039                 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1040                                 channel, num_periods, NUM_BD);
1041                 goto err_out;
1042         }
1043
1044         if (period_len > 0xffff) {
1045                 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %d > %d\n",
1046                                 channel, period_len, 0xffff);
1047                 goto err_out;
1048         }
1049
1050         while (buf < buf_len) {
1051                 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1052                 int param;
1053
1054                 bd->buffer_addr = dma_addr;
1055
1056                 bd->mode.count = period_len;
1057
1058                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1059                         goto err_out;
1060                 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1061                         bd->mode.command = 0;
1062                 else
1063                         bd->mode.command = sdmac->word_size;
1064
1065                 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1066                 if (i + 1 == num_periods)
1067                         param |= BD_WRAP;
1068
1069                 dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n",
1070                                 i, period_len, dma_addr,
1071                                 param & BD_WRAP ? "wrap" : "",
1072                                 param & BD_INTR ? " intr" : "");
1073
1074                 bd->mode.status = param;
1075
1076                 dma_addr += period_len;
1077                 buf += period_len;
1078
1079                 i++;
1080         }
1081
1082         sdmac->num_bd = num_periods;
1083         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1084
1085         return &sdmac->desc;
1086 err_out:
1087         sdmac->status = DMA_ERROR;
1088         return NULL;
1089 }
1090
1091 static int sdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1092                 unsigned long arg)
1093 {
1094         struct sdma_channel *sdmac = to_sdma_chan(chan);
1095         struct dma_slave_config *dmaengine_cfg = (void *)arg;
1096
1097         switch (cmd) {
1098         case DMA_TERMINATE_ALL:
1099                 sdma_disable_channel(sdmac);
1100                 return 0;
1101         case DMA_SLAVE_CONFIG:
1102                 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
1103                         sdmac->per_address = dmaengine_cfg->src_addr;
1104                         sdmac->watermark_level = dmaengine_cfg->src_maxburst *
1105                                                 dmaengine_cfg->src_addr_width;
1106                         sdmac->word_size = dmaengine_cfg->src_addr_width;
1107                 } else {
1108                         sdmac->per_address = dmaengine_cfg->dst_addr;
1109                         sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
1110                                                 dmaengine_cfg->dst_addr_width;
1111                         sdmac->word_size = dmaengine_cfg->dst_addr_width;
1112                 }
1113                 sdmac->direction = dmaengine_cfg->direction;
1114                 return sdma_config_channel(sdmac);
1115         default:
1116                 return -ENOSYS;
1117         }
1118
1119         return -EINVAL;
1120 }
1121
1122 static enum dma_status sdma_tx_status(struct dma_chan *chan,
1123                                             dma_cookie_t cookie,
1124                                             struct dma_tx_state *txstate)
1125 {
1126         struct sdma_channel *sdmac = to_sdma_chan(chan);
1127         dma_cookie_t last_used;
1128
1129         last_used = chan->cookie;
1130
1131         dma_set_tx_state(txstate, sdmac->last_completed, last_used,
1132                         sdmac->chn_count - sdmac->chn_real_count);
1133
1134         return sdmac->status;
1135 }
1136
1137 static void sdma_issue_pending(struct dma_chan *chan)
1138 {
1139         /*
1140          * Nothing to do. We only have a single descriptor
1141          */
1142 }
1143
1144 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1145
1146 static void sdma_add_scripts(struct sdma_engine *sdma,
1147                 const struct sdma_script_start_addrs *addr)
1148 {
1149         s32 *addr_arr = (u32 *)addr;
1150         s32 *saddr_arr = (u32 *)sdma->script_addrs;
1151         int i;
1152
1153         for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1154                 if (addr_arr[i] > 0)
1155                         saddr_arr[i] = addr_arr[i];
1156 }
1157
1158 static void sdma_load_firmware(const struct firmware *fw, void *context)
1159 {
1160         struct sdma_engine *sdma = context;
1161         const struct sdma_firmware_header *header;
1162         const struct sdma_script_start_addrs *addr;
1163         unsigned short *ram_code;
1164
1165         if (!fw) {
1166                 dev_err(sdma->dev, "firmware not found\n");
1167                 return;
1168         }
1169
1170         if (fw->size < sizeof(*header))
1171                 goto err_firmware;
1172
1173         header = (struct sdma_firmware_header *)fw->data;
1174
1175         if (header->magic != SDMA_FIRMWARE_MAGIC)
1176                 goto err_firmware;
1177         if (header->ram_code_start + header->ram_code_size > fw->size)
1178                 goto err_firmware;
1179
1180         addr = (void *)header + header->script_addrs_start;
1181         ram_code = (void *)header + header->ram_code_start;
1182
1183         clk_enable(sdma->clk);
1184         /* download the RAM image for SDMA */
1185         sdma_load_script(sdma, ram_code,
1186                         header->ram_code_size,
1187                         addr->ram_code_start_addr);
1188         clk_disable(sdma->clk);
1189
1190         sdma_add_scripts(sdma, addr);
1191
1192         dev_info(sdma->dev, "loaded firmware %d.%d\n",
1193                         header->version_major,
1194                         header->version_minor);
1195
1196 err_firmware:
1197         release_firmware(fw);
1198 }
1199
1200 static int __init sdma_get_firmware(struct sdma_engine *sdma,
1201                 const char *fw_name)
1202 {
1203         int ret;
1204
1205         ret = request_firmware_nowait(THIS_MODULE,
1206                         FW_ACTION_HOTPLUG, fw_name, sdma->dev,
1207                         GFP_KERNEL, sdma, sdma_load_firmware);
1208
1209         return ret;
1210 }
1211
1212 static int __init sdma_init(struct sdma_engine *sdma)
1213 {
1214         int i, ret;
1215         dma_addr_t ccb_phys;
1216
1217         switch (sdma->devtype) {
1218         case IMX31_SDMA:
1219                 sdma->num_events = 32;
1220                 break;
1221         case IMX35_SDMA:
1222                 sdma->num_events = 48;
1223                 break;
1224         default:
1225                 dev_err(sdma->dev, "Unknown sdma type %d. aborting\n",
1226                         sdma->devtype);
1227                 return -ENODEV;
1228         }
1229
1230         clk_enable(sdma->clk);
1231
1232         /* Be sure SDMA has not started yet */
1233         __raw_writel(0, sdma->regs + SDMA_H_C0PTR);
1234
1235         sdma->channel_control = dma_alloc_coherent(NULL,
1236                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
1237                         sizeof(struct sdma_context_data),
1238                         &ccb_phys, GFP_KERNEL);
1239
1240         if (!sdma->channel_control) {
1241                 ret = -ENOMEM;
1242                 goto err_dma_alloc;
1243         }
1244
1245         sdma->context = (void *)sdma->channel_control +
1246                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1247         sdma->context_phys = ccb_phys +
1248                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1249
1250         /* Zero-out the CCB structures array just allocated */
1251         memset(sdma->channel_control, 0,
1252                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control));
1253
1254         /* disable all channels */
1255         for (i = 0; i < sdma->num_events; i++)
1256                 __raw_writel(0, sdma->regs + chnenbl_ofs(sdma, i));
1257
1258         /* All channels have priority 0 */
1259         for (i = 0; i < MAX_DMA_CHANNELS; i++)
1260                 __raw_writel(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1261
1262         ret = sdma_request_channel(&sdma->channel[0]);
1263         if (ret)
1264                 goto err_dma_alloc;
1265
1266         sdma_config_ownership(&sdma->channel[0], false, true, false);
1267
1268         /* Set Command Channel (Channel Zero) */
1269         __raw_writel(0x4050, sdma->regs + SDMA_CHN0ADDR);
1270
1271         /* Set bits of CONFIG register but with static context switching */
1272         /* FIXME: Check whether to set ACR bit depending on clock ratios */
1273         __raw_writel(0, sdma->regs + SDMA_H_CONFIG);
1274
1275         __raw_writel(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1276
1277         /* Set bits of CONFIG register with given context switching mode */
1278         __raw_writel(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
1279
1280         /* Initializes channel's priorities */
1281         sdma_set_channel_priority(&sdma->channel[0], 7);
1282
1283         clk_disable(sdma->clk);
1284
1285         return 0;
1286
1287 err_dma_alloc:
1288         clk_disable(sdma->clk);
1289         dev_err(sdma->dev, "initialisation failed with %d\n", ret);
1290         return ret;
1291 }
1292
1293 static int __init sdma_probe(struct platform_device *pdev)
1294 {
1295         const struct of_device_id *of_id =
1296                         of_match_device(sdma_dt_ids, &pdev->dev);
1297         struct device_node *np = pdev->dev.of_node;
1298         const char *fw_name;
1299         int ret;
1300         int irq;
1301         struct resource *iores;
1302         struct sdma_platform_data *pdata = pdev->dev.platform_data;
1303         int i;
1304         struct sdma_engine *sdma;
1305         s32 *saddr_arr;
1306
1307         sdma = kzalloc(sizeof(*sdma), GFP_KERNEL);
1308         if (!sdma)
1309                 return -ENOMEM;
1310
1311         mutex_init(&sdma->channel_0_lock);
1312
1313         sdma->dev = &pdev->dev;
1314
1315         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1316         irq = platform_get_irq(pdev, 0);
1317         if (!iores || irq < 0) {
1318                 ret = -EINVAL;
1319                 goto err_irq;
1320         }
1321
1322         if (!request_mem_region(iores->start, resource_size(iores), pdev->name)) {
1323                 ret = -EBUSY;
1324                 goto err_request_region;
1325         }
1326
1327         sdma->clk = clk_get(&pdev->dev, NULL);
1328         if (IS_ERR(sdma->clk)) {
1329                 ret = PTR_ERR(sdma->clk);
1330                 goto err_clk;
1331         }
1332
1333         sdma->regs = ioremap(iores->start, resource_size(iores));
1334         if (!sdma->regs) {
1335                 ret = -ENOMEM;
1336                 goto err_ioremap;
1337         }
1338
1339         ret = request_irq(irq, sdma_int_handler, 0, "sdma", sdma);
1340         if (ret)
1341                 goto err_request_irq;
1342
1343         sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
1344         if (!sdma->script_addrs) {
1345                 ret = -ENOMEM;
1346                 goto err_alloc;
1347         }
1348
1349         /* initially no scripts available */
1350         saddr_arr = (s32 *)sdma->script_addrs;
1351         for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1352                 saddr_arr[i] = -EINVAL;
1353
1354         if (of_id)
1355                 pdev->id_entry = of_id->data;
1356         sdma->devtype = pdev->id_entry->driver_data;
1357
1358         dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
1359         dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
1360
1361         INIT_LIST_HEAD(&sdma->dma_device.channels);
1362         /* Initialize channel parameters */
1363         for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1364                 struct sdma_channel *sdmac = &sdma->channel[i];
1365
1366                 sdmac->sdma = sdma;
1367                 spin_lock_init(&sdmac->lock);
1368
1369                 sdmac->chan.device = &sdma->dma_device;
1370                 sdmac->channel = i;
1371
1372                 /*
1373                  * Add the channel to the DMAC list. Do not add channel 0 though
1374                  * because we need it internally in the SDMA driver. This also means
1375                  * that channel 0 in dmaengine counting matches sdma channel 1.
1376                  */
1377                 if (i)
1378                         list_add_tail(&sdmac->chan.device_node,
1379                                         &sdma->dma_device.channels);
1380         }
1381
1382         ret = sdma_init(sdma);
1383         if (ret)
1384                 goto err_init;
1385
1386         if (pdata && pdata->script_addrs)
1387                 sdma_add_scripts(sdma, pdata->script_addrs);
1388
1389         if (pdata) {
1390                 sdma_get_firmware(sdma, pdata->fw_name);
1391         } else {
1392                 /*
1393                  * Because that device tree does not encode ROM script address,
1394                  * the RAM script in firmware is mandatory for device tree
1395                  * probe, otherwise it fails.
1396                  */
1397                 ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
1398                                               &fw_name);
1399                 if (ret) {
1400                         dev_err(&pdev->dev, "failed to get firmware name\n");
1401                         goto err_init;
1402                 }
1403
1404                 ret = sdma_get_firmware(sdma, fw_name);
1405                 if (ret) {
1406                         dev_err(&pdev->dev, "failed to get firmware\n");
1407                         goto err_init;
1408                 }
1409         }
1410
1411         sdma->dma_device.dev = &pdev->dev;
1412
1413         sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
1414         sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
1415         sdma->dma_device.device_tx_status = sdma_tx_status;
1416         sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
1417         sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
1418         sdma->dma_device.device_control = sdma_control;
1419         sdma->dma_device.device_issue_pending = sdma_issue_pending;
1420         sdma->dma_device.dev->dma_parms = &sdma->dma_parms;
1421         dma_set_max_seg_size(sdma->dma_device.dev, 65535);
1422
1423         ret = dma_async_device_register(&sdma->dma_device);
1424         if (ret) {
1425                 dev_err(&pdev->dev, "unable to register\n");
1426                 goto err_init;
1427         }
1428
1429         dev_info(sdma->dev, "initialized\n");
1430
1431         return 0;
1432
1433 err_init:
1434         kfree(sdma->script_addrs);
1435 err_alloc:
1436         free_irq(irq, sdma);
1437 err_request_irq:
1438         iounmap(sdma->regs);
1439 err_ioremap:
1440         clk_put(sdma->clk);
1441 err_clk:
1442         release_mem_region(iores->start, resource_size(iores));
1443 err_request_region:
1444 err_irq:
1445         kfree(sdma);
1446         return ret;
1447 }
1448
1449 static int __exit sdma_remove(struct platform_device *pdev)
1450 {
1451         return -EBUSY;
1452 }
1453
1454 static struct platform_driver sdma_driver = {
1455         .driver         = {
1456                 .name   = "imx-sdma",
1457                 .of_match_table = sdma_dt_ids,
1458         },
1459         .id_table       = sdma_devtypes,
1460         .remove         = __exit_p(sdma_remove),
1461 };
1462
1463 static int __init sdma_module_init(void)
1464 {
1465         return platform_driver_probe(&sdma_driver, sdma_probe);
1466 }
1467 module_init(sdma_module_init);
1468
1469 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1470 MODULE_DESCRIPTION("i.MX SDMA driver");
1471 MODULE_LICENSE("GPL");