2 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in the
15 * file called COPYING.
20 /* PCI Configuration Space Values */
21 #define IOAT_MMIO_BAR 0
24 #define PCI_DEVICE_ID_INTEL_IOAT_IVB0 0x0e20
25 #define PCI_DEVICE_ID_INTEL_IOAT_IVB1 0x0e21
26 #define PCI_DEVICE_ID_INTEL_IOAT_IVB2 0x0e22
27 #define PCI_DEVICE_ID_INTEL_IOAT_IVB3 0x0e23
28 #define PCI_DEVICE_ID_INTEL_IOAT_IVB4 0x0e24
29 #define PCI_DEVICE_ID_INTEL_IOAT_IVB5 0x0e25
30 #define PCI_DEVICE_ID_INTEL_IOAT_IVB6 0x0e26
31 #define PCI_DEVICE_ID_INTEL_IOAT_IVB7 0x0e27
32 #define PCI_DEVICE_ID_INTEL_IOAT_IVB8 0x0e2e
33 #define PCI_DEVICE_ID_INTEL_IOAT_IVB9 0x0e2f
35 #define PCI_DEVICE_ID_INTEL_IOAT_HSW0 0x2f20
36 #define PCI_DEVICE_ID_INTEL_IOAT_HSW1 0x2f21
37 #define PCI_DEVICE_ID_INTEL_IOAT_HSW2 0x2f22
38 #define PCI_DEVICE_ID_INTEL_IOAT_HSW3 0x2f23
39 #define PCI_DEVICE_ID_INTEL_IOAT_HSW4 0x2f24
40 #define PCI_DEVICE_ID_INTEL_IOAT_HSW5 0x2f25
41 #define PCI_DEVICE_ID_INTEL_IOAT_HSW6 0x2f26
42 #define PCI_DEVICE_ID_INTEL_IOAT_HSW7 0x2f27
43 #define PCI_DEVICE_ID_INTEL_IOAT_HSW8 0x2f2e
44 #define PCI_DEVICE_ID_INTEL_IOAT_HSW9 0x2f2f
46 #define PCI_DEVICE_ID_INTEL_IOAT_BWD0 0x0C50
47 #define PCI_DEVICE_ID_INTEL_IOAT_BWD1 0x0C51
48 #define PCI_DEVICE_ID_INTEL_IOAT_BWD2 0x0C52
49 #define PCI_DEVICE_ID_INTEL_IOAT_BWD3 0x0C53
51 #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE0 0x6f50
52 #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE1 0x6f51
53 #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE2 0x6f52
54 #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE3 0x6f53
56 #define IOAT_VER_1_2 0x12 /* Version 1.2 */
57 #define IOAT_VER_2_0 0x20 /* Version 2.0 */
58 #define IOAT_VER_3_0 0x30 /* Version 3.0 */
59 #define IOAT_VER_3_2 0x32 /* Version 3.2 */
60 #define IOAT_VER_3_3 0x33 /* Version 3.3 */
63 int system_has_dca_enabled(struct pci_dev *pdev);
65 struct ioat_dma_descriptor {
70 unsigned int int_en:1;
71 unsigned int src_snoop_dis:1;
72 unsigned int dest_snoop_dis:1;
73 unsigned int compl_write:1;
76 unsigned int src_brk:1;
77 unsigned int dest_brk:1;
78 unsigned int bundle:1;
79 unsigned int dest_dca:1;
81 unsigned int rsvd2:13;
82 #define IOAT_OP_COPY 0x00
91 /* store some driver data in an unused portion of the descriptor */
99 struct ioat_xor_descriptor {
104 unsigned int int_en:1;
105 unsigned int src_snoop_dis:1;
106 unsigned int dest_snoop_dis:1;
107 unsigned int compl_write:1;
108 unsigned int fence:1;
109 unsigned int src_cnt:3;
110 unsigned int bundle:1;
111 unsigned int dest_dca:1;
113 unsigned int rsvd:13;
114 #define IOAT_OP_XOR 0x87
115 #define IOAT_OP_XOR_VAL 0x88
128 struct ioat_xor_ext_descriptor {
136 struct ioat_pq_descriptor {
141 unsigned int rsvd:25;
142 unsigned int p_val_err:1;
143 unsigned int q_val_err:1;
144 unsigned int rsvd1:4;
151 unsigned int int_en:1;
152 unsigned int src_snoop_dis:1;
153 unsigned int dest_snoop_dis:1;
154 unsigned int compl_write:1;
155 unsigned int fence:1;
156 unsigned int src_cnt:3;
157 unsigned int bundle:1;
158 unsigned int dest_dca:1;
160 unsigned int p_disable:1;
161 unsigned int q_disable:1;
162 unsigned int rsvd2:2;
163 unsigned int wb_en:1;
164 unsigned int prl_en:1;
165 unsigned int rsvd3:7;
166 #define IOAT_OP_PQ 0x89
167 #define IOAT_OP_PQ_VAL 0x8a
168 #define IOAT_OP_PQ_16S 0xa0
169 #define IOAT_OP_PQ_VAL_16S 0xa1
185 struct ioat_pq_ext_descriptor {
195 struct ioat_pq_update_descriptor {
200 unsigned int int_en:1;
201 unsigned int src_snoop_dis:1;
202 unsigned int dest_snoop_dis:1;
203 unsigned int compl_write:1;
204 unsigned int fence:1;
205 unsigned int src_cnt:3;
206 unsigned int bundle:1;
207 unsigned int dest_dca:1;
209 unsigned int p_disable:1;
210 unsigned int q_disable:1;
213 #define IOAT_OP_PQ_UP 0x8b
226 struct ioat_raw_descriptor {
230 struct ioat_pq16a_descriptor {
241 struct ioat_pq16b_descriptor {
252 union ioat_sed_pq_descriptor {
253 struct ioat_pq16a_descriptor a;
254 struct ioat_pq16b_descriptor b;
259 struct ioat_sed_raw_descriptor {