drivers/dma/pl330.c

   1 /* linux/drivers/dma/pl330.c
   2  *
   3  * Copyright (C) 2010 Samsung Electronics Co. Ltd.
   4  *      Jaswinder Singh <jassi.brar@samsung.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11
  12 #include <linux/io.h>
  13 #include <linux/init.h>
  14 #include <linux/slab.h>
  15 #include <linux/module.h>
  16 #include <linux/dmaengine.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/amba/bus.h>
  19 #include <linux/amba/pl330.h>
  20 #include <linux/pm_runtime.h>
  21 #include <linux/scatterlist.h>
  22 #include <linux/of.h>
  23
  24 #include "dmaengine.h"
  25
  26 #define NR_DEFAULT_DESC 16
  27
  28 enum desc_status {
  29         /* In the DMAC pool */
  30         FREE,
  31         /*
  32          * Allocted to some channel during prep_xxx
  33          * Also may be sitting on the work_list.
  34          */
  35         PREP,
  36         /*
  37          * Sitting on the work_list and already submitted
  38          * to the PL330 core. Not more than two descriptors
  39          * of a channel can be BUSY at any time.
  40          */
  41         BUSY,
  42         /*
  43          * Sitting on the channel work_list but xfer done
  44          * by PL330 core
  45          */
  46         DONE,
  47 };
  48
  49 struct dma_pl330_chan {
  50         /* Schedule desc completion */
  51         struct tasklet_struct task;
  52
  53         /* DMA-Engine Channel */
  54         struct dma_chan chan;
  55
  56         /* List of to be xfered descriptors */
  57         struct list_head work_list;
  58
  59         /* Pointer to the DMAC that manages this channel,
  60          * NULL if the channel is available to be acquired.
  61          * As the parent, this DMAC also provides descriptors
  62          * to the channel.
  63          */
  64         struct dma_pl330_dmac *dmac;
  65
  66         /* To protect channel manipulation */
  67         spinlock_t lock;
  68
  69         /* Token of a hardware channel thread of PL330 DMAC
  70          * NULL if the channel is available to be acquired.
  71          */
  72         void *pl330_chid;
  73
  74         /* For D-to-M and M-to-D channels */
  75         int burst_sz; /* the peripheral fifo width */
  76         int burst_len; /* the number of burst */
  77         dma_addr_t fifo_addr;
  78
  79         /* for cyclic capability */
  80         bool cyclic;
  81 };
  82
  83 struct dma_pl330_dmac {
  84         struct pl330_info pif;
  85
  86         /* DMA-Engine Device */
  87         struct dma_device ddma;
  88
  89         /* Pool of descriptors available for the DMAC's channels */
  90         struct list_head desc_pool;
  91         /* To protect desc_pool manipulation */
  92         spinlock_t pool_lock;
  93
  94         /* Peripheral channels connected to this DMAC */
  95         struct dma_pl330_chan *peripherals; /* keep at end */
  96
  97         struct clk *clk;
  98 };
  99
 100 struct dma_pl330_desc {
 101         /* To attach to a queue as child */
 102         struct list_head node;
 103
 104         /* Descriptor for the DMA Engine API */
 105         struct dma_async_tx_descriptor txd;
 106
 107         /* Xfer for PL330 core */
 108         struct pl330_xfer px;
 109
 110         struct pl330_reqcfg rqcfg;
 111         struct pl330_req req;
 112
 113         enum desc_status status;
 114
 115         /* The channel which currently holds this desc */
 116         struct dma_pl330_chan *pchan;
 117 };
 118
 119 /* forward declaration */
 120 static struct amba_driver pl330_driver;
 121
 122 static inline struct dma_pl330_chan *
 123 to_pchan(struct dma_chan *ch)
 124 {
 125         if (!ch)
 126                 return NULL;
 127
 128         return container_of(ch, struct dma_pl330_chan, chan);
 129 }
 130
 131 static inline struct dma_pl330_desc *
 132 to_desc(struct dma_async_tx_descriptor *tx)
 133 {
 134         return container_of(tx, struct dma_pl330_desc, txd);
 135 }
 136
 137 static inline void free_desc_list(struct list_head *list)
 138 {
 139         struct dma_pl330_dmac *pdmac;
 140         struct dma_pl330_desc *desc;
 141         struct dma_pl330_chan *pch;
 142         unsigned long flags;
 143
 144         if (list_empty(list))
 145                 return;
 146
 147         /* Finish off the work list */
 148         list_for_each_entry(desc, list, node) {
 149                 dma_async_tx_callback callback;
 150                 void *param;
 151
 152                 /* All desc in a list belong to same channel */
 153                 pch = desc->pchan;
 154                 callback = desc->txd.callback;
 155                 param = desc->txd.callback_param;
 156
 157                 if (callback)
 158                         callback(param);
 159
 160                 desc->pchan = NULL;
 161         }
 162
 163         pdmac = pch->dmac;
 164
 165         spin_lock_irqsave(&pdmac->pool_lock, flags);
 166         list_splice_tail_init(list, &pdmac->desc_pool);
 167         spin_unlock_irqrestore(&pdmac->pool_lock, flags);
 168 }
 169
 170 static inline void handle_cyclic_desc_list(struct list_head *list)
 171 {
 172         struct dma_pl330_desc *desc;
 173         struct dma_pl330_chan *pch;
 174         unsigned long flags;
 175
 176         if (list_empty(list))
 177                 return;
 178
 179         list_for_each_entry(desc, list, node) {
 180                 dma_async_tx_callback callback;
 181
 182                 /* Change status to reload it */
 183                 desc->status = PREP;
 184                 pch = desc->pchan;
 185                 callback = desc->txd.callback;
 186                 if (callback)
 187                         callback(desc->txd.callback_param);
 188         }
 189
 190         spin_lock_irqsave(&pch->lock, flags);
 191         list_splice_tail_init(list, &pch->work_list);
 192         spin_unlock_irqrestore(&pch->lock, flags);
 193 }
 194
 195 static inline void fill_queue(struct dma_pl330_chan *pch)
 196 {
 197         struct dma_pl330_desc *desc;
 198         int ret;
 199
 200         list_for_each_entry(desc, &pch->work_list, node) {
 201
 202                 /* If already submitted */
 203                 if (desc->status == BUSY)
 204                         break;
 205
 206                 ret = pl330_submit_req(pch->pl330_chid,
 207                                                 &desc->req);
 208                 if (!ret) {
 209                         desc->status = BUSY;
 210                         break;
 211                 } else if (ret == -EAGAIN) {
 212                         /* QFull or DMAC Dying */
 213                         break;
 214                 } else {
 215                         /* Unacceptable request */
 216                         desc->status = DONE;
 217                         dev_err(pch->dmac->pif.dev, "%s:%d Bad Desc(%d)\n",
 218                                         __func__, __LINE__, desc->txd.cookie);
 219                         tasklet_schedule(&pch->task);
 220                 }
 221         }
 222 }
 223
 224 static void pl330_tasklet(unsigned long data)
 225 {
 226         struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data;
 227         struct dma_pl330_desc *desc, *_dt;
 228         unsigned long flags;
 229         LIST_HEAD(list);
 230
 231         spin_lock_irqsave(&pch->lock, flags);
 232
 233         /* Pick up ripe tomatoes */
 234         list_for_each_entry_safe(desc, _dt, &pch->work_list, node)
 235                 if (desc->status == DONE) {
 236                         dma_cookie_complete(&desc->txd);
 237                         list_move_tail(&desc->node, &list);
 238                 }
 239
 240         /* Try to submit a req imm. next to the last completed cookie */
 241         fill_queue(pch);
 242
 243         /* Make sure the PL330 Channel thread is active */
 244         pl330_chan_ctrl(pch->pl330_chid, PL330_OP_START);
 245
 246         spin_unlock_irqrestore(&pch->lock, flags);
 247
 248         if (pch->cyclic)
 249                 handle_cyclic_desc_list(&list);
 250         else
 251                 free_desc_list(&list);
 252 }
 253
 254 static void dma_pl330_rqcb(void *token, enum pl330_op_err err)
 255 {
 256         struct dma_pl330_desc *desc = token;
 257         struct dma_pl330_chan *pch = desc->pchan;
 258         unsigned long flags;
 259
 260         /* If desc aborted */
 261         if (!pch)
 262                 return;
 263
 264         spin_lock_irqsave(&pch->lock, flags);
 265
 266         desc->status = DONE;
 267
 268         spin_unlock_irqrestore(&pch->lock, flags);
 269
 270         tasklet_schedule(&pch->task);
 271 }
 272
 273 bool pl330_filter(struct dma_chan *chan, void *param)
 274 {
 275         u8 *peri_id;
 276
 277         if (chan->device->dev->driver != &pl330_driver.drv)
 278                 return false;
 279
 280 #ifdef CONFIG_OF
 281         if (chan->device->dev->of_node) {
 282                 const __be32 *prop_value;
 283                 phandle phandle;
 284                 struct device_node *node;
 285
 286                 prop_value = ((struct property *)param)->value;
 287                 phandle = be32_to_cpup(prop_value++);
 288                 node = of_find_node_by_phandle(phandle);
 289                 return ((chan->private == node) &&
 290                                 (chan->chan_id == be32_to_cpup(prop_value)));
 291         }
 292 #endif
 293
 294         peri_id = chan->private;
 295         return *peri_id == (unsigned)param;
 296 }
 297 EXPORT_SYMBOL(pl330_filter);
 298
 299 static int pl330_alloc_chan_resources(struct dma_chan *chan)
 300 {
 301         struct dma_pl330_chan *pch = to_pchan(chan);
 302         struct dma_pl330_dmac *pdmac = pch->dmac;
 303         unsigned long flags;
 304
 305         spin_lock_irqsave(&pch->lock, flags);
 306
 307         dma_cookie_init(chan);
 308         pch->cyclic = false;
 309
 310         pch->pl330_chid = pl330_request_channel(&pdmac->pif);
 311         if (!pch->pl330_chid) {
 312                 spin_unlock_irqrestore(&pch->lock, flags);
 313                 return 0;
 314         }
 315
 316         tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch);
 317
 318         spin_unlock_irqrestore(&pch->lock, flags);
 319
 320         return 1;
 321 }
 322
 323 static int pl330_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, unsigned long arg)
 324 {
 325         struct dma_pl330_chan *pch = to_pchan(chan);
 326         struct dma_pl330_desc *desc, *_dt;
 327         unsigned long flags;
 328         struct dma_pl330_dmac *pdmac = pch->dmac;
 329         struct dma_slave_config *slave_config;
 330         LIST_HEAD(list);
 331
 332         switch (cmd) {
 333         case DMA_TERMINATE_ALL:
 334                 spin_lock_irqsave(&pch->lock, flags);
 335
 336                 /* FLUSH the PL330 Channel thread */
 337                 pl330_chan_ctrl(pch->pl330_chid, PL330_OP_FLUSH);
 338
 339                 /* Mark all desc done */
 340                 list_for_each_entry_safe(desc, _dt, &pch->work_list , node) {
 341                         desc->status = DONE;
 342                         list_move_tail(&desc->node, &list);
 343                 }
 344
 345                 list_splice_tail_init(&list, &pdmac->desc_pool);
 346                 spin_unlock_irqrestore(&pch->lock, flags);
 347                 break;
 348         case DMA_SLAVE_CONFIG:
 349                 slave_config = (struct dma_slave_config *)arg;
 350
 351                 if (slave_config->direction == DMA_MEM_TO_DEV) {
 352                         if (slave_config->dst_addr)
 353                                 pch->fifo_addr = slave_config->dst_addr;
 354                         if (slave_config->dst_addr_width)
 355                                 pch->burst_sz = __ffs(slave_config->dst_addr_width);
 356                         if (slave_config->dst_maxburst)
 357                                 pch->burst_len = slave_config->dst_maxburst;
 358                 } else if (slave_config->direction == DMA_DEV_TO_MEM) {
 359                         if (slave_config->src_addr)
 360                                 pch->fifo_addr = slave_config->src_addr;
 361                         if (slave_config->src_addr_width)
 362                                 pch->burst_sz = __ffs(slave_config->src_addr_width);
 363                         if (slave_config->src_maxburst)
 364                                 pch->burst_len = slave_config->src_maxburst;
 365                 }
 366                 break;
 367         default:
 368                 dev_err(pch->dmac->pif.dev, "Not supported command.\n");
 369                 return -ENXIO;
 370         }
 371
 372         return 0;
 373 }
 374
 375 static void pl330_free_chan_resources(struct dma_chan *chan)
 376 {
 377         struct dma_pl330_chan *pch = to_pchan(chan);
 378         unsigned long flags;
 379
 380         spin_lock_irqsave(&pch->lock, flags);
 381
 382         tasklet_kill(&pch->task);
 383
 384         pl330_release_channel(pch->pl330_chid);
 385         pch->pl330_chid = NULL;
 386
 387         if (pch->cyclic)
 388                 list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool);
 389
 390         spin_unlock_irqrestore(&pch->lock, flags);
 391 }
 392
 393 static enum dma_status
 394 pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 395                  struct dma_tx_state *txstate)
 396 {
 397         return dma_cookie_status(chan, cookie, txstate);
 398 }
 399
 400 static void pl330_issue_pending(struct dma_chan *chan)
 401 {
 402         pl330_tasklet((unsigned long) to_pchan(chan));
 403 }
 404
 405 /*
 406  * We returned the last one of the circular list of descriptor(s)
 407  * from prep_xxx, so the argument to submit corresponds to the last
 408  * descriptor of the list.
 409  */
 410 static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx)
 411 {
 412         struct dma_pl330_desc *desc, *last = to_desc(tx);
 413         struct dma_pl330_chan *pch = to_pchan(tx->chan);
 414         dma_cookie_t cookie;
 415         unsigned long flags;
 416
 417         spin_lock_irqsave(&pch->lock, flags);
 418
 419         /* Assign cookies to all nodes */
 420         while (!list_empty(&last->node)) {
 421                 desc = list_entry(last->node.next, struct dma_pl330_desc, node);
 422
 423                 dma_cookie_assign(&desc->txd);
 424
 425                 list_move_tail(&desc->node, &pch->work_list);
 426         }
 427
 428         cookie = dma_cookie_assign(&last->txd);
 429         list_add_tail(&last->node, &pch->work_list);
 430         spin_unlock_irqrestore(&pch->lock, flags);
 431
 432         return cookie;
 433 }
 434
 435 static inline void _init_desc(struct dma_pl330_desc *desc)
 436 {
 437         desc->pchan = NULL;
 438         desc->req.x = &desc->px;
 439         desc->req.token = desc;
 440         desc->rqcfg.swap = SWAP_NO;
 441         desc->rqcfg.privileged = 0;
 442         desc->rqcfg.insnaccess = 0;
 443         desc->rqcfg.scctl = SCCTRL0;
 444         desc->rqcfg.dcctl = DCCTRL0;
 445         desc->req.cfg = &desc->rqcfg;
 446         desc->req.xfer_cb = dma_pl330_rqcb;
 447         desc->txd.tx_submit = pl330_tx_submit;
 448
 449         INIT_LIST_HEAD(&desc->node);
 450 }
 451
 452 /* Returns the number of descriptors added to the DMAC pool */
 453 int add_desc(struct dma_pl330_dmac *pdmac, gfp_t flg, int count)
 454 {
 455         struct dma_pl330_desc *desc;
 456         unsigned long flags;
 457         int i;
 458
 459         if (!pdmac)
 460                 return 0;
 461
 462         desc = kmalloc(count * sizeof(*desc), flg);
 463         if (!desc)
 464                 return 0;
 465
 466         spin_lock_irqsave(&pdmac->pool_lock, flags);
 467
 468         for (i = 0; i < count; i++) {
 469                 _init_desc(&desc[i]);
 470                 list_add_tail(&desc[i].node, &pdmac->desc_pool);
 471         }
 472
 473         spin_unlock_irqrestore(&pdmac->pool_lock, flags);
 474
 475         return count;
 476 }
 477
 478 static struct dma_pl330_desc *
 479 pluck_desc(struct dma_pl330_dmac *pdmac)
 480 {
 481         struct dma_pl330_desc *desc = NULL;
 482         unsigned long flags;
 483
 484         if (!pdmac)
 485                 return NULL;
 486
 487         spin_lock_irqsave(&pdmac->pool_lock, flags);
 488
 489         if (!list_empty(&pdmac->desc_pool)) {
 490                 desc = list_entry(pdmac->desc_pool.next,
 491                                 struct dma_pl330_desc, node);
 492
 493                 list_del_init(&desc->node);
 494
 495                 desc->status = PREP;
 496                 desc->txd.callback = NULL;
 497         }
 498
 499         spin_unlock_irqrestore(&pdmac->pool_lock, flags);
 500
 501         return desc;
 502 }
 503
 504 static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch)
 505 {
 506         struct dma_pl330_dmac *pdmac = pch->dmac;
 507         u8 *peri_id = pch->chan.private;
 508         struct dma_pl330_desc *desc;
 509
 510         /* Pluck one desc from the pool of DMAC */
 511         desc = pluck_desc(pdmac);
 512
 513         /* If the DMAC pool is empty, alloc new */
 514         if (!desc) {
 515                 if (!add_desc(pdmac, GFP_ATOMIC, 1))
 516                         return NULL;
 517
 518                 /* Try again */
 519                 desc = pluck_desc(pdmac);
 520                 if (!desc) {
 521                         dev_err(pch->dmac->pif.dev,
 522                                 "%s:%d ALERT!\n", __func__, __LINE__);
 523                         return NULL;
 524                 }
 525         }
 526
 527         /* Initialize the descriptor */
 528         desc->pchan = pch;
 529         desc->txd.cookie = 0;
 530         async_tx_ack(&desc->txd);
 531
 532         desc->req.peri = peri_id ? pch->chan.chan_id : 0;
 533
 534         dma_async_tx_descriptor_init(&desc->txd, &pch->chan);
 535
 536         return desc;
 537 }
 538
 539 static inline void fill_px(struct pl330_xfer *px,
 540                 dma_addr_t dst, dma_addr_t src, size_t len)
 541 {
 542         px->next = NULL;
 543         px->bytes = len;
 544         px->dst_addr = dst;
 545         px->src_addr = src;
 546 }
 547
 548 static struct dma_pl330_desc *
 549 __pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst,
 550                 dma_addr_t src, size_t len)
 551 {
 552         struct dma_pl330_desc *desc = pl330_get_desc(pch);
 553
 554         if (!desc) {
 555                 dev_err(pch->dmac->pif.dev, "%s:%d Unable to fetch desc\n",
 556                         __func__, __LINE__);
 557                 return NULL;
 558         }
 559
 560         /*
 561          * Ideally we should lookout for reqs bigger than
 562          * those that can be programmed with 256 bytes of
 563          * MC buffer, but considering a req size is seldom
 564          * going to be word-unaligned and more than 200MB,
 565          * we take it easy.
 566          * Also, should the limit is reached we'd rather
 567          * have the platform increase MC buffer size than
 568          * complicating this API driver.
 569          */
 570         fill_px(&desc->px, dst, src, len);
 571
 572         return desc;
 573 }
 574
 575 /* Call after fixing burst size */
 576 static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len)
 577 {
 578         struct dma_pl330_chan *pch = desc->pchan;
 579         struct pl330_info *pi = &pch->dmac->pif;
 580         int burst_len;
 581
 582         burst_len = pi->pcfg.data_bus_width / 8;
 583         burst_len *= pi->pcfg.data_buf_dep;
 584         burst_len >>= desc->rqcfg.brst_size;
 585
 586         /* src/dst_burst_len can't be more than 16 */
 587         if (burst_len > 16)
 588                 burst_len = 16;
 589
 590         while (burst_len > 1) {
 591                 if (!(len % (burst_len << desc->rqcfg.brst_size)))
 592                         break;
 593                 burst_len--;
 594         }
 595
 596         return burst_len;
 597 }
 598
 599 static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
 600                 struct dma_chan *chan, dma_addr_t dma_addr, size_t len,
 601                 size_t period_len, enum dma_transfer_direction direction)
 602 {
 603         struct dma_pl330_desc *desc;
 604         struct dma_pl330_chan *pch = to_pchan(chan);
 605         dma_addr_t dst;
 606         dma_addr_t src;
 607
 608         desc = pl330_get_desc(pch);
 609         if (!desc) {
 610                 dev_err(pch->dmac->pif.dev, "%s:%d Unable to fetch desc\n",
 611                         __func__, __LINE__);
 612                 return NULL;
 613         }
 614
 615         switch (direction) {
 616         case DMA_MEM_TO_DEV:
 617                 desc->rqcfg.src_inc = 1;
 618                 desc->rqcfg.dst_inc = 0;
 619                 desc->req.rqtype = MEMTODEV;
 620                 src = dma_addr;
 621                 dst = pch->fifo_addr;
 622                 break;
 623         case DMA_DEV_TO_MEM:
 624                 desc->rqcfg.src_inc = 0;
 625                 desc->rqcfg.dst_inc = 1;
 626                 desc->req.rqtype = DEVTOMEM;
 627                 src = pch->fifo_addr;
 628                 dst = dma_addr;
 629                 break;
 630         default:
 631                 dev_err(pch->dmac->pif.dev, "%s:%d Invalid dma direction\n",
 632                 __func__, __LINE__);
 633                 return NULL;
 634         }
 635
 636         desc->rqcfg.brst_size = pch->burst_sz;
 637         desc->rqcfg.brst_len = 1;
 638
 639         pch->cyclic = true;
 640
 641         fill_px(&desc->px, dst, src, period_len);
 642
 643         return &desc->txd;
 644 }
 645
 646 static struct dma_async_tx_descriptor *
 647 pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
 648                 dma_addr_t src, size_t len, unsigned long flags)
 649 {
 650         struct dma_pl330_desc *desc;
 651         struct dma_pl330_chan *pch = to_pchan(chan);
 652         struct pl330_info *pi;
 653         int burst;
 654
 655         if (unlikely(!pch || !len))
 656                 return NULL;
 657
 658         pi = &pch->dmac->pif;
 659
 660         desc = __pl330_prep_dma_memcpy(pch, dst, src, len);
 661         if (!desc)
 662                 return NULL;
 663
 664         desc->rqcfg.src_inc = 1;
 665         desc->rqcfg.dst_inc = 1;
 666         desc->req.rqtype = MEMTOMEM;
 667
 668         /* Select max possible burst size */
 669         burst = pi->pcfg.data_bus_width / 8;
 670
 671         while (burst > 1) {
 672                 if (!(len % burst))
 673                         break;
 674                 burst /= 2;
 675         }
 676
 677         desc->rqcfg.brst_size = 0;
 678         while (burst != (1 << desc->rqcfg.brst_size))
 679                 desc->rqcfg.brst_size++;
 680
 681         desc->rqcfg.brst_len = get_burst_len(desc, len);
 682
 683         desc->txd.flags = flags;
 684
 685         return &desc->txd;
 686 }
 687
 688 static struct dma_async_tx_descriptor *
 689 pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 690                 unsigned int sg_len, enum dma_transfer_direction direction,
 691                 unsigned long flg)
 692 {
 693         struct dma_pl330_desc *first, *desc = NULL;
 694         struct dma_pl330_chan *pch = to_pchan(chan);
 695         struct scatterlist *sg;
 696         unsigned long flags;
 697         int i;
 698         dma_addr_t addr;
 699
 700         if (unlikely(!pch || !sgl || !sg_len))
 701                 return NULL;
 702
 703         addr = pch->fifo_addr;
 704
 705         first = NULL;
 706
 707         for_each_sg(sgl, sg, sg_len, i) {
 708
 709                 desc = pl330_get_desc(pch);
 710                 if (!desc) {
 711                         struct dma_pl330_dmac *pdmac = pch->dmac;
 712
 713                         dev_err(pch->dmac->pif.dev,
 714                                 "%s:%d Unable to fetch desc\n",
 715                                 __func__, __LINE__);
 716                         if (!first)
 717                                 return NULL;
 718
 719                         spin_lock_irqsave(&pdmac->pool_lock, flags);
 720
 721                         while (!list_empty(&first->node)) {
 722                                 desc = list_entry(first->node.next,
 723                                                 struct dma_pl330_desc, node);
 724                                 list_move_tail(&desc->node, &pdmac->desc_pool);
 725                         }
 726
 727                         list_move_tail(&first->node, &pdmac->desc_pool);
 728
 729                         spin_unlock_irqrestore(&pdmac->pool_lock, flags);
 730
 731                         return NULL;
 732                 }
 733
 734                 if (!first)
 735                         first = desc;
 736                 else
 737                         list_add_tail(&desc->node, &first->node);
 738
 739                 if (direction == DMA_MEM_TO_DEV) {
 740                         desc->rqcfg.src_inc = 1;
 741                         desc->rqcfg.dst_inc = 0;
 742                         desc->req.rqtype = MEMTODEV;
 743                         fill_px(&desc->px,
 744                                 addr, sg_dma_address(sg), sg_dma_len(sg));
 745                 } else {
 746                         desc->rqcfg.src_inc = 0;
 747                         desc->rqcfg.dst_inc = 1;
 748                         desc->req.rqtype = DEVTOMEM;
 749                         fill_px(&desc->px,
 750                                 sg_dma_address(sg), addr, sg_dma_len(sg));
 751                 }
 752
 753                 desc->rqcfg.brst_size = pch->burst_sz;
 754                 desc->rqcfg.brst_len = 1;
 755         }
 756
 757         /* Return the last desc in the chain */
 758         desc->txd.flags = flg;
 759         return &desc->txd;
 760 }
 761
 762 static irqreturn_t pl330_irq_handler(int irq, void *data)
 763 {
 764         if (pl330_update(data))
 765                 return IRQ_HANDLED;
 766         else
 767                 return IRQ_NONE;
 768 }
 769
 770 static int __devinit
 771 pl330_probe(struct amba_device *adev, const struct amba_id *id)
 772 {
 773         struct dma_pl330_platdata *pdat;
 774         struct dma_pl330_dmac *pdmac;
 775         struct dma_pl330_chan *pch;
 776         struct pl330_info *pi;
 777         struct dma_device *pd;
 778         struct resource *res;
 779         int i, ret, irq;
 780         int num_chan;
 781
 782         pdat = adev->dev.platform_data;
 783
 784         /* Allocate a new DMAC and its Channels */
 785         pdmac = kzalloc(sizeof(*pdmac), GFP_KERNEL);
 786         if (!pdmac) {
 787                 dev_err(&adev->dev, "unable to allocate mem\n");
 788                 return -ENOMEM;
 789         }
 790
 791         pi = &pdmac->pif;
 792         pi->dev = &adev->dev;
 793         pi->pl330_data = NULL;
 794         pi->mcbufsz = pdat ? pdat->mcbuf_sz : 0;
 795
 796         res = &adev->res;
 797         request_mem_region(res->start, resource_size(res), "dma-pl330");
 798
 799         pi->base = ioremap(res->start, resource_size(res));
 800         if (!pi->base) {
 801                 ret = -ENXIO;
 802                 goto probe_err1;
 803         }
 804
 805         pdmac->clk = clk_get(&adev->dev, "dma");
 806         if (IS_ERR(pdmac->clk)) {
 807                 dev_err(&adev->dev, "Cannot get operation clock.\n");
 808                 ret = -EINVAL;
 809                 goto probe_err2;
 810         }
 811
 812         amba_set_drvdata(adev, pdmac);
 813
 814 #ifndef CONFIG_PM_RUNTIME
 815         /* enable dma clk */
 816         clk_enable(pdmac->clk);
 817 #endif
 818
 819         irq = adev->irq[0];
 820         ret = request_irq(irq, pl330_irq_handler, 0,
 821                         dev_name(&adev->dev), pi);
 822         if (ret)
 823                 goto probe_err3;
 824
 825         ret = pl330_add(pi);
 826         if (ret)
 827                 goto probe_err4;
 828
 829         INIT_LIST_HEAD(&pdmac->desc_pool);
 830         spin_lock_init(&pdmac->pool_lock);
 831
 832         /* Create a descriptor pool of default size */
 833         if (!add_desc(pdmac, GFP_KERNEL, NR_DEFAULT_DESC))
 834                 dev_warn(&adev->dev, "unable to allocate desc\n");
 835
 836         pd = &pdmac->ddma;
 837         INIT_LIST_HEAD(&pd->channels);
 838
 839         /* Initialize channel parameters */
 840         num_chan = max(pdat ? pdat->nr_valid_peri : (u8)pi->pcfg.num_peri,
 841                         (u8)pi->pcfg.num_chan);
 842         pdmac->peripherals = kzalloc(num_chan * sizeof(*pch), GFP_KERNEL);
 843
 844         for (i = 0; i < num_chan; i++) {
 845                 pch = &pdmac->peripherals[i];
 846                 if (!adev->dev.of_node)
 847                         pch->chan.private = pdat ? &pdat->peri_id[i] : NULL;
 848                 else
 849                         pch->chan.private = adev->dev.of_node;
 850
 851                 INIT_LIST_HEAD(&pch->work_list);
 852                 spin_lock_init(&pch->lock);
 853                 pch->pl330_chid = NULL;
 854                 pch->chan.device = pd;
 855                 pch->dmac = pdmac;
 856
 857                 /* Add the channel to the DMAC list */
 858                 list_add_tail(&pch->chan.device_node, &pd->channels);
 859         }
 860
 861         pd->dev = &adev->dev;
 862         if (pdat) {
 863                 pd->cap_mask = pdat->cap_mask;
 864         } else {
 865                 dma_cap_set(DMA_MEMCPY, pd->cap_mask);
 866                 if (pi->pcfg.num_peri) {
 867                         dma_cap_set(DMA_SLAVE, pd->cap_mask);
 868                         dma_cap_set(DMA_CYCLIC, pd->cap_mask);
 869                 }
 870         }
 871
 872         pd->device_alloc_chan_resources = pl330_alloc_chan_resources;
 873         pd->device_free_chan_resources = pl330_free_chan_resources;
 874         pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy;
 875         pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic;
 876         pd->device_tx_status = pl330_tx_status;
 877         pd->device_prep_slave_sg = pl330_prep_slave_sg;
 878         pd->device_control = pl330_control;
 879         pd->device_issue_pending = pl330_issue_pending;
 880
 881         ret = dma_async_device_register(pd);
 882         if (ret) {
 883                 dev_err(&adev->dev, "unable to register DMAC\n");
 884                 goto probe_err5;
 885         }
 886
 887         dev_info(&adev->dev,
 888                 "Loaded driver for PL330 DMAC-%d\n", adev->periphid);
 889         dev_info(&adev->dev,
 890                 "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
 891                 pi->pcfg.data_buf_dep,
 892                 pi->pcfg.data_bus_width / 8, pi->pcfg.num_chan,
 893                 pi->pcfg.num_peri, pi->pcfg.num_events);
 894
 895         return 0;
 896
 897 probe_err5:
 898         pl330_del(pi);
 899 probe_err4:
 900         free_irq(irq, pi);
 901 probe_err3:
 902 #ifndef CONFIG_PM_RUNTIME
 903         clk_disable(pdmac->clk);
 904 #endif
 905         clk_put(pdmac->clk);
 906 probe_err2:
 907         iounmap(pi->base);
 908 probe_err1:
 909         release_mem_region(res->start, resource_size(res));
 910         kfree(pdmac);
 911
 912         return ret;
 913 }
 914
 915 static int __devexit pl330_remove(struct amba_device *adev)
 916 {
 917         struct dma_pl330_dmac *pdmac = amba_get_drvdata(adev);
 918         struct dma_pl330_chan *pch, *_p;
 919         struct pl330_info *pi;
 920         struct resource *res;
 921         int irq;
 922
 923         if (!pdmac)
 924                 return 0;
 925
 926         amba_set_drvdata(adev, NULL);
 927
 928         /* Idle the DMAC */
 929         list_for_each_entry_safe(pch, _p, &pdmac->ddma.channels,
 930                         chan.device_node) {
 931
 932                 /* Remove the channel */
 933                 list_del(&pch->chan.device_node);
 934
 935                 /* Flush the channel */
 936                 pl330_control(&pch->chan, DMA_TERMINATE_ALL, 0);
 937                 pl330_free_chan_resources(&pch->chan);
 938         }
 939
 940         pi = &pdmac->pif;
 941
 942         pl330_del(pi);
 943
 944         irq = adev->irq[0];
 945         free_irq(irq, pi);
 946
 947         iounmap(pi->base);
 948
 949         res = &adev->res;
 950         release_mem_region(res->start, resource_size(res));
 951
 952 #ifndef CONFIG_PM_RUNTIME
 953         clk_disable(pdmac->clk);
 954 #endif
 955
 956         kfree(pdmac);
 957
 958         return 0;
 959 }
 960
 961 static struct amba_id pl330_ids[] = {
 962         {
 963                 .id     = 0x00041330,
 964                 .mask   = 0x000fffff,
 965         },
 966         { 0, 0 },
 967 };
 968
 969 MODULE_DEVICE_TABLE(amba, pl330_ids);
 970
 971 #ifdef CONFIG_PM_RUNTIME
 972 static int pl330_runtime_suspend(struct device *dev)
 973 {
 974         struct dma_pl330_dmac *pdmac = dev_get_drvdata(dev);
 975
 976         if (!pdmac) {
 977                 dev_err(dev, "failed to get dmac\n");
 978                 return -ENODEV;
 979         }
 980
 981         clk_disable(pdmac->clk);
 982
 983         return 0;
 984 }
 985
 986 static int pl330_runtime_resume(struct device *dev)
 987 {
 988         struct dma_pl330_dmac *pdmac = dev_get_drvdata(dev);
 989
 990         if (!pdmac) {
 991                 dev_err(dev, "failed to get dmac\n");
 992                 return -ENODEV;
 993         }
 994
 995         clk_enable(pdmac->clk);
 996
 997         return 0;
 998 }
 999 #else
1000 #define pl330_runtime_suspend   NULL
1001 #define pl330_runtime_resume    NULL
1002 #endif /* CONFIG_PM_RUNTIME */
1003
1004 static const struct dev_pm_ops pl330_pm_ops = {
1005         .runtime_suspend = pl330_runtime_suspend,
1006         .runtime_resume = pl330_runtime_resume,
1007 };
1008
1009 static struct amba_driver pl330_driver = {
1010         .drv = {
1011                 .owner = THIS_MODULE,
1012                 .name = "dma-pl330",
1013                 .pm = &pl330_pm_ops,
1014         },
1015         .id_table = pl330_ids,
1016         .probe = pl330_probe,
1017         .remove = pl330_remove,
1018 };
1019
1020 static int __init pl330_init(void)
1021 {
1022         return amba_driver_register(&pl330_driver);
1023 }
1024 module_init(pl330_init);
1025
1026 static void __exit pl330_exit(void)
1027 {
1028         amba_driver_unregister(&pl330_driver);
1029         return;
1030 }
1031 module_exit(pl330_exit);
1032
1033 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1034 MODULE_DESCRIPTION("API Driver for PL330 DMAC");
1035 MODULE_LICENSE("GPL");