2 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com/
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
10 * SAMSUNG - GPIOlib support
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/irq.h>
20 #include <linux/gpio.h>
21 #include <linux/init.h>
22 #include <linux/spinlock.h>
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/device.h>
26 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/of_address.h>
33 #include <mach/hardware.h>
35 #include <mach/regs-clock.h>
36 #include <mach/regs-gpio.h>
39 #include <plat/gpio-core.h>
40 #include <plat/gpio-cfg.h>
41 #include <plat/gpio-cfg-helpers.h>
42 #include <plat/gpio-fns.h>
46 #define gpio_dbg(x...) do { } while (0)
48 #define gpio_dbg(x...) printk(KERN_DEBUG x)
51 int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip,
52 unsigned int off, samsung_gpio_pull_t pull)
54 void __iomem *reg = chip->base + 0x08;
58 pup = __raw_readl(reg);
61 __raw_writel(pup, reg);
66 samsung_gpio_pull_t samsung_gpio_getpull_updown(struct samsung_gpio_chip *chip,
69 void __iomem *reg = chip->base + 0x08;
71 u32 pup = __raw_readl(reg);
76 return (__force samsung_gpio_pull_t)pup;
79 int s3c2443_gpio_setpull(struct samsung_gpio_chip *chip,
80 unsigned int off, samsung_gpio_pull_t pull)
83 case S3C_GPIO_PULL_NONE:
86 case S3C_GPIO_PULL_UP:
89 case S3C_GPIO_PULL_DOWN:
93 return samsung_gpio_setpull_updown(chip, off, pull);
96 samsung_gpio_pull_t s3c2443_gpio_getpull(struct samsung_gpio_chip *chip,
99 samsung_gpio_pull_t pull;
101 pull = samsung_gpio_getpull_updown(chip, off);
105 pull = S3C_GPIO_PULL_UP;
109 pull = S3C_GPIO_PULL_NONE;
112 pull = S3C_GPIO_PULL_DOWN;
119 static int s3c24xx_gpio_setpull_1(struct samsung_gpio_chip *chip,
120 unsigned int off, samsung_gpio_pull_t pull,
121 samsung_gpio_pull_t updown)
123 void __iomem *reg = chip->base + 0x08;
124 u32 pup = __raw_readl(reg);
128 else if (pull == S3C_GPIO_PULL_NONE)
133 __raw_writel(pup, reg);
137 static samsung_gpio_pull_t s3c24xx_gpio_getpull_1(struct samsung_gpio_chip *chip,
139 samsung_gpio_pull_t updown)
141 void __iomem *reg = chip->base + 0x08;
142 u32 pup = __raw_readl(reg);
145 return pup ? S3C_GPIO_PULL_NONE : updown;
148 samsung_gpio_pull_t s3c24xx_gpio_getpull_1up(struct samsung_gpio_chip *chip,
151 return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_UP);
154 int s3c24xx_gpio_setpull_1up(struct samsung_gpio_chip *chip,
155 unsigned int off, samsung_gpio_pull_t pull)
157 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_UP);
160 samsung_gpio_pull_t s3c24xx_gpio_getpull_1down(struct samsung_gpio_chip *chip,
163 return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_DOWN);
166 int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip *chip,
167 unsigned int off, samsung_gpio_pull_t pull)
169 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_DOWN);
172 static int exynos_gpio_setpull(struct samsung_gpio_chip *chip,
173 unsigned int off, samsung_gpio_pull_t pull)
175 if (pull == S3C_GPIO_PULL_UP)
178 return samsung_gpio_setpull_updown(chip, off, pull);
181 static samsung_gpio_pull_t exynos_gpio_getpull(struct samsung_gpio_chip *chip,
184 samsung_gpio_pull_t pull;
186 pull = samsung_gpio_getpull_updown(chip, off);
189 pull = S3C_GPIO_PULL_UP;
195 * samsung_gpio_setcfg_2bit - Samsung 2bit style GPIO configuration.
196 * @chip: The gpio chip that is being configured.
197 * @off: The offset for the GPIO being configured.
198 * @cfg: The configuration value to set.
200 * This helper deal with the GPIO cases where the control register
201 * has two bits of configuration per gpio, which have the following
205 * 1x = special function
208 static int samsung_gpio_setcfg_2bit(struct samsung_gpio_chip *chip,
209 unsigned int off, unsigned int cfg)
211 void __iomem *reg = chip->base;
212 unsigned int shift = off * 2;
215 if (samsung_gpio_is_cfg_special(cfg)) {
223 con = __raw_readl(reg);
224 con &= ~(0x3 << shift);
226 __raw_writel(con, reg);
232 * samsung_gpio_getcfg_2bit - Samsung 2bit style GPIO configuration read.
233 * @chip: The gpio chip that is being configured.
234 * @off: The offset for the GPIO being configured.
236 * The reverse of samsung_gpio_setcfg_2bit(). Will return a value which
237 * could be directly passed back to samsung_gpio_setcfg_2bit(), from the
238 * S3C_GPIO_SPECIAL() macro.
241 static unsigned int samsung_gpio_getcfg_2bit(struct samsung_gpio_chip *chip,
246 con = __raw_readl(chip->base);
250 /* this conversion works for IN and OUT as well as special mode */
251 return S3C_GPIO_SPECIAL(con);
255 * samsung_gpio_setcfg_4bit - Samsung 4bit single register GPIO config.
256 * @chip: The gpio chip that is being configured.
257 * @off: The offset for the GPIO being configured.
258 * @cfg: The configuration value to set.
260 * This helper deal with the GPIO cases where the control register has 4 bits
261 * of control per GPIO, generally in the form of:
264 * others = Special functions (dependent on bank)
266 * Note, since the code to deal with the case where there are two control
267 * registers instead of one, we do not have a separate set of functions for
271 static int samsung_gpio_setcfg_4bit(struct samsung_gpio_chip *chip,
272 unsigned int off, unsigned int cfg)
274 void __iomem *reg = chip->base;
275 unsigned int shift = (off & 7) * 4;
278 if (off < 8 && chip->chip.ngpio > 8)
281 if (samsung_gpio_is_cfg_special(cfg)) {
286 con = __raw_readl(reg);
287 con &= ~(0xf << shift);
289 __raw_writel(con, reg);
295 * samsung_gpio_getcfg_4bit - Samsung 4bit single register GPIO config read.
296 * @chip: The gpio chip that is being configured.
297 * @off: The offset for the GPIO being configured.
299 * The reverse of samsung_gpio_setcfg_4bit(), turning a gpio configuration
300 * register setting into a value the software can use, such as could be passed
301 * to samsung_gpio_setcfg_4bit().
303 * @sa samsung_gpio_getcfg_2bit
306 static unsigned samsung_gpio_getcfg_4bit(struct samsung_gpio_chip *chip,
309 void __iomem *reg = chip->base;
310 unsigned int shift = (off & 7) * 4;
313 if (off < 8 && chip->chip.ngpio > 8)
316 con = __raw_readl(reg);
320 /* this conversion works for IN and OUT as well as special mode */
321 return S3C_GPIO_SPECIAL(con);
324 #ifdef CONFIG_PLAT_S3C24XX
326 * s3c24xx_gpio_setcfg_abank - S3C24XX style GPIO configuration (Bank A)
327 * @chip: The gpio chip that is being configured.
328 * @off: The offset for the GPIO being configured.
329 * @cfg: The configuration value to set.
331 * This helper deal with the GPIO cases where the control register
332 * has one bit of configuration for the gpio, where setting the bit
333 * means the pin is in special function mode and unset means output.
336 static int s3c24xx_gpio_setcfg_abank(struct samsung_gpio_chip *chip,
337 unsigned int off, unsigned int cfg)
339 void __iomem *reg = chip->base;
340 unsigned int shift = off;
343 if (samsung_gpio_is_cfg_special(cfg)) {
346 /* Map output to 0, and SFN2 to 1 */
354 con = __raw_readl(reg);
355 con &= ~(0x1 << shift);
357 __raw_writel(con, reg);
363 * s3c24xx_gpio_getcfg_abank - S3C24XX style GPIO configuration read (Bank A)
364 * @chip: The gpio chip that is being configured.
365 * @off: The offset for the GPIO being configured.
367 * The reverse of s3c24xx_gpio_setcfg_abank() turning an GPIO into a usable
368 * GPIO configuration value.
370 * @sa samsung_gpio_getcfg_2bit
371 * @sa samsung_gpio_getcfg_4bit
374 static unsigned s3c24xx_gpio_getcfg_abank(struct samsung_gpio_chip *chip,
379 con = __raw_readl(chip->base);
384 return S3C_GPIO_SFN(con);
388 #if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
389 static int s5p64x0_gpio_setcfg_rbank(struct samsung_gpio_chip *chip,
390 unsigned int off, unsigned int cfg)
392 void __iomem *reg = chip->base;
403 shift = (off & 7) * 4;
407 shift = ((off + 1) & 7) * 4;
410 shift = ((off + 1) & 7) * 4;
414 if (samsung_gpio_is_cfg_special(cfg)) {
419 con = __raw_readl(reg);
420 con &= ~(0xf << shift);
422 __raw_writel(con, reg);
428 static void __init samsung_gpiolib_set_cfg(struct samsung_gpio_cfg *chipcfg,
431 for (; nr_chips > 0; nr_chips--, chipcfg++) {
432 if (!chipcfg->set_config)
433 chipcfg->set_config = samsung_gpio_setcfg_4bit;
434 if (!chipcfg->get_config)
435 chipcfg->get_config = samsung_gpio_getcfg_4bit;
436 if (!chipcfg->set_pull)
437 chipcfg->set_pull = samsung_gpio_setpull_updown;
438 if (!chipcfg->get_pull)
439 chipcfg->get_pull = samsung_gpio_getpull_updown;
443 struct samsung_gpio_cfg s3c24xx_gpiocfg_default = {
444 .set_config = samsung_gpio_setcfg_2bit,
445 .get_config = samsung_gpio_getcfg_2bit,
448 #ifdef CONFIG_PLAT_S3C24XX
449 static struct samsung_gpio_cfg s3c24xx_gpiocfg_banka = {
450 .set_config = s3c24xx_gpio_setcfg_abank,
451 .get_config = s3c24xx_gpio_getcfg_abank,
455 #if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5)
456 static struct samsung_gpio_cfg exynos_gpio_cfg = {
457 .set_pull = exynos_gpio_setpull,
458 .get_pull = exynos_gpio_getpull,
459 .set_config = samsung_gpio_setcfg_4bit,
460 .get_config = samsung_gpio_getcfg_4bit,
464 #if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
465 static struct samsung_gpio_cfg s5p64x0_gpio_cfg_rbank = {
467 .set_config = s5p64x0_gpio_setcfg_rbank,
468 .get_config = samsung_gpio_getcfg_4bit,
469 .set_pull = samsung_gpio_setpull_updown,
470 .get_pull = samsung_gpio_getpull_updown,
474 static struct samsung_gpio_cfg samsung_gpio_cfgs[] = {
489 .set_config = samsung_gpio_setcfg_2bit,
490 .get_config = samsung_gpio_getcfg_2bit,
494 .set_config = samsung_gpio_setcfg_2bit,
495 .get_config = samsung_gpio_getcfg_2bit,
499 .set_config = samsung_gpio_setcfg_2bit,
500 .get_config = samsung_gpio_getcfg_2bit,
503 .set_config = samsung_gpio_setcfg_2bit,
504 .get_config = samsung_gpio_getcfg_2bit,
507 .set_pull = exynos_gpio_setpull,
508 .get_pull = exynos_gpio_getpull,
512 .set_pull = exynos_gpio_setpull,
513 .get_pull = exynos_gpio_getpull,
518 * Default routines for controlling GPIO, based on the original S3C24XX
519 * GPIO functions which deal with the case where each gpio bank of the
520 * chip is as following:
522 * base + 0x00: Control register, 2 bits per gpio
523 * gpio n: 2 bits starting at (2*n)
524 * 00 = input, 01 = output, others mean special-function
525 * base + 0x04: Data register, 1 bit per gpio
529 static int samsung_gpiolib_2bit_input(struct gpio_chip *chip, unsigned offset)
531 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
532 void __iomem *base = ourchip->base;
536 samsung_gpio_lock(ourchip, flags);
538 con = __raw_readl(base + 0x00);
539 con &= ~(3 << (offset * 2));
541 __raw_writel(con, base + 0x00);
543 samsung_gpio_unlock(ourchip, flags);
547 static int samsung_gpiolib_2bit_output(struct gpio_chip *chip,
548 unsigned offset, int value)
550 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
551 void __iomem *base = ourchip->base;
556 samsung_gpio_lock(ourchip, flags);
558 dat = __raw_readl(base + 0x04);
559 dat &= ~(1 << offset);
562 __raw_writel(dat, base + 0x04);
564 con = __raw_readl(base + 0x00);
565 con &= ~(3 << (offset * 2));
566 con |= 1 << (offset * 2);
568 __raw_writel(con, base + 0x00);
569 __raw_writel(dat, base + 0x04);
571 samsung_gpio_unlock(ourchip, flags);
576 * The samsung_gpiolib_4bit routines are to control the gpio banks where
577 * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
580 * base + 0x00: Control register, 4 bits per gpio
581 * gpio n: 4 bits starting at (4*n)
582 * 0000 = input, 0001 = output, others mean special-function
583 * base + 0x04: Data register, 1 bit per gpio
586 * Note, since the data register is one bit per gpio and is at base + 0x4
587 * we can use samsung_gpiolib_get and samsung_gpiolib_set to change the
588 * state of the output.
591 static int samsung_gpiolib_4bit_input(struct gpio_chip *chip,
594 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
595 void __iomem *base = ourchip->base;
598 con = __raw_readl(base + GPIOCON_OFF);
599 con &= ~(0xf << con_4bit_shift(offset));
600 __raw_writel(con, base + GPIOCON_OFF);
602 gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con);
607 static int samsung_gpiolib_4bit_output(struct gpio_chip *chip,
608 unsigned int offset, int value)
610 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
611 void __iomem *base = ourchip->base;
615 con = __raw_readl(base + GPIOCON_OFF);
616 con &= ~(0xf << con_4bit_shift(offset));
617 con |= 0x1 << con_4bit_shift(offset);
619 dat = __raw_readl(base + GPIODAT_OFF);
624 dat &= ~(1 << offset);
626 __raw_writel(dat, base + GPIODAT_OFF);
627 __raw_writel(con, base + GPIOCON_OFF);
628 __raw_writel(dat, base + GPIODAT_OFF);
630 gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
636 * The next set of routines are for the case where the GPIO configuration
637 * registers are 4 bits per GPIO but there is more than one register (the
638 * bank has more than 8 GPIOs.
640 * This case is the similar to the 4 bit case, but the registers are as
643 * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
644 * gpio n: 4 bits starting at (4*n)
645 * 0000 = input, 0001 = output, others mean special-function
646 * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
647 * gpio n: 4 bits starting at (4*n)
648 * 0000 = input, 0001 = output, others mean special-function
649 * base + 0x08: Data register, 1 bit per gpio
652 * To allow us to use the samsung_gpiolib_get and samsung_gpiolib_set
653 * routines we store the 'base + 0x4' address so that these routines see
654 * the data register at ourchip->base + 0x04.
657 static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip,
660 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
661 void __iomem *base = ourchip->base;
662 void __iomem *regcon = base;
670 con = __raw_readl(regcon);
671 con &= ~(0xf << con_4bit_shift(offset));
672 __raw_writel(con, regcon);
674 gpio_dbg("%s: %p: CON %08lx\n", __func__, base, con);
679 static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip,
680 unsigned int offset, int value)
682 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
683 void __iomem *base = ourchip->base;
684 void __iomem *regcon = base;
687 unsigned con_offset = offset;
694 con = __raw_readl(regcon);
695 con &= ~(0xf << con_4bit_shift(con_offset));
696 con |= 0x1 << con_4bit_shift(con_offset);
698 dat = __raw_readl(base + GPIODAT_OFF);
703 dat &= ~(1 << offset);
705 __raw_writel(dat, base + GPIODAT_OFF);
706 __raw_writel(con, regcon);
707 __raw_writel(dat, base + GPIODAT_OFF);
709 gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
714 #ifdef CONFIG_PLAT_S3C24XX
715 /* The next set of routines are for the case of s3c24xx bank a */
717 static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
722 static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
723 unsigned offset, int value)
725 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
726 void __iomem *base = ourchip->base;
731 local_irq_save(flags);
733 con = __raw_readl(base + 0x00);
734 dat = __raw_readl(base + 0x04);
736 dat &= ~(1 << offset);
740 __raw_writel(dat, base + 0x04);
742 con &= ~(1 << offset);
744 __raw_writel(con, base + 0x00);
745 __raw_writel(dat, base + 0x04);
747 local_irq_restore(flags);
752 /* The next set of routines are for the case of s5p64x0 bank r */
754 static int s5p64x0_gpiolib_rbank_input(struct gpio_chip *chip,
757 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
758 void __iomem *base = ourchip->base;
759 void __iomem *regcon = base;
779 samsung_gpio_lock(ourchip, flags);
781 con = __raw_readl(regcon);
782 con &= ~(0xf << con_4bit_shift(offset));
783 __raw_writel(con, regcon);
785 samsung_gpio_unlock(ourchip, flags);
790 static int s5p64x0_gpiolib_rbank_output(struct gpio_chip *chip,
791 unsigned int offset, int value)
793 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
794 void __iomem *base = ourchip->base;
795 void __iomem *regcon = base;
799 unsigned con_offset = offset;
801 switch (con_offset) {
817 samsung_gpio_lock(ourchip, flags);
819 con = __raw_readl(regcon);
820 con &= ~(0xf << con_4bit_shift(con_offset));
821 con |= 0x1 << con_4bit_shift(con_offset);
823 dat = __raw_readl(base + GPIODAT_OFF);
827 dat &= ~(1 << offset);
829 __raw_writel(con, regcon);
830 __raw_writel(dat, base + GPIODAT_OFF);
832 samsung_gpio_unlock(ourchip, flags);
837 static void samsung_gpiolib_set(struct gpio_chip *chip,
838 unsigned offset, int value)
840 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
841 void __iomem *base = ourchip->base;
845 samsung_gpio_lock(ourchip, flags);
847 dat = __raw_readl(base + 0x04);
848 dat &= ~(1 << offset);
851 __raw_writel(dat, base + 0x04);
853 samsung_gpio_unlock(ourchip, flags);
856 static int samsung_gpiolib_get(struct gpio_chip *chip, unsigned offset)
858 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
861 val = __raw_readl(ourchip->base + 0x04);
869 * CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios
870 * for use with the configuration calls, and other parts of the s3c gpiolib
873 * Not all s3c support code will need this, as some configurations of cpu
874 * may only support one or two different configuration options and have an
875 * easy gpio to samsung_gpio_chip mapping function. If this is the case, then
876 * the machine support file should provide its own samsung_gpiolib_getchip()
877 * and any other necessary functions.
880 #ifdef CONFIG_S3C_GPIO_TRACK
881 struct samsung_gpio_chip *s3c_gpios[S3C_GPIO_END];
883 static __init void s3c_gpiolib_track(struct samsung_gpio_chip *chip)
888 gpn = chip->chip.base;
889 for (i = 0; i < chip->chip.ngpio; i++, gpn++) {
890 BUG_ON(gpn >= ARRAY_SIZE(s3c_gpios));
891 s3c_gpios[gpn] = chip;
894 #endif /* CONFIG_S3C_GPIO_TRACK */
896 static __init void exynos_gpiolib_powerdown_cfg(struct samsung_gpio_chip *chip)
898 struct property *prop;
900 const __be32 *val_ptr;
901 u32 con_pdn, pud_pdn;
903 if (!of_find_property(chip->chip.of_node, "powerdown-support", NULL))
906 chip->pdn_supported = true; /* Indicate this chip supports saving */
907 prop = of_find_property(chip->chip.of_node, "powerdown-settings", NULL);
911 prop_count = prop->length / sizeof(u32);
912 if (prop_count != chip->chip.ngpio) {
913 pr_warn("%s: powerdown-settings has %d entries, %d expected\n",
914 chip->chip.label, prop_count, chip->chip.ngpio);
917 if (prop_count > 16) {
918 pr_warn("%s: powerdown-settings has %d entries (max 16)\n",
919 chip->chip.label, prop_count);
923 val_ptr = prop->value;
924 con_pdn = __raw_readl(chip->base + GPIOCONPDN_OFF);
925 pud_pdn = __raw_readl(chip->base + GPIOPUDPDN_OFF);
927 for (i = 0; i < prop_count; i++) {
928 u32 value = be32_to_cpup(val_ptr++);
930 continue; /* 0 = use existing */
931 con_pdn &= ~(0x3 << (i * 2));
932 pud_pdn &= ~(0x3 << (i * 2));
935 con_pdn |= 0x2 << (i * 2);
936 /* pud_pdn |= 0x0 << (i * 2); */
938 case 2: /* Pull up */
939 con_pdn |= 0x2 << (i * 2);
940 pud_pdn |= 0x3 << (i * 2);
942 case 3: /* Pull down */
943 con_pdn |= 0x2 << (i * 2);
944 pud_pdn |= 0x1 << (i * 2);
946 case 4: /* Drive high */
947 con_pdn |= 0x1 << (i * 2);
948 /* pud_pdn |= 0x0 << (i * 2); */
950 case 5: /* Drive low */
951 /* con_pdn |= 0x0 << (i * 2); */
952 /* pud_pdn |= 0x0 << (i * 2); */
954 case 6: /* Maintain powerup settings */
955 con_pdn |= 0x3 << (i * 2);
956 /* pud_pdn |= 0x0 << (i * 2); */
959 pr_warn("%s(%d): powerdown-settings illegal value %d\n",
960 chip->chip.label, i, value);
963 __raw_writel(con_pdn, chip->base + GPIOCONPDN_OFF);
964 __raw_writel(pud_pdn, chip->base + GPIOPUDPDN_OFF);
968 * samsung_gpiolib_add() - add the Samsung gpio_chip.
969 * @chip: The chip to register
971 * This is a wrapper to gpiochip_add() that takes our specific gpio chip
972 * information and makes the necessary alterations for the platform and
973 * notes the information for use with the configuration systems and any
974 * other parts of the system.
977 static void __init samsung_gpiolib_add(struct samsung_gpio_chip *chip)
979 struct gpio_chip *gc = &chip->chip;
986 spin_lock_init(&chip->lock);
988 if (!gc->direction_input)
989 gc->direction_input = samsung_gpiolib_2bit_input;
990 if (!gc->direction_output)
991 gc->direction_output = samsung_gpiolib_2bit_output;
993 gc->set = samsung_gpiolib_set;
995 gc->get = samsung_gpiolib_get;
998 if (chip->pm != NULL) {
999 if (!chip->pm->save || !chip->pm->resume)
1000 printk(KERN_ERR "gpio: %s has missing PM functions\n",
1003 printk(KERN_ERR "gpio: %s has no PM function\n", gc->label);
1006 exynos_gpiolib_powerdown_cfg(chip);
1009 /* gpiochip_add() prints own failure message on error. */
1010 ret = gpiochip_add(gc);
1012 s3c_gpiolib_track(chip);
1015 static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip,
1016 int nr_chips, void __iomem *base)
1019 struct gpio_chip *gc = &chip->chip;
1021 for (i = 0 ; i < nr_chips; i++, chip++) {
1022 /* skip banks not present on SoC */
1023 if (chip->chip.base >= S3C_GPIO_END)
1027 chip->config = &s3c24xx_gpiocfg_default;
1029 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
1030 if ((base != NULL) && (chip->base == NULL))
1031 chip->base = base + ((i) * 0x10);
1033 if (!gc->direction_input)
1034 gc->direction_input = samsung_gpiolib_2bit_input;
1035 if (!gc->direction_output)
1036 gc->direction_output = samsung_gpiolib_2bit_output;
1038 samsung_gpiolib_add(chip);
1042 static void __init samsung_gpiolib_add_2bit_chips(struct samsung_gpio_chip *chip,
1043 int nr_chips, void __iomem *base,
1044 unsigned int offset)
1048 for (i = 0 ; i < nr_chips; i++, chip++) {
1049 chip->chip.direction_input = samsung_gpiolib_2bit_input;
1050 chip->chip.direction_output = samsung_gpiolib_2bit_output;
1053 chip->config = &samsung_gpio_cfgs[7];
1055 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
1056 if ((base != NULL) && (chip->base == NULL))
1057 chip->base = base + ((i) * offset);
1059 samsung_gpiolib_add(chip);
1064 * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config.
1065 * @chip: The gpio chip that is being configured.
1066 * @nr_chips: The no of chips (gpio ports) for the GPIO being configured.
1068 * This helper deal with the GPIO cases where the control register has 4 bits
1069 * of control per GPIO, generally in the form of:
1072 * others = Special functions (dependent on bank)
1074 * Note, since the code to deal with the case where there are two control
1075 * registers instead of one, we do not have a separate set of function
1076 * (samsung_gpiolib_add_4bit2_chips)for each case.
1079 static void __init samsung_gpiolib_add_4bit_chips(struct samsung_gpio_chip *chip,
1080 int nr_chips, void __iomem *base)
1084 for (i = 0 ; i < nr_chips; i++, chip++) {
1085 chip->chip.direction_input = samsung_gpiolib_4bit_input;
1086 chip->chip.direction_output = samsung_gpiolib_4bit_output;
1089 chip->config = &samsung_gpio_cfgs[2];
1091 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1092 if ((base != NULL) && (chip->base == NULL))
1093 chip->base = base + ((i) * 0x20);
1095 samsung_gpiolib_add(chip);
1099 static void __init samsung_gpiolib_add_4bit2_chips(struct samsung_gpio_chip *chip,
1102 for (; nr_chips > 0; nr_chips--, chip++) {
1103 chip->chip.direction_input = samsung_gpiolib_4bit2_input;
1104 chip->chip.direction_output = samsung_gpiolib_4bit2_output;
1107 chip->config = &samsung_gpio_cfgs[2];
1109 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1111 samsung_gpiolib_add(chip);
1115 static void __init s5p64x0_gpiolib_add_rbank(struct samsung_gpio_chip *chip,
1118 for (; nr_chips > 0; nr_chips--, chip++) {
1119 chip->chip.direction_input = s5p64x0_gpiolib_rbank_input;
1120 chip->chip.direction_output = s5p64x0_gpiolib_rbank_output;
1123 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1125 samsung_gpiolib_add(chip);
1129 int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
1131 struct samsung_gpio_chip *samsung_chip = container_of(chip, struct samsung_gpio_chip, chip);
1133 return samsung_chip->irq_base + offset;
1136 #ifdef CONFIG_PLAT_S3C24XX
1137 static int s3c24xx_gpiolib_fbank_to_irq(struct gpio_chip *chip, unsigned offset)
1140 return IRQ_EINT0 + offset;
1143 return IRQ_EINT4 + offset - 4;
1149 #ifdef CONFIG_PLAT_S3C64XX
1150 static int s3c64xx_gpiolib_mbank_to_irq(struct gpio_chip *chip, unsigned pin)
1152 return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
1155 static int s3c64xx_gpiolib_lbank_to_irq(struct gpio_chip *chip, unsigned pin)
1157 return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
1161 struct samsung_gpio_chip s3c24xx_gpios[] = {
1162 #ifdef CONFIG_PLAT_S3C24XX
1164 .config = &s3c24xx_gpiocfg_banka,
1166 .base = S3C2410_GPA(0),
1167 .owner = THIS_MODULE,
1170 .direction_input = s3c24xx_gpiolib_banka_input,
1171 .direction_output = s3c24xx_gpiolib_banka_output,
1175 .base = S3C2410_GPB(0),
1176 .owner = THIS_MODULE,
1182 .base = S3C2410_GPC(0),
1183 .owner = THIS_MODULE,
1189 .base = S3C2410_GPD(0),
1190 .owner = THIS_MODULE,
1196 .base = S3C2410_GPE(0),
1198 .owner = THIS_MODULE,
1203 .base = S3C2410_GPF(0),
1204 .owner = THIS_MODULE,
1207 .to_irq = s3c24xx_gpiolib_fbank_to_irq,
1210 .irq_base = IRQ_EINT8,
1212 .base = S3C2410_GPG(0),
1213 .owner = THIS_MODULE,
1216 .to_irq = samsung_gpiolib_to_irq,
1220 .base = S3C2410_GPH(0),
1221 .owner = THIS_MODULE,
1226 /* GPIOS for the S3C2443 and later devices. */
1228 .base = S3C2440_GPJCON,
1230 .base = S3C2410_GPJ(0),
1231 .owner = THIS_MODULE,
1236 .base = S3C2443_GPKCON,
1238 .base = S3C2410_GPK(0),
1239 .owner = THIS_MODULE,
1244 .base = S3C2443_GPLCON,
1246 .base = S3C2410_GPL(0),
1247 .owner = THIS_MODULE,
1252 .base = S3C2443_GPMCON,
1254 .base = S3C2410_GPM(0),
1255 .owner = THIS_MODULE,
1264 * GPIO bank summary:
1266 * Bank GPIOs Style SlpCon ExtInt Group
1272 * F 16 2Bit Yes 4 [1]
1274 * H 10 4Bit[2] Yes 6
1275 * I 16 2Bit Yes None
1276 * J 12 2Bit Yes None
1277 * K 16 4Bit[2] No None
1278 * L 15 4Bit[2] No None
1279 * M 6 4Bit No IRQ_EINT
1280 * N 16 2Bit No IRQ_EINT
1285 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1286 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1289 static struct samsung_gpio_chip s3c64xx_gpios_4bit[] = {
1290 #ifdef CONFIG_PLAT_S3C64XX
1293 .base = S3C64XX_GPA(0),
1294 .ngpio = S3C64XX_GPIO_A_NR,
1299 .base = S3C64XX_GPB(0),
1300 .ngpio = S3C64XX_GPIO_B_NR,
1305 .base = S3C64XX_GPC(0),
1306 .ngpio = S3C64XX_GPIO_C_NR,
1311 .base = S3C64XX_GPD(0),
1312 .ngpio = S3C64XX_GPIO_D_NR,
1316 .config = &samsung_gpio_cfgs[0],
1318 .base = S3C64XX_GPE(0),
1319 .ngpio = S3C64XX_GPIO_E_NR,
1323 .base = S3C64XX_GPG_BASE,
1325 .base = S3C64XX_GPG(0),
1326 .ngpio = S3C64XX_GPIO_G_NR,
1330 .base = S3C64XX_GPM_BASE,
1331 .config = &samsung_gpio_cfgs[1],
1333 .base = S3C64XX_GPM(0),
1334 .ngpio = S3C64XX_GPIO_M_NR,
1336 .to_irq = s3c64xx_gpiolib_mbank_to_irq,
1342 static struct samsung_gpio_chip s3c64xx_gpios_4bit2[] = {
1343 #ifdef CONFIG_PLAT_S3C64XX
1345 .base = S3C64XX_GPH_BASE + 0x4,
1347 .base = S3C64XX_GPH(0),
1348 .ngpio = S3C64XX_GPIO_H_NR,
1352 .base = S3C64XX_GPK_BASE + 0x4,
1353 .config = &samsung_gpio_cfgs[0],
1355 .base = S3C64XX_GPK(0),
1356 .ngpio = S3C64XX_GPIO_K_NR,
1360 .base = S3C64XX_GPL_BASE + 0x4,
1361 .config = &samsung_gpio_cfgs[1],
1363 .base = S3C64XX_GPL(0),
1364 .ngpio = S3C64XX_GPIO_L_NR,
1366 .to_irq = s3c64xx_gpiolib_lbank_to_irq,
1372 static struct samsung_gpio_chip s3c64xx_gpios_2bit[] = {
1373 #ifdef CONFIG_PLAT_S3C64XX
1375 .base = S3C64XX_GPF_BASE,
1376 .config = &samsung_gpio_cfgs[6],
1378 .base = S3C64XX_GPF(0),
1379 .ngpio = S3C64XX_GPIO_F_NR,
1383 .config = &samsung_gpio_cfgs[7],
1385 .base = S3C64XX_GPI(0),
1386 .ngpio = S3C64XX_GPIO_I_NR,
1390 .config = &samsung_gpio_cfgs[7],
1392 .base = S3C64XX_GPJ(0),
1393 .ngpio = S3C64XX_GPIO_J_NR,
1397 .config = &samsung_gpio_cfgs[6],
1399 .base = S3C64XX_GPO(0),
1400 .ngpio = S3C64XX_GPIO_O_NR,
1404 .config = &samsung_gpio_cfgs[6],
1406 .base = S3C64XX_GPP(0),
1407 .ngpio = S3C64XX_GPIO_P_NR,
1411 .config = &samsung_gpio_cfgs[6],
1413 .base = S3C64XX_GPQ(0),
1414 .ngpio = S3C64XX_GPIO_Q_NR,
1418 .base = S3C64XX_GPN_BASE,
1419 .irq_base = IRQ_EINT(0),
1420 .config = &samsung_gpio_cfgs[5],
1422 .base = S3C64XX_GPN(0),
1423 .ngpio = S3C64XX_GPIO_N_NR,
1425 .to_irq = samsung_gpiolib_to_irq,
1432 * S5P6440 GPIO bank summary:
1434 * Bank GPIOs Style SlpCon ExtInt Group
1438 * F 2 2Bit Yes 4 [1]
1440 * H 10 4Bit[2] Yes 6
1441 * I 16 2Bit Yes None
1442 * J 12 2Bit Yes None
1443 * N 16 2Bit No IRQ_EINT
1445 * R 15 4Bit[2] Yes 8
1448 static struct samsung_gpio_chip s5p6440_gpios_4bit[] = {
1449 #ifdef CONFIG_CPU_S5P6440
1452 .base = S5P6440_GPA(0),
1453 .ngpio = S5P6440_GPIO_A_NR,
1458 .base = S5P6440_GPB(0),
1459 .ngpio = S5P6440_GPIO_B_NR,
1464 .base = S5P6440_GPC(0),
1465 .ngpio = S5P6440_GPIO_C_NR,
1469 .base = S5P64X0_GPG_BASE,
1471 .base = S5P6440_GPG(0),
1472 .ngpio = S5P6440_GPIO_G_NR,
1479 static struct samsung_gpio_chip s5p6440_gpios_4bit2[] = {
1480 #ifdef CONFIG_CPU_S5P6440
1482 .base = S5P64X0_GPH_BASE + 0x4,
1484 .base = S5P6440_GPH(0),
1485 .ngpio = S5P6440_GPIO_H_NR,
1492 static struct samsung_gpio_chip s5p6440_gpios_rbank[] = {
1493 #ifdef CONFIG_CPU_S5P6440
1495 .base = S5P64X0_GPR_BASE + 0x4,
1496 .config = &s5p64x0_gpio_cfg_rbank,
1498 .base = S5P6440_GPR(0),
1499 .ngpio = S5P6440_GPIO_R_NR,
1506 static struct samsung_gpio_chip s5p6440_gpios_2bit[] = {
1507 #ifdef CONFIG_CPU_S5P6440
1509 .base = S5P64X0_GPF_BASE,
1510 .config = &samsung_gpio_cfgs[6],
1512 .base = S5P6440_GPF(0),
1513 .ngpio = S5P6440_GPIO_F_NR,
1517 .base = S5P64X0_GPI_BASE,
1518 .config = &samsung_gpio_cfgs[4],
1520 .base = S5P6440_GPI(0),
1521 .ngpio = S5P6440_GPIO_I_NR,
1525 .base = S5P64X0_GPJ_BASE,
1526 .config = &samsung_gpio_cfgs[4],
1528 .base = S5P6440_GPJ(0),
1529 .ngpio = S5P6440_GPIO_J_NR,
1533 .base = S5P64X0_GPN_BASE,
1534 .config = &samsung_gpio_cfgs[5],
1536 .base = S5P6440_GPN(0),
1537 .ngpio = S5P6440_GPIO_N_NR,
1541 .base = S5P64X0_GPP_BASE,
1542 .config = &samsung_gpio_cfgs[6],
1544 .base = S5P6440_GPP(0),
1545 .ngpio = S5P6440_GPIO_P_NR,
1553 * S5P6450 GPIO bank summary:
1555 * Bank GPIOs Style SlpCon ExtInt Group
1561 * G 14 4Bit[2] Yes 5
1562 * H 10 4Bit[2] Yes 6
1563 * I 16 2Bit Yes None
1564 * J 12 2Bit Yes None
1566 * N 16 2Bit No IRQ_EINT
1568 * Q 14 2Bit Yes None
1569 * R 15 4Bit[2] Yes None
1572 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1573 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1576 static struct samsung_gpio_chip s5p6450_gpios_4bit[] = {
1577 #ifdef CONFIG_CPU_S5P6450
1580 .base = S5P6450_GPA(0),
1581 .ngpio = S5P6450_GPIO_A_NR,
1586 .base = S5P6450_GPB(0),
1587 .ngpio = S5P6450_GPIO_B_NR,
1592 .base = S5P6450_GPC(0),
1593 .ngpio = S5P6450_GPIO_C_NR,
1598 .base = S5P6450_GPD(0),
1599 .ngpio = S5P6450_GPIO_D_NR,
1603 .base = S5P6450_GPK_BASE,
1605 .base = S5P6450_GPK(0),
1606 .ngpio = S5P6450_GPIO_K_NR,
1613 static struct samsung_gpio_chip s5p6450_gpios_4bit2[] = {
1614 #ifdef CONFIG_CPU_S5P6450
1616 .base = S5P64X0_GPG_BASE + 0x4,
1618 .base = S5P6450_GPG(0),
1619 .ngpio = S5P6450_GPIO_G_NR,
1623 .base = S5P64X0_GPH_BASE + 0x4,
1625 .base = S5P6450_GPH(0),
1626 .ngpio = S5P6450_GPIO_H_NR,
1633 static struct samsung_gpio_chip s5p6450_gpios_rbank[] = {
1634 #ifdef CONFIG_CPU_S5P6450
1636 .base = S5P64X0_GPR_BASE + 0x4,
1637 .config = &s5p64x0_gpio_cfg_rbank,
1639 .base = S5P6450_GPR(0),
1640 .ngpio = S5P6450_GPIO_R_NR,
1647 static struct samsung_gpio_chip s5p6450_gpios_2bit[] = {
1648 #ifdef CONFIG_CPU_S5P6450
1650 .base = S5P64X0_GPF_BASE,
1651 .config = &samsung_gpio_cfgs[6],
1653 .base = S5P6450_GPF(0),
1654 .ngpio = S5P6450_GPIO_F_NR,
1658 .base = S5P64X0_GPI_BASE,
1659 .config = &samsung_gpio_cfgs[4],
1661 .base = S5P6450_GPI(0),
1662 .ngpio = S5P6450_GPIO_I_NR,
1666 .base = S5P64X0_GPJ_BASE,
1667 .config = &samsung_gpio_cfgs[4],
1669 .base = S5P6450_GPJ(0),
1670 .ngpio = S5P6450_GPIO_J_NR,
1674 .base = S5P64X0_GPN_BASE,
1675 .config = &samsung_gpio_cfgs[5],
1677 .base = S5P6450_GPN(0),
1678 .ngpio = S5P6450_GPIO_N_NR,
1682 .base = S5P64X0_GPP_BASE,
1683 .config = &samsung_gpio_cfgs[6],
1685 .base = S5P6450_GPP(0),
1686 .ngpio = S5P6450_GPIO_P_NR,
1690 .base = S5P6450_GPQ_BASE,
1691 .config = &samsung_gpio_cfgs[5],
1693 .base = S5P6450_GPQ(0),
1694 .ngpio = S5P6450_GPIO_Q_NR,
1698 .base = S5P6450_GPS_BASE,
1699 .config = &samsung_gpio_cfgs[6],
1701 .base = S5P6450_GPS(0),
1702 .ngpio = S5P6450_GPIO_S_NR,
1710 * S5PC100 GPIO bank summary:
1712 * Bank GPIOs Style INT Type
1713 * A0 8 4Bit GPIO_INT0
1714 * A1 5 4Bit GPIO_INT1
1715 * B 8 4Bit GPIO_INT2
1716 * C 5 4Bit GPIO_INT3
1717 * D 7 4Bit GPIO_INT4
1718 * E0 8 4Bit GPIO_INT5
1719 * E1 6 4Bit GPIO_INT6
1720 * F0 8 4Bit GPIO_INT7
1721 * F1 8 4Bit GPIO_INT8
1722 * F2 8 4Bit GPIO_INT9
1723 * F3 4 4Bit GPIO_INT10
1724 * G0 8 4Bit GPIO_INT11
1725 * G1 3 4Bit GPIO_INT12
1726 * G2 7 4Bit GPIO_INT13
1727 * G3 7 4Bit GPIO_INT14
1728 * H0 8 4Bit WKUP_INT
1729 * H1 8 4Bit WKUP_INT
1730 * H2 8 4Bit WKUP_INT
1731 * H3 8 4Bit WKUP_INT
1732 * I 8 4Bit GPIO_INT15
1733 * J0 8 4Bit GPIO_INT16
1734 * J1 5 4Bit GPIO_INT17
1735 * J2 8 4Bit GPIO_INT18
1736 * J3 8 4Bit GPIO_INT19
1737 * J4 4 4Bit GPIO_INT20
1748 static struct samsung_gpio_chip s5pc100_gpios_4bit[] = {
1749 #ifdef CONFIG_CPU_S5PC100
1752 .base = S5PC100_GPA0(0),
1753 .ngpio = S5PC100_GPIO_A0_NR,
1758 .base = S5PC100_GPA1(0),
1759 .ngpio = S5PC100_GPIO_A1_NR,
1764 .base = S5PC100_GPB(0),
1765 .ngpio = S5PC100_GPIO_B_NR,
1770 .base = S5PC100_GPC(0),
1771 .ngpio = S5PC100_GPIO_C_NR,
1776 .base = S5PC100_GPD(0),
1777 .ngpio = S5PC100_GPIO_D_NR,
1782 .base = S5PC100_GPE0(0),
1783 .ngpio = S5PC100_GPIO_E0_NR,
1788 .base = S5PC100_GPE1(0),
1789 .ngpio = S5PC100_GPIO_E1_NR,
1794 .base = S5PC100_GPF0(0),
1795 .ngpio = S5PC100_GPIO_F0_NR,
1800 .base = S5PC100_GPF1(0),
1801 .ngpio = S5PC100_GPIO_F1_NR,
1806 .base = S5PC100_GPF2(0),
1807 .ngpio = S5PC100_GPIO_F2_NR,
1812 .base = S5PC100_GPF3(0),
1813 .ngpio = S5PC100_GPIO_F3_NR,
1818 .base = S5PC100_GPG0(0),
1819 .ngpio = S5PC100_GPIO_G0_NR,
1824 .base = S5PC100_GPG1(0),
1825 .ngpio = S5PC100_GPIO_G1_NR,
1830 .base = S5PC100_GPG2(0),
1831 .ngpio = S5PC100_GPIO_G2_NR,
1836 .base = S5PC100_GPG3(0),
1837 .ngpio = S5PC100_GPIO_G3_NR,
1842 .base = S5PC100_GPI(0),
1843 .ngpio = S5PC100_GPIO_I_NR,
1848 .base = S5PC100_GPJ0(0),
1849 .ngpio = S5PC100_GPIO_J0_NR,
1854 .base = S5PC100_GPJ1(0),
1855 .ngpio = S5PC100_GPIO_J1_NR,
1860 .base = S5PC100_GPJ2(0),
1861 .ngpio = S5PC100_GPIO_J2_NR,
1866 .base = S5PC100_GPJ3(0),
1867 .ngpio = S5PC100_GPIO_J3_NR,
1872 .base = S5PC100_GPJ4(0),
1873 .ngpio = S5PC100_GPIO_J4_NR,
1878 .base = S5PC100_GPK0(0),
1879 .ngpio = S5PC100_GPIO_K0_NR,
1884 .base = S5PC100_GPK1(0),
1885 .ngpio = S5PC100_GPIO_K1_NR,
1890 .base = S5PC100_GPK2(0),
1891 .ngpio = S5PC100_GPIO_K2_NR,
1896 .base = S5PC100_GPK3(0),
1897 .ngpio = S5PC100_GPIO_K3_NR,
1902 .base = S5PC100_GPL0(0),
1903 .ngpio = S5PC100_GPIO_L0_NR,
1908 .base = S5PC100_GPL1(0),
1909 .ngpio = S5PC100_GPIO_L1_NR,
1914 .base = S5PC100_GPL2(0),
1915 .ngpio = S5PC100_GPIO_L2_NR,
1920 .base = S5PC100_GPL3(0),
1921 .ngpio = S5PC100_GPIO_L3_NR,
1926 .base = S5PC100_GPL4(0),
1927 .ngpio = S5PC100_GPIO_L4_NR,
1931 .base = (S5P_VA_GPIO + 0xC00),
1932 .irq_base = IRQ_EINT(0),
1934 .base = S5PC100_GPH0(0),
1935 .ngpio = S5PC100_GPIO_H0_NR,
1937 .to_irq = samsung_gpiolib_to_irq,
1940 .base = (S5P_VA_GPIO + 0xC20),
1941 .irq_base = IRQ_EINT(8),
1943 .base = S5PC100_GPH1(0),
1944 .ngpio = S5PC100_GPIO_H1_NR,
1946 .to_irq = samsung_gpiolib_to_irq,
1949 .base = (S5P_VA_GPIO + 0xC40),
1950 .irq_base = IRQ_EINT(16),
1952 .base = S5PC100_GPH2(0),
1953 .ngpio = S5PC100_GPIO_H2_NR,
1955 .to_irq = samsung_gpiolib_to_irq,
1958 .base = (S5P_VA_GPIO + 0xC60),
1959 .irq_base = IRQ_EINT(24),
1961 .base = S5PC100_GPH3(0),
1962 .ngpio = S5PC100_GPIO_H3_NR,
1964 .to_irq = samsung_gpiolib_to_irq,
1971 * Followings are the gpio banks in S5PV210/S5PC110
1973 * The 'config' member when left to NULL, is initialized to the default
1974 * structure samsung_gpio_cfgs[3] in the init function below.
1976 * The 'base' member is also initialized in the init function below.
1977 * Note: The initialization of 'base' member of samsung_gpio_chip structure
1978 * uses the above macro and depends on the banks being listed in order here.
1981 static struct samsung_gpio_chip s5pv210_gpios_4bit[] = {
1982 #ifdef CONFIG_CPU_S5PV210
1985 .base = S5PV210_GPA0(0),
1986 .ngpio = S5PV210_GPIO_A0_NR,
1991 .base = S5PV210_GPA1(0),
1992 .ngpio = S5PV210_GPIO_A1_NR,
1997 .base = S5PV210_GPB(0),
1998 .ngpio = S5PV210_GPIO_B_NR,
2003 .base = S5PV210_GPC0(0),
2004 .ngpio = S5PV210_GPIO_C0_NR,
2009 .base = S5PV210_GPC1(0),
2010 .ngpio = S5PV210_GPIO_C1_NR,
2015 .base = S5PV210_GPD0(0),
2016 .ngpio = S5PV210_GPIO_D0_NR,
2021 .base = S5PV210_GPD1(0),
2022 .ngpio = S5PV210_GPIO_D1_NR,
2027 .base = S5PV210_GPE0(0),
2028 .ngpio = S5PV210_GPIO_E0_NR,
2033 .base = S5PV210_GPE1(0),
2034 .ngpio = S5PV210_GPIO_E1_NR,
2039 .base = S5PV210_GPF0(0),
2040 .ngpio = S5PV210_GPIO_F0_NR,
2045 .base = S5PV210_GPF1(0),
2046 .ngpio = S5PV210_GPIO_F1_NR,
2051 .base = S5PV210_GPF2(0),
2052 .ngpio = S5PV210_GPIO_F2_NR,
2057 .base = S5PV210_GPF3(0),
2058 .ngpio = S5PV210_GPIO_F3_NR,
2063 .base = S5PV210_GPG0(0),
2064 .ngpio = S5PV210_GPIO_G0_NR,
2069 .base = S5PV210_GPG1(0),
2070 .ngpio = S5PV210_GPIO_G1_NR,
2075 .base = S5PV210_GPG2(0),
2076 .ngpio = S5PV210_GPIO_G2_NR,
2081 .base = S5PV210_GPG3(0),
2082 .ngpio = S5PV210_GPIO_G3_NR,
2087 .base = S5PV210_GPI(0),
2088 .ngpio = S5PV210_GPIO_I_NR,
2093 .base = S5PV210_GPJ0(0),
2094 .ngpio = S5PV210_GPIO_J0_NR,
2099 .base = S5PV210_GPJ1(0),
2100 .ngpio = S5PV210_GPIO_J1_NR,
2105 .base = S5PV210_GPJ2(0),
2106 .ngpio = S5PV210_GPIO_J2_NR,
2111 .base = S5PV210_GPJ3(0),
2112 .ngpio = S5PV210_GPIO_J3_NR,
2117 .base = S5PV210_GPJ4(0),
2118 .ngpio = S5PV210_GPIO_J4_NR,
2123 .base = S5PV210_MP01(0),
2124 .ngpio = S5PV210_GPIO_MP01_NR,
2129 .base = S5PV210_MP02(0),
2130 .ngpio = S5PV210_GPIO_MP02_NR,
2135 .base = S5PV210_MP03(0),
2136 .ngpio = S5PV210_GPIO_MP03_NR,
2141 .base = S5PV210_MP04(0),
2142 .ngpio = S5PV210_GPIO_MP04_NR,
2147 .base = S5PV210_MP05(0),
2148 .ngpio = S5PV210_GPIO_MP05_NR,
2152 .base = (S5P_VA_GPIO + 0xC00),
2153 .irq_base = IRQ_EINT(0),
2155 .base = S5PV210_GPH0(0),
2156 .ngpio = S5PV210_GPIO_H0_NR,
2158 .to_irq = samsung_gpiolib_to_irq,
2161 .base = (S5P_VA_GPIO + 0xC20),
2162 .irq_base = IRQ_EINT(8),
2164 .base = S5PV210_GPH1(0),
2165 .ngpio = S5PV210_GPIO_H1_NR,
2167 .to_irq = samsung_gpiolib_to_irq,
2170 .base = (S5P_VA_GPIO + 0xC40),
2171 .irq_base = IRQ_EINT(16),
2173 .base = S5PV210_GPH2(0),
2174 .ngpio = S5PV210_GPIO_H2_NR,
2176 .to_irq = samsung_gpiolib_to_irq,
2179 .base = (S5P_VA_GPIO + 0xC60),
2180 .irq_base = IRQ_EINT(24),
2182 .base = S5PV210_GPH3(0),
2183 .ngpio = S5PV210_GPIO_H3_NR,
2185 .to_irq = samsung_gpiolib_to_irq,
2192 * Followings are the gpio banks in EXYNOS SoCs
2194 * The 'config' member when left to NULL, is initialized to the default
2195 * structure exynos_gpio_cfg in the init function below.
2197 * The 'base' member is also initialized in the init function below.
2198 * Note: The initialization of 'base' member of samsung_gpio_chip structure
2199 * uses the above macro and depends on the banks being listed in order here.
2202 #ifdef CONFIG_ARCH_EXYNOS4
2203 static struct samsung_gpio_chip exynos4_gpios_1[] = {
2206 .base = EXYNOS4_GPA0(0),
2207 .ngpio = EXYNOS4_GPIO_A0_NR,
2212 .base = EXYNOS4_GPA1(0),
2213 .ngpio = EXYNOS4_GPIO_A1_NR,
2218 .base = EXYNOS4_GPB(0),
2219 .ngpio = EXYNOS4_GPIO_B_NR,
2224 .base = EXYNOS4_GPC0(0),
2225 .ngpio = EXYNOS4_GPIO_C0_NR,
2230 .base = EXYNOS4_GPC1(0),
2231 .ngpio = EXYNOS4_GPIO_C1_NR,
2236 .base = EXYNOS4_GPD0(0),
2237 .ngpio = EXYNOS4_GPIO_D0_NR,
2242 .base = EXYNOS4_GPD1(0),
2243 .ngpio = EXYNOS4_GPIO_D1_NR,
2248 .base = EXYNOS4_GPE0(0),
2249 .ngpio = EXYNOS4_GPIO_E0_NR,
2254 .base = EXYNOS4_GPE1(0),
2255 .ngpio = EXYNOS4_GPIO_E1_NR,
2260 .base = EXYNOS4_GPE2(0),
2261 .ngpio = EXYNOS4_GPIO_E2_NR,
2266 .base = EXYNOS4_GPE3(0),
2267 .ngpio = EXYNOS4_GPIO_E3_NR,
2272 .base = EXYNOS4_GPE4(0),
2273 .ngpio = EXYNOS4_GPIO_E4_NR,
2278 .base = EXYNOS4_GPF0(0),
2279 .ngpio = EXYNOS4_GPIO_F0_NR,
2284 .base = EXYNOS4_GPF1(0),
2285 .ngpio = EXYNOS4_GPIO_F1_NR,
2290 .base = EXYNOS4_GPF2(0),
2291 .ngpio = EXYNOS4_GPIO_F2_NR,
2296 .base = EXYNOS4_GPF3(0),
2297 .ngpio = EXYNOS4_GPIO_F3_NR,
2304 #ifdef CONFIG_ARCH_EXYNOS4
2305 static struct samsung_gpio_chip exynos4_gpios_2[] = {
2308 .base = EXYNOS4_GPJ0(0),
2309 .ngpio = EXYNOS4_GPIO_J0_NR,
2314 .base = EXYNOS4_GPJ1(0),
2315 .ngpio = EXYNOS4_GPIO_J1_NR,
2320 .base = EXYNOS4_GPK0(0),
2321 .ngpio = EXYNOS4_GPIO_K0_NR,
2326 .base = EXYNOS4_GPK1(0),
2327 .ngpio = EXYNOS4_GPIO_K1_NR,
2332 .base = EXYNOS4_GPK2(0),
2333 .ngpio = EXYNOS4_GPIO_K2_NR,
2338 .base = EXYNOS4_GPK3(0),
2339 .ngpio = EXYNOS4_GPIO_K3_NR,
2344 .base = EXYNOS4_GPL0(0),
2345 .ngpio = EXYNOS4_GPIO_L0_NR,
2350 .base = EXYNOS4_GPL1(0),
2351 .ngpio = EXYNOS4_GPIO_L1_NR,
2356 .base = EXYNOS4_GPL2(0),
2357 .ngpio = EXYNOS4_GPIO_L2_NR,
2361 .config = &samsung_gpio_cfgs[8],
2363 .base = EXYNOS4_GPY0(0),
2364 .ngpio = EXYNOS4_GPIO_Y0_NR,
2368 .config = &samsung_gpio_cfgs[8],
2370 .base = EXYNOS4_GPY1(0),
2371 .ngpio = EXYNOS4_GPIO_Y1_NR,
2375 .config = &samsung_gpio_cfgs[8],
2377 .base = EXYNOS4_GPY2(0),
2378 .ngpio = EXYNOS4_GPIO_Y2_NR,
2382 .config = &samsung_gpio_cfgs[8],
2384 .base = EXYNOS4_GPY3(0),
2385 .ngpio = EXYNOS4_GPIO_Y3_NR,
2389 .config = &samsung_gpio_cfgs[8],
2391 .base = EXYNOS4_GPY4(0),
2392 .ngpio = EXYNOS4_GPIO_Y4_NR,
2396 .config = &samsung_gpio_cfgs[8],
2398 .base = EXYNOS4_GPY5(0),
2399 .ngpio = EXYNOS4_GPIO_Y5_NR,
2403 .config = &samsung_gpio_cfgs[8],
2405 .base = EXYNOS4_GPY6(0),
2406 .ngpio = EXYNOS4_GPIO_Y6_NR,
2410 .config = &samsung_gpio_cfgs[9],
2411 .irq_base = IRQ_EINT(0),
2413 .base = EXYNOS4_GPX0(0),
2414 .ngpio = EXYNOS4_GPIO_X0_NR,
2416 .to_irq = samsung_gpiolib_to_irq,
2419 .config = &samsung_gpio_cfgs[9],
2420 .irq_base = IRQ_EINT(8),
2422 .base = EXYNOS4_GPX1(0),
2423 .ngpio = EXYNOS4_GPIO_X1_NR,
2425 .to_irq = samsung_gpiolib_to_irq,
2428 .config = &samsung_gpio_cfgs[9],
2429 .irq_base = IRQ_EINT(16),
2431 .base = EXYNOS4_GPX2(0),
2432 .ngpio = EXYNOS4_GPIO_X2_NR,
2434 .to_irq = samsung_gpiolib_to_irq,
2437 .config = &samsung_gpio_cfgs[9],
2438 .irq_base = IRQ_EINT(24),
2440 .base = EXYNOS4_GPX3(0),
2441 .ngpio = EXYNOS4_GPIO_X3_NR,
2443 .to_irq = samsung_gpiolib_to_irq,
2449 #ifdef CONFIG_ARCH_EXYNOS4
2450 static struct samsung_gpio_chip exynos4_gpios_3[] = {
2453 .base = EXYNOS4_GPZ(0),
2454 .ngpio = EXYNOS4_GPIO_Z_NR,
2461 #ifdef CONFIG_ARCH_EXYNOS5
2462 static struct samsung_gpio_chip exynos5_gpios_1[] = {
2465 .base = EXYNOS5_GPA0(0),
2466 .ngpio = EXYNOS5_GPIO_A0_NR,
2471 .base = EXYNOS5_GPA1(0),
2472 .ngpio = EXYNOS5_GPIO_A1_NR,
2477 .base = EXYNOS5_GPA2(0),
2478 .ngpio = EXYNOS5_GPIO_A2_NR,
2483 .base = EXYNOS5_GPB0(0),
2484 .ngpio = EXYNOS5_GPIO_B0_NR,
2489 .base = EXYNOS5_GPB1(0),
2490 .ngpio = EXYNOS5_GPIO_B1_NR,
2495 .base = EXYNOS5_GPB2(0),
2496 .ngpio = EXYNOS5_GPIO_B2_NR,
2501 .base = EXYNOS5_GPB3(0),
2502 .ngpio = EXYNOS5_GPIO_B3_NR,
2507 .base = EXYNOS5_GPC0(0),
2508 .ngpio = EXYNOS5_GPIO_C0_NR,
2513 .base = EXYNOS5_GPC1(0),
2514 .ngpio = EXYNOS5_GPIO_C1_NR,
2519 .base = EXYNOS5_GPC2(0),
2520 .ngpio = EXYNOS5_GPIO_C2_NR,
2525 .base = EXYNOS5_GPC3(0),
2526 .ngpio = EXYNOS5_GPIO_C3_NR,
2531 .base = EXYNOS5_GPD0(0),
2532 .ngpio = EXYNOS5_GPIO_D0_NR,
2537 .base = EXYNOS5_GPD1(0),
2538 .ngpio = EXYNOS5_GPIO_D1_NR,
2543 .base = EXYNOS5_GPY0(0),
2544 .ngpio = EXYNOS5_GPIO_Y0_NR,
2549 .base = EXYNOS5_GPY1(0),
2550 .ngpio = EXYNOS5_GPIO_Y1_NR,
2555 .base = EXYNOS5_GPY2(0),
2556 .ngpio = EXYNOS5_GPIO_Y2_NR,
2561 .base = EXYNOS5_GPY3(0),
2562 .ngpio = EXYNOS5_GPIO_Y3_NR,
2567 .base = EXYNOS5_GPY4(0),
2568 .ngpio = EXYNOS5_GPIO_Y4_NR,
2573 .base = EXYNOS5_GPY5(0),
2574 .ngpio = EXYNOS5_GPIO_Y5_NR,
2579 .base = EXYNOS5_GPY6(0),
2580 .ngpio = EXYNOS5_GPIO_Y6_NR,
2585 .base = EXYNOS5_GPC4(0),
2586 .ngpio = EXYNOS5_GPIO_C4_NR,
2590 .config = &samsung_gpio_cfgs[9],
2591 .irq_base = IRQ_EINT(0),
2593 .base = EXYNOS5_GPX0(0),
2594 .ngpio = EXYNOS5_GPIO_X0_NR,
2596 .to_irq = samsung_gpiolib_to_irq,
2599 .config = &samsung_gpio_cfgs[9],
2600 .irq_base = IRQ_EINT(8),
2602 .base = EXYNOS5_GPX1(0),
2603 .ngpio = EXYNOS5_GPIO_X1_NR,
2605 .to_irq = samsung_gpiolib_to_irq,
2608 .config = &samsung_gpio_cfgs[9],
2609 .irq_base = IRQ_EINT(16),
2611 .base = EXYNOS5_GPX2(0),
2612 .ngpio = EXYNOS5_GPIO_X2_NR,
2614 .to_irq = samsung_gpiolib_to_irq,
2617 .config = &samsung_gpio_cfgs[9],
2618 .irq_base = IRQ_EINT(24),
2620 .base = EXYNOS5_GPX3(0),
2621 .ngpio = EXYNOS5_GPIO_X3_NR,
2623 .to_irq = samsung_gpiolib_to_irq,
2629 #ifdef CONFIG_ARCH_EXYNOS5
2630 static struct samsung_gpio_chip exynos5_gpios_2[] = {
2633 .base = EXYNOS5_GPE0(0),
2634 .ngpio = EXYNOS5_GPIO_E0_NR,
2639 .base = EXYNOS5_GPE1(0),
2640 .ngpio = EXYNOS5_GPIO_E1_NR,
2645 .base = EXYNOS5_GPF0(0),
2646 .ngpio = EXYNOS5_GPIO_F0_NR,
2651 .base = EXYNOS5_GPF1(0),
2652 .ngpio = EXYNOS5_GPIO_F1_NR,
2657 .base = EXYNOS5_GPG0(0),
2658 .ngpio = EXYNOS5_GPIO_G0_NR,
2663 .base = EXYNOS5_GPG1(0),
2664 .ngpio = EXYNOS5_GPIO_G1_NR,
2669 .base = EXYNOS5_GPG2(0),
2670 .ngpio = EXYNOS5_GPIO_G2_NR,
2675 .base = EXYNOS5_GPH0(0),
2676 .ngpio = EXYNOS5_GPIO_H0_NR,
2681 .base = EXYNOS5_GPH1(0),
2682 .ngpio = EXYNOS5_GPIO_H1_NR,
2690 #ifdef CONFIG_ARCH_EXYNOS5
2691 static struct samsung_gpio_chip exynos5_gpios_3[] = {
2694 .base = EXYNOS5_GPV0(0),
2695 .ngpio = EXYNOS5_GPIO_V0_NR,
2700 .base = EXYNOS5_GPV1(0),
2701 .ngpio = EXYNOS5_GPIO_V1_NR,
2706 .base = EXYNOS5_GPV2(0),
2707 .ngpio = EXYNOS5_GPIO_V2_NR,
2712 .base = EXYNOS5_GPV3(0),
2713 .ngpio = EXYNOS5_GPIO_V3_NR,
2718 .base = EXYNOS5_GPV4(0),
2719 .ngpio = EXYNOS5_GPIO_V4_NR,
2726 #ifdef CONFIG_ARCH_EXYNOS5
2727 static struct samsung_gpio_chip exynos5_gpios_4[] = {
2730 .base = EXYNOS5_GPZ(0),
2731 .ngpio = EXYNOS5_GPIO_Z_NR,
2739 #if defined(CONFIG_ARCH_EXYNOS) && defined(CONFIG_OF)
2740 static int exynos_gpio_xlate(struct gpio_chip *gc,
2741 const struct of_phandle_args *gpiospec, u32 *flags)
2745 if (WARN_ON(gc->of_gpio_n_cells < 4))
2748 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
2751 if (gpiospec->args[0] > gc->ngpio)
2754 pin = gc->base + gpiospec->args[0];
2756 if (s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(gpiospec->args[1])))
2757 pr_warn("gpio_xlate: failed to set pin function\n");
2758 if (s3c_gpio_setpull(pin, gpiospec->args[2] & 0xffff))
2759 pr_warn("gpio_xlate: failed to set pin pull up/down\n");
2760 if (s5p_gpio_set_drvstr(pin, gpiospec->args[3]))
2761 pr_warn("gpio_xlate: failed to set pin drive strength\n");
2763 /* flags are the upper 16 bits of the pull up/down cell, and currently
2764 * they correspond to the of_gpio_flags so we can just do a straight
2768 *flags = gpiospec->args[2] >> 16;
2770 return gpiospec->args[0];
2773 static const struct of_device_id exynos_gpio_dt_match[] __initdata = {
2774 { .compatible = "samsung,exynos4-gpio", },
2778 static __init void exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
2779 u64 base, u64 offset)
2781 struct gpio_chip *gc = &chip->chip;
2784 if (!of_have_populated_dt())
2787 address = chip->base ? base + ((u32)chip->base & 0xfff) : base + offset;
2788 gc->of_node = of_find_matching_node_by_address(NULL,
2789 exynos_gpio_dt_match, address);
2791 pr_info("gpio: device tree node not found for gpio controller"
2792 " with base address %08llx\n", address);
2795 gc->of_gpio_n_cells = 4;
2796 gc->of_xlate = exynos_gpio_xlate;
2798 #elif defined(CONFIG_ARCH_EXYNOS)
2799 static __init void exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
2800 u64 base, u64 offset)
2804 #endif /* defined(CONFIG_ARCH_EXYNOS) && defined(CONFIG_OF) */
2806 /* TODO: cleanup soc_is_* */
2807 static __init int samsung_gpiolib_init(void)
2809 struct samsung_gpio_chip *chip;
2811 #if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS5250)
2812 void __iomem *gpio_base1, *gpio_base2, *gpio_base3, *gpio_base4;
2816 samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs));
2818 if (soc_is_s3c24xx()) {
2819 s3c24xx_gpiolib_add_chips(s3c24xx_gpios,
2820 ARRAY_SIZE(s3c24xx_gpios), S3C24XX_VA_GPIO);
2821 } else if (soc_is_s3c64xx()) {
2822 samsung_gpiolib_add_2bit_chips(s3c64xx_gpios_2bit,
2823 ARRAY_SIZE(s3c64xx_gpios_2bit),
2824 S3C64XX_VA_GPIO + 0xE0, 0x20);
2825 samsung_gpiolib_add_4bit_chips(s3c64xx_gpios_4bit,
2826 ARRAY_SIZE(s3c64xx_gpios_4bit),
2828 samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2,
2829 ARRAY_SIZE(s3c64xx_gpios_4bit2));
2830 } else if (soc_is_s5p6440()) {
2831 samsung_gpiolib_add_2bit_chips(s5p6440_gpios_2bit,
2832 ARRAY_SIZE(s5p6440_gpios_2bit), NULL, 0x0);
2833 samsung_gpiolib_add_4bit_chips(s5p6440_gpios_4bit,
2834 ARRAY_SIZE(s5p6440_gpios_4bit), S5P_VA_GPIO);
2835 samsung_gpiolib_add_4bit2_chips(s5p6440_gpios_4bit2,
2836 ARRAY_SIZE(s5p6440_gpios_4bit2));
2837 s5p64x0_gpiolib_add_rbank(s5p6440_gpios_rbank,
2838 ARRAY_SIZE(s5p6440_gpios_rbank));
2839 } else if (soc_is_s5p6450()) {
2840 samsung_gpiolib_add_2bit_chips(s5p6450_gpios_2bit,
2841 ARRAY_SIZE(s5p6450_gpios_2bit), NULL, 0x0);
2842 samsung_gpiolib_add_4bit_chips(s5p6450_gpios_4bit,
2843 ARRAY_SIZE(s5p6450_gpios_4bit), S5P_VA_GPIO);
2844 samsung_gpiolib_add_4bit2_chips(s5p6450_gpios_4bit2,
2845 ARRAY_SIZE(s5p6450_gpios_4bit2));
2846 s5p64x0_gpiolib_add_rbank(s5p6450_gpios_rbank,
2847 ARRAY_SIZE(s5p6450_gpios_rbank));
2848 } else if (soc_is_s5pc100()) {
2850 chip = s5pc100_gpios_4bit;
2851 nr_chips = ARRAY_SIZE(s5pc100_gpios_4bit);
2853 for (i = 0; i < nr_chips; i++, chip++) {
2854 if (!chip->config) {
2855 chip->config = &samsung_gpio_cfgs[3];
2856 chip->group = group++;
2859 samsung_gpiolib_add_4bit_chips(s5pc100_gpios_4bit, nr_chips, S5P_VA_GPIO);
2860 #if defined(CONFIG_CPU_S5PC100) && defined(CONFIG_S5P_GPIO_INT)
2861 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
2863 } else if (soc_is_s5pv210()) {
2865 chip = s5pv210_gpios_4bit;
2866 nr_chips = ARRAY_SIZE(s5pv210_gpios_4bit);
2868 for (i = 0; i < nr_chips; i++, chip++) {
2869 if (!chip->config) {
2870 chip->config = &samsung_gpio_cfgs[3];
2871 chip->group = group++;
2874 samsung_gpiolib_add_4bit_chips(s5pv210_gpios_4bit, nr_chips, S5P_VA_GPIO);
2875 #if defined(CONFIG_CPU_S5PV210) && defined(CONFIG_S5P_GPIO_INT)
2876 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
2878 } else if (soc_is_exynos4210()) {
2879 #ifdef CONFIG_CPU_EXYNOS4210
2880 void __iomem *gpx_base;
2883 gpio_base1 = ioremap(EXYNOS4_PA_GPIO1, SZ_4K);
2884 if (gpio_base1 == NULL) {
2885 pr_err("unable to ioremap for gpio_base1\n");
2889 chip = exynos4_gpios_1;
2890 nr_chips = ARRAY_SIZE(exynos4_gpios_1);
2892 for (i = 0; i < nr_chips; i++, chip++) {
2893 if (!chip->config) {
2894 chip->config = &exynos_gpio_cfg;
2895 chip->group = group++;
2897 exynos_gpiolib_attach_ofnode(chip,
2898 EXYNOS4_PA_GPIO1, i * 0x20);
2900 samsung_gpiolib_add_4bit_chips(exynos4_gpios_1,
2901 nr_chips, gpio_base1);
2904 gpio_base2 = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
2905 if (gpio_base2 == NULL) {
2906 pr_err("unable to ioremap for gpio_base2\n");
2910 /* need to set base address for gpx */
2911 chip = &exynos4_gpios_2[16];
2912 gpx_base = gpio_base2 + 0xC00;
2913 for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
2914 chip->base = gpx_base;
2916 chip = exynos4_gpios_2;
2917 nr_chips = ARRAY_SIZE(exynos4_gpios_2);
2919 for (i = 0; i < nr_chips; i++, chip++) {
2920 if (!chip->config) {
2921 chip->config = &exynos_gpio_cfg;
2922 chip->group = group++;
2924 exynos_gpiolib_attach_ofnode(chip,
2925 EXYNOS4_PA_GPIO2, i * 0x20);
2927 samsung_gpiolib_add_4bit_chips(exynos4_gpios_2,
2928 nr_chips, gpio_base2);
2931 gpio_base3 = ioremap(EXYNOS4_PA_GPIO3, SZ_256);
2932 if (gpio_base3 == NULL) {
2933 pr_err("unable to ioremap for gpio_base3\n");
2937 chip = exynos4_gpios_3;
2938 nr_chips = ARRAY_SIZE(exynos4_gpios_3);
2940 for (i = 0; i < nr_chips; i++, chip++) {
2941 if (!chip->config) {
2942 chip->config = &exynos_gpio_cfg;
2943 chip->group = group++;
2945 exynos_gpiolib_attach_ofnode(chip,
2946 EXYNOS4_PA_GPIO3, i * 0x20);
2948 samsung_gpiolib_add_4bit_chips(exynos4_gpios_3,
2949 nr_chips, gpio_base3);
2951 #if defined(CONFIG_CPU_EXYNOS4210) && defined(CONFIG_S5P_GPIO_INT)
2952 s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS);
2953 s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS);
2956 #endif /* CONFIG_CPU_EXYNOS4210 */
2957 } else if (soc_is_exynos5250()) {
2958 #ifdef CONFIG_SOC_EXYNOS5250
2959 void __iomem *gpx_base;
2962 gpio_base1 = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
2963 if (gpio_base1 == NULL) {
2964 pr_err("unable to ioremap for gpio_base1\n");
2968 /* need to set base address for gpc4 */
2969 exynos5_gpios_1[20].base = gpio_base1 + 0x2E0;
2971 /* need to set base address for gpx */
2972 chip = &exynos5_gpios_1[21];
2973 gpx_base = gpio_base1 + 0xC00;
2974 for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
2975 chip->base = gpx_base;
2977 chip = exynos5_gpios_1;
2978 nr_chips = ARRAY_SIZE(exynos5_gpios_1);
2980 for (i = 0; i < nr_chips; i++, chip++) {
2981 if (!chip->config) {
2982 chip->config = &exynos_gpio_cfg;
2983 chip->group = group++;
2985 exynos_gpiolib_attach_ofnode(chip,
2986 EXYNOS5_PA_GPIO1, i * 0x20);
2988 samsung_gpiolib_add_4bit_chips(exynos5_gpios_1,
2989 nr_chips, gpio_base1);
2992 gpio_base2 = ioremap(EXYNOS5_PA_GPIO2, SZ_4K);
2993 if (gpio_base2 == NULL) {
2994 pr_err("unable to ioremap for gpio_base2\n");
2998 chip = exynos5_gpios_2;
2999 nr_chips = ARRAY_SIZE(exynos5_gpios_2);
3001 for (i = 0; i < nr_chips; i++, chip++) {
3002 if (!chip->config) {
3003 chip->config = &exynos_gpio_cfg;
3004 chip->group = group++;
3006 exynos_gpiolib_attach_ofnode(chip,
3007 EXYNOS5_PA_GPIO2, i * 0x20);
3009 samsung_gpiolib_add_4bit_chips(exynos5_gpios_2,
3010 nr_chips, gpio_base2);
3013 gpio_base3 = ioremap(EXYNOS5_PA_GPIO3, SZ_4K);
3014 if (gpio_base3 == NULL) {
3015 pr_err("unable to ioremap for gpio_base3\n");
3019 /* need to set base address for gpv */
3020 exynos5_gpios_3[0].base = gpio_base3;
3021 exynos5_gpios_3[1].base = gpio_base3 + 0x20;
3022 exynos5_gpios_3[2].base = gpio_base3 + 0x60;
3023 exynos5_gpios_3[3].base = gpio_base3 + 0x80;
3024 exynos5_gpios_3[4].base = gpio_base3 + 0xC0;
3026 chip = exynos5_gpios_3;
3027 nr_chips = ARRAY_SIZE(exynos5_gpios_3);
3029 for (i = 0; i < nr_chips; i++, chip++) {
3030 if (!chip->config) {
3031 chip->config = &exynos_gpio_cfg;
3032 chip->group = group++;
3034 exynos_gpiolib_attach_ofnode(chip,
3035 EXYNOS5_PA_GPIO3, i * 0x20);
3037 samsung_gpiolib_add_4bit_chips(exynos5_gpios_3,
3038 nr_chips, gpio_base3);
3041 gpio_base4 = ioremap(EXYNOS5_PA_GPIO4, SZ_4K);
3042 if (gpio_base4 == NULL) {
3043 pr_err("unable to ioremap for gpio_base4\n");
3047 chip = exynos5_gpios_4;
3048 nr_chips = ARRAY_SIZE(exynos5_gpios_4);
3050 for (i = 0; i < nr_chips; i++, chip++) {
3051 if (!chip->config) {
3052 chip->config = &exynos_gpio_cfg;
3053 chip->group = group++;
3055 exynos_gpiolib_attach_ofnode(chip,
3056 EXYNOS5_PA_GPIO4, i * 0x20);
3058 samsung_gpiolib_add_4bit_chips(exynos5_gpios_4,
3059 nr_chips, gpio_base4);
3060 #ifdef CONFIG_S5P_GPIO_INT
3061 s5p_register_gpioint_bank(EXYNOS5_IRQ_GPIO_XA, 0,
3062 EXYNOS5_IRQ_GPIO1_NR_GROUPS);
3063 s5p_register_gpioint_bank(EXYNOS5_IRQ_GPIO_XB,
3064 EXYNOS5_IRQ_GPIO1_NR_GROUPS,
3065 EXYNOS5_IRQ_GPIO2_NR_GROUPS);
3067 #endif /* CONFIG_SOC_EXYNOS5250 */
3069 WARN(1, "Unknown SoC in gpio-samsung, no GPIOs added\n");
3075 #if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS5250)
3077 iounmap(gpio_base3);
3079 iounmap(gpio_base2);
3081 iounmap(gpio_base1);
3086 core_initcall(samsung_gpiolib_init);
3088 int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
3090 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3091 unsigned long flags;
3098 offset = pin - chip->chip.base;
3100 samsung_gpio_lock(chip, flags);
3101 ret = samsung_gpio_do_setcfg(chip, offset, config);
3102 samsung_gpio_unlock(chip, flags);
3106 EXPORT_SYMBOL(s3c_gpio_cfgpin);
3108 int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
3113 for (; nr > 0; nr--, start++) {
3114 ret = s3c_gpio_cfgpin(start, cfg);
3121 EXPORT_SYMBOL_GPL(s3c_gpio_cfgpin_range);
3123 int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr,
3124 unsigned int cfg, samsung_gpio_pull_t pull)
3128 for (; nr > 0; nr--, start++) {
3129 s3c_gpio_setpull(start, pull);
3130 ret = s3c_gpio_cfgpin(start, cfg);
3137 EXPORT_SYMBOL_GPL(s3c_gpio_cfgall_range);
3139 unsigned s3c_gpio_getcfg(unsigned int pin)
3141 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3142 unsigned long flags;
3147 offset = pin - chip->chip.base;
3149 samsung_gpio_lock(chip, flags);
3150 ret = samsung_gpio_do_getcfg(chip, offset);
3151 samsung_gpio_unlock(chip, flags);
3156 EXPORT_SYMBOL(s3c_gpio_getcfg);
3158 int s3c_gpio_setpull(unsigned int pin, samsung_gpio_pull_t pull)
3160 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3161 unsigned long flags;
3167 offset = pin - chip->chip.base;
3169 samsung_gpio_lock(chip, flags);
3170 ret = samsung_gpio_do_setpull(chip, offset, pull);
3171 samsung_gpio_unlock(chip, flags);
3175 EXPORT_SYMBOL(s3c_gpio_setpull);
3177 samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin)
3179 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3180 unsigned long flags;
3185 offset = pin - chip->chip.base;
3187 samsung_gpio_lock(chip, flags);
3188 pup = samsung_gpio_do_getpull(chip, offset);
3189 samsung_gpio_unlock(chip, flags);
3192 return (__force samsung_gpio_pull_t)pup;
3194 EXPORT_SYMBOL(s3c_gpio_getpull);
3196 /* gpiolib wrappers until these are totally eliminated */
3198 void s3c2410_gpio_pullup(unsigned int pin, unsigned int to)
3202 WARN_ON(to); /* should be none of these left */
3205 /* if pull is enabled, try first with up, and if that
3206 * fails, try using down */
3208 ret = s3c_gpio_setpull(pin, S3C_GPIO_PULL_UP);
3210 s3c_gpio_setpull(pin, S3C_GPIO_PULL_DOWN);
3212 s3c_gpio_setpull(pin, S3C_GPIO_PULL_NONE);
3215 EXPORT_SYMBOL(s3c2410_gpio_pullup);
3217 void s3c2410_gpio_setpin(unsigned int pin, unsigned int to)
3219 /* do this via gpiolib until all users removed */
3221 gpio_request(pin, "temporary");
3222 gpio_set_value(pin, to);
3225 EXPORT_SYMBOL(s3c2410_gpio_setpin);
3227 unsigned int s3c2410_gpio_getpin(unsigned int pin)
3229 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3230 unsigned long offs = pin - chip->chip.base;
3232 return __raw_readl(chip->base + 0x04) & (1 << offs);
3234 EXPORT_SYMBOL(s3c2410_gpio_getpin);
3236 #ifdef CONFIG_S5P_GPIO_DRVSTR
3237 s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin)
3239 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3248 off = pin - chip->chip.base;
3250 reg = chip->base + 0x0C;
3252 drvstr = __raw_readl(reg);
3253 drvstr = drvstr >> shift;
3256 return (__force s5p_gpio_drvstr_t)drvstr;
3258 EXPORT_SYMBOL(s5p_gpio_get_drvstr);
3260 int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr)
3262 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3271 off = pin - chip->chip.base;
3273 reg = chip->base + 0x0C;
3275 tmp = __raw_readl(reg);
3276 tmp &= ~(0x3 << shift);
3277 tmp |= drvstr << shift;
3279 __raw_writel(tmp, reg);
3283 EXPORT_SYMBOL(s5p_gpio_set_drvstr);
3284 #endif /* CONFIG_S5P_GPIO_DRVSTR */
3286 #ifdef CONFIG_PLAT_S3C24XX
3287 unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
3289 unsigned long flags;
3290 unsigned long misccr;
3292 local_irq_save(flags);
3293 misccr = __raw_readl(S3C24XX_MISCCR);
3296 __raw_writel(misccr, S3C24XX_MISCCR);
3297 local_irq_restore(flags);
3301 EXPORT_SYMBOL(s3c2410_modify_misccr);