2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/amdgpu_drm.h>
29 #include "amdgpu_atombios.h"
30 #include "amdgpu_i2c.h"
33 #include "atom-bits.h"
34 #include "atombios_encoders.h"
35 #include "bif/bif_4_1_d.h"
37 static void amdgpu_atombios_lookup_i2c_gpio_quirks(struct amdgpu_device *adev,
38 ATOM_GPIO_I2C_ASSIGMENT *gpio,
44 static struct amdgpu_i2c_bus_rec amdgpu_atombios_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
46 struct amdgpu_i2c_bus_rec i2c;
48 memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec));
50 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex);
51 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex);
52 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex);
53 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex);
54 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex);
55 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex);
56 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex);
57 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex);
58 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
59 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
60 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
61 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
62 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
63 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
64 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
65 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
67 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
68 i2c.hw_capable = true;
70 i2c.hw_capable = false;
72 if (gpio->sucI2cId.ucAccess == 0xa0)
77 i2c.i2c_id = gpio->sucI2cId.ucAccess;
87 struct amdgpu_i2c_bus_rec amdgpu_atombios_lookup_i2c_gpio(struct amdgpu_device *adev,
90 struct atom_context *ctx = adev->mode_info.atom_context;
91 ATOM_GPIO_I2C_ASSIGMENT *gpio;
92 struct amdgpu_i2c_bus_rec i2c;
93 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
94 struct _ATOM_GPIO_I2C_INFO *i2c_info;
95 uint16_t data_offset, size;
98 memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec));
101 if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
102 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
104 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
105 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
107 gpio = &i2c_info->asGPIO_Info[0];
108 for (i = 0; i < num_indices; i++) {
110 amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i);
112 if (gpio->sucI2cId.ucAccess == id) {
113 i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio);
116 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
117 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
124 void amdgpu_atombios_i2c_init(struct amdgpu_device *adev)
126 struct atom_context *ctx = adev->mode_info.atom_context;
127 ATOM_GPIO_I2C_ASSIGMENT *gpio;
128 struct amdgpu_i2c_bus_rec i2c;
129 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
130 struct _ATOM_GPIO_I2C_INFO *i2c_info;
131 uint16_t data_offset, size;
135 if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
136 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
138 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
139 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
141 gpio = &i2c_info->asGPIO_Info[0];
142 for (i = 0; i < num_indices; i++) {
143 amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i);
145 i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio);
148 sprintf(stmp, "0x%x", i2c.i2c_id);
149 adev->i2c_bus[i] = amdgpu_i2c_create(adev->ddev, &i2c, stmp);
151 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
152 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
157 struct amdgpu_gpio_rec
158 amdgpu_atombios_lookup_gpio(struct amdgpu_device *adev,
161 struct atom_context *ctx = adev->mode_info.atom_context;
162 struct amdgpu_gpio_rec gpio;
163 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
164 struct _ATOM_GPIO_PIN_LUT *gpio_info;
165 ATOM_GPIO_PIN_ASSIGNMENT *pin;
166 u16 data_offset, size;
169 memset(&gpio, 0, sizeof(struct amdgpu_gpio_rec));
172 if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
173 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
175 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
176 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
178 pin = gpio_info->asGPIO_Pin;
179 for (i = 0; i < num_indices; i++) {
180 if (id == pin->ucGPIO_ID) {
181 gpio.id = pin->ucGPIO_ID;
182 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex);
183 gpio.shift = pin->ucGpioPinBitShift;
184 gpio.mask = (1 << pin->ucGpioPinBitShift);
188 pin = (ATOM_GPIO_PIN_ASSIGNMENT *)
189 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));
196 static struct amdgpu_hpd
197 amdgpu_atombios_get_hpd_info_from_gpio(struct amdgpu_device *adev,
198 struct amdgpu_gpio_rec *gpio)
200 struct amdgpu_hpd hpd;
203 memset(&hpd, 0, sizeof(struct amdgpu_hpd));
205 reg = amdgpu_display_hpd_get_gpio_reg(adev);
208 if (gpio->reg == reg) {
211 hpd.hpd = AMDGPU_HPD_1;
214 hpd.hpd = AMDGPU_HPD_2;
217 hpd.hpd = AMDGPU_HPD_3;
220 hpd.hpd = AMDGPU_HPD_4;
223 hpd.hpd = AMDGPU_HPD_5;
226 hpd.hpd = AMDGPU_HPD_6;
229 hpd.hpd = AMDGPU_HPD_NONE;
233 hpd.hpd = AMDGPU_HPD_NONE;
237 static const int object_connector_convert[] = {
238 DRM_MODE_CONNECTOR_Unknown,
239 DRM_MODE_CONNECTOR_DVII,
240 DRM_MODE_CONNECTOR_DVII,
241 DRM_MODE_CONNECTOR_DVID,
242 DRM_MODE_CONNECTOR_DVID,
243 DRM_MODE_CONNECTOR_VGA,
244 DRM_MODE_CONNECTOR_Composite,
245 DRM_MODE_CONNECTOR_SVIDEO,
246 DRM_MODE_CONNECTOR_Unknown,
247 DRM_MODE_CONNECTOR_Unknown,
248 DRM_MODE_CONNECTOR_9PinDIN,
249 DRM_MODE_CONNECTOR_Unknown,
250 DRM_MODE_CONNECTOR_HDMIA,
251 DRM_MODE_CONNECTOR_HDMIB,
252 DRM_MODE_CONNECTOR_LVDS,
253 DRM_MODE_CONNECTOR_9PinDIN,
254 DRM_MODE_CONNECTOR_Unknown,
255 DRM_MODE_CONNECTOR_Unknown,
256 DRM_MODE_CONNECTOR_Unknown,
257 DRM_MODE_CONNECTOR_DisplayPort,
258 DRM_MODE_CONNECTOR_eDP,
259 DRM_MODE_CONNECTOR_Unknown
262 bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *adev)
264 struct amdgpu_mode_info *mode_info = &adev->mode_info;
265 struct atom_context *ctx = mode_info->atom_context;
266 int index = GetIndexIntoMasterTable(DATA, Object_Header);
267 u16 size, data_offset;
269 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
270 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
271 ATOM_OBJECT_TABLE *router_obj;
272 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
273 ATOM_OBJECT_HEADER *obj_header;
274 int i, j, k, path_size, device_support;
276 u16 conn_id, connector_object_id;
277 struct amdgpu_i2c_bus_rec ddc_bus;
278 struct amdgpu_router router;
279 struct amdgpu_gpio_rec gpio;
280 struct amdgpu_hpd hpd;
282 if (!amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
288 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
289 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
290 (ctx->bios + data_offset +
291 le16_to_cpu(obj_header->usDisplayPathTableOffset));
292 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
293 (ctx->bios + data_offset +
294 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
295 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
296 (ctx->bios + data_offset +
297 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
298 router_obj = (ATOM_OBJECT_TABLE *)
299 (ctx->bios + data_offset +
300 le16_to_cpu(obj_header->usRouterObjectTableOffset));
301 device_support = le16_to_cpu(obj_header->usDeviceSupport);
304 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
305 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
306 ATOM_DISPLAY_OBJECT_PATH *path;
308 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
309 path_size += le16_to_cpu(path->usSize);
311 if (device_support & le16_to_cpu(path->usDeviceTag)) {
312 uint8_t con_obj_id, con_obj_num, con_obj_type;
315 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
318 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
321 (le16_to_cpu(path->usConnObjectId) &
322 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
324 /* Skip TV/CV support */
325 if ((le16_to_cpu(path->usDeviceTag) ==
326 ATOM_DEVICE_TV1_SUPPORT) ||
327 (le16_to_cpu(path->usDeviceTag) ==
328 ATOM_DEVICE_CV_SUPPORT))
331 if (con_obj_id >= ARRAY_SIZE(object_connector_convert)) {
332 DRM_ERROR("invalid con_obj_id %d for device tag 0x%04x\n",
333 con_obj_id, le16_to_cpu(path->usDeviceTag));
338 object_connector_convert[con_obj_id];
339 connector_object_id = con_obj_id;
341 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
344 router.ddc_valid = false;
345 router.cd_valid = false;
346 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
347 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
350 (le16_to_cpu(path->usGraphicObjIds[j]) &
351 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
353 (le16_to_cpu(path->usGraphicObjIds[j]) &
354 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
356 (le16_to_cpu(path->usGraphicObjIds[j]) &
357 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
359 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
360 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
361 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
362 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
363 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
364 (ctx->bios + data_offset +
365 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
366 ATOM_ENCODER_CAP_RECORD *cap_record;
369 while (record->ucRecordSize > 0 &&
370 record->ucRecordType > 0 &&
371 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
372 switch (record->ucRecordType) {
373 case ATOM_ENCODER_CAP_RECORD_TYPE:
374 cap_record =(ATOM_ENCODER_CAP_RECORD *)
376 caps = le16_to_cpu(cap_record->usEncoderCap);
379 record = (ATOM_COMMON_RECORD_HEADER *)
380 ((char *)record + record->ucRecordSize);
382 amdgpu_display_add_encoder(adev, encoder_obj,
383 le16_to_cpu(path->usDeviceTag),
387 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
388 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
389 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
390 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
391 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
392 (ctx->bios + data_offset +
393 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
394 ATOM_I2C_RECORD *i2c_record;
395 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
396 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
397 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
398 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
399 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
400 (ctx->bios + data_offset +
401 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
402 u8 *num_dst_objs = (u8 *)
403 ((u8 *)router_src_dst_table + 1 +
404 (router_src_dst_table->ucNumberOfSrc * 2));
405 u16 *dst_objs = (u16 *)(num_dst_objs + 1);
408 router.router_id = router_obj_id;
409 for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
410 if (le16_to_cpu(path->usConnObjectId) ==
411 le16_to_cpu(dst_objs[enum_id]))
415 while (record->ucRecordSize > 0 &&
416 record->ucRecordType > 0 &&
417 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
418 switch (record->ucRecordType) {
419 case ATOM_I2C_RECORD_TYPE:
424 (ATOM_I2C_ID_CONFIG_ACCESS *)
425 &i2c_record->sucI2cId;
427 amdgpu_atombios_lookup_i2c_gpio(adev,
430 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
432 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
433 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
435 router.ddc_valid = true;
436 router.ddc_mux_type = ddc_path->ucMuxType;
437 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
438 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
440 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
441 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
443 router.cd_valid = true;
444 router.cd_mux_type = cd_path->ucMuxType;
445 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
446 router.cd_mux_state = cd_path->ucMuxState[enum_id];
449 record = (ATOM_COMMON_RECORD_HEADER *)
450 ((char *)record + record->ucRecordSize);
457 /* look up gpio for ddc, hpd */
458 ddc_bus.valid = false;
459 hpd.hpd = AMDGPU_HPD_NONE;
460 if ((le16_to_cpu(path->usDeviceTag) &
461 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
462 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
463 if (le16_to_cpu(path->usConnObjectId) ==
464 le16_to_cpu(con_obj->asObjects[j].
466 ATOM_COMMON_RECORD_HEADER
468 (ATOM_COMMON_RECORD_HEADER
470 (ctx->bios + data_offset +
471 le16_to_cpu(con_obj->
474 ATOM_I2C_RECORD *i2c_record;
475 ATOM_HPD_INT_RECORD *hpd_record;
476 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
478 while (record->ucRecordSize > 0 &&
479 record->ucRecordType > 0 &&
480 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
481 switch (record->ucRecordType) {
482 case ATOM_I2C_RECORD_TYPE:
487 (ATOM_I2C_ID_CONFIG_ACCESS *)
488 &i2c_record->sucI2cId;
489 ddc_bus = amdgpu_atombios_lookup_i2c_gpio(adev,
493 case ATOM_HPD_INT_RECORD_TYPE:
495 (ATOM_HPD_INT_RECORD *)
497 gpio = amdgpu_atombios_lookup_gpio(adev,
498 hpd_record->ucHPDIntGPIOID);
499 hpd = amdgpu_atombios_get_hpd_info_from_gpio(adev, &gpio);
500 hpd.plugged_state = hpd_record->ucPlugged_PinState;
504 (ATOM_COMMON_RECORD_HEADER
515 /* needed for aux chan transactions */
516 ddc_bus.hpd = hpd.hpd;
518 conn_id = le16_to_cpu(path->usConnObjectId);
520 amdgpu_display_add_connector(adev,
522 le16_to_cpu(path->usDeviceTag),
523 connector_type, &ddc_bus,
531 amdgpu_link_encoder_connector(adev->ddev);
536 union firmware_info {
537 ATOM_FIRMWARE_INFO info;
538 ATOM_FIRMWARE_INFO_V1_2 info_12;
539 ATOM_FIRMWARE_INFO_V1_3 info_13;
540 ATOM_FIRMWARE_INFO_V1_4 info_14;
541 ATOM_FIRMWARE_INFO_V2_1 info_21;
542 ATOM_FIRMWARE_INFO_V2_2 info_22;
545 int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev)
547 struct amdgpu_mode_info *mode_info = &adev->mode_info;
548 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
550 uint16_t data_offset;
553 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
554 &frev, &crev, &data_offset)) {
556 struct amdgpu_pll *ppll = &adev->clock.ppll[0];
557 struct amdgpu_pll *spll = &adev->clock.spll;
558 struct amdgpu_pll *mpll = &adev->clock.mpll;
559 union firmware_info *firmware_info =
560 (union firmware_info *)(mode_info->atom_context->bios +
563 ppll->reference_freq =
564 le16_to_cpu(firmware_info->info.usReferenceClock);
565 ppll->reference_div = 0;
568 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
570 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
572 ppll->lcd_pll_out_min =
573 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
574 if (ppll->lcd_pll_out_min == 0)
575 ppll->lcd_pll_out_min = ppll->pll_out_min;
576 ppll->lcd_pll_out_max =
577 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
578 if (ppll->lcd_pll_out_max == 0)
579 ppll->lcd_pll_out_max = ppll->pll_out_max;
581 if (ppll->pll_out_min == 0)
582 ppll->pll_out_min = 64800;
585 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
587 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
589 ppll->min_post_div = 2;
590 ppll->max_post_div = 0x7f;
591 ppll->min_frac_feedback_div = 0;
592 ppll->max_frac_feedback_div = 9;
593 ppll->min_ref_div = 2;
594 ppll->max_ref_div = 0x3ff;
595 ppll->min_feedback_div = 4;
596 ppll->max_feedback_div = 0xfff;
599 for (i = 1; i < AMDGPU_MAX_PPLL; i++)
600 adev->clock.ppll[i] = *ppll;
603 spll->reference_freq =
604 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
605 spll->reference_div = 0;
608 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
610 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
613 if (spll->pll_out_min == 0)
614 spll->pll_out_min = 64800;
617 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
619 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
621 spll->min_post_div = 1;
622 spll->max_post_div = 1;
623 spll->min_ref_div = 2;
624 spll->max_ref_div = 0xff;
625 spll->min_feedback_div = 4;
626 spll->max_feedback_div = 0xff;
630 mpll->reference_freq =
631 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
632 mpll->reference_div = 0;
635 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
637 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
640 if (mpll->pll_out_min == 0)
641 mpll->pll_out_min = 64800;
644 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
646 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
648 adev->clock.default_sclk =
649 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
650 adev->clock.default_mclk =
651 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
653 mpll->min_post_div = 1;
654 mpll->max_post_div = 1;
655 mpll->min_ref_div = 2;
656 mpll->max_ref_div = 0xff;
657 mpll->min_feedback_div = 4;
658 mpll->max_feedback_div = 0xff;
662 adev->clock.default_dispclk =
663 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
664 /* set a reasonable default for DP */
665 if (adev->clock.default_dispclk < 53900) {
666 DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
667 adev->clock.default_dispclk / 100);
668 adev->clock.default_dispclk = 60000;
670 adev->clock.dp_extclk =
671 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
672 adev->clock.current_dispclk = adev->clock.default_dispclk;
674 adev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
675 if (adev->clock.max_pixel_clock == 0)
676 adev->clock.max_pixel_clock = 40000;
678 /* not technically a clock, but... */
679 adev->mode_info.firmware_flags =
680 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
685 adev->pm.current_sclk = adev->clock.default_sclk;
686 adev->pm.current_mclk = adev->clock.default_mclk;
692 ATOM_GFX_INFO_V2_1 info;
695 int amdgpu_atombios_get_gfx_info(struct amdgpu_device *adev)
697 struct amdgpu_mode_info *mode_info = &adev->mode_info;
698 int index = GetIndexIntoMasterTable(DATA, GFX_Info);
700 uint16_t data_offset;
703 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
704 &frev, &crev, &data_offset)) {
705 union gfx_info *gfx_info = (union gfx_info *)
706 (mode_info->atom_context->bios + data_offset);
708 adev->gfx.config.max_shader_engines = gfx_info->info.max_shader_engines;
709 adev->gfx.config.max_tile_pipes = gfx_info->info.max_tile_pipes;
710 adev->gfx.config.max_cu_per_sh = gfx_info->info.max_cu_per_sh;
711 adev->gfx.config.max_sh_per_se = gfx_info->info.max_sh_per_se;
712 adev->gfx.config.max_backends_per_se = gfx_info->info.max_backends_per_se;
713 adev->gfx.config.max_texture_channel_caches =
714 gfx_info->info.max_texture_channel_caches;
722 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
723 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
724 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
725 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
726 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
727 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 info_9;
730 static void amdgpu_atombios_get_igp_ss_overrides(struct amdgpu_device *adev,
731 struct amdgpu_atom_ss *ss,
734 struct amdgpu_mode_info *mode_info = &adev->mode_info;
735 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
736 u16 data_offset, size;
737 union igp_info *igp_info;
739 u16 percentage = 0, rate = 0;
741 /* get any igp specific overrides */
742 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
743 &frev, &crev, &data_offset)) {
744 igp_info = (union igp_info *)
745 (mode_info->atom_context->bios + data_offset);
749 case ASIC_INTERNAL_SS_ON_TMDS:
750 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
751 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
753 case ASIC_INTERNAL_SS_ON_HDMI:
754 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
755 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
757 case ASIC_INTERNAL_SS_ON_LVDS:
758 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
759 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
765 case ASIC_INTERNAL_SS_ON_TMDS:
766 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
767 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
769 case ASIC_INTERNAL_SS_ON_HDMI:
770 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
771 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
773 case ASIC_INTERNAL_SS_ON_LVDS:
774 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
775 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
781 case ASIC_INTERNAL_SS_ON_TMDS:
782 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
783 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
785 case ASIC_INTERNAL_SS_ON_HDMI:
786 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
787 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
789 case ASIC_INTERNAL_SS_ON_LVDS:
790 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
791 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
797 case ASIC_INTERNAL_SS_ON_TMDS:
798 percentage = le16_to_cpu(igp_info->info_9.usDVISSPercentage);
799 rate = le16_to_cpu(igp_info->info_9.usDVISSpreadRateIn10Hz);
801 case ASIC_INTERNAL_SS_ON_HDMI:
802 percentage = le16_to_cpu(igp_info->info_9.usHDMISSPercentage);
803 rate = le16_to_cpu(igp_info->info_9.usHDMISSpreadRateIn10Hz);
805 case ASIC_INTERNAL_SS_ON_LVDS:
806 percentage = le16_to_cpu(igp_info->info_9.usLvdsSSPercentage);
807 rate = le16_to_cpu(igp_info->info_9.usLvdsSSpreadRateIn10Hz);
812 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
816 ss->percentage = percentage;
823 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
824 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
825 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
828 union asic_ss_assignment {
829 struct _ATOM_ASIC_SS_ASSIGNMENT v1;
830 struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2;
831 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3;
834 bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device *adev,
835 struct amdgpu_atom_ss *ss,
838 struct amdgpu_mode_info *mode_info = &adev->mode_info;
839 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
840 uint16_t data_offset, size;
841 union asic_ss_info *ss_info;
842 union asic_ss_assignment *ss_assign;
846 if (id == ASIC_INTERNAL_MEMORY_SS) {
847 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
850 if (id == ASIC_INTERNAL_ENGINE_SS) {
851 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
855 memset(ss, 0, sizeof(struct amdgpu_atom_ss));
856 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
857 &frev, &crev, &data_offset)) {
860 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
864 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
865 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
867 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);
868 for (i = 0; i < num_indices; i++) {
869 if ((ss_assign->v1.ucClockIndication == id) &&
870 (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
872 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
873 ss->type = ss_assign->v1.ucSpreadSpectrumMode;
874 ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
875 ss->percentage_divider = 100;
878 ss_assign = (union asic_ss_assignment *)
879 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));
883 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
884 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
885 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);
886 for (i = 0; i < num_indices; i++) {
887 if ((ss_assign->v2.ucClockIndication == id) &&
888 (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
890 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
891 ss->type = ss_assign->v2.ucSpreadSpectrumMode;
892 ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
893 ss->percentage_divider = 100;
895 ((id == ASIC_INTERNAL_ENGINE_SS) ||
896 (id == ASIC_INTERNAL_MEMORY_SS)))
900 ss_assign = (union asic_ss_assignment *)
901 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));
905 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
906 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
907 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);
908 for (i = 0; i < num_indices; i++) {
909 if ((ss_assign->v3.ucClockIndication == id) &&
910 (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
912 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
913 ss->type = ss_assign->v3.ucSpreadSpectrumMode;
914 ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
915 if (ss_assign->v3.ucSpreadSpectrumMode &
916 SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK)
917 ss->percentage_divider = 1000;
919 ss->percentage_divider = 100;
920 if ((id == ASIC_INTERNAL_ENGINE_SS) ||
921 (id == ASIC_INTERNAL_MEMORY_SS))
923 if (adev->flags & AMD_IS_APU)
924 amdgpu_atombios_get_igp_ss_overrides(adev, ss, id);
927 ss_assign = (union asic_ss_assignment *)
928 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));
932 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
940 union get_clock_dividers {
941 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
942 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
943 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
944 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
945 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
946 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
947 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
950 int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev,
954 struct atom_clock_dividers *dividers)
956 union get_clock_dividers args;
957 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
960 memset(&args, 0, sizeof(args));
961 memset(dividers, 0, sizeof(struct atom_clock_dividers));
963 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
969 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */
971 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
973 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
974 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
978 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
979 args.v6_in.ulClock.ulComputeClockFlag = clock_type;
980 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */
982 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
984 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
985 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
986 dividers->ref_div = args.v6_out.ucPllRefDiv;
987 dividers->post_div = args.v6_out.ucPllPostDiv;
988 dividers->flags = args.v6_out.ucPllCntlFlag;
989 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
990 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
998 int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev,
1001 struct atom_mpll_param *mpll_param)
1003 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
1004 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
1007 memset(&args, 0, sizeof(args));
1008 memset(mpll_param, 0, sizeof(struct atom_mpll_param));
1010 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1018 args.ulClock = cpu_to_le32(clock); /* 10 khz */
1019 args.ucInputFlag = 0;
1021 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;
1023 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1025 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
1026 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
1027 mpll_param->post_div = args.ucPostDiv;
1028 mpll_param->dll_speed = args.ucDllSpeed;
1029 mpll_param->bwcntl = args.ucBWCntl;
1030 mpll_param->vco_mode =
1031 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK);
1032 mpll_param->yclk_sel =
1033 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
1035 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
1036 mpll_param->half_rate =
1037 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
1049 uint32_t amdgpu_atombios_get_engine_clock(struct amdgpu_device *adev)
1051 GET_ENGINE_CLOCK_PS_ALLOCATION args;
1052 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
1054 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1055 return le32_to_cpu(args.ulReturnEngineClock);
1058 uint32_t amdgpu_atombios_get_memory_clock(struct amdgpu_device *adev)
1060 GET_MEMORY_CLOCK_PS_ALLOCATION args;
1061 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
1063 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1064 return le32_to_cpu(args.ulReturnMemoryClock);
1067 void amdgpu_atombios_set_engine_clock(struct amdgpu_device *adev,
1070 SET_ENGINE_CLOCK_PS_ALLOCATION args;
1071 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
1073 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */
1075 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1078 void amdgpu_atombios_set_memory_clock(struct amdgpu_device *adev,
1081 SET_MEMORY_CLOCK_PS_ALLOCATION args;
1082 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
1084 if (adev->flags & AMD_IS_APU)
1087 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */
1089 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1092 void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev,
1093 u32 eng_clock, u32 mem_clock)
1095 SET_ENGINE_CLOCK_PS_ALLOCATION args;
1096 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
1099 memset(&args, 0, sizeof(args));
1101 tmp = eng_clock & SET_CLOCK_FREQ_MASK;
1102 tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
1104 args.ulTargetEngineClock = cpu_to_le32(tmp);
1106 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
1108 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1112 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
1113 struct _SET_VOLTAGE_PARAMETERS v1;
1114 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
1115 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
1118 void amdgpu_atombios_set_voltage(struct amdgpu_device *adev,
1122 union set_voltage args;
1123 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
1124 u8 frev, crev, volt_index = voltage_level;
1126 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1129 /* 0xff01 is a flag rather then an actual voltage */
1130 if (voltage_level == 0xff01)
1135 args.v1.ucVoltageType = voltage_type;
1136 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
1137 args.v1.ucVoltageIndex = volt_index;
1140 args.v2.ucVoltageType = voltage_type;
1141 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
1142 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
1145 args.v3.ucVoltageType = voltage_type;
1146 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
1147 args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
1150 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1154 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1157 int amdgpu_atombios_get_leakage_id_from_vbios(struct amdgpu_device *adev,
1160 union set_voltage args;
1161 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
1164 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1170 args.v3.ucVoltageType = 0;
1171 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID;
1172 args.v3.usVoltageLevel = 0;
1174 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1176 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel);
1179 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1186 int amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(struct amdgpu_device *adev,
1187 u16 *vddc, u16 *vddci,
1188 u16 virtual_voltage_id,
1189 u16 vbios_voltage_id)
1191 int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
1193 u16 data_offset, size;
1195 ATOM_ASIC_PROFILING_INFO_V2_1 *profile;
1196 u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf;
1201 if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1202 &frev, &crev, &data_offset))
1205 profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
1206 (adev->mode_info.atom_context->bios + data_offset);
1214 if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))
1216 leakage_bin = (u16 *)
1217 (adev->mode_info.atom_context->bios + data_offset +
1218 le16_to_cpu(profile->usLeakageBinArrayOffset));
1219 vddc_id_buf = (u16 *)
1220 (adev->mode_info.atom_context->bios + data_offset +
1221 le16_to_cpu(profile->usElbVDDC_IdArrayOffset));
1223 (adev->mode_info.atom_context->bios + data_offset +
1224 le16_to_cpu(profile->usElbVDDC_LevelArrayOffset));
1225 vddci_id_buf = (u16 *)
1226 (adev->mode_info.atom_context->bios + data_offset +
1227 le16_to_cpu(profile->usElbVDDCI_IdArrayOffset));
1229 (adev->mode_info.atom_context->bios + data_offset +
1230 le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset));
1232 if (profile->ucElbVDDC_Num > 0) {
1233 for (i = 0; i < profile->ucElbVDDC_Num; i++) {
1234 if (vddc_id_buf[i] == virtual_voltage_id) {
1235 for (j = 0; j < profile->ucLeakageBinNum; j++) {
1236 if (vbios_voltage_id <= leakage_bin[j]) {
1237 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i];
1245 if (profile->ucElbVDDCI_Num > 0) {
1246 for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
1247 if (vddci_id_buf[i] == virtual_voltage_id) {
1248 for (j = 0; j < profile->ucLeakageBinNum; j++) {
1249 if (vbios_voltage_id <= leakage_bin[j]) {
1250 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
1260 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1265 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1272 union get_voltage_info {
1273 struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in;
1274 struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out;
1277 int amdgpu_atombios_get_voltage_evv(struct amdgpu_device *adev,
1278 u16 virtual_voltage_id,
1281 int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo);
1283 u32 count = adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;
1284 union get_voltage_info args;
1286 for (entry_id = 0; entry_id < count; entry_id++) {
1287 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v ==
1292 if (entry_id >= count)
1295 args.in.ucVoltageType = VOLTAGE_TYPE_VDDC;
1296 args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
1297 args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id);
1298 args.in.ulSCLKFreq =
1299 cpu_to_le32(adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk);
1301 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1303 *voltage = le16_to_cpu(args.evv_out.usVoltageLevel);
1308 union voltage_object_info {
1309 struct _ATOM_VOLTAGE_OBJECT_INFO v1;
1310 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
1311 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
1314 union voltage_object {
1315 struct _ATOM_VOLTAGE_OBJECT v1;
1316 struct _ATOM_VOLTAGE_OBJECT_V2 v2;
1317 union _ATOM_VOLTAGE_OBJECT_V3 v3;
1321 static ATOM_VOLTAGE_OBJECT_V3 *amdgpu_atombios_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3,
1322 u8 voltage_type, u8 voltage_mode)
1324 u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
1325 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
1326 u8 *start = (u8*)v3;
1328 while (offset < size) {
1329 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
1330 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
1331 (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
1333 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize);
1339 amdgpu_atombios_is_voltage_gpio(struct amdgpu_device *adev,
1340 u8 voltage_type, u8 voltage_mode)
1342 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1344 u16 data_offset, size;
1345 union voltage_object_info *voltage_info;
1347 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1348 &frev, &crev, &data_offset)) {
1349 voltage_info = (union voltage_object_info *)
1350 (adev->mode_info.atom_context->bios + data_offset);
1356 if (amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
1357 voltage_type, voltage_mode))
1361 DRM_ERROR("unknown voltage object table\n");
1366 DRM_ERROR("unknown voltage object table\n");
1374 int amdgpu_atombios_get_voltage_table(struct amdgpu_device *adev,
1375 u8 voltage_type, u8 voltage_mode,
1376 struct atom_voltage_table *voltage_table)
1378 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1380 u16 data_offset, size;
1382 union voltage_object_info *voltage_info;
1383 union voltage_object *voltage_object = NULL;
1385 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1386 &frev, &crev, &data_offset)) {
1387 voltage_info = (union voltage_object_info *)
1388 (adev->mode_info.atom_context->bios + data_offset);
1394 voltage_object = (union voltage_object *)
1395 amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
1396 voltage_type, voltage_mode);
1397 if (voltage_object) {
1398 ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
1399 &voltage_object->v3.asGpioVoltageObj;
1400 VOLTAGE_LUT_ENTRY_V2 *lut;
1401 if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
1403 lut = &gpio->asVolGpioLut[0];
1404 for (i = 0; i < gpio->ucGpioEntryNum; i++) {
1405 voltage_table->entries[i].value =
1406 le16_to_cpu(lut->usVoltageValue);
1407 voltage_table->entries[i].smio_low =
1408 le32_to_cpu(lut->ulVoltageId);
1409 lut = (VOLTAGE_LUT_ENTRY_V2 *)
1410 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));
1412 voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
1413 voltage_table->count = gpio->ucGpioEntryNum;
1414 voltage_table->phase_delay = gpio->ucPhaseDelay;
1419 DRM_ERROR("unknown voltage object table\n");
1424 DRM_ERROR("unknown voltage object table\n");
1432 struct _ATOM_VRAM_INFO_V3 v1_3;
1433 struct _ATOM_VRAM_INFO_V4 v1_4;
1434 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
1437 #define MEM_ID_MASK 0xff000000
1438 #define MEM_ID_SHIFT 24
1439 #define CLOCK_RANGE_MASK 0x00ffffff
1440 #define CLOCK_RANGE_SHIFT 0
1441 #define LOW_NIBBLE_MASK 0xf
1442 #define DATA_EQU_PREV 0
1443 #define DATA_FROM_TABLE 4
1445 int amdgpu_atombios_init_mc_reg_table(struct amdgpu_device *adev,
1447 struct atom_mc_reg_table *reg_table)
1449 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
1450 u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
1452 u16 data_offset, size;
1453 union vram_info *vram_info;
1455 memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
1457 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1458 &frev, &crev, &data_offset)) {
1459 vram_info = (union vram_info *)
1460 (adev->mode_info.atom_context->bios + data_offset);
1463 DRM_ERROR("old table version %d, %d\n", frev, crev);
1468 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
1469 ATOM_INIT_REG_BLOCK *reg_block =
1470 (ATOM_INIT_REG_BLOCK *)
1471 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
1472 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
1473 (ATOM_MEMORY_SETTING_DATA_BLOCK *)
1474 ((u8 *)reg_block + (2 * sizeof(u16)) +
1475 le16_to_cpu(reg_block->usRegIndexTblSize));
1476 ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0];
1477 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
1478 sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
1479 if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
1481 while (i < num_entries) {
1482 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER)
1484 reg_table->mc_reg_address[i].s1 =
1485 (u16)(le16_to_cpu(format->usRegIndex));
1486 reg_table->mc_reg_address[i].pre_reg_data =
1487 (u8)(format->ucPreRegDataLength);
1489 format = (ATOM_INIT_REG_INDEX_FORMAT *)
1490 ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
1492 reg_table->last = i;
1493 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&
1494 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
1495 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)
1497 if (module_index == t_mem_id) {
1498 reg_table->mc_reg_table_entry[num_ranges].mclk_max =
1499 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)
1500 >> CLOCK_RANGE_SHIFT);
1501 for (i = 0, j = 1; i < reg_table->last; i++) {
1502 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
1503 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
1504 (u32)le32_to_cpu(*((u32 *)reg_data + j));
1506 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
1507 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
1508 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
1513 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
1514 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
1516 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
1518 reg_table->num_entries = num_ranges;
1523 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1528 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1536 bool amdgpu_atombios_has_gpu_virtualization_table(struct amdgpu_device *adev)
1538 int index = GetIndexIntoMasterTable(DATA, GPUVirtualizationInfo);
1540 u16 data_offset, size;
1542 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1543 &frev, &crev, &data_offset))
1549 void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock)
1551 uint32_t bios_6_scratch;
1553 bios_6_scratch = RREG32(mmBIOS_SCRATCH_6);
1556 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1557 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
1559 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1560 bios_6_scratch |= ATOM_S6_ACC_MODE;
1563 WREG32(mmBIOS_SCRATCH_6, bios_6_scratch);
1566 void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev)
1568 uint32_t bios_2_scratch, bios_6_scratch;
1570 bios_2_scratch = RREG32(mmBIOS_SCRATCH_2);
1571 bios_6_scratch = RREG32(mmBIOS_SCRATCH_6);
1573 /* let the bios control the backlight */
1574 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1576 /* tell the bios not to handle mode switching */
1577 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
1579 /* clear the vbios dpms state */
1580 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
1582 WREG32(mmBIOS_SCRATCH_2, bios_2_scratch);
1583 WREG32(mmBIOS_SCRATCH_6, bios_6_scratch);
1586 void amdgpu_atombios_scratch_regs_save(struct amdgpu_device *adev)
1590 for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++)
1591 adev->bios_scratch[i] = RREG32(mmBIOS_SCRATCH_0 + i);
1594 void amdgpu_atombios_scratch_regs_restore(struct amdgpu_device *adev)
1598 for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++)
1599 WREG32(mmBIOS_SCRATCH_0 + i, adev->bios_scratch[i]);
1602 /* Atom needs data in little endian format
1603 * so swap as appropriate when copying data to
1604 * or from atom. Note that atom operates on
1607 void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
1610 u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */
1614 memcpy(src_tmp, src, num_bytes);
1615 src32 = (u32 *)src_tmp;
1616 dst32 = (u32 *)dst_tmp;
1618 for (i = 0; i < ((num_bytes + 3) / 4); i++)
1619 dst32[i] = cpu_to_le32(src32[i]);
1620 memcpy(dst, dst_tmp, num_bytes);
1622 u8 dws = num_bytes & ~3;
1623 for (i = 0; i < ((num_bytes + 3) / 4); i++)
1624 dst32[i] = le32_to_cpu(src32[i]);
1625 memcpy(dst, dst_tmp, dws);
1626 if (num_bytes % 4) {
1627 for (i = 0; i < (num_bytes % 4); i++)
1628 dst[dws+i] = dst_tmp[dws+i];
1632 memcpy(dst, src, num_bytes);