drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/amdgpu_drm.h>
  28 #include "amdgpu.h"
  29 #include "amdgpu_i2c.h"
  30 #include "atom.h"
  31 #include "amdgpu_connectors.h"
  32 #include <asm/div64.h>
  33
  34 #include <linux/pm_runtime.h>
  35 #include <drm/drm_crtc_helper.h>
  36 #include <drm/drm_edid.h>
  37
  38 static void amdgpu_flip_callback(struct fence *f, struct fence_cb *cb)
  39 {
  40         struct amdgpu_flip_work *work =
  41                 container_of(cb, struct amdgpu_flip_work, cb);
  42
  43         fence_put(f);
  44         schedule_work(&work->flip_work);
  45 }
  46
  47 static bool amdgpu_flip_handle_fence(struct amdgpu_flip_work *work,
  48                                      struct fence **f)
  49 {
  50         struct fence *fence= *f;
  51
  52         if (fence == NULL)
  53                 return false;
  54
  55         *f = NULL;
  56
  57         if (!fence_add_callback(fence, &work->cb, amdgpu_flip_callback))
  58                 return true;
  59
  60         fence_put(fence);
  61         return false;
  62 }
  63
  64 static void amdgpu_flip_work_func(struct work_struct *__work)
  65 {
  66         struct amdgpu_flip_work *work =
  67                 container_of(__work, struct amdgpu_flip_work, flip_work);
  68         struct amdgpu_device *adev = work->adev;
  69         struct amdgpu_crtc *amdgpuCrtc = adev->mode_info.crtcs[work->crtc_id];
  70
  71         struct drm_crtc *crtc = &amdgpuCrtc->base;
  72         unsigned long flags;
  73         unsigned i, repcnt = 4;
  74         int vpos, hpos, stat, min_udelay = 0;
  75         struct drm_vblank_crtc *vblank = &crtc->dev->vblank[work->crtc_id];
  76
  77         if (amdgpu_flip_handle_fence(work, &work->excl))
  78                 return;
  79
  80         for (i = 0; i < work->shared_count; ++i)
  81                 if (amdgpu_flip_handle_fence(work, &work->shared[i]))
  82                         return;
  83
  84         /* We borrow the event spin lock for protecting flip_status */
  85         spin_lock_irqsave(&crtc->dev->event_lock, flags);
  86
  87         /* If this happens to execute within the "virtually extended" vblank
  88          * interval before the start of the real vblank interval then it needs
  89          * to delay programming the mmio flip until the real vblank is entered.
  90          * This prevents completing a flip too early due to the way we fudge
  91          * our vblank counter and vblank timestamps in order to work around the
  92          * problem that the hw fires vblank interrupts before actual start of
  93          * vblank (when line buffer refilling is done for a frame). It
  94          * complements the fudging logic in amdgpu_get_crtc_scanoutpos() for
  95          * timestamping and amdgpu_get_vblank_counter_kms() for vblank counts.
  96          *
  97          * In practice this won't execute very often unless on very fast
  98          * machines because the time window for this to happen is very small.
  99          */
 100         while (amdgpuCrtc->enabled && --repcnt) {
 101                 /* GET_DISTANCE_TO_VBLANKSTART returns distance to real vblank
 102                  * start in hpos, and to the "fudged earlier" vblank start in
 103                  * vpos.
 104                  */
 105                 stat = amdgpu_get_crtc_scanoutpos(adev->ddev, work->crtc_id,
 106                                                   GET_DISTANCE_TO_VBLANKSTART,
 107                                                   &vpos, &hpos, NULL, NULL,
 108                                                   &crtc->hwmode);
 109
 110                 if ((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
 111                     (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE) ||
 112                     !(vpos >= 0 && hpos <= 0))
 113                         break;
 114
 115                 /* Sleep at least until estimated real start of hw vblank */
 116                 min_udelay = (-hpos + 1) * max(vblank->linedur_ns / 1000, 5);
 117                 if (min_udelay > vblank->framedur_ns / 2000) {
 118                         /* Don't wait ridiculously long - something is wrong */
 119                         repcnt = 0;
 120                         break;
 121                 }
 122                 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 123                 usleep_range(min_udelay, 2 * min_udelay);
 124                 spin_lock_irqsave(&crtc->dev->event_lock, flags);
 125         };
 126
 127         if (!repcnt)
 128                 DRM_DEBUG_DRIVER("Delay problem on crtc %d: min_udelay %d, "
 129                                  "framedur %d, linedur %d, stat %d, vpos %d, "
 130                                  "hpos %d\n", work->crtc_id, min_udelay,
 131                                  vblank->framedur_ns / 1000,
 132                                  vblank->linedur_ns / 1000, stat, vpos, hpos);
 133
 134         /* Do the flip (mmio) */
 135         adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async);
 136
 137         /* Set the flip status */
 138         amdgpuCrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
 139         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 140
 141
 142         DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n",
 143                                          amdgpuCrtc->crtc_id, amdgpuCrtc, work);
 144
 145 }
 146
 147 /*
 148  * Handle unpin events outside the interrupt handler proper.
 149  */
 150 static void amdgpu_unpin_work_func(struct work_struct *__work)
 151 {
 152         struct amdgpu_flip_work *work =
 153                 container_of(__work, struct amdgpu_flip_work, unpin_work);
 154         int r;
 155
 156         /* unpin of the old buffer */
 157         r = amdgpu_bo_reserve(work->old_rbo, false);
 158         if (likely(r == 0)) {
 159                 r = amdgpu_bo_unpin(work->old_rbo);
 160                 if (unlikely(r != 0)) {
 161                         DRM_ERROR("failed to unpin buffer after flip\n");
 162                 }
 163                 amdgpu_bo_unreserve(work->old_rbo);
 164         } else
 165                 DRM_ERROR("failed to reserve buffer after flip\n");
 166
 167         amdgpu_bo_unref(&work->old_rbo);
 168         kfree(work->shared);
 169         kfree(work);
 170 }
 171
 172 int amdgpu_crtc_page_flip(struct drm_crtc *crtc,
 173                           struct drm_framebuffer *fb,
 174                           struct drm_pending_vblank_event *event,
 175                           uint32_t page_flip_flags)
 176 {
 177         struct drm_device *dev = crtc->dev;
 178         struct amdgpu_device *adev = dev->dev_private;
 179         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 180         struct amdgpu_framebuffer *old_amdgpu_fb;
 181         struct amdgpu_framebuffer *new_amdgpu_fb;
 182         struct drm_gem_object *obj;
 183         struct amdgpu_flip_work *work;
 184         struct amdgpu_bo *new_rbo;
 185         unsigned long flags;
 186         u64 tiling_flags;
 187         u64 base;
 188         int i, r;
 189
 190         work = kzalloc(sizeof *work, GFP_KERNEL);
 191         if (work == NULL)
 192                 return -ENOMEM;
 193
 194         INIT_WORK(&work->flip_work, amdgpu_flip_work_func);
 195         INIT_WORK(&work->unpin_work, amdgpu_unpin_work_func);
 196
 197         work->event = event;
 198         work->adev = adev;
 199         work->crtc_id = amdgpu_crtc->crtc_id;
 200         work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
 201
 202         /* schedule unpin of the old buffer */
 203         old_amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
 204         obj = old_amdgpu_fb->obj;
 205
 206         /* take a reference to the old object */
 207         work->old_rbo = gem_to_amdgpu_bo(obj);
 208         amdgpu_bo_ref(work->old_rbo);
 209
 210         new_amdgpu_fb = to_amdgpu_framebuffer(fb);
 211         obj = new_amdgpu_fb->obj;
 212         new_rbo = gem_to_amdgpu_bo(obj);
 213
 214         /* pin the new buffer */
 215         r = amdgpu_bo_reserve(new_rbo, false);
 216         if (unlikely(r != 0)) {
 217                 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
 218                 goto cleanup;
 219         }
 220
 221         r = amdgpu_bo_pin_restricted(new_rbo, AMDGPU_GEM_DOMAIN_VRAM, 0, 0, &base);
 222         if (unlikely(r != 0)) {
 223                 amdgpu_bo_unreserve(new_rbo);
 224                 r = -EINVAL;
 225                 DRM_ERROR("failed to pin new rbo buffer before flip\n");
 226                 goto cleanup;
 227         }
 228
 229         r = reservation_object_get_fences_rcu(new_rbo->tbo.resv, &work->excl,
 230                                               &work->shared_count,
 231                                               &work->shared);
 232         if (unlikely(r != 0)) {
 233                 amdgpu_bo_unreserve(new_rbo);
 234                 DRM_ERROR("failed to get fences for buffer\n");
 235                 goto cleanup;
 236         }
 237
 238         amdgpu_bo_get_tiling_flags(new_rbo, &tiling_flags);
 239         amdgpu_bo_unreserve(new_rbo);
 240
 241         work->base = base;
 242
 243         r = drm_vblank_get(crtc->dev, amdgpu_crtc->crtc_id);
 244         if (r) {
 245                 DRM_ERROR("failed to get vblank before flip\n");
 246                 goto pflip_cleanup;
 247         }
 248
 249         /* we borrow the event spin lock for protecting flip_wrok */
 250         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 251         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) {
 252                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
 253                 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 254                 r = -EBUSY;
 255                 goto vblank_cleanup;
 256         }
 257
 258         amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING;
 259         amdgpu_crtc->pflip_works = work;
 260
 261
 262         DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n",
 263                                          amdgpu_crtc->crtc_id, amdgpu_crtc, work);
 264         /* update crtc fb */
 265         crtc->primary->fb = fb;
 266         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 267         amdgpu_flip_work_func(&work->flip_work);
 268         return 0;
 269
 270 vblank_cleanup:
 271         drm_vblank_put(crtc->dev, amdgpu_crtc->crtc_id);
 272
 273 pflip_cleanup:
 274         if (unlikely(amdgpu_bo_reserve(new_rbo, false) != 0)) {
 275                 DRM_ERROR("failed to reserve new rbo in error path\n");
 276                 goto cleanup;
 277         }
 278         if (unlikely(amdgpu_bo_unpin(new_rbo) != 0)) {
 279                 DRM_ERROR("failed to unpin new rbo in error path\n");
 280         }
 281         amdgpu_bo_unreserve(new_rbo);
 282
 283 cleanup:
 284         amdgpu_bo_unref(&work->old_rbo);
 285         fence_put(work->excl);
 286         for (i = 0; i < work->shared_count; ++i)
 287                 fence_put(work->shared[i]);
 288         kfree(work->shared);
 289         kfree(work);
 290
 291         return r;
 292 }
 293
 294 int amdgpu_crtc_set_config(struct drm_mode_set *set)
 295 {
 296         struct drm_device *dev;
 297         struct amdgpu_device *adev;
 298         struct drm_crtc *crtc;
 299         bool active = false;
 300         int ret;
 301
 302         if (!set || !set->crtc)
 303                 return -EINVAL;
 304
 305         dev = set->crtc->dev;
 306
 307         ret = pm_runtime_get_sync(dev->dev);
 308         if (ret < 0)
 309                 return ret;
 310
 311         ret = drm_crtc_helper_set_config(set);
 312
 313         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 314                 if (crtc->enabled)
 315                         active = true;
 316
 317         pm_runtime_mark_last_busy(dev->dev);
 318
 319         adev = dev->dev_private;
 320         /* if we have active crtcs and we don't have a power ref,
 321            take the current one */
 322         if (active && !adev->have_disp_power_ref) {
 323                 adev->have_disp_power_ref = true;
 324                 return ret;
 325         }
 326         /* if we have no active crtcs, then drop the power ref
 327            we got before */
 328         if (!active && adev->have_disp_power_ref) {
 329                 pm_runtime_put_autosuspend(dev->dev);
 330                 adev->have_disp_power_ref = false;
 331         }
 332
 333         /* drop the power reference we got coming in here */
 334         pm_runtime_put_autosuspend(dev->dev);
 335         return ret;
 336 }
 337
 338 static const char *encoder_names[38] = {
 339         "NONE",
 340         "INTERNAL_LVDS",
 341         "INTERNAL_TMDS1",
 342         "INTERNAL_TMDS2",
 343         "INTERNAL_DAC1",
 344         "INTERNAL_DAC2",
 345         "INTERNAL_SDVOA",
 346         "INTERNAL_SDVOB",
 347         "SI170B",
 348         "CH7303",
 349         "CH7301",
 350         "INTERNAL_DVO1",
 351         "EXTERNAL_SDVOA",
 352         "EXTERNAL_SDVOB",
 353         "TITFP513",
 354         "INTERNAL_LVTM1",
 355         "VT1623",
 356         "HDMI_SI1930",
 357         "HDMI_INTERNAL",
 358         "INTERNAL_KLDSCP_TMDS1",
 359         "INTERNAL_KLDSCP_DVO1",
 360         "INTERNAL_KLDSCP_DAC1",
 361         "INTERNAL_KLDSCP_DAC2",
 362         "SI178",
 363         "MVPU_FPGA",
 364         "INTERNAL_DDI",
 365         "VT1625",
 366         "HDMI_SI1932",
 367         "DP_AN9801",
 368         "DP_DP501",
 369         "INTERNAL_UNIPHY",
 370         "INTERNAL_KLDSCP_LVTMA",
 371         "INTERNAL_UNIPHY1",
 372         "INTERNAL_UNIPHY2",
 373         "NUTMEG",
 374         "TRAVIS",
 375         "INTERNAL_VCE",
 376         "INTERNAL_UNIPHY3",
 377 };
 378
 379 static const char *hpd_names[6] = {
 380         "HPD1",
 381         "HPD2",
 382         "HPD3",
 383         "HPD4",
 384         "HPD5",
 385         "HPD6",
 386 };
 387
 388 void amdgpu_print_display_setup(struct drm_device *dev)
 389 {
 390         struct drm_connector *connector;
 391         struct amdgpu_connector *amdgpu_connector;
 392         struct drm_encoder *encoder;
 393         struct amdgpu_encoder *amdgpu_encoder;
 394         uint32_t devices;
 395         int i = 0;
 396
 397         DRM_INFO("AMDGPU Display Connectors\n");
 398         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 399                 amdgpu_connector = to_amdgpu_connector(connector);
 400                 DRM_INFO("Connector %d:\n", i);
 401                 DRM_INFO("  %s\n", connector->name);
 402                 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE)
 403                         DRM_INFO("  %s\n", hpd_names[amdgpu_connector->hpd.hpd]);
 404                 if (amdgpu_connector->ddc_bus) {
 405                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 406                                  amdgpu_connector->ddc_bus->rec.mask_clk_reg,
 407                                  amdgpu_connector->ddc_bus->rec.mask_data_reg,
 408                                  amdgpu_connector->ddc_bus->rec.a_clk_reg,
 409                                  amdgpu_connector->ddc_bus->rec.a_data_reg,
 410                                  amdgpu_connector->ddc_bus->rec.en_clk_reg,
 411                                  amdgpu_connector->ddc_bus->rec.en_data_reg,
 412                                  amdgpu_connector->ddc_bus->rec.y_clk_reg,
 413                                  amdgpu_connector->ddc_bus->rec.y_data_reg);
 414                         if (amdgpu_connector->router.ddc_valid)
 415                                 DRM_INFO("  DDC Router 0x%x/0x%x\n",
 416                                          amdgpu_connector->router.ddc_mux_control_pin,
 417                                          amdgpu_connector->router.ddc_mux_state);
 418                         if (amdgpu_connector->router.cd_valid)
 419                                 DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
 420                                          amdgpu_connector->router.cd_mux_control_pin,
 421                                          amdgpu_connector->router.cd_mux_state);
 422                 } else {
 423                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 424                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 425                             connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 426                             connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 427                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 428                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 429                                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
 430                 }
 431                 DRM_INFO("  Encoders:\n");
 432                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 433                         amdgpu_encoder = to_amdgpu_encoder(encoder);
 434                         devices = amdgpu_encoder->devices & amdgpu_connector->devices;
 435                         if (devices) {
 436                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 437                                         DRM_INFO("    CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 438                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 439                                         DRM_INFO("    CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 440                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 441                                         DRM_INFO("    LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 442                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 443                                         DRM_INFO("    DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 444                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 445                                         DRM_INFO("    DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 446                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 447                                         DRM_INFO("    DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 448                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 449                                         DRM_INFO("    DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 450                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 451                                         DRM_INFO("    DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 452                                 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
 453                                         DRM_INFO("    DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 454                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
 455                                         DRM_INFO("    TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 456                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
 457                                         DRM_INFO("    CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 458                         }
 459                 }
 460                 i++;
 461         }
 462 }
 463
 464 /**
 465  * amdgpu_ddc_probe
 466  *
 467  */
 468 bool amdgpu_ddc_probe(struct amdgpu_connector *amdgpu_connector,
 469                        bool use_aux)
 470 {
 471         u8 out = 0x0;
 472         u8 buf[8];
 473         int ret;
 474         struct i2c_msg msgs[] = {
 475                 {
 476                         .addr = DDC_ADDR,
 477                         .flags = 0,
 478                         .len = 1,
 479                         .buf = &out,
 480                 },
 481                 {
 482                         .addr = DDC_ADDR,
 483                         .flags = I2C_M_RD,
 484                         .len = 8,
 485                         .buf = buf,
 486                 }
 487         };
 488
 489         /* on hw with routers, select right port */
 490         if (amdgpu_connector->router.ddc_valid)
 491                 amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
 492
 493         if (use_aux) {
 494                 ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2);
 495         } else {
 496                 ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2);
 497         }
 498
 499         if (ret != 2)
 500                 /* Couldn't find an accessible DDC on this connector */
 501                 return false;
 502         /* Probe also for valid EDID header
 503          * EDID header starts with:
 504          * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
 505          * Only the first 6 bytes must be valid as
 506          * drm_edid_block_valid() can fix the last 2 bytes */
 507         if (drm_edid_header_is_valid(buf) < 6) {
 508                 /* Couldn't find an accessible EDID on this
 509                  * connector */
 510                 return false;
 511         }
 512         return true;
 513 }
 514
 515 static void amdgpu_user_framebuffer_destroy(struct drm_framebuffer *fb)
 516 {
 517         struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb);
 518
 519         if (amdgpu_fb->obj) {
 520                 drm_gem_object_unreference_unlocked(amdgpu_fb->obj);
 521         }
 522         drm_framebuffer_cleanup(fb);
 523         kfree(amdgpu_fb);
 524 }
 525
 526 static int amdgpu_user_framebuffer_create_handle(struct drm_framebuffer *fb,
 527                                                   struct drm_file *file_priv,
 528                                                   unsigned int *handle)
 529 {
 530         struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb);
 531
 532         return drm_gem_handle_create(file_priv, amdgpu_fb->obj, handle);
 533 }
 534
 535 static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
 536         .destroy = amdgpu_user_framebuffer_destroy,
 537         .create_handle = amdgpu_user_framebuffer_create_handle,
 538 };
 539
 540 int
 541 amdgpu_framebuffer_init(struct drm_device *dev,
 542                         struct amdgpu_framebuffer *rfb,
 543                         const struct drm_mode_fb_cmd2 *mode_cmd,
 544                         struct drm_gem_object *obj)
 545 {
 546         int ret;
 547         rfb->obj = obj;
 548         drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
 549         ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
 550         if (ret) {
 551                 rfb->obj = NULL;
 552                 return ret;
 553         }
 554         return 0;
 555 }
 556
 557 static struct drm_framebuffer *
 558 amdgpu_user_framebuffer_create(struct drm_device *dev,
 559                                struct drm_file *file_priv,
 560                                const struct drm_mode_fb_cmd2 *mode_cmd)
 561 {
 562         struct drm_gem_object *obj;
 563         struct amdgpu_framebuffer *amdgpu_fb;
 564         int ret;
 565
 566         obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
 567         if (obj ==  NULL) {
 568                 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
 569                         "can't create framebuffer\n", mode_cmd->handles[0]);
 570                 return ERR_PTR(-ENOENT);
 571         }
 572
 573         amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL);
 574         if (amdgpu_fb == NULL) {
 575                 drm_gem_object_unreference_unlocked(obj);
 576                 return ERR_PTR(-ENOMEM);
 577         }
 578
 579         ret = amdgpu_framebuffer_init(dev, amdgpu_fb, mode_cmd, obj);
 580         if (ret) {
 581                 kfree(amdgpu_fb);
 582                 drm_gem_object_unreference_unlocked(obj);
 583                 return ERR_PTR(ret);
 584         }
 585
 586         return &amdgpu_fb->base;
 587 }
 588
 589 static void amdgpu_output_poll_changed(struct drm_device *dev)
 590 {
 591         struct amdgpu_device *adev = dev->dev_private;
 592         amdgpu_fb_output_poll_changed(adev);
 593 }
 594
 595 const struct drm_mode_config_funcs amdgpu_mode_funcs = {
 596         .fb_create = amdgpu_user_framebuffer_create,
 597         .output_poll_changed = amdgpu_output_poll_changed
 598 };
 599
 600 static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] =
 601 {       { UNDERSCAN_OFF, "off" },
 602         { UNDERSCAN_ON, "on" },
 603         { UNDERSCAN_AUTO, "auto" },
 604 };
 605
 606 static const struct drm_prop_enum_list amdgpu_audio_enum_list[] =
 607 {       { AMDGPU_AUDIO_DISABLE, "off" },
 608         { AMDGPU_AUDIO_ENABLE, "on" },
 609         { AMDGPU_AUDIO_AUTO, "auto" },
 610 };
 611
 612 /* XXX support different dither options? spatial, temporal, both, etc. */
 613 static const struct drm_prop_enum_list amdgpu_dither_enum_list[] =
 614 {       { AMDGPU_FMT_DITHER_DISABLE, "off" },
 615         { AMDGPU_FMT_DITHER_ENABLE, "on" },
 616 };
 617
 618 int amdgpu_modeset_create_props(struct amdgpu_device *adev)
 619 {
 620         int sz;
 621
 622         if (adev->is_atom_bios) {
 623                 adev->mode_info.coherent_mode_property =
 624                         drm_property_create_range(adev->ddev, 0 , "coherent", 0, 1);
 625                 if (!adev->mode_info.coherent_mode_property)
 626                         return -ENOMEM;
 627         }
 628
 629         adev->mode_info.load_detect_property =
 630                 drm_property_create_range(adev->ddev, 0, "load detection", 0, 1);
 631         if (!adev->mode_info.load_detect_property)
 632                 return -ENOMEM;
 633
 634         drm_mode_create_scaling_mode_property(adev->ddev);
 635
 636         sz = ARRAY_SIZE(amdgpu_underscan_enum_list);
 637         adev->mode_info.underscan_property =
 638                 drm_property_create_enum(adev->ddev, 0,
 639                                     "underscan",
 640                                     amdgpu_underscan_enum_list, sz);
 641
 642         adev->mode_info.underscan_hborder_property =
 643                 drm_property_create_range(adev->ddev, 0,
 644                                         "underscan hborder", 0, 128);
 645         if (!adev->mode_info.underscan_hborder_property)
 646                 return -ENOMEM;
 647
 648         adev->mode_info.underscan_vborder_property =
 649                 drm_property_create_range(adev->ddev, 0,
 650                                         "underscan vborder", 0, 128);
 651         if (!adev->mode_info.underscan_vborder_property)
 652                 return -ENOMEM;
 653
 654         sz = ARRAY_SIZE(amdgpu_audio_enum_list);
 655         adev->mode_info.audio_property =
 656                 drm_property_create_enum(adev->ddev, 0,
 657                                          "audio",
 658                                          amdgpu_audio_enum_list, sz);
 659
 660         sz = ARRAY_SIZE(amdgpu_dither_enum_list);
 661         adev->mode_info.dither_property =
 662                 drm_property_create_enum(adev->ddev, 0,
 663                                          "dither",
 664                                          amdgpu_dither_enum_list, sz);
 665
 666         return 0;
 667 }
 668
 669 void amdgpu_update_display_priority(struct amdgpu_device *adev)
 670 {
 671         /* adjustment options for the display watermarks */
 672         if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2))
 673                 adev->mode_info.disp_priority = 0;
 674         else
 675                 adev->mode_info.disp_priority = amdgpu_disp_priority;
 676
 677 }
 678
 679 static bool is_hdtv_mode(const struct drm_display_mode *mode)
 680 {
 681         /* try and guess if this is a tv or a monitor */
 682         if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
 683             (mode->vdisplay == 576) || /* 576p */
 684             (mode->vdisplay == 720) || /* 720p */
 685             (mode->vdisplay == 1080)) /* 1080p */
 686                 return true;
 687         else
 688                 return false;
 689 }
 690
 691 bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
 692                                     const struct drm_display_mode *mode,
 693                                     struct drm_display_mode *adjusted_mode)
 694 {
 695         struct drm_device *dev = crtc->dev;
 696         struct drm_encoder *encoder;
 697         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 698         struct amdgpu_encoder *amdgpu_encoder;
 699         struct drm_connector *connector;
 700         struct amdgpu_connector *amdgpu_connector;
 701         u32 src_v = 1, dst_v = 1;
 702         u32 src_h = 1, dst_h = 1;
 703
 704         amdgpu_crtc->h_border = 0;
 705         amdgpu_crtc->v_border = 0;
 706
 707         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 708                 if (encoder->crtc != crtc)
 709                         continue;
 710                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 711                 connector = amdgpu_get_connector_for_encoder(encoder);
 712                 amdgpu_connector = to_amdgpu_connector(connector);
 713
 714                 /* set scaling */
 715                 if (amdgpu_encoder->rmx_type == RMX_OFF)
 716                         amdgpu_crtc->rmx_type = RMX_OFF;
 717                 else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay ||
 718                          mode->vdisplay < amdgpu_encoder->native_mode.vdisplay)
 719                         amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type;
 720                 else
 721                         amdgpu_crtc->rmx_type = RMX_OFF;
 722                 /* copy native mode */
 723                 memcpy(&amdgpu_crtc->native_mode,
 724                        &amdgpu_encoder->native_mode,
 725                        sizeof(struct drm_display_mode));
 726                 src_v = crtc->mode.vdisplay;
 727                 dst_v = amdgpu_crtc->native_mode.vdisplay;
 728                 src_h = crtc->mode.hdisplay;
 729                 dst_h = amdgpu_crtc->native_mode.hdisplay;
 730
 731                 /* fix up for overscan on hdmi */
 732                 if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
 733                     ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) ||
 734                      ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) &&
 735                       drm_detect_hdmi_monitor(amdgpu_connector_edid(connector)) &&
 736                       is_hdtv_mode(mode)))) {
 737                         if (amdgpu_encoder->underscan_hborder != 0)
 738                                 amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder;
 739                         else
 740                                 amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16;
 741                         if (amdgpu_encoder->underscan_vborder != 0)
 742                                 amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder;
 743                         else
 744                                 amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16;
 745                         amdgpu_crtc->rmx_type = RMX_FULL;
 746                         src_v = crtc->mode.vdisplay;
 747                         dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2);
 748                         src_h = crtc->mode.hdisplay;
 749                         dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2);
 750                 }
 751         }
 752         if (amdgpu_crtc->rmx_type != RMX_OFF) {
 753                 fixed20_12 a, b;
 754                 a.full = dfixed_const(src_v);
 755                 b.full = dfixed_const(dst_v);
 756                 amdgpu_crtc->vsc.full = dfixed_div(a, b);
 757                 a.full = dfixed_const(src_h);
 758                 b.full = dfixed_const(dst_h);
 759                 amdgpu_crtc->hsc.full = dfixed_div(a, b);
 760         } else {
 761                 amdgpu_crtc->vsc.full = dfixed_const(1);
 762                 amdgpu_crtc->hsc.full = dfixed_const(1);
 763         }
 764         return true;
 765 }
 766
 767 /*
 768  * Retrieve current video scanout position of crtc on a given gpu, and
 769  * an optional accurate timestamp of when query happened.
 770  *
 771  * \param dev Device to query.
 772  * \param pipe Crtc to query.
 773  * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
 774  *              For driver internal use only also supports these flags:
 775  *
 776  *              USE_REAL_VBLANKSTART to use the real start of vblank instead
 777  *              of a fudged earlier start of vblank.
 778  *
 779  *              GET_DISTANCE_TO_VBLANKSTART to return distance to the
 780  *              fudged earlier start of vblank in *vpos and the distance
 781  *              to true start of vblank in *hpos.
 782  *
 783  * \param *vpos Location where vertical scanout position should be stored.
 784  * \param *hpos Location where horizontal scanout position should go.
 785  * \param *stime Target location for timestamp taken immediately before
 786  *               scanout position query. Can be NULL to skip timestamp.
 787  * \param *etime Target location for timestamp taken immediately after
 788  *               scanout position query. Can be NULL to skip timestamp.
 789  *
 790  * Returns vpos as a positive number while in active scanout area.
 791  * Returns vpos as a negative number inside vblank, counting the number
 792  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
 793  * until start of active scanout / end of vblank."
 794  *
 795  * \return Flags, or'ed together as follows:
 796  *
 797  * DRM_SCANOUTPOS_VALID = Query successful.
 798  * DRM_SCANOUTPOS_INVBL = Inside vblank.
 799  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
 800  * this flag means that returned position may be offset by a constant but
 801  * unknown small number of scanlines wrt. real scanout position.
 802  *
 803  */
 804 int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
 805                                unsigned int flags, int *vpos, int *hpos,
 806                                ktime_t *stime, ktime_t *etime,
 807                                const struct drm_display_mode *mode)
 808 {
 809         u32 vbl = 0, position = 0;
 810         int vbl_start, vbl_end, vtotal, ret = 0;
 811         bool in_vbl = true;
 812
 813         struct amdgpu_device *adev = dev->dev_private;
 814
 815         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 816
 817         /* Get optional system timestamp before query. */
 818         if (stime)
 819                 *stime = ktime_get();
 820
 821         if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0)
 822                 ret |= DRM_SCANOUTPOS_VALID;
 823
 824         /* Get optional system timestamp after query. */
 825         if (etime)
 826                 *etime = ktime_get();
 827
 828         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 829
 830         /* Decode into vertical and horizontal scanout position. */
 831         *vpos = position & 0x1fff;
 832         *hpos = (position >> 16) & 0x1fff;
 833
 834         /* Valid vblank area boundaries from gpu retrieved? */
 835         if (vbl > 0) {
 836                 /* Yes: Decode. */
 837                 ret |= DRM_SCANOUTPOS_ACCURATE;
 838                 vbl_start = vbl & 0x1fff;
 839                 vbl_end = (vbl >> 16) & 0x1fff;
 840         }
 841         else {
 842                 /* No: Fake something reasonable which gives at least ok results. */
 843                 vbl_start = mode->crtc_vdisplay;
 844                 vbl_end = 0;
 845         }
 846
 847         /* Called from driver internal vblank counter query code? */
 848         if (flags & GET_DISTANCE_TO_VBLANKSTART) {
 849             /* Caller wants distance from real vbl_start in *hpos */
 850             *hpos = *vpos - vbl_start;
 851         }
 852
 853         /* Fudge vblank to start a few scanlines earlier to handle the
 854          * problem that vblank irqs fire a few scanlines before start
 855          * of vblank. Some driver internal callers need the true vblank
 856          * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
 857          *
 858          * The cause of the "early" vblank irq is that the irq is triggered
 859          * by the line buffer logic when the line buffer read position enters
 860          * the vblank, whereas our crtc scanout position naturally lags the
 861          * line buffer read position.
 862          */
 863         if (!(flags & USE_REAL_VBLANKSTART))
 864                 vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
 865
 866         /* Test scanout position against vblank region. */
 867         if ((*vpos < vbl_start) && (*vpos >= vbl_end))
 868                 in_vbl = false;
 869
 870         /* In vblank? */
 871         if (in_vbl)
 872             ret |= DRM_SCANOUTPOS_IN_VBLANK;
 873
 874         /* Called from driver internal vblank counter query code? */
 875         if (flags & GET_DISTANCE_TO_VBLANKSTART) {
 876                 /* Caller wants distance from fudged earlier vbl_start */
 877                 *vpos -= vbl_start;
 878                 return ret;
 879         }
 880
 881         /* Check if inside vblank area and apply corrective offsets:
 882          * vpos will then be >=0 in video scanout area, but negative
 883          * within vblank area, counting down the number of lines until
 884          * start of scanout.
 885          */
 886
 887         /* Inside "upper part" of vblank area? Apply corrective offset if so: */
 888         if (in_vbl && (*vpos >= vbl_start)) {
 889                 vtotal = mode->crtc_vtotal;
 890                 *vpos = *vpos - vtotal;
 891         }
 892
 893         /* Correct for shifted end of vbl at vbl_end. */
 894         *vpos = *vpos - vbl_end;
 895
 896         return ret;
 897 }
 898
 899 int amdgpu_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc)
 900 {
 901         if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
 902                 return AMDGPU_CRTC_IRQ_NONE;
 903
 904         switch (crtc) {
 905         case 0:
 906                 return AMDGPU_CRTC_IRQ_VBLANK1;
 907         case 1:
 908                 return AMDGPU_CRTC_IRQ_VBLANK2;
 909         case 2:
 910                 return AMDGPU_CRTC_IRQ_VBLANK3;
 911         case 3:
 912                 return AMDGPU_CRTC_IRQ_VBLANK4;
 913         case 4:
 914                 return AMDGPU_CRTC_IRQ_VBLANK5;
 915         case 5:
 916                 return AMDGPU_CRTC_IRQ_VBLANK6;
 917         default:
 918                 return AMDGPU_CRTC_IRQ_NONE;
 919         }
 920 }