drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #include "atom.h"
  26 #include "amdgpu.h"
  27 #include "amd_shared.h"
  28 #include <linux/module.h>
  29 #include <linux/moduleparam.h>
  30 #include "amdgpu_pm.h"
  31 #include <drm/amdgpu_drm.h>
  32 #include "amdgpu_powerplay.h"
  33 #include "si_dpm.h"
  34 #include "cik_dpm.h"
  35 #include "vi_dpm.h"
  36
  37 static int amdgpu_powerplay_init(struct amdgpu_device *adev)
  38 {
  39         int ret = 0;
  40         struct amd_powerplay *amd_pp;
  41
  42         amd_pp = &(adev->powerplay);
  43
  44         if (adev->pp_enabled) {
  45 #ifdef CONFIG_DRM_AMD_POWERPLAY
  46                 struct amd_pp_init *pp_init;
  47
  48                 pp_init = kzalloc(sizeof(struct amd_pp_init), GFP_KERNEL);
  49
  50                 if (pp_init == NULL)
  51                         return -ENOMEM;
  52
  53                 pp_init->chip_family = adev->family;
  54                 pp_init->chip_id = adev->asic_type;
  55                 pp_init->device = amdgpu_cgs_create_device(adev);
  56                 ret = amd_powerplay_init(pp_init, amd_pp);
  57                 kfree(pp_init);
  58 #endif
  59         } else {
  60                 amd_pp->pp_handle = (void *)adev;
  61
  62                 switch (adev->asic_type) {
  63 #ifdef CONFIG_DRM_AMDGPU_SI
  64                 case CHIP_TAHITI:
  65                 case CHIP_PITCAIRN:
  66                 case CHIP_VERDE:
  67                 case CHIP_OLAND:
  68                 case CHIP_HAINAN:
  69                         amd_pp->ip_funcs = &si_dpm_ip_funcs;
  70                 break;
  71 #endif
  72 #ifdef CONFIG_DRM_AMDGPU_CIK
  73                 case CHIP_BONAIRE:
  74                 case CHIP_HAWAII:
  75                         amd_pp->ip_funcs = &ci_dpm_ip_funcs;
  76                         break;
  77                 case CHIP_KABINI:
  78                 case CHIP_MULLINS:
  79                 case CHIP_KAVERI:
  80                         amd_pp->ip_funcs = &kv_dpm_ip_funcs;
  81                         break;
  82 #endif
  83                 case CHIP_CARRIZO:
  84                 case CHIP_STONEY:
  85                         amd_pp->ip_funcs = &cz_dpm_ip_funcs;
  86                         break;
  87                 default:
  88                         ret = -EINVAL;
  89                         break;
  90                 }
  91         }
  92         return ret;
  93 }
  94
  95 static int amdgpu_pp_early_init(void *handle)
  96 {
  97         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  98         int ret = 0;
  99
 100 #ifdef CONFIG_DRM_AMD_POWERPLAY
 101         switch (adev->asic_type) {
 102         case CHIP_POLARIS11:
 103         case CHIP_POLARIS10:
 104         case CHIP_TONGA:
 105         case CHIP_FIJI:
 106         case CHIP_TOPAZ:
 107                 adev->pp_enabled = true;
 108                 break;
 109         case CHIP_CARRIZO:
 110         case CHIP_STONEY:
 111                 adev->pp_enabled = (amdgpu_powerplay == 0) ? false : true;
 112                 break;
 113         /* These chips don't have powerplay implemenations */
 114         case CHIP_BONAIRE:
 115         case CHIP_HAWAII:
 116         case CHIP_KABINI:
 117         case CHIP_MULLINS:
 118         case CHIP_KAVERI:
 119         default:
 120                 adev->pp_enabled = false;
 121                 break;
 122         }
 123 #else
 124         adev->pp_enabled = false;
 125 #endif
 126
 127         ret = amdgpu_powerplay_init(adev);
 128         if (ret)
 129                 return ret;
 130
 131         if (adev->powerplay.ip_funcs->early_init)
 132                 ret = adev->powerplay.ip_funcs->early_init(
 133                                         adev->powerplay.pp_handle);
 134         return ret;
 135 }
 136
 137
 138 static int amdgpu_pp_late_init(void *handle)
 139 {
 140         int ret = 0;
 141         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 142
 143         if (adev->powerplay.ip_funcs->late_init)
 144                 ret = adev->powerplay.ip_funcs->late_init(
 145                                         adev->powerplay.pp_handle);
 146
 147 #ifdef CONFIG_DRM_AMD_POWERPLAY
 148         if (adev->pp_enabled && adev->pm.dpm_enabled) {
 149                 amdgpu_pm_sysfs_init(adev);
 150                 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_COMPLETE_INIT, NULL, NULL);
 151         }
 152 #endif
 153         return ret;
 154 }
 155
 156 static int amdgpu_pp_sw_init(void *handle)
 157 {
 158         int ret = 0;
 159         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 160
 161         if (adev->powerplay.ip_funcs->sw_init)
 162                 ret = adev->powerplay.ip_funcs->sw_init(
 163                                         adev->powerplay.pp_handle);
 164
 165 #ifdef CONFIG_DRM_AMD_POWERPLAY
 166         if (adev->pp_enabled)
 167                 adev->pm.dpm_enabled = true;
 168 #endif
 169
 170         return ret;
 171 }
 172
 173 static int amdgpu_pp_sw_fini(void *handle)
 174 {
 175         int ret = 0;
 176         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 177
 178         if (adev->powerplay.ip_funcs->sw_fini)
 179                 ret = adev->powerplay.ip_funcs->sw_fini(
 180                                         adev->powerplay.pp_handle);
 181         if (ret)
 182                 return ret;
 183
 184         return ret;
 185 }
 186
 187 static int amdgpu_pp_hw_init(void *handle)
 188 {
 189         int ret = 0;
 190         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 191
 192         if (adev->pp_enabled && adev->firmware.smu_load)
 193                 amdgpu_ucode_init_bo(adev);
 194
 195         if (adev->powerplay.ip_funcs->hw_init)
 196                 ret = adev->powerplay.ip_funcs->hw_init(
 197                                         adev->powerplay.pp_handle);
 198
 199         return ret;
 200 }
 201
 202 static int amdgpu_pp_hw_fini(void *handle)
 203 {
 204         int ret = 0;
 205         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 206
 207         if (adev->powerplay.ip_funcs->hw_fini)
 208                 ret = adev->powerplay.ip_funcs->hw_fini(
 209                                         adev->powerplay.pp_handle);
 210
 211         if (adev->pp_enabled && adev->firmware.smu_load)
 212                 amdgpu_ucode_fini_bo(adev);
 213
 214         return ret;
 215 }
 216
 217 static void amdgpu_pp_late_fini(void *handle)
 218 {
 219 #ifdef CONFIG_DRM_AMD_POWERPLAY
 220         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 221
 222         if (adev->pp_enabled) {
 223                 amdgpu_pm_sysfs_fini(adev);
 224                 amd_powerplay_fini(adev->powerplay.pp_handle);
 225         }
 226
 227         if (adev->powerplay.ip_funcs->late_fini)
 228                 adev->powerplay.ip_funcs->late_fini(
 229                           adev->powerplay.pp_handle);
 230 #endif
 231 }
 232
 233 static int amdgpu_pp_suspend(void *handle)
 234 {
 235         int ret = 0;
 236         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 237
 238         if (adev->powerplay.ip_funcs->suspend)
 239                 ret = adev->powerplay.ip_funcs->suspend(
 240                                          adev->powerplay.pp_handle);
 241         return ret;
 242 }
 243
 244 static int amdgpu_pp_resume(void *handle)
 245 {
 246         int ret = 0;
 247         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 248
 249         if (adev->powerplay.ip_funcs->resume)
 250                 ret = adev->powerplay.ip_funcs->resume(
 251                                         adev->powerplay.pp_handle);
 252         return ret;
 253 }
 254
 255 static int amdgpu_pp_set_clockgating_state(void *handle,
 256                                         enum amd_clockgating_state state)
 257 {
 258         int ret = 0;
 259         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 260
 261         if (adev->powerplay.ip_funcs->set_clockgating_state)
 262                 ret = adev->powerplay.ip_funcs->set_clockgating_state(
 263                                 adev->powerplay.pp_handle, state);
 264         return ret;
 265 }
 266
 267 static int amdgpu_pp_set_powergating_state(void *handle,
 268                                         enum amd_powergating_state state)
 269 {
 270         int ret = 0;
 271         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 272
 273         if (adev->powerplay.ip_funcs->set_powergating_state)
 274                 ret = adev->powerplay.ip_funcs->set_powergating_state(
 275                                  adev->powerplay.pp_handle, state);
 276         return ret;
 277 }
 278
 279
 280 static bool amdgpu_pp_is_idle(void *handle)
 281 {
 282         bool ret = true;
 283         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 284
 285         if (adev->powerplay.ip_funcs->is_idle)
 286                 ret = adev->powerplay.ip_funcs->is_idle(
 287                                         adev->powerplay.pp_handle);
 288         return ret;
 289 }
 290
 291 static int amdgpu_pp_wait_for_idle(void *handle)
 292 {
 293         int ret = 0;
 294         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 295
 296         if (adev->powerplay.ip_funcs->wait_for_idle)
 297                 ret = adev->powerplay.ip_funcs->wait_for_idle(
 298                                         adev->powerplay.pp_handle);
 299         return ret;
 300 }
 301
 302 static int amdgpu_pp_soft_reset(void *handle)
 303 {
 304         int ret = 0;
 305         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 306
 307         if (adev->powerplay.ip_funcs->soft_reset)
 308                 ret = adev->powerplay.ip_funcs->soft_reset(
 309                                         adev->powerplay.pp_handle);
 310         return ret;
 311 }
 312
 313 const struct amd_ip_funcs amdgpu_pp_ip_funcs = {
 314         .name = "amdgpu_powerplay",
 315         .early_init = amdgpu_pp_early_init,
 316         .late_init = amdgpu_pp_late_init,
 317         .sw_init = amdgpu_pp_sw_init,
 318         .sw_fini = amdgpu_pp_sw_fini,
 319         .hw_init = amdgpu_pp_hw_init,
 320         .hw_fini = amdgpu_pp_hw_fini,
 321         .late_fini = amdgpu_pp_late_fini,
 322         .suspend = amdgpu_pp_suspend,
 323         .resume = amdgpu_pp_resume,
 324         .is_idle = amdgpu_pp_is_idle,
 325         .wait_for_idle = amdgpu_pp_wait_for_idle,
 326         .soft_reset = amdgpu_pp_soft_reset,
 327         .set_clockgating_state = amdgpu_pp_set_clockgating_state,
 328         .set_powergating_state = amdgpu_pp_set_powergating_state,
 329 };