9b244c5a62956cf56338946b6b3172fa6ed0e2ac
[cascardo/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ttm.c
1 /*
2  * Copyright 2009 Jerome Glisse.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the
7  * "Software"), to deal in the Software without restriction, including
8  * without limitation the rights to use, copy, modify, merge, publish,
9  * distribute, sub license, and/or sell copies of the Software, and to
10  * permit persons to whom the Software is furnished to do so, subject to
11  * the following conditions:
12  *
13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
20  *
21  * The above copyright notice and this permission notice (including the
22  * next paragraph) shall be included in all copies or substantial portions
23  * of the Software.
24  *
25  */
26 /*
27  * Authors:
28  *    Jerome Glisse <glisse@freedesktop.org>
29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30  *    Dave Airlie
31  */
32 #include <ttm/ttm_bo_api.h>
33 #include <ttm/ttm_bo_driver.h>
34 #include <ttm/ttm_placement.h>
35 #include <ttm/ttm_module.h>
36 #include <ttm/ttm_page_alloc.h>
37 #include <drm/drmP.h>
38 #include <drm/amdgpu_drm.h>
39 #include <linux/seq_file.h>
40 #include <linux/slab.h>
41 #include <linux/swiotlb.h>
42 #include <linux/swap.h>
43 #include <linux/pagemap.h>
44 #include <linux/debugfs.h>
45 #include "amdgpu.h"
46 #include "bif/bif_4_1_d.h"
47
48 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
49
50 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
51 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
52
53 static struct amdgpu_device *amdgpu_get_adev(struct ttm_bo_device *bdev)
54 {
55         struct amdgpu_mman *mman;
56         struct amdgpu_device *adev;
57
58         mman = container_of(bdev, struct amdgpu_mman, bdev);
59         adev = container_of(mman, struct amdgpu_device, mman);
60         return adev;
61 }
62
63
64 /*
65  * Global memory.
66  */
67 static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref)
68 {
69         return ttm_mem_global_init(ref->object);
70 }
71
72 static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
73 {
74         ttm_mem_global_release(ref->object);
75 }
76
77 static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
78 {
79         struct drm_global_reference *global_ref;
80         struct amdgpu_ring *ring;
81         struct amd_sched_rq *rq;
82         int r;
83
84         adev->mman.mem_global_referenced = false;
85         global_ref = &adev->mman.mem_global_ref;
86         global_ref->global_type = DRM_GLOBAL_TTM_MEM;
87         global_ref->size = sizeof(struct ttm_mem_global);
88         global_ref->init = &amdgpu_ttm_mem_global_init;
89         global_ref->release = &amdgpu_ttm_mem_global_release;
90         r = drm_global_item_ref(global_ref);
91         if (r != 0) {
92                 DRM_ERROR("Failed setting up TTM memory accounting "
93                           "subsystem.\n");
94                 return r;
95         }
96
97         adev->mman.bo_global_ref.mem_glob =
98                 adev->mman.mem_global_ref.object;
99         global_ref = &adev->mman.bo_global_ref.ref;
100         global_ref->global_type = DRM_GLOBAL_TTM_BO;
101         global_ref->size = sizeof(struct ttm_bo_global);
102         global_ref->init = &ttm_bo_global_init;
103         global_ref->release = &ttm_bo_global_release;
104         r = drm_global_item_ref(global_ref);
105         if (r != 0) {
106                 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
107                 drm_global_item_unref(&adev->mman.mem_global_ref);
108                 return r;
109         }
110
111         ring = adev->mman.buffer_funcs_ring;
112         rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
113         r = amd_sched_entity_init(&ring->sched, &adev->mman.entity,
114                                   rq, amdgpu_sched_jobs);
115         if (r != 0) {
116                 DRM_ERROR("Failed setting up TTM BO move run queue.\n");
117                 drm_global_item_unref(&adev->mman.mem_global_ref);
118                 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
119                 return r;
120         }
121
122         adev->mman.mem_global_referenced = true;
123
124         return 0;
125 }
126
127 static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
128 {
129         if (adev->mman.mem_global_referenced) {
130                 amd_sched_entity_fini(adev->mman.entity.sched,
131                                       &adev->mman.entity);
132                 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
133                 drm_global_item_unref(&adev->mman.mem_global_ref);
134                 adev->mman.mem_global_referenced = false;
135         }
136 }
137
138 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
139 {
140         return 0;
141 }
142
143 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
144                                 struct ttm_mem_type_manager *man)
145 {
146         struct amdgpu_device *adev;
147
148         adev = amdgpu_get_adev(bdev);
149
150         switch (type) {
151         case TTM_PL_SYSTEM:
152                 /* System memory */
153                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
154                 man->available_caching = TTM_PL_MASK_CACHING;
155                 man->default_caching = TTM_PL_FLAG_CACHED;
156                 break;
157         case TTM_PL_TT:
158                 man->func = &ttm_bo_manager_func;
159                 man->gpu_offset = adev->mc.gtt_start;
160                 man->available_caching = TTM_PL_MASK_CACHING;
161                 man->default_caching = TTM_PL_FLAG_CACHED;
162                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
163                 break;
164         case TTM_PL_VRAM:
165                 /* "On-card" video ram */
166                 man->func = &ttm_bo_manager_func;
167                 man->gpu_offset = adev->mc.vram_start;
168                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
169                              TTM_MEMTYPE_FLAG_MAPPABLE;
170                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
171                 man->default_caching = TTM_PL_FLAG_WC;
172                 break;
173         case AMDGPU_PL_GDS:
174         case AMDGPU_PL_GWS:
175         case AMDGPU_PL_OA:
176                 /* On-chip GDS memory*/
177                 man->func = &ttm_bo_manager_func;
178                 man->gpu_offset = 0;
179                 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
180                 man->available_caching = TTM_PL_FLAG_UNCACHED;
181                 man->default_caching = TTM_PL_FLAG_UNCACHED;
182                 break;
183         default:
184                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
185                 return -EINVAL;
186         }
187         return 0;
188 }
189
190 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
191                                 struct ttm_placement *placement)
192 {
193         struct amdgpu_bo *rbo;
194         static struct ttm_place placements = {
195                 .fpfn = 0,
196                 .lpfn = 0,
197                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
198         };
199
200         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) {
201                 placement->placement = &placements;
202                 placement->busy_placement = &placements;
203                 placement->num_placement = 1;
204                 placement->num_busy_placement = 1;
205                 return;
206         }
207         rbo = container_of(bo, struct amdgpu_bo, tbo);
208         switch (bo->mem.mem_type) {
209         case TTM_PL_VRAM:
210                 if (rbo->adev->mman.buffer_funcs_ring->ready == false)
211                         amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_CPU);
212                 else
213                         amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_GTT);
214                 break;
215         case TTM_PL_TT:
216         default:
217                 amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_CPU);
218         }
219         *placement = rbo->placement;
220 }
221
222 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
223 {
224         struct amdgpu_bo *rbo = container_of(bo, struct amdgpu_bo, tbo);
225
226         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
227                 return -EPERM;
228         return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp);
229 }
230
231 static void amdgpu_move_null(struct ttm_buffer_object *bo,
232                              struct ttm_mem_reg *new_mem)
233 {
234         struct ttm_mem_reg *old_mem = &bo->mem;
235
236         BUG_ON(old_mem->mm_node != NULL);
237         *old_mem = *new_mem;
238         new_mem->mm_node = NULL;
239 }
240
241 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
242                         bool evict, bool no_wait_gpu,
243                         struct ttm_mem_reg *new_mem,
244                         struct ttm_mem_reg *old_mem)
245 {
246         struct amdgpu_device *adev;
247         struct amdgpu_ring *ring;
248         uint64_t old_start, new_start;
249         struct fence *fence;
250         int r;
251
252         adev = amdgpu_get_adev(bo->bdev);
253         ring = adev->mman.buffer_funcs_ring;
254         old_start = old_mem->start << PAGE_SHIFT;
255         new_start = new_mem->start << PAGE_SHIFT;
256
257         switch (old_mem->mem_type) {
258         case TTM_PL_VRAM:
259                 old_start += adev->mc.vram_start;
260                 break;
261         case TTM_PL_TT:
262                 old_start += adev->mc.gtt_start;
263                 break;
264         default:
265                 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
266                 return -EINVAL;
267         }
268         switch (new_mem->mem_type) {
269         case TTM_PL_VRAM:
270                 new_start += adev->mc.vram_start;
271                 break;
272         case TTM_PL_TT:
273                 new_start += adev->mc.gtt_start;
274                 break;
275         default:
276                 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
277                 return -EINVAL;
278         }
279         if (!ring->ready) {
280                 DRM_ERROR("Trying to move memory with ring turned off.\n");
281                 return -EINVAL;
282         }
283
284         BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0);
285
286         r = amdgpu_copy_buffer(ring, old_start, new_start,
287                                new_mem->num_pages * PAGE_SIZE, /* bytes */
288                                bo->resv, &fence);
289         /* FIXME: handle copy error */
290         r = ttm_bo_move_accel_cleanup(bo, fence,
291                                       evict, no_wait_gpu, new_mem);
292         fence_put(fence);
293         return r;
294 }
295
296 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo,
297                                 bool evict, bool interruptible,
298                                 bool no_wait_gpu,
299                                 struct ttm_mem_reg *new_mem)
300 {
301         struct amdgpu_device *adev;
302         struct ttm_mem_reg *old_mem = &bo->mem;
303         struct ttm_mem_reg tmp_mem;
304         struct ttm_place placements;
305         struct ttm_placement placement;
306         int r;
307
308         adev = amdgpu_get_adev(bo->bdev);
309         tmp_mem = *new_mem;
310         tmp_mem.mm_node = NULL;
311         placement.num_placement = 1;
312         placement.placement = &placements;
313         placement.num_busy_placement = 1;
314         placement.busy_placement = &placements;
315         placements.fpfn = 0;
316         placements.lpfn = 0;
317         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
318         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
319                              interruptible, no_wait_gpu);
320         if (unlikely(r)) {
321                 return r;
322         }
323
324         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
325         if (unlikely(r)) {
326                 goto out_cleanup;
327         }
328
329         r = ttm_tt_bind(bo->ttm, &tmp_mem);
330         if (unlikely(r)) {
331                 goto out_cleanup;
332         }
333         r = amdgpu_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
334         if (unlikely(r)) {
335                 goto out_cleanup;
336         }
337         r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem);
338 out_cleanup:
339         ttm_bo_mem_put(bo, &tmp_mem);
340         return r;
341 }
342
343 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo,
344                                 bool evict, bool interruptible,
345                                 bool no_wait_gpu,
346                                 struct ttm_mem_reg *new_mem)
347 {
348         struct amdgpu_device *adev;
349         struct ttm_mem_reg *old_mem = &bo->mem;
350         struct ttm_mem_reg tmp_mem;
351         struct ttm_placement placement;
352         struct ttm_place placements;
353         int r;
354
355         adev = amdgpu_get_adev(bo->bdev);
356         tmp_mem = *new_mem;
357         tmp_mem.mm_node = NULL;
358         placement.num_placement = 1;
359         placement.placement = &placements;
360         placement.num_busy_placement = 1;
361         placement.busy_placement = &placements;
362         placements.fpfn = 0;
363         placements.lpfn = 0;
364         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
365         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
366                              interruptible, no_wait_gpu);
367         if (unlikely(r)) {
368                 return r;
369         }
370         r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem);
371         if (unlikely(r)) {
372                 goto out_cleanup;
373         }
374         r = amdgpu_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
375         if (unlikely(r)) {
376                 goto out_cleanup;
377         }
378 out_cleanup:
379         ttm_bo_mem_put(bo, &tmp_mem);
380         return r;
381 }
382
383 static int amdgpu_bo_move(struct ttm_buffer_object *bo,
384                         bool evict, bool interruptible,
385                         bool no_wait_gpu,
386                         struct ttm_mem_reg *new_mem)
387 {
388         struct amdgpu_device *adev;
389         struct amdgpu_bo *abo;
390         struct ttm_mem_reg *old_mem = &bo->mem;
391         int r;
392
393         r = ttm_bo_wait(bo, interruptible, no_wait_gpu);
394         if (r)
395                 return r;
396
397         /* Can't move a pinned BO */
398         abo = container_of(bo, struct amdgpu_bo, tbo);
399         if (WARN_ON_ONCE(abo->pin_count > 0))
400                 return -EINVAL;
401
402         adev = amdgpu_get_adev(bo->bdev);
403         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
404                 amdgpu_move_null(bo, new_mem);
405                 return 0;
406         }
407         if ((old_mem->mem_type == TTM_PL_TT &&
408              new_mem->mem_type == TTM_PL_SYSTEM) ||
409             (old_mem->mem_type == TTM_PL_SYSTEM &&
410              new_mem->mem_type == TTM_PL_TT)) {
411                 /* bind is enough */
412                 amdgpu_move_null(bo, new_mem);
413                 return 0;
414         }
415         if (adev->mman.buffer_funcs == NULL ||
416             adev->mman.buffer_funcs_ring == NULL ||
417             !adev->mman.buffer_funcs_ring->ready) {
418                 /* use memcpy */
419                 goto memcpy;
420         }
421
422         if (old_mem->mem_type == TTM_PL_VRAM &&
423             new_mem->mem_type == TTM_PL_SYSTEM) {
424                 r = amdgpu_move_vram_ram(bo, evict, interruptible,
425                                         no_wait_gpu, new_mem);
426         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
427                    new_mem->mem_type == TTM_PL_VRAM) {
428                 r = amdgpu_move_ram_vram(bo, evict, interruptible,
429                                             no_wait_gpu, new_mem);
430         } else {
431                 r = amdgpu_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
432         }
433
434         if (r) {
435 memcpy:
436                 r = ttm_bo_move_memcpy(bo, evict, interruptible,
437                                        no_wait_gpu, new_mem);
438                 if (r) {
439                         return r;
440                 }
441         }
442
443         /* update statistics */
444         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
445         return 0;
446 }
447
448 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
449 {
450         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
451         struct amdgpu_device *adev = amdgpu_get_adev(bdev);
452
453         mem->bus.addr = NULL;
454         mem->bus.offset = 0;
455         mem->bus.size = mem->num_pages << PAGE_SHIFT;
456         mem->bus.base = 0;
457         mem->bus.is_iomem = false;
458         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
459                 return -EINVAL;
460         switch (mem->mem_type) {
461         case TTM_PL_SYSTEM:
462                 /* system memory */
463                 return 0;
464         case TTM_PL_TT:
465                 break;
466         case TTM_PL_VRAM:
467                 mem->bus.offset = mem->start << PAGE_SHIFT;
468                 /* check if it's visible */
469                 if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size)
470                         return -EINVAL;
471                 mem->bus.base = adev->mc.aper_base;
472                 mem->bus.is_iomem = true;
473 #ifdef __alpha__
474                 /*
475                  * Alpha: use bus.addr to hold the ioremap() return,
476                  * so we can modify bus.base below.
477                  */
478                 if (mem->placement & TTM_PL_FLAG_WC)
479                         mem->bus.addr =
480                                 ioremap_wc(mem->bus.base + mem->bus.offset,
481                                            mem->bus.size);
482                 else
483                         mem->bus.addr =
484                                 ioremap_nocache(mem->bus.base + mem->bus.offset,
485                                                 mem->bus.size);
486
487                 /*
488                  * Alpha: Use just the bus offset plus
489                  * the hose/domain memory base for bus.base.
490                  * It then can be used to build PTEs for VRAM
491                  * access, as done in ttm_bo_vm_fault().
492                  */
493                 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
494                         adev->ddev->hose->dense_mem_base;
495 #endif
496                 break;
497         default:
498                 return -EINVAL;
499         }
500         return 0;
501 }
502
503 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
504 {
505 }
506
507 /*
508  * TTM backend functions.
509  */
510 struct amdgpu_ttm_gup_task_list {
511         struct list_head        list;
512         struct task_struct      *task;
513 };
514
515 struct amdgpu_ttm_tt {
516         struct ttm_dma_tt       ttm;
517         struct amdgpu_device    *adev;
518         u64                     offset;
519         uint64_t                userptr;
520         struct mm_struct        *usermm;
521         uint32_t                userflags;
522         spinlock_t              guptasklock;
523         struct list_head        guptasks;
524         atomic_t                mmu_invalidations;
525 };
526
527 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
528 {
529         struct amdgpu_ttm_tt *gtt = (void *)ttm;
530         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
531         unsigned pinned = 0;
532         int r;
533
534         if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
535                 /* check that we only use anonymous memory
536                    to prevent problems with writeback */
537                 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
538                 struct vm_area_struct *vma;
539
540                 vma = find_vma(gtt->usermm, gtt->userptr);
541                 if (!vma || vma->vm_file || vma->vm_end < end)
542                         return -EPERM;
543         }
544
545         do {
546                 unsigned num_pages = ttm->num_pages - pinned;
547                 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
548                 struct page **p = pages + pinned;
549                 struct amdgpu_ttm_gup_task_list guptask;
550
551                 guptask.task = current;
552                 spin_lock(&gtt->guptasklock);
553                 list_add(&guptask.list, &gtt->guptasks);
554                 spin_unlock(&gtt->guptasklock);
555
556                 r = get_user_pages(userptr, num_pages, write, 0, p, NULL);
557
558                 spin_lock(&gtt->guptasklock);
559                 list_del(&guptask.list);
560                 spin_unlock(&gtt->guptasklock);
561
562                 if (r < 0)
563                         goto release_pages;
564
565                 pinned += r;
566
567         } while (pinned < ttm->num_pages);
568
569         return 0;
570
571 release_pages:
572         release_pages(pages, pinned, 0);
573         return r;
574 }
575
576 /* prepare the sg table with the user pages */
577 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
578 {
579         struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev);
580         struct amdgpu_ttm_tt *gtt = (void *)ttm;
581         unsigned nents;
582         int r;
583
584         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
585         enum dma_data_direction direction = write ?
586                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
587
588         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
589                                       ttm->num_pages << PAGE_SHIFT,
590                                       GFP_KERNEL);
591         if (r)
592                 goto release_sg;
593
594         r = -ENOMEM;
595         nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
596         if (nents != ttm->sg->nents)
597                 goto release_sg;
598
599         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
600                                          gtt->ttm.dma_address, ttm->num_pages);
601
602         return 0;
603
604 release_sg:
605         kfree(ttm->sg);
606         return r;
607 }
608
609 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
610 {
611         struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev);
612         struct amdgpu_ttm_tt *gtt = (void *)ttm;
613         struct sg_page_iter sg_iter;
614
615         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
616         enum dma_data_direction direction = write ?
617                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
618
619         /* double check that we don't free the table twice */
620         if (!ttm->sg->sgl)
621                 return;
622
623         /* free the sg table and pages again */
624         dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
625
626         for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) {
627                 struct page *page = sg_page_iter_page(&sg_iter);
628                 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
629                         set_page_dirty(page);
630
631                 mark_page_accessed(page);
632                 put_page(page);
633         }
634
635         sg_free_table(ttm->sg);
636 }
637
638 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
639                                    struct ttm_mem_reg *bo_mem)
640 {
641         struct amdgpu_ttm_tt *gtt = (void*)ttm;
642         uint32_t flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem);
643         int r;
644
645         if (gtt->userptr) {
646                 r = amdgpu_ttm_tt_pin_userptr(ttm);
647                 if (r) {
648                         DRM_ERROR("failed to pin userptr\n");
649                         return r;
650                 }
651         }
652         gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
653         if (!ttm->num_pages) {
654                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
655                      ttm->num_pages, bo_mem, ttm);
656         }
657
658         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
659             bo_mem->mem_type == AMDGPU_PL_GWS ||
660             bo_mem->mem_type == AMDGPU_PL_OA)
661                 return -EINVAL;
662
663         r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages,
664                 ttm->pages, gtt->ttm.dma_address, flags);
665
666         if (r) {
667                 DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
668                           ttm->num_pages, (unsigned)gtt->offset);
669                 return r;
670         }
671         return 0;
672 }
673
674 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
675 {
676         struct amdgpu_ttm_tt *gtt = (void *)ttm;
677
678         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
679         if (gtt->adev->gart.ready)
680                 amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages);
681
682         if (gtt->userptr)
683                 amdgpu_ttm_tt_unpin_userptr(ttm);
684
685         return 0;
686 }
687
688 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
689 {
690         struct amdgpu_ttm_tt *gtt = (void *)ttm;
691
692         ttm_dma_tt_fini(&gtt->ttm);
693         kfree(gtt);
694 }
695
696 static struct ttm_backend_func amdgpu_backend_func = {
697         .bind = &amdgpu_ttm_backend_bind,
698         .unbind = &amdgpu_ttm_backend_unbind,
699         .destroy = &amdgpu_ttm_backend_destroy,
700 };
701
702 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev,
703                                     unsigned long size, uint32_t page_flags,
704                                     struct page *dummy_read_page)
705 {
706         struct amdgpu_device *adev;
707         struct amdgpu_ttm_tt *gtt;
708
709         adev = amdgpu_get_adev(bdev);
710
711         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
712         if (gtt == NULL) {
713                 return NULL;
714         }
715         gtt->ttm.ttm.func = &amdgpu_backend_func;
716         gtt->adev = adev;
717         if (ttm_dma_tt_init(&gtt->ttm, bdev, size, page_flags, dummy_read_page)) {
718                 kfree(gtt);
719                 return NULL;
720         }
721         return &gtt->ttm.ttm;
722 }
723
724 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm)
725 {
726         struct amdgpu_device *adev;
727         struct amdgpu_ttm_tt *gtt = (void *)ttm;
728         unsigned i;
729         int r;
730         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
731
732         if (ttm->state != tt_unpopulated)
733                 return 0;
734
735         if (gtt && gtt->userptr) {
736                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
737                 if (!ttm->sg)
738                         return -ENOMEM;
739
740                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
741                 ttm->state = tt_unbound;
742                 return 0;
743         }
744
745         if (slave && ttm->sg) {
746                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
747                                                  gtt->ttm.dma_address, ttm->num_pages);
748                 ttm->state = tt_unbound;
749                 return 0;
750         }
751
752         adev = amdgpu_get_adev(ttm->bdev);
753
754 #ifdef CONFIG_SWIOTLB
755         if (swiotlb_nr_tbl()) {
756                 return ttm_dma_populate(&gtt->ttm, adev->dev);
757         }
758 #endif
759
760         r = ttm_pool_populate(ttm);
761         if (r) {
762                 return r;
763         }
764
765         for (i = 0; i < ttm->num_pages; i++) {
766                 gtt->ttm.dma_address[i] = pci_map_page(adev->pdev, ttm->pages[i],
767                                                        0, PAGE_SIZE,
768                                                        PCI_DMA_BIDIRECTIONAL);
769                 if (pci_dma_mapping_error(adev->pdev, gtt->ttm.dma_address[i])) {
770                         while (i--) {
771                                 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
772                                                PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
773                                 gtt->ttm.dma_address[i] = 0;
774                         }
775                         ttm_pool_unpopulate(ttm);
776                         return -EFAULT;
777                 }
778         }
779         return 0;
780 }
781
782 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
783 {
784         struct amdgpu_device *adev;
785         struct amdgpu_ttm_tt *gtt = (void *)ttm;
786         unsigned i;
787         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
788
789         if (gtt && gtt->userptr) {
790                 kfree(ttm->sg);
791                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
792                 return;
793         }
794
795         if (slave)
796                 return;
797
798         adev = amdgpu_get_adev(ttm->bdev);
799
800 #ifdef CONFIG_SWIOTLB
801         if (swiotlb_nr_tbl()) {
802                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
803                 return;
804         }
805 #endif
806
807         for (i = 0; i < ttm->num_pages; i++) {
808                 if (gtt->ttm.dma_address[i]) {
809                         pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
810                                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
811                 }
812         }
813
814         ttm_pool_unpopulate(ttm);
815 }
816
817 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
818                               uint32_t flags)
819 {
820         struct amdgpu_ttm_tt *gtt = (void *)ttm;
821
822         if (gtt == NULL)
823                 return -EINVAL;
824
825         gtt->userptr = addr;
826         gtt->usermm = current->mm;
827         gtt->userflags = flags;
828         spin_lock_init(&gtt->guptasklock);
829         INIT_LIST_HEAD(&gtt->guptasks);
830         atomic_set(&gtt->mmu_invalidations, 0);
831
832         return 0;
833 }
834
835 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
836 {
837         struct amdgpu_ttm_tt *gtt = (void *)ttm;
838
839         if (gtt == NULL)
840                 return NULL;
841
842         return gtt->usermm;
843 }
844
845 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
846                                   unsigned long end)
847 {
848         struct amdgpu_ttm_tt *gtt = (void *)ttm;
849         struct amdgpu_ttm_gup_task_list *entry;
850         unsigned long size;
851
852         if (gtt == NULL || !gtt->userptr)
853                 return false;
854
855         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
856         if (gtt->userptr > end || gtt->userptr + size <= start)
857                 return false;
858
859         spin_lock(&gtt->guptasklock);
860         list_for_each_entry(entry, &gtt->guptasks, list) {
861                 if (entry->task == current) {
862                         spin_unlock(&gtt->guptasklock);
863                         return false;
864                 }
865         }
866         spin_unlock(&gtt->guptasklock);
867
868         atomic_inc(&gtt->mmu_invalidations);
869
870         return true;
871 }
872
873 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
874                                        int *last_invalidated)
875 {
876         struct amdgpu_ttm_tt *gtt = (void *)ttm;
877         int prev_invalidated = *last_invalidated;
878
879         *last_invalidated = atomic_read(&gtt->mmu_invalidations);
880         return prev_invalidated != *last_invalidated;
881 }
882
883 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
884 {
885         struct amdgpu_ttm_tt *gtt = (void *)ttm;
886
887         if (gtt == NULL)
888                 return false;
889
890         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
891 }
892
893 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
894                                  struct ttm_mem_reg *mem)
895 {
896         uint32_t flags = 0;
897
898         if (mem && mem->mem_type != TTM_PL_SYSTEM)
899                 flags |= AMDGPU_PTE_VALID;
900
901         if (mem && mem->mem_type == TTM_PL_TT) {
902                 flags |= AMDGPU_PTE_SYSTEM;
903
904                 if (ttm->caching_state == tt_cached)
905                         flags |= AMDGPU_PTE_SNOOPED;
906         }
907
908         if (adev->asic_type >= CHIP_TONGA)
909                 flags |= AMDGPU_PTE_EXECUTABLE;
910
911         flags |= AMDGPU_PTE_READABLE;
912
913         if (!amdgpu_ttm_tt_is_readonly(ttm))
914                 flags |= AMDGPU_PTE_WRITEABLE;
915
916         return flags;
917 }
918
919 static void amdgpu_ttm_lru_removal(struct ttm_buffer_object *tbo)
920 {
921         struct amdgpu_device *adev = amdgpu_get_adev(tbo->bdev);
922         unsigned i, j;
923
924         for (i = 0; i < AMDGPU_TTM_LRU_SIZE; ++i) {
925                 struct amdgpu_mman_lru *lru = &adev->mman.log2_size[i];
926
927                 for (j = 0; j < TTM_NUM_MEM_TYPES; ++j)
928                         if (&tbo->lru == lru->lru[j])
929                                 lru->lru[j] = tbo->lru.prev;
930
931                 if (&tbo->swap == lru->swap_lru)
932                         lru->swap_lru = tbo->swap.prev;
933         }
934 }
935
936 static struct amdgpu_mman_lru *amdgpu_ttm_lru(struct ttm_buffer_object *tbo)
937 {
938         struct amdgpu_device *adev = amdgpu_get_adev(tbo->bdev);
939         unsigned log2_size = min(ilog2(tbo->num_pages),
940                                  AMDGPU_TTM_LRU_SIZE - 1);
941
942         return &adev->mman.log2_size[log2_size];
943 }
944
945 static struct list_head *amdgpu_ttm_lru_tail(struct ttm_buffer_object *tbo)
946 {
947         struct amdgpu_mman_lru *lru = amdgpu_ttm_lru(tbo);
948         struct list_head *res = lru->lru[tbo->mem.mem_type];
949
950         lru->lru[tbo->mem.mem_type] = &tbo->lru;
951
952         return res;
953 }
954
955 static struct list_head *amdgpu_ttm_swap_lru_tail(struct ttm_buffer_object *tbo)
956 {
957         struct amdgpu_mman_lru *lru = amdgpu_ttm_lru(tbo);
958         struct list_head *res = lru->swap_lru;
959
960         lru->swap_lru = &tbo->swap;
961
962         return res;
963 }
964
965 static struct ttm_bo_driver amdgpu_bo_driver = {
966         .ttm_tt_create = &amdgpu_ttm_tt_create,
967         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
968         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
969         .invalidate_caches = &amdgpu_invalidate_caches,
970         .init_mem_type = &amdgpu_init_mem_type,
971         .evict_flags = &amdgpu_evict_flags,
972         .move = &amdgpu_bo_move,
973         .verify_access = &amdgpu_verify_access,
974         .move_notify = &amdgpu_bo_move_notify,
975         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
976         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
977         .io_mem_free = &amdgpu_ttm_io_mem_free,
978         .lru_removal = &amdgpu_ttm_lru_removal,
979         .lru_tail = &amdgpu_ttm_lru_tail,
980         .swap_lru_tail = &amdgpu_ttm_swap_lru_tail,
981 };
982
983 int amdgpu_ttm_init(struct amdgpu_device *adev)
984 {
985         unsigned i, j;
986         int r;
987
988         r = amdgpu_ttm_global_init(adev);
989         if (r) {
990                 return r;
991         }
992         /* No others user of address space so set it to 0 */
993         r = ttm_bo_device_init(&adev->mman.bdev,
994                                adev->mman.bo_global_ref.ref.object,
995                                &amdgpu_bo_driver,
996                                adev->ddev->anon_inode->i_mapping,
997                                DRM_FILE_PAGE_OFFSET,
998                                adev->need_dma32);
999         if (r) {
1000                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1001                 return r;
1002         }
1003
1004         for (i = 0; i < AMDGPU_TTM_LRU_SIZE; ++i) {
1005                 struct amdgpu_mman_lru *lru = &adev->mman.log2_size[i];
1006
1007                 for (j = 0; j < TTM_NUM_MEM_TYPES; ++j)
1008                         lru->lru[j] = &adev->mman.bdev.man[j].lru;
1009                 lru->swap_lru = &adev->mman.bdev.glob->swap_lru;
1010         }
1011
1012         adev->mman.initialized = true;
1013         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1014                                 adev->mc.real_vram_size >> PAGE_SHIFT);
1015         if (r) {
1016                 DRM_ERROR("Failed initializing VRAM heap.\n");
1017                 return r;
1018         }
1019         /* Change the size here instead of the init above so only lpfn is affected */
1020         amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
1021
1022         r = amdgpu_bo_create(adev, 256 * 1024, PAGE_SIZE, true,
1023                              AMDGPU_GEM_DOMAIN_VRAM,
1024                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
1025                              NULL, NULL, &adev->stollen_vga_memory);
1026         if (r) {
1027                 return r;
1028         }
1029         r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
1030         if (r)
1031                 return r;
1032         r = amdgpu_bo_pin(adev->stollen_vga_memory, AMDGPU_GEM_DOMAIN_VRAM, NULL);
1033         amdgpu_bo_unreserve(adev->stollen_vga_memory);
1034         if (r) {
1035                 amdgpu_bo_unref(&adev->stollen_vga_memory);
1036                 return r;
1037         }
1038         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1039                  (unsigned) (adev->mc.real_vram_size / (1024 * 1024)));
1040         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT,
1041                                 adev->mc.gtt_size >> PAGE_SHIFT);
1042         if (r) {
1043                 DRM_ERROR("Failed initializing GTT heap.\n");
1044                 return r;
1045         }
1046         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1047                  (unsigned)(adev->mc.gtt_size / (1024 * 1024)));
1048
1049         adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT;
1050         adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT;
1051         adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT;
1052         adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT;
1053         adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT;
1054         adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT;
1055         adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT;
1056         adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT;
1057         adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT;
1058         /* GDS Memory */
1059         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1060                                 adev->gds.mem.total_size >> PAGE_SHIFT);
1061         if (r) {
1062                 DRM_ERROR("Failed initializing GDS heap.\n");
1063                 return r;
1064         }
1065
1066         /* GWS */
1067         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1068                                 adev->gds.gws.total_size >> PAGE_SHIFT);
1069         if (r) {
1070                 DRM_ERROR("Failed initializing gws heap.\n");
1071                 return r;
1072         }
1073
1074         /* OA */
1075         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1076                                 adev->gds.oa.total_size >> PAGE_SHIFT);
1077         if (r) {
1078                 DRM_ERROR("Failed initializing oa heap.\n");
1079                 return r;
1080         }
1081
1082         r = amdgpu_ttm_debugfs_init(adev);
1083         if (r) {
1084                 DRM_ERROR("Failed to init debugfs\n");
1085                 return r;
1086         }
1087         return 0;
1088 }
1089
1090 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1091 {
1092         int r;
1093
1094         if (!adev->mman.initialized)
1095                 return;
1096         amdgpu_ttm_debugfs_fini(adev);
1097         if (adev->stollen_vga_memory) {
1098                 r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
1099                 if (r == 0) {
1100                         amdgpu_bo_unpin(adev->stollen_vga_memory);
1101                         amdgpu_bo_unreserve(adev->stollen_vga_memory);
1102                 }
1103                 amdgpu_bo_unref(&adev->stollen_vga_memory);
1104         }
1105         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1106         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1107         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1108         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1109         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1110         ttm_bo_device_release(&adev->mman.bdev);
1111         amdgpu_gart_fini(adev);
1112         amdgpu_ttm_global_fini(adev);
1113         adev->mman.initialized = false;
1114         DRM_INFO("amdgpu: ttm finalized\n");
1115 }
1116
1117 /* this should only be called at bootup or when userspace
1118  * isn't running */
1119 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size)
1120 {
1121         struct ttm_mem_type_manager *man;
1122
1123         if (!adev->mman.initialized)
1124                 return;
1125
1126         man = &adev->mman.bdev.man[TTM_PL_VRAM];
1127         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1128         man->size = size >> PAGE_SHIFT;
1129 }
1130
1131 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1132 {
1133         struct drm_file *file_priv;
1134         struct amdgpu_device *adev;
1135
1136         if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
1137                 return -EINVAL;
1138
1139         file_priv = filp->private_data;
1140         adev = file_priv->minor->dev->dev_private;
1141         if (adev == NULL)
1142                 return -EINVAL;
1143
1144         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1145 }
1146
1147 int amdgpu_copy_buffer(struct amdgpu_ring *ring,
1148                        uint64_t src_offset,
1149                        uint64_t dst_offset,
1150                        uint32_t byte_count,
1151                        struct reservation_object *resv,
1152                        struct fence **fence)
1153 {
1154         struct amdgpu_device *adev = ring->adev;
1155         struct amdgpu_job *job;
1156
1157         uint32_t max_bytes;
1158         unsigned num_loops, num_dw;
1159         unsigned i;
1160         int r;
1161
1162         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1163         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1164         num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
1165
1166         /* for IB padding */
1167         while (num_dw & 0x7)
1168                 num_dw++;
1169
1170         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1171         if (r)
1172                 return r;
1173
1174         if (resv) {
1175                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1176                                      AMDGPU_FENCE_OWNER_UNDEFINED);
1177                 if (r) {
1178                         DRM_ERROR("sync failed (%d).\n", r);
1179                         goto error_free;
1180                 }
1181         }
1182
1183         for (i = 0; i < num_loops; i++) {
1184                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1185
1186                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1187                                         dst_offset, cur_size_in_bytes);
1188
1189                 src_offset += cur_size_in_bytes;
1190                 dst_offset += cur_size_in_bytes;
1191                 byte_count -= cur_size_in_bytes;
1192         }
1193
1194         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1195         WARN_ON(job->ibs[0].length_dw > num_dw);
1196         r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1197                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1198         if (r)
1199                 goto error_free;
1200
1201         return 0;
1202
1203 error_free:
1204         amdgpu_job_free(job);
1205         return r;
1206 }
1207
1208 #if defined(CONFIG_DEBUG_FS)
1209
1210 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
1211 {
1212         struct drm_info_node *node = (struct drm_info_node *)m->private;
1213         unsigned ttm_pl = *(int *)node->info_ent->data;
1214         struct drm_device *dev = node->minor->dev;
1215         struct amdgpu_device *adev = dev->dev_private;
1216         struct drm_mm *mm = (struct drm_mm *)adev->mman.bdev.man[ttm_pl].priv;
1217         int ret;
1218         struct ttm_bo_global *glob = adev->mman.bdev.glob;
1219
1220         spin_lock(&glob->lru_lock);
1221         ret = drm_mm_dump_table(m, mm);
1222         spin_unlock(&glob->lru_lock);
1223         if (ttm_pl == TTM_PL_VRAM)
1224                 seq_printf(m, "man size:%llu pages, ram usage:%lluMB, vis usage:%lluMB\n",
1225                            adev->mman.bdev.man[ttm_pl].size,
1226                            (u64)atomic64_read(&adev->vram_usage) >> 20,
1227                            (u64)atomic64_read(&adev->vram_vis_usage) >> 20);
1228         return ret;
1229 }
1230
1231 static int ttm_pl_vram = TTM_PL_VRAM;
1232 static int ttm_pl_tt = TTM_PL_TT;
1233
1234 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
1235         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram},
1236         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt},
1237         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1238 #ifdef CONFIG_SWIOTLB
1239         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1240 #endif
1241 };
1242
1243 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
1244                                     size_t size, loff_t *pos)
1245 {
1246         struct amdgpu_device *adev = f->f_inode->i_private;
1247         ssize_t result = 0;
1248         int r;
1249
1250         if (size & 0x3 || *pos & 0x3)
1251                 return -EINVAL;
1252
1253         while (size) {
1254                 unsigned long flags;
1255                 uint32_t value;
1256
1257                 if (*pos >= adev->mc.mc_vram_size)
1258                         return result;
1259
1260                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1261                 WREG32(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
1262                 WREG32(mmMM_INDEX_HI, *pos >> 31);
1263                 value = RREG32(mmMM_DATA);
1264                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1265
1266                 r = put_user(value, (uint32_t *)buf);
1267                 if (r)
1268                         return r;
1269
1270                 result += 4;
1271                 buf += 4;
1272                 *pos += 4;
1273                 size -= 4;
1274         }
1275
1276         return result;
1277 }
1278
1279 static const struct file_operations amdgpu_ttm_vram_fops = {
1280         .owner = THIS_MODULE,
1281         .read = amdgpu_ttm_vram_read,
1282         .llseek = default_llseek
1283 };
1284
1285 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1286
1287 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
1288                                    size_t size, loff_t *pos)
1289 {
1290         struct amdgpu_device *adev = f->f_inode->i_private;
1291         ssize_t result = 0;
1292         int r;
1293
1294         while (size) {
1295                 loff_t p = *pos / PAGE_SIZE;
1296                 unsigned off = *pos & ~PAGE_MASK;
1297                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1298                 struct page *page;
1299                 void *ptr;
1300
1301                 if (p >= adev->gart.num_cpu_pages)
1302                         return result;
1303
1304                 page = adev->gart.pages[p];
1305                 if (page) {
1306                         ptr = kmap(page);
1307                         ptr += off;
1308
1309                         r = copy_to_user(buf, ptr, cur_size);
1310                         kunmap(adev->gart.pages[p]);
1311                 } else
1312                         r = clear_user(buf, cur_size);
1313
1314                 if (r)
1315                         return -EFAULT;
1316
1317                 result += cur_size;
1318                 buf += cur_size;
1319                 *pos += cur_size;
1320                 size -= cur_size;
1321         }
1322
1323         return result;
1324 }
1325
1326 static const struct file_operations amdgpu_ttm_gtt_fops = {
1327         .owner = THIS_MODULE,
1328         .read = amdgpu_ttm_gtt_read,
1329         .llseek = default_llseek
1330 };
1331
1332 #endif
1333
1334 #endif
1335
1336 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
1337 {
1338 #if defined(CONFIG_DEBUG_FS)
1339         unsigned count;
1340
1341         struct drm_minor *minor = adev->ddev->primary;
1342         struct dentry *ent, *root = minor->debugfs_root;
1343
1344         ent = debugfs_create_file("amdgpu_vram", S_IFREG | S_IRUGO, root,
1345                                   adev, &amdgpu_ttm_vram_fops);
1346         if (IS_ERR(ent))
1347                 return PTR_ERR(ent);
1348         i_size_write(ent->d_inode, adev->mc.mc_vram_size);
1349         adev->mman.vram = ent;
1350
1351 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1352         ent = debugfs_create_file("amdgpu_gtt", S_IFREG | S_IRUGO, root,
1353                                   adev, &amdgpu_ttm_gtt_fops);
1354         if (IS_ERR(ent))
1355                 return PTR_ERR(ent);
1356         i_size_write(ent->d_inode, adev->mc.gtt_size);
1357         adev->mman.gtt = ent;
1358
1359 #endif
1360         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
1361
1362 #ifdef CONFIG_SWIOTLB
1363         if (!swiotlb_nr_tbl())
1364                 --count;
1365 #endif
1366
1367         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
1368 #else
1369
1370         return 0;
1371 #endif
1372 }
1373
1374 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
1375 {
1376 #if defined(CONFIG_DEBUG_FS)
1377
1378         debugfs_remove(adev->mman.vram);
1379         adev->mman.vram = NULL;
1380
1381 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1382         debugfs_remove(adev->mman.gtt);
1383         adev->mman.gtt = NULL;
1384 #endif
1385
1386 #endif
1387 }