drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <ttm/ttm_bo_api.h>
  33 #include <ttm/ttm_bo_driver.h>
  34 #include <ttm/ttm_placement.h>
  35 #include <ttm/ttm_module.h>
  36 #include <ttm/ttm_page_alloc.h>
  37 #include <ttm/ttm_memory.h>
  38 #include <drm/drmP.h>
  39 #include <drm/amdgpu_drm.h>
  40 #include <linux/seq_file.h>
  41 #include <linux/slab.h>
  42 #include <linux/swiotlb.h>
  43 #include <linux/swap.h>
  44 #include <linux/pagemap.h>
  45 #include <linux/debugfs.h>
  46 #include "amdgpu.h"
  47 #include "bif/bif_4_1_d.h"
  48
  49 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
  50
  51 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
  52 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
  53
  54 static struct amdgpu_device *amdgpu_get_adev(struct ttm_bo_device *bdev)
  55 {
  56         struct amdgpu_mman *mman;
  57         struct amdgpu_device *adev;
  58
  59         mman = container_of(bdev, struct amdgpu_mman, bdev);
  60         adev = container_of(mman, struct amdgpu_device, mman);
  61         return adev;
  62 }
  63
  64
  65 /*
  66  * Global memory.
  67  */
  68 static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref)
  69 {
  70         return ttm_mem_global_init(ref->object);
  71 }
  72
  73 static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
  74 {
  75         ttm_mem_global_release(ref->object);
  76 }
  77
  78 int amdgpu_ttm_global_init(struct amdgpu_device *adev)
  79 {
  80         struct drm_global_reference *global_ref;
  81         struct amdgpu_ring *ring;
  82         struct amd_sched_rq *rq;
  83         int r;
  84
  85         adev->mman.mem_global_referenced = false;
  86         global_ref = &adev->mman.mem_global_ref;
  87         global_ref->global_type = DRM_GLOBAL_TTM_MEM;
  88         global_ref->size = sizeof(struct ttm_mem_global);
  89         global_ref->init = &amdgpu_ttm_mem_global_init;
  90         global_ref->release = &amdgpu_ttm_mem_global_release;
  91         r = drm_global_item_ref(global_ref);
  92         if (r) {
  93                 DRM_ERROR("Failed setting up TTM memory accounting "
  94                           "subsystem.\n");
  95                 goto error_mem;
  96         }
  97
  98         adev->mman.bo_global_ref.mem_glob =
  99                 adev->mman.mem_global_ref.object;
 100         global_ref = &adev->mman.bo_global_ref.ref;
 101         global_ref->global_type = DRM_GLOBAL_TTM_BO;
 102         global_ref->size = sizeof(struct ttm_bo_global);
 103         global_ref->init = &ttm_bo_global_init;
 104         global_ref->release = &ttm_bo_global_release;
 105         r = drm_global_item_ref(global_ref);
 106         if (r) {
 107                 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
 108                 goto error_bo;
 109         }
 110
 111         ring = adev->mman.buffer_funcs_ring;
 112         rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
 113         r = amd_sched_entity_init(&ring->sched, &adev->mman.entity,
 114                                   rq, amdgpu_sched_jobs);
 115         if (r) {
 116                 DRM_ERROR("Failed setting up TTM BO move run queue.\n");
 117                 goto error_entity;
 118         }
 119
 120         adev->mman.mem_global_referenced = true;
 121
 122         return 0;
 123
 124 error_entity:
 125         drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 126 error_bo:
 127         drm_global_item_unref(&adev->mman.mem_global_ref);
 128 error_mem:
 129         return r;
 130 }
 131
 132 static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
 133 {
 134         if (adev->mman.mem_global_referenced) {
 135                 amd_sched_entity_fini(adev->mman.entity.sched,
 136                                       &adev->mman.entity);
 137                 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 138                 drm_global_item_unref(&adev->mman.mem_global_ref);
 139                 adev->mman.mem_global_referenced = false;
 140         }
 141 }
 142
 143 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
 144 {
 145         return 0;
 146 }
 147
 148 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 149                                 struct ttm_mem_type_manager *man)
 150 {
 151         struct amdgpu_device *adev;
 152
 153         adev = amdgpu_get_adev(bdev);
 154
 155         switch (type) {
 156         case TTM_PL_SYSTEM:
 157                 /* System memory */
 158                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 159                 man->available_caching = TTM_PL_MASK_CACHING;
 160                 man->default_caching = TTM_PL_FLAG_CACHED;
 161                 break;
 162         case TTM_PL_TT:
 163                 man->func = &ttm_bo_manager_func;
 164                 man->gpu_offset = adev->mc.gtt_start;
 165                 man->available_caching = TTM_PL_MASK_CACHING;
 166                 man->default_caching = TTM_PL_FLAG_CACHED;
 167                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
 168                 break;
 169         case TTM_PL_VRAM:
 170                 /* "On-card" video ram */
 171                 man->func = &ttm_bo_manager_func;
 172                 man->gpu_offset = adev->mc.vram_start;
 173                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 174                              TTM_MEMTYPE_FLAG_MAPPABLE;
 175                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 176                 man->default_caching = TTM_PL_FLAG_WC;
 177                 break;
 178         case AMDGPU_PL_GDS:
 179         case AMDGPU_PL_GWS:
 180         case AMDGPU_PL_OA:
 181                 /* On-chip GDS memory*/
 182                 man->func = &ttm_bo_manager_func;
 183                 man->gpu_offset = 0;
 184                 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
 185                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 186                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 187                 break;
 188         default:
 189                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 190                 return -EINVAL;
 191         }
 192         return 0;
 193 }
 194
 195 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 196                                 struct ttm_placement *placement)
 197 {
 198         struct amdgpu_bo *rbo;
 199         static struct ttm_place placements = {
 200                 .fpfn = 0,
 201                 .lpfn = 0,
 202                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 203         };
 204         unsigned i;
 205
 206         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) {
 207                 placement->placement = &placements;
 208                 placement->busy_placement = &placements;
 209                 placement->num_placement = 1;
 210                 placement->num_busy_placement = 1;
 211                 return;
 212         }
 213         rbo = container_of(bo, struct amdgpu_bo, tbo);
 214         switch (bo->mem.mem_type) {
 215         case TTM_PL_VRAM:
 216                 if (rbo->adev->mman.buffer_funcs_ring->ready == false) {
 217                         amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_CPU);
 218                 } else {
 219                         amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_GTT);
 220                         for (i = 0; i < rbo->placement.num_placement; ++i) {
 221                                 if (!(rbo->placements[i].flags &
 222                                       TTM_PL_FLAG_TT))
 223                                         continue;
 224
 225                                 if (rbo->placements[i].lpfn)
 226                                         continue;
 227
 228                                 /* set an upper limit to force directly
 229                                  * allocating address space for the BO.
 230                                  */
 231                                 rbo->placements[i].lpfn =
 232                                         rbo->adev->mc.gtt_size >> PAGE_SHIFT;
 233                         }
 234                 }
 235                 break;
 236         case TTM_PL_TT:
 237         default:
 238                 amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_CPU);
 239         }
 240         *placement = rbo->placement;
 241 }
 242
 243 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 244 {
 245         struct amdgpu_bo *rbo = container_of(bo, struct amdgpu_bo, tbo);
 246
 247         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 248                 return -EPERM;
 249         return drm_vma_node_verify_access(&rbo->gem_base.vma_node,
 250                                           filp->private_data);
 251 }
 252
 253 static void amdgpu_move_null(struct ttm_buffer_object *bo,
 254                              struct ttm_mem_reg *new_mem)
 255 {
 256         struct ttm_mem_reg *old_mem = &bo->mem;
 257
 258         BUG_ON(old_mem->mm_node != NULL);
 259         *old_mem = *new_mem;
 260         new_mem->mm_node = NULL;
 261 }
 262
 263 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 264                         bool evict, bool no_wait_gpu,
 265                         struct ttm_mem_reg *new_mem,
 266                         struct ttm_mem_reg *old_mem)
 267 {
 268         struct amdgpu_device *adev;
 269         struct amdgpu_ring *ring;
 270         uint64_t old_start, new_start;
 271         struct fence *fence;
 272         int r;
 273
 274         adev = amdgpu_get_adev(bo->bdev);
 275         ring = adev->mman.buffer_funcs_ring;
 276         old_start = old_mem->start << PAGE_SHIFT;
 277         new_start = new_mem->start << PAGE_SHIFT;
 278
 279         switch (old_mem->mem_type) {
 280         case TTM_PL_TT:
 281                 r = amdgpu_ttm_bind(bo->ttm, old_mem);
 282                 if (r)
 283                         return r;
 284
 285         case TTM_PL_VRAM:
 286                 old_start += bo->bdev->man[old_mem->mem_type].gpu_offset;
 287                 break;
 288         default:
 289                 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
 290                 return -EINVAL;
 291         }
 292         switch (new_mem->mem_type) {
 293         case TTM_PL_TT:
 294                 r = amdgpu_ttm_bind(bo->ttm, new_mem);
 295                 if (r)
 296                         return r;
 297
 298         case TTM_PL_VRAM:
 299                 new_start += bo->bdev->man[new_mem->mem_type].gpu_offset;
 300                 break;
 301         default:
 302                 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
 303                 return -EINVAL;
 304         }
 305         if (!ring->ready) {
 306                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 307                 return -EINVAL;
 308         }
 309
 310         BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0);
 311
 312         r = amdgpu_copy_buffer(ring, old_start, new_start,
 313                                new_mem->num_pages * PAGE_SIZE, /* bytes */
 314                                bo->resv, &fence, false);
 315         if (r)
 316                 return r;
 317
 318         r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
 319         fence_put(fence);
 320         return r;
 321 }
 322
 323 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo,
 324                                 bool evict, bool interruptible,
 325                                 bool no_wait_gpu,
 326                                 struct ttm_mem_reg *new_mem)
 327 {
 328         struct amdgpu_device *adev;
 329         struct ttm_mem_reg *old_mem = &bo->mem;
 330         struct ttm_mem_reg tmp_mem;
 331         struct ttm_place placements;
 332         struct ttm_placement placement;
 333         int r;
 334
 335         adev = amdgpu_get_adev(bo->bdev);
 336         tmp_mem = *new_mem;
 337         tmp_mem.mm_node = NULL;
 338         placement.num_placement = 1;
 339         placement.placement = &placements;
 340         placement.num_busy_placement = 1;
 341         placement.busy_placement = &placements;
 342         placements.fpfn = 0;
 343         placements.lpfn = adev->mc.gtt_size >> PAGE_SHIFT;
 344         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 345         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 346                              interruptible, no_wait_gpu);
 347         if (unlikely(r)) {
 348                 return r;
 349         }
 350
 351         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 352         if (unlikely(r)) {
 353                 goto out_cleanup;
 354         }
 355
 356         r = ttm_tt_bind(bo->ttm, &tmp_mem);
 357         if (unlikely(r)) {
 358                 goto out_cleanup;
 359         }
 360         r = amdgpu_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
 361         if (unlikely(r)) {
 362                 goto out_cleanup;
 363         }
 364         r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, new_mem);
 365 out_cleanup:
 366         ttm_bo_mem_put(bo, &tmp_mem);
 367         return r;
 368 }
 369
 370 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo,
 371                                 bool evict, bool interruptible,
 372                                 bool no_wait_gpu,
 373                                 struct ttm_mem_reg *new_mem)
 374 {
 375         struct amdgpu_device *adev;
 376         struct ttm_mem_reg *old_mem = &bo->mem;
 377         struct ttm_mem_reg tmp_mem;
 378         struct ttm_placement placement;
 379         struct ttm_place placements;
 380         int r;
 381
 382         adev = amdgpu_get_adev(bo->bdev);
 383         tmp_mem = *new_mem;
 384         tmp_mem.mm_node = NULL;
 385         placement.num_placement = 1;
 386         placement.placement = &placements;
 387         placement.num_busy_placement = 1;
 388         placement.busy_placement = &placements;
 389         placements.fpfn = 0;
 390         placements.lpfn = adev->mc.gtt_size >> PAGE_SHIFT;
 391         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 392         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 393                              interruptible, no_wait_gpu);
 394         if (unlikely(r)) {
 395                 return r;
 396         }
 397         r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, &tmp_mem);
 398         if (unlikely(r)) {
 399                 goto out_cleanup;
 400         }
 401         r = amdgpu_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
 402         if (unlikely(r)) {
 403                 goto out_cleanup;
 404         }
 405 out_cleanup:
 406         ttm_bo_mem_put(bo, &tmp_mem);
 407         return r;
 408 }
 409
 410 static int amdgpu_bo_move(struct ttm_buffer_object *bo,
 411                         bool evict, bool interruptible,
 412                         bool no_wait_gpu,
 413                         struct ttm_mem_reg *new_mem)
 414 {
 415         struct amdgpu_device *adev;
 416         struct amdgpu_bo *abo;
 417         struct ttm_mem_reg *old_mem = &bo->mem;
 418         int r;
 419
 420         /* Can't move a pinned BO */
 421         abo = container_of(bo, struct amdgpu_bo, tbo);
 422         if (WARN_ON_ONCE(abo->pin_count > 0))
 423                 return -EINVAL;
 424
 425         adev = amdgpu_get_adev(bo->bdev);
 426
 427         /* remember the eviction */
 428         if (evict)
 429                 atomic64_inc(&adev->num_evictions);
 430
 431         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 432                 amdgpu_move_null(bo, new_mem);
 433                 return 0;
 434         }
 435         if ((old_mem->mem_type == TTM_PL_TT &&
 436              new_mem->mem_type == TTM_PL_SYSTEM) ||
 437             (old_mem->mem_type == TTM_PL_SYSTEM &&
 438              new_mem->mem_type == TTM_PL_TT)) {
 439                 /* bind is enough */
 440                 amdgpu_move_null(bo, new_mem);
 441                 return 0;
 442         }
 443         if (adev->mman.buffer_funcs == NULL ||
 444             adev->mman.buffer_funcs_ring == NULL ||
 445             !adev->mman.buffer_funcs_ring->ready) {
 446                 /* use memcpy */
 447                 goto memcpy;
 448         }
 449
 450         if (old_mem->mem_type == TTM_PL_VRAM &&
 451             new_mem->mem_type == TTM_PL_SYSTEM) {
 452                 r = amdgpu_move_vram_ram(bo, evict, interruptible,
 453                                         no_wait_gpu, new_mem);
 454         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 455                    new_mem->mem_type == TTM_PL_VRAM) {
 456                 r = amdgpu_move_ram_vram(bo, evict, interruptible,
 457                                             no_wait_gpu, new_mem);
 458         } else {
 459                 r = amdgpu_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
 460         }
 461
 462         if (r) {
 463 memcpy:
 464                 r = ttm_bo_move_memcpy(bo, interruptible, no_wait_gpu, new_mem);
 465                 if (r) {
 466                         return r;
 467                 }
 468         }
 469
 470         /* update statistics */
 471         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 472         return 0;
 473 }
 474
 475 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 476 {
 477         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 478         struct amdgpu_device *adev = amdgpu_get_adev(bdev);
 479
 480         mem->bus.addr = NULL;
 481         mem->bus.offset = 0;
 482         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 483         mem->bus.base = 0;
 484         mem->bus.is_iomem = false;
 485         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 486                 return -EINVAL;
 487         switch (mem->mem_type) {
 488         case TTM_PL_SYSTEM:
 489                 /* system memory */
 490                 return 0;
 491         case TTM_PL_TT:
 492                 break;
 493         case TTM_PL_VRAM:
 494                 mem->bus.offset = mem->start << PAGE_SHIFT;
 495                 /* check if it's visible */
 496                 if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size)
 497                         return -EINVAL;
 498                 mem->bus.base = adev->mc.aper_base;
 499                 mem->bus.is_iomem = true;
 500 #ifdef __alpha__
 501                 /*
 502                  * Alpha: use bus.addr to hold the ioremap() return,
 503                  * so we can modify bus.base below.
 504                  */
 505                 if (mem->placement & TTM_PL_FLAG_WC)
 506                         mem->bus.addr =
 507                                 ioremap_wc(mem->bus.base + mem->bus.offset,
 508                                            mem->bus.size);
 509                 else
 510                         mem->bus.addr =
 511                                 ioremap_nocache(mem->bus.base + mem->bus.offset,
 512                                                 mem->bus.size);
 513
 514                 /*
 515                  * Alpha: Use just the bus offset plus
 516                  * the hose/domain memory base for bus.base.
 517                  * It then can be used to build PTEs for VRAM
 518                  * access, as done in ttm_bo_vm_fault().
 519                  */
 520                 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
 521                         adev->ddev->hose->dense_mem_base;
 522 #endif
 523                 break;
 524         default:
 525                 return -EINVAL;
 526         }
 527         return 0;
 528 }
 529
 530 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 531 {
 532 }
 533
 534 /*
 535  * TTM backend functions.
 536  */
 537 struct amdgpu_ttm_gup_task_list {
 538         struct list_head        list;
 539         struct task_struct      *task;
 540 };
 541
 542 struct amdgpu_ttm_tt {
 543         struct ttm_dma_tt       ttm;
 544         struct amdgpu_device    *adev;
 545         u64                     offset;
 546         uint64_t                userptr;
 547         struct mm_struct        *usermm;
 548         uint32_t                userflags;
 549         spinlock_t              guptasklock;
 550         struct list_head        guptasks;
 551         atomic_t                mmu_invalidations;
 552         struct list_head        list;
 553 };
 554
 555 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
 556 {
 557         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 558         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 559         unsigned pinned = 0;
 560         int r;
 561
 562         if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
 563                 /* check that we only use anonymous memory
 564                    to prevent problems with writeback */
 565                 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
 566                 struct vm_area_struct *vma;
 567
 568                 vma = find_vma(gtt->usermm, gtt->userptr);
 569                 if (!vma || vma->vm_file || vma->vm_end < end)
 570                         return -EPERM;
 571         }
 572
 573         do {
 574                 unsigned num_pages = ttm->num_pages - pinned;
 575                 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
 576                 struct page **p = pages + pinned;
 577                 struct amdgpu_ttm_gup_task_list guptask;
 578
 579                 guptask.task = current;
 580                 spin_lock(&gtt->guptasklock);
 581                 list_add(&guptask.list, &gtt->guptasks);
 582                 spin_unlock(&gtt->guptasklock);
 583
 584                 r = get_user_pages(userptr, num_pages, write, 0, p, NULL);
 585
 586                 spin_lock(&gtt->guptasklock);
 587                 list_del(&guptask.list);
 588                 spin_unlock(&gtt->guptasklock);
 589
 590                 if (r < 0)
 591                         goto release_pages;
 592
 593                 pinned += r;
 594
 595         } while (pinned < ttm->num_pages);
 596
 597         return 0;
 598
 599 release_pages:
 600         release_pages(pages, pinned, 0);
 601         return r;
 602 }
 603
 604 /* prepare the sg table with the user pages */
 605 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 606 {
 607         struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev);
 608         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 609         unsigned nents;
 610         int r;
 611
 612         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 613         enum dma_data_direction direction = write ?
 614                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 615
 616         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 617                                       ttm->num_pages << PAGE_SHIFT,
 618                                       GFP_KERNEL);
 619         if (r)
 620                 goto release_sg;
 621
 622         r = -ENOMEM;
 623         nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 624         if (nents != ttm->sg->nents)
 625                 goto release_sg;
 626
 627         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 628                                          gtt->ttm.dma_address, ttm->num_pages);
 629
 630         return 0;
 631
 632 release_sg:
 633         kfree(ttm->sg);
 634         return r;
 635 }
 636
 637 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 638 {
 639         struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev);
 640         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 641         struct sg_page_iter sg_iter;
 642
 643         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 644         enum dma_data_direction direction = write ?
 645                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 646
 647         /* double check that we don't free the table twice */
 648         if (!ttm->sg->sgl)
 649                 return;
 650
 651         /* free the sg table and pages again */
 652         dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 653
 654         for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) {
 655                 struct page *page = sg_page_iter_page(&sg_iter);
 656                 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
 657                         set_page_dirty(page);
 658
 659                 mark_page_accessed(page);
 660                 put_page(page);
 661         }
 662
 663         sg_free_table(ttm->sg);
 664 }
 665
 666 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
 667                                    struct ttm_mem_reg *bo_mem)
 668 {
 669         struct amdgpu_ttm_tt *gtt = (void*)ttm;
 670         int r;
 671
 672         if (gtt->userptr) {
 673                 r = amdgpu_ttm_tt_pin_userptr(ttm);
 674                 if (r) {
 675                         DRM_ERROR("failed to pin userptr\n");
 676                         return r;
 677                 }
 678         }
 679         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
 680         if (!ttm->num_pages) {
 681                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
 682                      ttm->num_pages, bo_mem, ttm);
 683         }
 684
 685         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
 686             bo_mem->mem_type == AMDGPU_PL_GWS ||
 687             bo_mem->mem_type == AMDGPU_PL_OA)
 688                 return -EINVAL;
 689
 690         return 0;
 691 }
 692
 693 bool amdgpu_ttm_is_bound(struct ttm_tt *ttm)
 694 {
 695         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 696
 697         return gtt && !list_empty(&gtt->list);
 698 }
 699
 700 int amdgpu_ttm_bind(struct ttm_tt *ttm, struct ttm_mem_reg *bo_mem)
 701 {
 702         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 703         uint32_t flags;
 704         int r;
 705
 706         if (!ttm || amdgpu_ttm_is_bound(ttm))
 707                 return 0;
 708
 709         flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem);
 710         r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages,
 711                 ttm->pages, gtt->ttm.dma_address, flags);
 712
 713         if (r) {
 714                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
 715                           ttm->num_pages, gtt->offset);
 716                 return r;
 717         }
 718         spin_lock(&gtt->adev->gtt_list_lock);
 719         list_add_tail(&gtt->list, &gtt->adev->gtt_list);
 720         spin_unlock(&gtt->adev->gtt_list_lock);
 721         return 0;
 722 }
 723
 724 int amdgpu_ttm_recover_gart(struct amdgpu_device *adev)
 725 {
 726         struct amdgpu_ttm_tt *gtt, *tmp;
 727         struct ttm_mem_reg bo_mem;
 728         uint32_t flags;
 729         int r;
 730
 731         bo_mem.mem_type = TTM_PL_TT;
 732         spin_lock(&adev->gtt_list_lock);
 733         list_for_each_entry_safe(gtt, tmp, &adev->gtt_list, list) {
 734                 flags = amdgpu_ttm_tt_pte_flags(gtt->adev, &gtt->ttm.ttm, &bo_mem);
 735                 r = amdgpu_gart_bind(adev, gtt->offset, gtt->ttm.ttm.num_pages,
 736                                      gtt->ttm.ttm.pages, gtt->ttm.dma_address,
 737                                      flags);
 738                 if (r) {
 739                         spin_unlock(&adev->gtt_list_lock);
 740                         DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
 741                                   gtt->ttm.ttm.num_pages, gtt->offset);
 742                         return r;
 743                 }
 744         }
 745         spin_unlock(&adev->gtt_list_lock);
 746         return 0;
 747 }
 748
 749 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
 750 {
 751         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 752
 753         if (!amdgpu_ttm_is_bound(ttm))
 754                 return 0;
 755
 756         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
 757         if (gtt->adev->gart.ready)
 758                 amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages);
 759
 760         if (gtt->userptr)
 761                 amdgpu_ttm_tt_unpin_userptr(ttm);
 762
 763         spin_lock(&gtt->adev->gtt_list_lock);
 764         list_del_init(&gtt->list);
 765         spin_unlock(&gtt->adev->gtt_list_lock);
 766
 767         return 0;
 768 }
 769
 770 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
 771 {
 772         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 773
 774         ttm_dma_tt_fini(&gtt->ttm);
 775         kfree(gtt);
 776 }
 777
 778 static struct ttm_backend_func amdgpu_backend_func = {
 779         .bind = &amdgpu_ttm_backend_bind,
 780         .unbind = &amdgpu_ttm_backend_unbind,
 781         .destroy = &amdgpu_ttm_backend_destroy,
 782 };
 783
 784 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev,
 785                                     unsigned long size, uint32_t page_flags,
 786                                     struct page *dummy_read_page)
 787 {
 788         struct amdgpu_device *adev;
 789         struct amdgpu_ttm_tt *gtt;
 790
 791         adev = amdgpu_get_adev(bdev);
 792
 793         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
 794         if (gtt == NULL) {
 795                 return NULL;
 796         }
 797         gtt->ttm.ttm.func = &amdgpu_backend_func;
 798         gtt->adev = adev;
 799         if (ttm_dma_tt_init(&gtt->ttm, bdev, size, page_flags, dummy_read_page)) {
 800                 kfree(gtt);
 801                 return NULL;
 802         }
 803         INIT_LIST_HEAD(&gtt->list);
 804         return &gtt->ttm.ttm;
 805 }
 806
 807 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm)
 808 {
 809         struct amdgpu_device *adev;
 810         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 811         unsigned i;
 812         int r;
 813         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 814
 815         if (ttm->state != tt_unpopulated)
 816                 return 0;
 817
 818         if (gtt && gtt->userptr) {
 819                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
 820                 if (!ttm->sg)
 821                         return -ENOMEM;
 822
 823                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
 824                 ttm->state = tt_unbound;
 825                 return 0;
 826         }
 827
 828         if (slave && ttm->sg) {
 829                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 830                                                  gtt->ttm.dma_address, ttm->num_pages);
 831                 ttm->state = tt_unbound;
 832                 return 0;
 833         }
 834
 835         adev = amdgpu_get_adev(ttm->bdev);
 836
 837 #ifdef CONFIG_SWIOTLB
 838         if (swiotlb_nr_tbl()) {
 839                 return ttm_dma_populate(&gtt->ttm, adev->dev);
 840         }
 841 #endif
 842
 843         r = ttm_pool_populate(ttm);
 844         if (r) {
 845                 return r;
 846         }
 847
 848         for (i = 0; i < ttm->num_pages; i++) {
 849                 gtt->ttm.dma_address[i] = pci_map_page(adev->pdev, ttm->pages[i],
 850                                                        0, PAGE_SIZE,
 851                                                        PCI_DMA_BIDIRECTIONAL);
 852                 if (pci_dma_mapping_error(adev->pdev, gtt->ttm.dma_address[i])) {
 853                         while (i--) {
 854                                 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
 855                                                PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 856                                 gtt->ttm.dma_address[i] = 0;
 857                         }
 858                         ttm_pool_unpopulate(ttm);
 859                         return -EFAULT;
 860                 }
 861         }
 862         return 0;
 863 }
 864
 865 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
 866 {
 867         struct amdgpu_device *adev;
 868         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 869         unsigned i;
 870         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 871
 872         if (gtt && gtt->userptr) {
 873                 kfree(ttm->sg);
 874                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
 875                 return;
 876         }
 877
 878         if (slave)
 879                 return;
 880
 881         adev = amdgpu_get_adev(ttm->bdev);
 882
 883 #ifdef CONFIG_SWIOTLB
 884         if (swiotlb_nr_tbl()) {
 885                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
 886                 return;
 887         }
 888 #endif
 889
 890         for (i = 0; i < ttm->num_pages; i++) {
 891                 if (gtt->ttm.dma_address[i]) {
 892                         pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
 893                                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 894                 }
 895         }
 896
 897         ttm_pool_unpopulate(ttm);
 898 }
 899
 900 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
 901                               uint32_t flags)
 902 {
 903         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 904
 905         if (gtt == NULL)
 906                 return -EINVAL;
 907
 908         gtt->userptr = addr;
 909         gtt->usermm = current->mm;
 910         gtt->userflags = flags;
 911         spin_lock_init(&gtt->guptasklock);
 912         INIT_LIST_HEAD(&gtt->guptasks);
 913         atomic_set(&gtt->mmu_invalidations, 0);
 914
 915         return 0;
 916 }
 917
 918 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
 919 {
 920         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 921
 922         if (gtt == NULL)
 923                 return NULL;
 924
 925         return gtt->usermm;
 926 }
 927
 928 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
 929                                   unsigned long end)
 930 {
 931         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 932         struct amdgpu_ttm_gup_task_list *entry;
 933         unsigned long size;
 934
 935         if (gtt == NULL || !gtt->userptr)
 936                 return false;
 937
 938         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
 939         if (gtt->userptr > end || gtt->userptr + size <= start)
 940                 return false;
 941
 942         spin_lock(&gtt->guptasklock);
 943         list_for_each_entry(entry, &gtt->guptasks, list) {
 944                 if (entry->task == current) {
 945                         spin_unlock(&gtt->guptasklock);
 946                         return false;
 947                 }
 948         }
 949         spin_unlock(&gtt->guptasklock);
 950
 951         atomic_inc(&gtt->mmu_invalidations);
 952
 953         return true;
 954 }
 955
 956 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
 957                                        int *last_invalidated)
 958 {
 959         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 960         int prev_invalidated = *last_invalidated;
 961
 962         *last_invalidated = atomic_read(&gtt->mmu_invalidations);
 963         return prev_invalidated != *last_invalidated;
 964 }
 965
 966 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
 967 {
 968         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 969
 970         if (gtt == NULL)
 971                 return false;
 972
 973         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 974 }
 975
 976 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
 977                                  struct ttm_mem_reg *mem)
 978 {
 979         uint32_t flags = 0;
 980
 981         if (mem && mem->mem_type != TTM_PL_SYSTEM)
 982                 flags |= AMDGPU_PTE_VALID;
 983
 984         if (mem && mem->mem_type == TTM_PL_TT) {
 985                 flags |= AMDGPU_PTE_SYSTEM;
 986
 987                 if (ttm->caching_state == tt_cached)
 988                         flags |= AMDGPU_PTE_SNOOPED;
 989         }
 990
 991         if (adev->asic_type >= CHIP_TONGA)
 992                 flags |= AMDGPU_PTE_EXECUTABLE;
 993
 994         flags |= AMDGPU_PTE_READABLE;
 995
 996         if (!amdgpu_ttm_tt_is_readonly(ttm))
 997                 flags |= AMDGPU_PTE_WRITEABLE;
 998
 999         return flags;
1000 }
1001
1002 static void amdgpu_ttm_lru_removal(struct ttm_buffer_object *tbo)
1003 {
1004         struct amdgpu_device *adev = amdgpu_get_adev(tbo->bdev);
1005         unsigned i, j;
1006
1007         for (i = 0; i < AMDGPU_TTM_LRU_SIZE; ++i) {
1008                 struct amdgpu_mman_lru *lru = &adev->mman.log2_size[i];
1009
1010                 for (j = 0; j < TTM_NUM_MEM_TYPES; ++j)
1011                         if (&tbo->lru == lru->lru[j])
1012                                 lru->lru[j] = tbo->lru.prev;
1013
1014                 if (&tbo->swap == lru->swap_lru)
1015                         lru->swap_lru = tbo->swap.prev;
1016         }
1017 }
1018
1019 static struct amdgpu_mman_lru *amdgpu_ttm_lru(struct ttm_buffer_object *tbo)
1020 {
1021         struct amdgpu_device *adev = amdgpu_get_adev(tbo->bdev);
1022         unsigned log2_size = min(ilog2(tbo->num_pages),
1023                                  AMDGPU_TTM_LRU_SIZE - 1);
1024
1025         return &adev->mman.log2_size[log2_size];
1026 }
1027
1028 static struct list_head *amdgpu_ttm_lru_tail(struct ttm_buffer_object *tbo)
1029 {
1030         struct amdgpu_mman_lru *lru = amdgpu_ttm_lru(tbo);
1031         struct list_head *res = lru->lru[tbo->mem.mem_type];
1032
1033         lru->lru[tbo->mem.mem_type] = &tbo->lru;
1034         while ((++lru)->lru[tbo->mem.mem_type] == res)
1035                 lru->lru[tbo->mem.mem_type] = &tbo->lru;
1036
1037         return res;
1038 }
1039
1040 static struct list_head *amdgpu_ttm_swap_lru_tail(struct ttm_buffer_object *tbo)
1041 {
1042         struct amdgpu_mman_lru *lru = amdgpu_ttm_lru(tbo);
1043         struct list_head *res = lru->swap_lru;
1044
1045         lru->swap_lru = &tbo->swap;
1046         while ((++lru)->swap_lru == res)
1047                 lru->swap_lru = &tbo->swap;
1048
1049         return res;
1050 }
1051
1052 static struct ttm_bo_driver amdgpu_bo_driver = {
1053         .ttm_tt_create = &amdgpu_ttm_tt_create,
1054         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1055         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1056         .invalidate_caches = &amdgpu_invalidate_caches,
1057         .init_mem_type = &amdgpu_init_mem_type,
1058         .evict_flags = &amdgpu_evict_flags,
1059         .move = &amdgpu_bo_move,
1060         .verify_access = &amdgpu_verify_access,
1061         .move_notify = &amdgpu_bo_move_notify,
1062         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1063         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1064         .io_mem_free = &amdgpu_ttm_io_mem_free,
1065         .lru_removal = &amdgpu_ttm_lru_removal,
1066         .lru_tail = &amdgpu_ttm_lru_tail,
1067         .swap_lru_tail = &amdgpu_ttm_swap_lru_tail,
1068 };
1069
1070 int amdgpu_ttm_init(struct amdgpu_device *adev)
1071 {
1072         unsigned i, j;
1073         int r;
1074
1075         /* No others user of address space so set it to 0 */
1076         r = ttm_bo_device_init(&adev->mman.bdev,
1077                                adev->mman.bo_global_ref.ref.object,
1078                                &amdgpu_bo_driver,
1079                                adev->ddev->anon_inode->i_mapping,
1080                                DRM_FILE_PAGE_OFFSET,
1081                                adev->need_dma32);
1082         if (r) {
1083                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1084                 return r;
1085         }
1086
1087         for (i = 0; i < AMDGPU_TTM_LRU_SIZE; ++i) {
1088                 struct amdgpu_mman_lru *lru = &adev->mman.log2_size[i];
1089
1090                 for (j = 0; j < TTM_NUM_MEM_TYPES; ++j)
1091                         lru->lru[j] = &adev->mman.bdev.man[j].lru;
1092                 lru->swap_lru = &adev->mman.bdev.glob->swap_lru;
1093         }
1094
1095         for (j = 0; j < TTM_NUM_MEM_TYPES; ++j)
1096                 adev->mman.guard.lru[j] = NULL;
1097         adev->mman.guard.swap_lru = NULL;
1098
1099         adev->mman.initialized = true;
1100         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1101                                 adev->mc.real_vram_size >> PAGE_SHIFT);
1102         if (r) {
1103                 DRM_ERROR("Failed initializing VRAM heap.\n");
1104                 return r;
1105         }
1106         /* Change the size here instead of the init above so only lpfn is affected */
1107         amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
1108
1109         r = amdgpu_bo_create(adev, 256 * 1024, PAGE_SIZE, true,
1110                              AMDGPU_GEM_DOMAIN_VRAM,
1111                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
1112                              NULL, NULL, &adev->stollen_vga_memory);
1113         if (r) {
1114                 return r;
1115         }
1116         r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
1117         if (r)
1118                 return r;
1119         r = amdgpu_bo_pin(adev->stollen_vga_memory, AMDGPU_GEM_DOMAIN_VRAM, NULL);
1120         amdgpu_bo_unreserve(adev->stollen_vga_memory);
1121         if (r) {
1122                 amdgpu_bo_unref(&adev->stollen_vga_memory);
1123                 return r;
1124         }
1125         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1126                  (unsigned) (adev->mc.real_vram_size / (1024 * 1024)));
1127         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT,
1128                                 adev->mc.gtt_size >> PAGE_SHIFT);
1129         if (r) {
1130                 DRM_ERROR("Failed initializing GTT heap.\n");
1131                 return r;
1132         }
1133         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1134                  (unsigned)(adev->mc.gtt_size / (1024 * 1024)));
1135
1136         adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT;
1137         adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT;
1138         adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT;
1139         adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT;
1140         adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT;
1141         adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT;
1142         adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT;
1143         adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT;
1144         adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT;
1145         /* GDS Memory */
1146         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1147                                 adev->gds.mem.total_size >> PAGE_SHIFT);
1148         if (r) {
1149                 DRM_ERROR("Failed initializing GDS heap.\n");
1150                 return r;
1151         }
1152
1153         /* GWS */
1154         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1155                                 adev->gds.gws.total_size >> PAGE_SHIFT);
1156         if (r) {
1157                 DRM_ERROR("Failed initializing gws heap.\n");
1158                 return r;
1159         }
1160
1161         /* OA */
1162         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1163                                 adev->gds.oa.total_size >> PAGE_SHIFT);
1164         if (r) {
1165                 DRM_ERROR("Failed initializing oa heap.\n");
1166                 return r;
1167         }
1168
1169         r = amdgpu_ttm_debugfs_init(adev);
1170         if (r) {
1171                 DRM_ERROR("Failed to init debugfs\n");
1172                 return r;
1173         }
1174         return 0;
1175 }
1176
1177 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1178 {
1179         int r;
1180
1181         if (!adev->mman.initialized)
1182                 return;
1183         amdgpu_ttm_debugfs_fini(adev);
1184         if (adev->stollen_vga_memory) {
1185                 r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
1186                 if (r == 0) {
1187                         amdgpu_bo_unpin(adev->stollen_vga_memory);
1188                         amdgpu_bo_unreserve(adev->stollen_vga_memory);
1189                 }
1190                 amdgpu_bo_unref(&adev->stollen_vga_memory);
1191         }
1192         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1193         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1194         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1195         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1196         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1197         ttm_bo_device_release(&adev->mman.bdev);
1198         amdgpu_gart_fini(adev);
1199         amdgpu_ttm_global_fini(adev);
1200         adev->mman.initialized = false;
1201         DRM_INFO("amdgpu: ttm finalized\n");
1202 }
1203
1204 /* this should only be called at bootup or when userspace
1205  * isn't running */
1206 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size)
1207 {
1208         struct ttm_mem_type_manager *man;
1209
1210         if (!adev->mman.initialized)
1211                 return;
1212
1213         man = &adev->mman.bdev.man[TTM_PL_VRAM];
1214         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1215         man->size = size >> PAGE_SHIFT;
1216 }
1217
1218 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1219 {
1220         struct drm_file *file_priv;
1221         struct amdgpu_device *adev;
1222
1223         if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
1224                 return -EINVAL;
1225
1226         file_priv = filp->private_data;
1227         adev = file_priv->minor->dev->dev_private;
1228         if (adev == NULL)
1229                 return -EINVAL;
1230
1231         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1232 }
1233
1234 int amdgpu_copy_buffer(struct amdgpu_ring *ring,
1235                        uint64_t src_offset,
1236                        uint64_t dst_offset,
1237                        uint32_t byte_count,
1238                        struct reservation_object *resv,
1239                        struct fence **fence, bool direct_submit)
1240 {
1241         struct amdgpu_device *adev = ring->adev;
1242         struct amdgpu_job *job;
1243
1244         uint32_t max_bytes;
1245         unsigned num_loops, num_dw;
1246         unsigned i;
1247         int r;
1248
1249         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1250         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1251         num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
1252
1253         /* for IB padding */
1254         while (num_dw & 0x7)
1255                 num_dw++;
1256
1257         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1258         if (r)
1259                 return r;
1260
1261         if (resv) {
1262                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1263                                      AMDGPU_FENCE_OWNER_UNDEFINED);
1264                 if (r) {
1265                         DRM_ERROR("sync failed (%d).\n", r);
1266                         goto error_free;
1267                 }
1268         }
1269
1270         for (i = 0; i < num_loops; i++) {
1271                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1272
1273                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1274                                         dst_offset, cur_size_in_bytes);
1275
1276                 src_offset += cur_size_in_bytes;
1277                 dst_offset += cur_size_in_bytes;
1278                 byte_count -= cur_size_in_bytes;
1279         }
1280
1281         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1282         WARN_ON(job->ibs[0].length_dw > num_dw);
1283         if (direct_submit) {
1284                 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs,
1285                                        NULL, NULL, fence);
1286                 job->fence = fence_get(*fence);
1287                 if (r)
1288                         DRM_ERROR("Error scheduling IBs (%d)\n", r);
1289                 amdgpu_job_free(job);
1290         } else {
1291                 r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1292                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1293                 if (r)
1294                         goto error_free;
1295         }
1296
1297         return r;
1298
1299 error_free:
1300         amdgpu_job_free(job);
1301         return r;
1302 }
1303
1304 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
1305                 uint32_t src_data,
1306                 struct reservation_object *resv,
1307                 struct fence **fence)
1308 {
1309         struct amdgpu_device *adev = bo->adev;
1310         struct amdgpu_job *job;
1311         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
1312
1313         uint32_t max_bytes, byte_count;
1314         uint64_t dst_offset;
1315         unsigned int num_loops, num_dw;
1316         unsigned int i;
1317         int r;
1318
1319         byte_count = bo->tbo.num_pages << PAGE_SHIFT;
1320         max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
1321         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1322         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
1323
1324         /* for IB padding */
1325         while (num_dw & 0x7)
1326                 num_dw++;
1327
1328         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1329         if (r)
1330                 return r;
1331
1332         if (resv) {
1333                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1334                                 AMDGPU_FENCE_OWNER_UNDEFINED);
1335                 if (r) {
1336                         DRM_ERROR("sync failed (%d).\n", r);
1337                         goto error_free;
1338                 }
1339         }
1340
1341         dst_offset = bo->tbo.mem.start << PAGE_SHIFT;
1342         for (i = 0; i < num_loops; i++) {
1343                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1344
1345                 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
1346                                 dst_offset, cur_size_in_bytes);
1347
1348                 dst_offset += cur_size_in_bytes;
1349                 byte_count -= cur_size_in_bytes;
1350         }
1351
1352         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1353         WARN_ON(job->ibs[0].length_dw > num_dw);
1354         r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1355                         AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1356         if (r)
1357                 goto error_free;
1358
1359         return 0;
1360
1361 error_free:
1362         amdgpu_job_free(job);
1363         return r;
1364 }
1365
1366 #if defined(CONFIG_DEBUG_FS)
1367
1368 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
1369 {
1370         struct drm_info_node *node = (struct drm_info_node *)m->private;
1371         unsigned ttm_pl = *(int *)node->info_ent->data;
1372         struct drm_device *dev = node->minor->dev;
1373         struct amdgpu_device *adev = dev->dev_private;
1374         struct drm_mm *mm = (struct drm_mm *)adev->mman.bdev.man[ttm_pl].priv;
1375         int ret;
1376         struct ttm_bo_global *glob = adev->mman.bdev.glob;
1377
1378         spin_lock(&glob->lru_lock);
1379         ret = drm_mm_dump_table(m, mm);
1380         spin_unlock(&glob->lru_lock);
1381         if (ttm_pl == TTM_PL_VRAM)
1382                 seq_printf(m, "man size:%llu pages, ram usage:%lluMB, vis usage:%lluMB\n",
1383                            adev->mman.bdev.man[ttm_pl].size,
1384                            (u64)atomic64_read(&adev->vram_usage) >> 20,
1385                            (u64)atomic64_read(&adev->vram_vis_usage) >> 20);
1386         return ret;
1387 }
1388
1389 static int ttm_pl_vram = TTM_PL_VRAM;
1390 static int ttm_pl_tt = TTM_PL_TT;
1391
1392 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
1393         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram},
1394         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt},
1395         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1396 #ifdef CONFIG_SWIOTLB
1397         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1398 #endif
1399 };
1400
1401 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
1402                                     size_t size, loff_t *pos)
1403 {
1404         struct amdgpu_device *adev = f->f_inode->i_private;
1405         ssize_t result = 0;
1406         int r;
1407
1408         if (size & 0x3 || *pos & 0x3)
1409                 return -EINVAL;
1410
1411         while (size) {
1412                 unsigned long flags;
1413                 uint32_t value;
1414
1415                 if (*pos >= adev->mc.mc_vram_size)
1416                         return result;
1417
1418                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1419                 WREG32(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
1420                 WREG32(mmMM_INDEX_HI, *pos >> 31);
1421                 value = RREG32(mmMM_DATA);
1422                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1423
1424                 r = put_user(value, (uint32_t *)buf);
1425                 if (r)
1426                         return r;
1427
1428                 result += 4;
1429                 buf += 4;
1430                 *pos += 4;
1431                 size -= 4;
1432         }
1433
1434         return result;
1435 }
1436
1437 static const struct file_operations amdgpu_ttm_vram_fops = {
1438         .owner = THIS_MODULE,
1439         .read = amdgpu_ttm_vram_read,
1440         .llseek = default_llseek
1441 };
1442
1443 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1444
1445 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
1446                                    size_t size, loff_t *pos)
1447 {
1448         struct amdgpu_device *adev = f->f_inode->i_private;
1449         ssize_t result = 0;
1450         int r;
1451
1452         while (size) {
1453                 loff_t p = *pos / PAGE_SIZE;
1454                 unsigned off = *pos & ~PAGE_MASK;
1455                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1456                 struct page *page;
1457                 void *ptr;
1458
1459                 if (p >= adev->gart.num_cpu_pages)
1460                         return result;
1461
1462                 page = adev->gart.pages[p];
1463                 if (page) {
1464                         ptr = kmap(page);
1465                         ptr += off;
1466
1467                         r = copy_to_user(buf, ptr, cur_size);
1468                         kunmap(adev->gart.pages[p]);
1469                 } else
1470                         r = clear_user(buf, cur_size);
1471
1472                 if (r)
1473                         return -EFAULT;
1474
1475                 result += cur_size;
1476                 buf += cur_size;
1477                 *pos += cur_size;
1478                 size -= cur_size;
1479         }
1480
1481         return result;
1482 }
1483
1484 static const struct file_operations amdgpu_ttm_gtt_fops = {
1485         .owner = THIS_MODULE,
1486         .read = amdgpu_ttm_gtt_read,
1487         .llseek = default_llseek
1488 };
1489
1490 #endif
1491
1492 #endif
1493
1494 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
1495 {
1496 #if defined(CONFIG_DEBUG_FS)
1497         unsigned count;
1498
1499         struct drm_minor *minor = adev->ddev->primary;
1500         struct dentry *ent, *root = minor->debugfs_root;
1501
1502         ent = debugfs_create_file("amdgpu_vram", S_IFREG | S_IRUGO, root,
1503                                   adev, &amdgpu_ttm_vram_fops);
1504         if (IS_ERR(ent))
1505                 return PTR_ERR(ent);
1506         i_size_write(ent->d_inode, adev->mc.mc_vram_size);
1507         adev->mman.vram = ent;
1508
1509 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1510         ent = debugfs_create_file("amdgpu_gtt", S_IFREG | S_IRUGO, root,
1511                                   adev, &amdgpu_ttm_gtt_fops);
1512         if (IS_ERR(ent))
1513                 return PTR_ERR(ent);
1514         i_size_write(ent->d_inode, adev->mc.gtt_size);
1515         adev->mman.gtt = ent;
1516
1517 #endif
1518         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
1519
1520 #ifdef CONFIG_SWIOTLB
1521         if (!swiotlb_nr_tbl())
1522                 --count;
1523 #endif
1524
1525         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
1526 #else
1527
1528         return 0;
1529 #endif
1530 }
1531
1532 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
1533 {
1534 #if defined(CONFIG_DEBUG_FS)
1535
1536         debugfs_remove(adev->mman.vram);
1537         adev->mman.vram = NULL;
1538
1539 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1540         debugfs_remove(adev->mman.gtt);
1541         adev->mman.gtt = NULL;
1542 #endif
1543
1544 #endif
1545 }
1546
1547 u64 amdgpu_ttm_get_gtt_mem_size(struct amdgpu_device *adev)
1548 {
1549         return ttm_get_kernel_zone_memory_size(adev->mman.mem_global_ref.object);
1550 }