2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/fence-array.h>
30 #include <drm/amdgpu_drm.h>
32 #include "amdgpu_trace.h"
36 * GPUVM is similar to the legacy gart on older asics, however
37 * rather than there being a single global gart table
38 * for the entire GPU, there are multiple VM page tables active
39 * at any given time. The VM page tables can contain a mix
40 * vram pages and system memory pages and system memory pages
41 * can be mapped as snooped (cached system pages) or unsnooped
42 * (uncached system pages).
43 * Each VM has an ID associated with it and there is a page table
44 * associated with each VMID. When execting a command buffer,
45 * the kernel tells the the ring what VMID to use for that command
46 * buffer. VMIDs are allocated dynamically as commands are submitted.
47 * The userspace drivers maintain their own address space and the kernel
48 * sets up their pages tables accordingly when they submit their
49 * command buffers and a VMID is assigned.
50 * Cayman/Trinity support up to 8 active VMs at any given time;
54 /* Special value that no flush is necessary */
55 #define AMDGPU_VM_NO_FLUSH (~0ll)
57 /* Local structure. Encapsulate some VM table update parameters to reduce
58 * the number of function parameters
60 struct amdgpu_vm_update_params {
61 /* address where to copy page table entries from */
63 /* DMA addresses to use for mapping */
64 dma_addr_t *pages_addr;
65 /* indirect buffer to fill with commands */
70 * amdgpu_vm_num_pde - return the number of page directory entries
72 * @adev: amdgpu_device pointer
74 * Calculate the number of page directory entries.
76 static unsigned amdgpu_vm_num_pdes(struct amdgpu_device *adev)
78 return adev->vm_manager.max_pfn >> amdgpu_vm_block_size;
82 * amdgpu_vm_directory_size - returns the size of the page directory in bytes
84 * @adev: amdgpu_device pointer
86 * Calculate the size of the page directory in bytes.
88 static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev)
90 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev) * 8);
94 * amdgpu_vm_get_pd_bo - add the VM PD to a validation list
96 * @vm: vm providing the BOs
97 * @validated: head of validation list
98 * @entry: entry to add
100 * Add the page directory to the list of BOs to
101 * validate for command submission.
103 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
104 struct list_head *validated,
105 struct amdgpu_bo_list_entry *entry)
107 entry->robj = vm->page_directory;
109 entry->tv.bo = &vm->page_directory->tbo;
110 entry->tv.shared = true;
111 entry->user_pages = NULL;
112 list_add(&entry->tv.head, validated);
116 * amdgpu_vm_get_bos - add the vm BOs to a duplicates list
118 * @vm: vm providing the BOs
119 * @duplicates: head of duplicates list
121 * Add the page directory to the BO duplicates list
122 * for command submission.
124 void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates)
128 /* add the vm page table to the list */
129 for (i = 0; i <= vm->max_pde_used; ++i) {
130 struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry;
135 list_add(&entry->tv.head, duplicates);
141 * amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail
143 * @adev: amdgpu device instance
144 * @vm: vm providing the BOs
146 * Move the PT BOs to the tail of the LRU.
148 void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
149 struct amdgpu_vm *vm)
151 struct ttm_bo_global *glob = adev->mman.bdev.glob;
154 spin_lock(&glob->lru_lock);
155 for (i = 0; i <= vm->max_pde_used; ++i) {
156 struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry;
161 ttm_bo_move_to_lru_tail(&entry->robj->tbo);
163 spin_unlock(&glob->lru_lock);
167 * amdgpu_vm_grab_id - allocate the next free VMID
169 * @vm: vm to allocate id for
170 * @ring: ring we want to submit job to
171 * @sync: sync object where we add dependencies
172 * @fence: fence protecting ID from reuse
174 * Allocate an id for the vm, adding fences to the sync obj as necessary.
176 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
177 struct amdgpu_sync *sync, struct fence *fence,
178 unsigned *vm_id, uint64_t *vm_pd_addr)
180 struct amdgpu_device *adev = ring->adev;
181 struct fence *updates = sync->last_vm_update;
182 struct amdgpu_vm_id *id, *idle;
183 struct fence **fences;
187 fences = kmalloc_array(sizeof(void *), adev->vm_manager.num_ids,
192 mutex_lock(&adev->vm_manager.lock);
194 /* Check if we have an idle VMID */
196 list_for_each_entry(idle, &adev->vm_manager.ids_lru, list) {
197 fences[i] = amdgpu_sync_peek_fence(&idle->active, ring);
203 /* If we can't find a idle VMID to use, wait till one becomes available */
204 if (&idle->list == &adev->vm_manager.ids_lru) {
205 u64 fence_context = adev->vm_manager.fence_context + ring->idx;
206 unsigned seqno = ++adev->vm_manager.seqno[ring->idx];
207 struct fence_array *array;
210 for (j = 0; j < i; ++j)
211 fence_get(fences[j]);
213 array = fence_array_create(i, fences, fence_context,
216 for (j = 0; j < i; ++j)
217 fence_put(fences[j]);
224 r = amdgpu_sync_fence(ring->adev, sync, &array->base);
225 fence_put(&array->base);
229 mutex_unlock(&adev->vm_manager.lock);
235 /* Check if we can use a VMID already assigned to this VM */
238 struct fence *flushed;
239 bool same_ring = ring->idx == i;
242 if (i == AMDGPU_MAX_RINGS)
245 /* Check all the prerequisites to using this VMID */
249 if (atomic64_read(&id->owner) != vm->client_id)
252 if (*vm_pd_addr != id->pd_gpu_addr)
256 (!id->last_flush || !fence_is_signaled(id->last_flush)))
259 flushed = id->flushed_updates;
261 (!flushed || fence_is_later(updates, flushed)))
264 /* Good we can use this VMID. Remember this submission as
267 r = amdgpu_sync_fence(ring->adev, &id->active, fence);
271 list_move_tail(&id->list, &adev->vm_manager.ids_lru);
272 vm->ids[ring->idx] = id;
274 *vm_id = id - adev->vm_manager.ids;
275 *vm_pd_addr = AMDGPU_VM_NO_FLUSH;
276 trace_amdgpu_vm_grab_id(vm, ring->idx, *vm_id, *vm_pd_addr);
278 mutex_unlock(&adev->vm_manager.lock);
281 } while (i != ring->idx);
283 /* Still no ID to use? Then use the idle one found earlier */
286 /* Remember this submission as user of the VMID */
287 r = amdgpu_sync_fence(ring->adev, &id->active, fence);
291 fence_put(id->first);
292 id->first = fence_get(fence);
294 fence_put(id->last_flush);
295 id->last_flush = NULL;
297 fence_put(id->flushed_updates);
298 id->flushed_updates = fence_get(updates);
300 id->pd_gpu_addr = *vm_pd_addr;
302 list_move_tail(&id->list, &adev->vm_manager.ids_lru);
303 atomic64_set(&id->owner, vm->client_id);
304 vm->ids[ring->idx] = id;
306 *vm_id = id - adev->vm_manager.ids;
307 trace_amdgpu_vm_grab_id(vm, ring->idx, *vm_id, *vm_pd_addr);
310 mutex_unlock(&adev->vm_manager.lock);
314 static bool amdgpu_vm_ring_has_compute_vm_bug(struct amdgpu_ring *ring)
316 struct amdgpu_device *adev = ring->adev;
317 const struct amdgpu_ip_block_version *ip_block;
319 if (ring->type != AMDGPU_RING_TYPE_COMPUTE)
320 /* only compute rings */
323 ip_block = amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
327 if (ip_block->major <= 7) {
328 /* gfx7 has no workaround */
330 } else if (ip_block->major == 8) {
331 if (adev->gfx.mec_fw_version >= 673)
332 /* gfx8 is fixed in MEC firmware 673 */
341 * amdgpu_vm_flush - hardware flush the vm
343 * @ring: ring to use for flush
344 * @vm_id: vmid number to use
345 * @pd_addr: address of the page directory
347 * Emit a VM flush when it is necessary.
349 int amdgpu_vm_flush(struct amdgpu_ring *ring,
350 unsigned vm_id, uint64_t pd_addr,
351 uint32_t gds_base, uint32_t gds_size,
352 uint32_t gws_base, uint32_t gws_size,
353 uint32_t oa_base, uint32_t oa_size)
355 struct amdgpu_device *adev = ring->adev;
356 struct amdgpu_vm_id *id = &adev->vm_manager.ids[vm_id];
357 bool gds_switch_needed = ring->funcs->emit_gds_switch && (
358 id->gds_base != gds_base ||
359 id->gds_size != gds_size ||
360 id->gws_base != gws_base ||
361 id->gws_size != gws_size ||
362 id->oa_base != oa_base ||
363 id->oa_size != oa_size);
366 if (ring->funcs->emit_pipeline_sync && (
367 pd_addr != AMDGPU_VM_NO_FLUSH || gds_switch_needed ||
368 amdgpu_vm_ring_has_compute_vm_bug(ring)))
369 amdgpu_ring_emit_pipeline_sync(ring);
371 if (ring->funcs->emit_vm_flush &&
372 pd_addr != AMDGPU_VM_NO_FLUSH) {
375 trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id);
376 amdgpu_ring_emit_vm_flush(ring, vm_id, pd_addr);
378 r = amdgpu_fence_emit(ring, &fence);
382 mutex_lock(&adev->vm_manager.lock);
383 fence_put(id->last_flush);
384 id->last_flush = fence;
385 mutex_unlock(&adev->vm_manager.lock);
388 if (gds_switch_needed) {
389 id->gds_base = gds_base;
390 id->gds_size = gds_size;
391 id->gws_base = gws_base;
392 id->gws_size = gws_size;
393 id->oa_base = oa_base;
394 id->oa_size = oa_size;
395 amdgpu_ring_emit_gds_switch(ring, vm_id,
405 * amdgpu_vm_reset_id - reset VMID to zero
407 * @adev: amdgpu device structure
408 * @vm_id: vmid number to use
410 * Reset saved GDW, GWS and OA to force switch on next flush.
412 void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id)
414 struct amdgpu_vm_id *id = &adev->vm_manager.ids[vm_id];
425 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
428 * @bo: requested buffer object
430 * Find @bo inside the requested vm.
431 * Search inside the @bos vm list for the requested vm
432 * Returns the found bo_va or NULL if none is found
434 * Object has to be reserved!
436 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
437 struct amdgpu_bo *bo)
439 struct amdgpu_bo_va *bo_va;
441 list_for_each_entry(bo_va, &bo->va, bo_list) {
442 if (bo_va->vm == vm) {
450 * amdgpu_vm_update_pages - helper to call the right asic function
452 * @adev: amdgpu_device pointer
453 * @vm_update_params: see amdgpu_vm_update_params definition
454 * @pe: addr of the page entry
455 * @addr: dst addr to write into pe
456 * @count: number of page entries to update
457 * @incr: increase next addr by incr bytes
458 * @flags: hw access flags
460 * Traces the parameters and calls the right asic functions
461 * to setup the page table using the DMA.
463 static void amdgpu_vm_update_pages(struct amdgpu_device *adev,
464 struct amdgpu_vm_update_params
466 uint64_t pe, uint64_t addr,
467 unsigned count, uint32_t incr,
470 trace_amdgpu_vm_set_page(pe, addr, count, incr, flags);
472 if (vm_update_params->src) {
473 amdgpu_vm_copy_pte(adev, vm_update_params->ib,
474 pe, (vm_update_params->src + (addr >> 12) * 8), count);
476 } else if (vm_update_params->pages_addr) {
477 amdgpu_vm_write_pte(adev, vm_update_params->ib,
478 vm_update_params->pages_addr,
479 pe, addr, count, incr, flags);
481 } else if (count < 3) {
482 amdgpu_vm_write_pte(adev, vm_update_params->ib, NULL, pe, addr,
486 amdgpu_vm_set_pte_pde(adev, vm_update_params->ib, pe, addr,
492 * amdgpu_vm_clear_bo - initially clear the page dir/table
494 * @adev: amdgpu_device pointer
497 * need to reserve bo first before calling it.
499 static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
500 struct amdgpu_vm *vm,
501 struct amdgpu_bo *bo)
503 struct amdgpu_ring *ring;
504 struct fence *fence = NULL;
505 struct amdgpu_job *job;
506 struct amdgpu_vm_update_params vm_update_params;
511 memset(&vm_update_params, 0, sizeof(vm_update_params));
512 ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
514 r = reservation_object_reserve_shared(bo->tbo.resv);
518 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
522 addr = amdgpu_bo_gpu_offset(bo);
523 entries = amdgpu_bo_size(bo) / 8;
525 r = amdgpu_job_alloc_with_ib(adev, 64, &job);
529 vm_update_params.ib = &job->ibs[0];
530 amdgpu_vm_update_pages(adev, &vm_update_params, addr, 0, entries,
532 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
534 WARN_ON(job->ibs[0].length_dw > 64);
535 r = amdgpu_job_submit(job, ring, &vm->entity,
536 AMDGPU_FENCE_OWNER_VM, &fence);
540 amdgpu_bo_fence(bo, fence, true);
545 amdgpu_job_free(job);
552 * amdgpu_vm_map_gart - Resolve gart mapping of addr
554 * @pages_addr: optional DMA address to use for lookup
555 * @addr: the unmapped addr
557 * Look up the physical address of the page that the pte resolves
558 * to and return the pointer for the page table entry.
560 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
565 /* page table offset */
566 result = pages_addr[addr >> PAGE_SHIFT];
568 /* in case cpu page size != gpu page size*/
569 result |= addr & (~PAGE_MASK);
572 /* No mapping required */
576 result &= 0xFFFFFFFFFFFFF000ULL;
582 * amdgpu_vm_update_pdes - make sure that page directory is valid
584 * @adev: amdgpu_device pointer
586 * @start: start of GPU address range
587 * @end: end of GPU address range
589 * Allocates new page tables if necessary
590 * and updates the page directory.
591 * Returns 0 for success, error for failure.
593 int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
594 struct amdgpu_vm *vm)
596 struct amdgpu_ring *ring;
597 struct amdgpu_bo *pd = vm->page_directory;
598 uint64_t pd_addr = amdgpu_bo_gpu_offset(pd);
599 uint32_t incr = AMDGPU_VM_PTE_COUNT * 8;
600 uint64_t last_pde = ~0, last_pt = ~0;
601 unsigned count = 0, pt_idx, ndw;
602 struct amdgpu_job *job;
603 struct amdgpu_vm_update_params vm_update_params;
604 struct fence *fence = NULL;
608 memset(&vm_update_params, 0, sizeof(vm_update_params));
609 ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
614 /* assume the worst case */
615 ndw += vm->max_pde_used * 6;
617 r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
621 vm_update_params.ib = &job->ibs[0];
623 /* walk over the address space and update the page directory */
624 for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) {
625 struct amdgpu_bo *bo = vm->page_tables[pt_idx].entry.robj;
631 pt = amdgpu_bo_gpu_offset(bo);
632 if (vm->page_tables[pt_idx].addr == pt)
634 vm->page_tables[pt_idx].addr = pt;
636 pde = pd_addr + pt_idx * 8;
637 if (((last_pde + 8 * count) != pde) ||
638 ((last_pt + incr * count) != pt)) {
641 amdgpu_vm_update_pages(adev, &vm_update_params,
656 amdgpu_vm_update_pages(adev, &vm_update_params,
658 count, incr, AMDGPU_PTE_VALID);
660 if (vm_update_params.ib->length_dw != 0) {
661 amdgpu_ring_pad_ib(ring, vm_update_params.ib);
662 amdgpu_sync_resv(adev, &job->sync, pd->tbo.resv,
663 AMDGPU_FENCE_OWNER_VM);
664 WARN_ON(vm_update_params.ib->length_dw > ndw);
665 r = amdgpu_job_submit(job, ring, &vm->entity,
666 AMDGPU_FENCE_OWNER_VM, &fence);
670 amdgpu_bo_fence(pd, fence, true);
671 fence_put(vm->page_directory_fence);
672 vm->page_directory_fence = fence_get(fence);
676 amdgpu_job_free(job);
682 amdgpu_job_free(job);
687 * amdgpu_vm_frag_ptes - add fragment information to PTEs
689 * @adev: amdgpu_device pointer
690 * @vm_update_params: see amdgpu_vm_update_params definition
691 * @pe_start: first PTE to handle
692 * @pe_end: last PTE to handle
693 * @addr: addr those PTEs should point to
694 * @flags: hw mapping flags
696 static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev,
697 struct amdgpu_vm_update_params
699 uint64_t pe_start, uint64_t pe_end,
700 uint64_t addr, uint32_t flags)
703 * The MC L1 TLB supports variable sized pages, based on a fragment
704 * field in the PTE. When this field is set to a non-zero value, page
705 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
706 * flags are considered valid for all PTEs within the fragment range
707 * and corresponding mappings are assumed to be physically contiguous.
709 * The L1 TLB can store a single PTE for the whole fragment,
710 * significantly increasing the space available for translation
711 * caching. This leads to large improvements in throughput when the
712 * TLB is under pressure.
714 * The L2 TLB distributes small and large fragments into two
715 * asymmetric partitions. The large fragment cache is significantly
716 * larger. Thus, we try to use large fragments wherever possible.
717 * Userspace can support this by aligning virtual base address and
718 * allocation size to the fragment size.
721 /* SI and newer are optimized for 64KB */
722 uint64_t frag_flags = AMDGPU_PTE_FRAG_64KB;
723 uint64_t frag_align = 0x80;
725 uint64_t frag_start = ALIGN(pe_start, frag_align);
726 uint64_t frag_end = pe_end & ~(frag_align - 1);
730 /* Abort early if there isn't anything to do */
731 if (pe_start == pe_end)
734 /* system pages are non continuously */
735 if (vm_update_params->src || vm_update_params->pages_addr ||
736 !(flags & AMDGPU_PTE_VALID) || (frag_start >= frag_end)) {
738 count = (pe_end - pe_start) / 8;
739 amdgpu_vm_update_pages(adev, vm_update_params, pe_start,
740 addr, count, AMDGPU_GPU_PAGE_SIZE,
745 /* handle the 4K area at the beginning */
746 if (pe_start != frag_start) {
747 count = (frag_start - pe_start) / 8;
748 amdgpu_vm_update_pages(adev, vm_update_params, pe_start, addr,
749 count, AMDGPU_GPU_PAGE_SIZE, flags);
750 addr += AMDGPU_GPU_PAGE_SIZE * count;
753 /* handle the area in the middle */
754 count = (frag_end - frag_start) / 8;
755 amdgpu_vm_update_pages(adev, vm_update_params, frag_start, addr, count,
756 AMDGPU_GPU_PAGE_SIZE, flags | frag_flags);
758 /* handle the 4K area at the end */
759 if (frag_end != pe_end) {
760 addr += AMDGPU_GPU_PAGE_SIZE * count;
761 count = (pe_end - frag_end) / 8;
762 amdgpu_vm_update_pages(adev, vm_update_params, frag_end, addr,
763 count, AMDGPU_GPU_PAGE_SIZE, flags);
768 * amdgpu_vm_update_ptes - make sure that page tables are valid
770 * @adev: amdgpu_device pointer
771 * @vm_update_params: see amdgpu_vm_update_params definition
773 * @start: start of GPU address range
774 * @end: end of GPU address range
775 * @dst: destination address to map to, the next dst inside the function
776 * @flags: mapping flags
778 * Update the page tables in the range @start - @end.
780 static void amdgpu_vm_update_ptes(struct amdgpu_device *adev,
781 struct amdgpu_vm_update_params
783 struct amdgpu_vm *vm,
784 uint64_t start, uint64_t end,
785 uint64_t dst, uint32_t flags)
787 const uint64_t mask = AMDGPU_VM_PTE_COUNT - 1;
789 uint64_t cur_pe_start, cur_pe_end, cur_dst;
790 uint64_t addr; /* next GPU address to be updated */
792 struct amdgpu_bo *pt;
793 unsigned nptes; /* next number of ptes to be updated */
794 uint64_t next_pe_start;
796 /* initialize the variables */
798 pt_idx = addr >> amdgpu_vm_block_size;
799 pt = vm->page_tables[pt_idx].entry.robj;
801 if ((addr & ~mask) == (end & ~mask))
804 nptes = AMDGPU_VM_PTE_COUNT - (addr & mask);
806 cur_pe_start = amdgpu_bo_gpu_offset(pt);
807 cur_pe_start += (addr & mask) * 8;
808 cur_pe_end = cur_pe_start + 8 * nptes;
813 dst += nptes * AMDGPU_GPU_PAGE_SIZE;
815 /* walk over the address space and update the page tables */
817 pt_idx = addr >> amdgpu_vm_block_size;
818 pt = vm->page_tables[pt_idx].entry.robj;
820 if ((addr & ~mask) == (end & ~mask))
823 nptes = AMDGPU_VM_PTE_COUNT - (addr & mask);
825 next_pe_start = amdgpu_bo_gpu_offset(pt);
826 next_pe_start += (addr & mask) * 8;
828 if (cur_pe_end == next_pe_start) {
829 /* The next ptb is consecutive to current ptb.
830 * Don't call amdgpu_vm_frag_ptes now.
831 * Will update two ptbs together in future.
833 cur_pe_end += 8 * nptes;
835 amdgpu_vm_frag_ptes(adev, vm_update_params,
836 cur_pe_start, cur_pe_end,
839 cur_pe_start = next_pe_start;
840 cur_pe_end = next_pe_start + 8 * nptes;
846 dst += nptes * AMDGPU_GPU_PAGE_SIZE;
849 amdgpu_vm_frag_ptes(adev, vm_update_params, cur_pe_start,
850 cur_pe_end, cur_dst, flags);
854 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
856 * @adev: amdgpu_device pointer
857 * @exclusive: fence we need to sync to
858 * @src: address where to copy page table entries from
859 * @pages_addr: DMA addresses to use for mapping
861 * @start: start of mapped range
862 * @last: last mapped entry
863 * @flags: flags for the entries
864 * @addr: addr to set the area to
865 * @fence: optional resulting fence
867 * Fill in the page table entries between @start and @last.
868 * Returns 0 for success, -EINVAL for failure.
870 static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
871 struct fence *exclusive,
873 dma_addr_t *pages_addr,
874 struct amdgpu_vm *vm,
875 uint64_t start, uint64_t last,
876 uint32_t flags, uint64_t addr,
877 struct fence **fence)
879 struct amdgpu_ring *ring;
880 void *owner = AMDGPU_FENCE_OWNER_VM;
881 unsigned nptes, ncmds, ndw;
882 struct amdgpu_job *job;
883 struct amdgpu_vm_update_params vm_update_params;
884 struct fence *f = NULL;
887 ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
888 memset(&vm_update_params, 0, sizeof(vm_update_params));
889 vm_update_params.src = src;
890 vm_update_params.pages_addr = pages_addr;
892 /* sync to everything on unmapping */
893 if (!(flags & AMDGPU_PTE_VALID))
894 owner = AMDGPU_FENCE_OWNER_UNDEFINED;
896 nptes = last - start + 1;
899 * reserve space for one command every (1 << BLOCK_SIZE)
900 * entries or 2k dwords (whatever is smaller)
902 ncmds = (nptes >> min(amdgpu_vm_block_size, 11)) + 1;
907 if (vm_update_params.src) {
908 /* only copy commands needed */
911 } else if (vm_update_params.pages_addr) {
912 /* header for write data commands */
915 /* body of write data command */
919 /* set page commands needed */
922 /* two extra commands for begin/end of fragment */
926 r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
930 vm_update_params.ib = &job->ibs[0];
932 r = amdgpu_sync_fence(adev, &job->sync, exclusive);
936 r = amdgpu_sync_resv(adev, &job->sync, vm->page_directory->tbo.resv,
941 r = reservation_object_reserve_shared(vm->page_directory->tbo.resv);
945 amdgpu_vm_update_ptes(adev, &vm_update_params, vm, start,
946 last + 1, addr, flags);
948 amdgpu_ring_pad_ib(ring, vm_update_params.ib);
949 WARN_ON(vm_update_params.ib->length_dw > ndw);
950 r = amdgpu_job_submit(job, ring, &vm->entity,
951 AMDGPU_FENCE_OWNER_VM, &f);
955 amdgpu_bo_fence(vm->page_directory, f, true);
958 *fence = fence_get(f);
964 amdgpu_job_free(job);
969 * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks
971 * @adev: amdgpu_device pointer
972 * @exclusive: fence we need to sync to
973 * @gtt_flags: flags as they are used for GTT
974 * @pages_addr: DMA addresses to use for mapping
976 * @mapping: mapped range and flags to use for the update
977 * @addr: addr to set the area to
978 * @flags: HW flags for the mapping
979 * @fence: optional resulting fence
981 * Split the mapping into smaller chunks so that each update fits
983 * Returns 0 for success, -EINVAL for failure.
985 static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
986 struct fence *exclusive,
988 dma_addr_t *pages_addr,
989 struct amdgpu_vm *vm,
990 struct amdgpu_bo_va_mapping *mapping,
991 uint32_t flags, uint64_t addr,
992 struct fence **fence)
994 const uint64_t max_size = 64ULL * 1024ULL * 1024ULL / AMDGPU_GPU_PAGE_SIZE;
996 uint64_t src = 0, start = mapping->it.start;
999 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1000 * but in case of something, we filter the flags in first place
1002 if (!(mapping->flags & AMDGPU_PTE_READABLE))
1003 flags &= ~AMDGPU_PTE_READABLE;
1004 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
1005 flags &= ~AMDGPU_PTE_WRITEABLE;
1007 trace_amdgpu_vm_bo_update(mapping);
1010 if (flags == gtt_flags)
1011 src = adev->gart.table_addr + (addr >> 12) * 8;
1014 addr += mapping->offset;
1016 if (!pages_addr || src)
1017 return amdgpu_vm_bo_update_mapping(adev, exclusive,
1018 src, pages_addr, vm,
1019 start, mapping->it.last,
1020 flags, addr, fence);
1022 while (start != mapping->it.last + 1) {
1025 last = min((uint64_t)mapping->it.last, start + max_size - 1);
1026 r = amdgpu_vm_bo_update_mapping(adev, exclusive,
1027 src, pages_addr, vm,
1028 start, last, flags, addr,
1034 addr += max_size * AMDGPU_GPU_PAGE_SIZE;
1041 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1043 * @adev: amdgpu_device pointer
1044 * @bo_va: requested BO and VM object
1047 * Fill in the page table entries for @bo_va.
1048 * Returns 0 for success, -EINVAL for failure.
1050 * Object have to be reserved and mutex must be locked!
1052 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
1053 struct amdgpu_bo_va *bo_va,
1054 struct ttm_mem_reg *mem)
1056 struct amdgpu_vm *vm = bo_va->vm;
1057 struct amdgpu_bo_va_mapping *mapping;
1058 dma_addr_t *pages_addr = NULL;
1059 uint32_t gtt_flags, flags;
1060 struct fence *exclusive;
1065 struct ttm_dma_tt *ttm;
1067 addr = (u64)mem->start << PAGE_SHIFT;
1068 switch (mem->mem_type) {
1070 ttm = container_of(bo_va->bo->tbo.ttm, struct
1072 pages_addr = ttm->dma_address;
1076 addr += adev->vm_manager.vram_base_offset;
1083 exclusive = reservation_object_get_excl(bo_va->bo->tbo.resv);
1089 flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem);
1090 gtt_flags = (adev == bo_va->bo->adev) ? flags : 0;
1092 spin_lock(&vm->status_lock);
1093 if (!list_empty(&bo_va->vm_status))
1094 list_splice_init(&bo_va->valids, &bo_va->invalids);
1095 spin_unlock(&vm->status_lock);
1097 list_for_each_entry(mapping, &bo_va->invalids, list) {
1098 r = amdgpu_vm_bo_split_mapping(adev, exclusive,
1099 gtt_flags, pages_addr, vm,
1100 mapping, flags, addr,
1101 &bo_va->last_pt_update);
1106 if (trace_amdgpu_vm_bo_mapping_enabled()) {
1107 list_for_each_entry(mapping, &bo_va->valids, list)
1108 trace_amdgpu_vm_bo_mapping(mapping);
1110 list_for_each_entry(mapping, &bo_va->invalids, list)
1111 trace_amdgpu_vm_bo_mapping(mapping);
1114 spin_lock(&vm->status_lock);
1115 list_splice_init(&bo_va->invalids, &bo_va->valids);
1116 list_del_init(&bo_va->vm_status);
1118 list_add(&bo_va->vm_status, &vm->cleared);
1119 spin_unlock(&vm->status_lock);
1125 * amdgpu_vm_clear_freed - clear freed BOs in the PT
1127 * @adev: amdgpu_device pointer
1130 * Make sure all freed BOs are cleared in the PT.
1131 * Returns 0 for success.
1133 * PTs have to be reserved and mutex must be locked!
1135 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
1136 struct amdgpu_vm *vm)
1138 struct amdgpu_bo_va_mapping *mapping;
1141 while (!list_empty(&vm->freed)) {
1142 mapping = list_first_entry(&vm->freed,
1143 struct amdgpu_bo_va_mapping, list);
1144 list_del(&mapping->list);
1146 r = amdgpu_vm_bo_split_mapping(adev, NULL, 0, NULL, vm, mapping,
1158 * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT
1160 * @adev: amdgpu_device pointer
1163 * Make sure all invalidated BOs are cleared in the PT.
1164 * Returns 0 for success.
1166 * PTs have to be reserved and mutex must be locked!
1168 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev,
1169 struct amdgpu_vm *vm, struct amdgpu_sync *sync)
1171 struct amdgpu_bo_va *bo_va = NULL;
1174 spin_lock(&vm->status_lock);
1175 while (!list_empty(&vm->invalidated)) {
1176 bo_va = list_first_entry(&vm->invalidated,
1177 struct amdgpu_bo_va, vm_status);
1178 spin_unlock(&vm->status_lock);
1180 r = amdgpu_vm_bo_update(adev, bo_va, NULL);
1184 spin_lock(&vm->status_lock);
1186 spin_unlock(&vm->status_lock);
1189 r = amdgpu_sync_fence(adev, sync, bo_va->last_pt_update);
1195 * amdgpu_vm_bo_add - add a bo to a specific vm
1197 * @adev: amdgpu_device pointer
1199 * @bo: amdgpu buffer object
1201 * Add @bo into the requested vm.
1202 * Add @bo to the list of bos associated with the vm
1203 * Returns newly added bo_va or NULL for failure
1205 * Object has to be reserved!
1207 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
1208 struct amdgpu_vm *vm,
1209 struct amdgpu_bo *bo)
1211 struct amdgpu_bo_va *bo_va;
1213 bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
1214 if (bo_va == NULL) {
1219 bo_va->ref_count = 1;
1220 INIT_LIST_HEAD(&bo_va->bo_list);
1221 INIT_LIST_HEAD(&bo_va->valids);
1222 INIT_LIST_HEAD(&bo_va->invalids);
1223 INIT_LIST_HEAD(&bo_va->vm_status);
1225 list_add_tail(&bo_va->bo_list, &bo->va);
1231 * amdgpu_vm_bo_map - map bo inside a vm
1233 * @adev: amdgpu_device pointer
1234 * @bo_va: bo_va to store the address
1235 * @saddr: where to map the BO
1236 * @offset: requested offset in the BO
1237 * @flags: attributes of pages (read/write/valid/etc.)
1239 * Add a mapping of the BO at the specefied addr into the VM.
1240 * Returns 0 for success, error for failure.
1242 * Object has to be reserved and unreserved outside!
1244 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
1245 struct amdgpu_bo_va *bo_va,
1246 uint64_t saddr, uint64_t offset,
1247 uint64_t size, uint32_t flags)
1249 struct amdgpu_bo_va_mapping *mapping;
1250 struct amdgpu_vm *vm = bo_va->vm;
1251 struct interval_tree_node *it;
1252 unsigned last_pfn, pt_idx;
1256 /* validate the parameters */
1257 if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
1258 size == 0 || size & AMDGPU_GPU_PAGE_MASK)
1261 /* make sure object fit at this offset */
1262 eaddr = saddr + size - 1;
1263 if ((saddr >= eaddr) || (offset + size > amdgpu_bo_size(bo_va->bo)))
1266 last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE;
1267 if (last_pfn >= adev->vm_manager.max_pfn) {
1268 dev_err(adev->dev, "va above limit (0x%08X >= 0x%08X)\n",
1269 last_pfn, adev->vm_manager.max_pfn);
1273 saddr /= AMDGPU_GPU_PAGE_SIZE;
1274 eaddr /= AMDGPU_GPU_PAGE_SIZE;
1276 it = interval_tree_iter_first(&vm->va, saddr, eaddr);
1278 struct amdgpu_bo_va_mapping *tmp;
1279 tmp = container_of(it, struct amdgpu_bo_va_mapping, it);
1280 /* bo and tmp overlap, invalid addr */
1281 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
1282 "0x%010lx-0x%010lx\n", bo_va->bo, saddr, eaddr,
1283 tmp->it.start, tmp->it.last + 1);
1288 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1294 INIT_LIST_HEAD(&mapping->list);
1295 mapping->it.start = saddr;
1296 mapping->it.last = eaddr;
1297 mapping->offset = offset;
1298 mapping->flags = flags;
1300 list_add(&mapping->list, &bo_va->invalids);
1301 interval_tree_insert(&mapping->it, &vm->va);
1303 /* Make sure the page tables are allocated */
1304 saddr >>= amdgpu_vm_block_size;
1305 eaddr >>= amdgpu_vm_block_size;
1307 BUG_ON(eaddr >= amdgpu_vm_num_pdes(adev));
1309 if (eaddr > vm->max_pde_used)
1310 vm->max_pde_used = eaddr;
1312 /* walk over the address space and allocate the page tables */
1313 for (pt_idx = saddr; pt_idx <= eaddr; ++pt_idx) {
1314 struct reservation_object *resv = vm->page_directory->tbo.resv;
1315 struct amdgpu_bo_list_entry *entry;
1316 struct amdgpu_bo *pt;
1318 entry = &vm->page_tables[pt_idx].entry;
1322 r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8,
1323 AMDGPU_GPU_PAGE_SIZE, true,
1324 AMDGPU_GEM_DOMAIN_VRAM,
1325 AMDGPU_GEM_CREATE_NO_CPU_ACCESS,
1330 /* Keep a reference to the page table to avoid freeing
1331 * them up in the wrong order.
1333 pt->parent = amdgpu_bo_ref(vm->page_directory);
1335 r = amdgpu_vm_clear_bo(adev, vm, pt);
1337 amdgpu_bo_unref(&pt);
1342 entry->priority = 0;
1343 entry->tv.bo = &entry->robj->tbo;
1344 entry->tv.shared = true;
1345 entry->user_pages = NULL;
1346 vm->page_tables[pt_idx].addr = 0;
1352 list_del(&mapping->list);
1353 interval_tree_remove(&mapping->it, &vm->va);
1354 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1362 * amdgpu_vm_bo_unmap - remove bo mapping from vm
1364 * @adev: amdgpu_device pointer
1365 * @bo_va: bo_va to remove the address from
1366 * @saddr: where to the BO is mapped
1368 * Remove a mapping of the BO at the specefied addr from the VM.
1369 * Returns 0 for success, error for failure.
1371 * Object has to be reserved and unreserved outside!
1373 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
1374 struct amdgpu_bo_va *bo_va,
1377 struct amdgpu_bo_va_mapping *mapping;
1378 struct amdgpu_vm *vm = bo_va->vm;
1381 saddr /= AMDGPU_GPU_PAGE_SIZE;
1383 list_for_each_entry(mapping, &bo_va->valids, list) {
1384 if (mapping->it.start == saddr)
1388 if (&mapping->list == &bo_va->valids) {
1391 list_for_each_entry(mapping, &bo_va->invalids, list) {
1392 if (mapping->it.start == saddr)
1396 if (&mapping->list == &bo_va->invalids)
1400 list_del(&mapping->list);
1401 interval_tree_remove(&mapping->it, &vm->va);
1402 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1405 list_add(&mapping->list, &vm->freed);
1413 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
1415 * @adev: amdgpu_device pointer
1416 * @bo_va: requested bo_va
1418 * Remove @bo_va->bo from the requested vm.
1420 * Object have to be reserved!
1422 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
1423 struct amdgpu_bo_va *bo_va)
1425 struct amdgpu_bo_va_mapping *mapping, *next;
1426 struct amdgpu_vm *vm = bo_va->vm;
1428 list_del(&bo_va->bo_list);
1430 spin_lock(&vm->status_lock);
1431 list_del(&bo_va->vm_status);
1432 spin_unlock(&vm->status_lock);
1434 list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
1435 list_del(&mapping->list);
1436 interval_tree_remove(&mapping->it, &vm->va);
1437 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1438 list_add(&mapping->list, &vm->freed);
1440 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
1441 list_del(&mapping->list);
1442 interval_tree_remove(&mapping->it, &vm->va);
1446 fence_put(bo_va->last_pt_update);
1451 * amdgpu_vm_bo_invalidate - mark the bo as invalid
1453 * @adev: amdgpu_device pointer
1455 * @bo: amdgpu buffer object
1457 * Mark @bo as invalid.
1459 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
1460 struct amdgpu_bo *bo)
1462 struct amdgpu_bo_va *bo_va;
1464 list_for_each_entry(bo_va, &bo->va, bo_list) {
1465 spin_lock(&bo_va->vm->status_lock);
1466 if (list_empty(&bo_va->vm_status))
1467 list_add(&bo_va->vm_status, &bo_va->vm->invalidated);
1468 spin_unlock(&bo_va->vm->status_lock);
1473 * amdgpu_vm_init - initialize a vm instance
1475 * @adev: amdgpu_device pointer
1480 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1482 const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
1483 AMDGPU_VM_PTE_COUNT * 8);
1484 unsigned pd_size, pd_entries;
1485 unsigned ring_instance;
1486 struct amdgpu_ring *ring;
1487 struct amd_sched_rq *rq;
1490 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
1493 vm->client_id = atomic64_inc_return(&adev->vm_manager.client_counter);
1494 spin_lock_init(&vm->status_lock);
1495 INIT_LIST_HEAD(&vm->invalidated);
1496 INIT_LIST_HEAD(&vm->cleared);
1497 INIT_LIST_HEAD(&vm->freed);
1499 pd_size = amdgpu_vm_directory_size(adev);
1500 pd_entries = amdgpu_vm_num_pdes(adev);
1502 /* allocate page table array */
1503 vm->page_tables = drm_calloc_large(pd_entries, sizeof(struct amdgpu_vm_pt));
1504 if (vm->page_tables == NULL) {
1505 DRM_ERROR("Cannot allocate memory for page table array\n");
1509 /* create scheduler entity for page table updates */
1511 ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring);
1512 ring_instance %= adev->vm_manager.vm_pte_num_rings;
1513 ring = adev->vm_manager.vm_pte_rings[ring_instance];
1514 rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
1515 r = amd_sched_entity_init(&ring->sched, &vm->entity,
1516 rq, amdgpu_sched_jobs);
1520 vm->page_directory_fence = NULL;
1522 r = amdgpu_bo_create(adev, pd_size, align, true,
1523 AMDGPU_GEM_DOMAIN_VRAM,
1524 AMDGPU_GEM_CREATE_NO_CPU_ACCESS,
1525 NULL, NULL, &vm->page_directory);
1527 goto error_free_sched_entity;
1529 r = amdgpu_bo_reserve(vm->page_directory, false);
1531 goto error_free_page_directory;
1533 r = amdgpu_vm_clear_bo(adev, vm, vm->page_directory);
1534 amdgpu_bo_unreserve(vm->page_directory);
1536 goto error_free_page_directory;
1540 error_free_page_directory:
1541 amdgpu_bo_unref(&vm->page_directory);
1542 vm->page_directory = NULL;
1544 error_free_sched_entity:
1545 amd_sched_entity_fini(&ring->sched, &vm->entity);
1551 * amdgpu_vm_fini - tear down a vm instance
1553 * @adev: amdgpu_device pointer
1557 * Unbind the VM and remove all bos from the vm bo list
1559 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1561 struct amdgpu_bo_va_mapping *mapping, *tmp;
1564 amd_sched_entity_fini(vm->entity.sched, &vm->entity);
1566 if (!RB_EMPTY_ROOT(&vm->va)) {
1567 dev_err(adev->dev, "still active bo inside vm\n");
1569 rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, it.rb) {
1570 list_del(&mapping->list);
1571 interval_tree_remove(&mapping->it, &vm->va);
1574 list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
1575 list_del(&mapping->list);
1579 for (i = 0; i < amdgpu_vm_num_pdes(adev); i++)
1580 amdgpu_bo_unref(&vm->page_tables[i].entry.robj);
1581 drm_free_large(vm->page_tables);
1583 amdgpu_bo_unref(&vm->page_directory);
1584 fence_put(vm->page_directory_fence);
1588 * amdgpu_vm_manager_init - init the VM manager
1590 * @adev: amdgpu_device pointer
1592 * Initialize the VM manager structures
1594 void amdgpu_vm_manager_init(struct amdgpu_device *adev)
1598 INIT_LIST_HEAD(&adev->vm_manager.ids_lru);
1600 /* skip over VMID 0, since it is the system VM */
1601 for (i = 1; i < adev->vm_manager.num_ids; ++i) {
1602 amdgpu_vm_reset_id(adev, i);
1603 amdgpu_sync_create(&adev->vm_manager.ids[i].active);
1604 list_add_tail(&adev->vm_manager.ids[i].list,
1605 &adev->vm_manager.ids_lru);
1608 adev->vm_manager.fence_context = fence_context_alloc(AMDGPU_MAX_RINGS);
1609 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
1610 adev->vm_manager.seqno[i] = 0;
1612 atomic_set(&adev->vm_manager.vm_pte_next_ring, 0);
1613 atomic64_set(&adev->vm_manager.client_counter, 0);
1617 * amdgpu_vm_manager_fini - cleanup VM manager
1619 * @adev: amdgpu_device pointer
1621 * Cleanup the VM manager and free resources.
1623 void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
1627 for (i = 0; i < AMDGPU_NUM_VM; ++i) {
1628 struct amdgpu_vm_id *id = &adev->vm_manager.ids[i];
1630 fence_put(adev->vm_manager.ids[i].first);
1631 amdgpu_sync_free(&adev->vm_manager.ids[i].active);
1632 fence_put(id->flushed_updates);