drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/fence-array.h>
  29 #include <drm/drmP.h>
  30 #include <drm/amdgpu_drm.h>
  31 #include "amdgpu.h"
  32 #include "amdgpu_trace.h"
  33
  34 /*
  35  * GPUVM
  36  * GPUVM is similar to the legacy gart on older asics, however
  37  * rather than there being a single global gart table
  38  * for the entire GPU, there are multiple VM page tables active
  39  * at any given time.  The VM page tables can contain a mix
  40  * vram pages and system memory pages and system memory pages
  41  * can be mapped as snooped (cached system pages) or unsnooped
  42  * (uncached system pages).
  43  * Each VM has an ID associated with it and there is a page table
  44  * associated with each VMID.  When execting a command buffer,
  45  * the kernel tells the the ring what VMID to use for that command
  46  * buffer.  VMIDs are allocated dynamically as commands are submitted.
  47  * The userspace drivers maintain their own address space and the kernel
  48  * sets up their pages tables accordingly when they submit their
  49  * command buffers and a VMID is assigned.
  50  * Cayman/Trinity support up to 8 active VMs at any given time;
  51  * SI supports 16.
  52  */
  53
  54 /* Special value that no flush is necessary */
  55 #define AMDGPU_VM_NO_FLUSH (~0ll)
  56
  57 /* Local structure. Encapsulate some VM table update parameters to reduce
  58  * the number of function parameters
  59  */
  60 struct amdgpu_vm_update_params {
  61         /* address where to copy page table entries from */
  62         uint64_t src;
  63         /* DMA addresses to use for mapping */
  64         dma_addr_t *pages_addr;
  65         /* indirect buffer to fill with commands */
  66         struct amdgpu_ib *ib;
  67 };
  68
  69 /**
  70  * amdgpu_vm_num_pde - return the number of page directory entries
  71  *
  72  * @adev: amdgpu_device pointer
  73  *
  74  * Calculate the number of page directory entries.
  75  */
  76 static unsigned amdgpu_vm_num_pdes(struct amdgpu_device *adev)
  77 {
  78         return adev->vm_manager.max_pfn >> amdgpu_vm_block_size;
  79 }
  80
  81 /**
  82  * amdgpu_vm_directory_size - returns the size of the page directory in bytes
  83  *
  84  * @adev: amdgpu_device pointer
  85  *
  86  * Calculate the size of the page directory in bytes.
  87  */
  88 static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev)
  89 {
  90         return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev) * 8);
  91 }
  92
  93 /**
  94  * amdgpu_vm_get_pd_bo - add the VM PD to a validation list
  95  *
  96  * @vm: vm providing the BOs
  97  * @validated: head of validation list
  98  * @entry: entry to add
  99  *
 100  * Add the page directory to the list of BOs to
 101  * validate for command submission.
 102  */
 103 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
 104                          struct list_head *validated,
 105                          struct amdgpu_bo_list_entry *entry)
 106 {
 107         entry->robj = vm->page_directory;
 108         entry->priority = 0;
 109         entry->tv.bo = &vm->page_directory->tbo;
 110         entry->tv.shared = true;
 111         entry->user_pages = NULL;
 112         list_add(&entry->tv.head, validated);
 113 }
 114
 115 /**
 116  * amdgpu_vm_get_bos - add the vm BOs to a duplicates list
 117  *
 118  * @adev: amdgpu device pointer
 119  * @vm: vm providing the BOs
 120  * @duplicates: head of duplicates list
 121  *
 122  * Add the page directory to the BO duplicates list
 123  * for command submission.
 124  */
 125 void amdgpu_vm_get_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 126                           struct list_head *duplicates)
 127 {
 128         uint64_t num_evictions;
 129         unsigned i;
 130
 131         /* We only need to validate the page tables
 132          * if they aren't already valid.
 133          */
 134         num_evictions = atomic64_read(&adev->num_evictions);
 135         if (num_evictions == vm->last_eviction_counter)
 136                 return;
 137
 138         /* add the vm page table to the list */
 139         for (i = 0; i <= vm->max_pde_used; ++i) {
 140                 struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry;
 141
 142                 if (!entry->robj)
 143                         continue;
 144
 145                 list_add(&entry->tv.head, duplicates);
 146         }
 147
 148 }
 149
 150 /**
 151  * amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail
 152  *
 153  * @adev: amdgpu device instance
 154  * @vm: vm providing the BOs
 155  *
 156  * Move the PT BOs to the tail of the LRU.
 157  */
 158 void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
 159                                   struct amdgpu_vm *vm)
 160 {
 161         struct ttm_bo_global *glob = adev->mman.bdev.glob;
 162         unsigned i;
 163
 164         spin_lock(&glob->lru_lock);
 165         for (i = 0; i <= vm->max_pde_used; ++i) {
 166                 struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry;
 167
 168                 if (!entry->robj)
 169                         continue;
 170
 171                 ttm_bo_move_to_lru_tail(&entry->robj->tbo);
 172         }
 173         spin_unlock(&glob->lru_lock);
 174 }
 175
 176 /**
 177  * amdgpu_vm_grab_id - allocate the next free VMID
 178  *
 179  * @vm: vm to allocate id for
 180  * @ring: ring we want to submit job to
 181  * @sync: sync object where we add dependencies
 182  * @fence: fence protecting ID from reuse
 183  *
 184  * Allocate an id for the vm, adding fences to the sync obj as necessary.
 185  */
 186 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
 187                       struct amdgpu_sync *sync, struct fence *fence,
 188                       unsigned *vm_id, uint64_t *vm_pd_addr)
 189 {
 190         struct amdgpu_device *adev = ring->adev;
 191         struct fence *updates = sync->last_vm_update;
 192         struct amdgpu_vm_id *id, *idle;
 193         struct fence **fences;
 194         unsigned i;
 195         int r = 0;
 196
 197         fences = kmalloc_array(sizeof(void *), adev->vm_manager.num_ids,
 198                                GFP_KERNEL);
 199         if (!fences)
 200                 return -ENOMEM;
 201
 202         mutex_lock(&adev->vm_manager.lock);
 203
 204         /* Check if we have an idle VMID */
 205         i = 0;
 206         list_for_each_entry(idle, &adev->vm_manager.ids_lru, list) {
 207                 fences[i] = amdgpu_sync_peek_fence(&idle->active, ring);
 208                 if (!fences[i])
 209                         break;
 210                 ++i;
 211         }
 212
 213         /* If we can't find a idle VMID to use, wait till one becomes available */
 214         if (&idle->list == &adev->vm_manager.ids_lru) {
 215                 u64 fence_context = adev->vm_manager.fence_context + ring->idx;
 216                 unsigned seqno = ++adev->vm_manager.seqno[ring->idx];
 217                 struct fence_array *array;
 218                 unsigned j;
 219
 220                 for (j = 0; j < i; ++j)
 221                         fence_get(fences[j]);
 222
 223                 array = fence_array_create(i, fences, fence_context,
 224                                            seqno, true);
 225                 if (!array) {
 226                         for (j = 0; j < i; ++j)
 227                                 fence_put(fences[j]);
 228                         kfree(fences);
 229                         r = -ENOMEM;
 230                         goto error;
 231                 }
 232
 233
 234                 r = amdgpu_sync_fence(ring->adev, sync, &array->base);
 235                 fence_put(&array->base);
 236                 if (r)
 237                         goto error;
 238
 239                 mutex_unlock(&adev->vm_manager.lock);
 240                 return 0;
 241
 242         }
 243         kfree(fences);
 244
 245         /* Check if we can use a VMID already assigned to this VM */
 246         i = ring->idx;
 247         do {
 248                 struct fence *flushed;
 249                 bool same_ring = ring->idx == i;
 250
 251                 id = vm->ids[i++];
 252                 if (i == AMDGPU_MAX_RINGS)
 253                         i = 0;
 254
 255                 /* Check all the prerequisites to using this VMID */
 256                 if (!id)
 257                         continue;
 258
 259                 if (atomic64_read(&id->owner) != vm->client_id)
 260                         continue;
 261
 262                 if (*vm_pd_addr != id->pd_gpu_addr)
 263                         continue;
 264
 265                 if (!same_ring &&
 266                     (!id->last_flush || !fence_is_signaled(id->last_flush)))
 267                         continue;
 268
 269                 flushed  = id->flushed_updates;
 270                 if (updates &&
 271                     (!flushed || fence_is_later(updates, flushed)))
 272                         continue;
 273
 274                 /* Good we can use this VMID. Remember this submission as
 275                  * user of the VMID.
 276                  */
 277                 r = amdgpu_sync_fence(ring->adev, &id->active, fence);
 278                 if (r)
 279                         goto error;
 280
 281                 list_move_tail(&id->list, &adev->vm_manager.ids_lru);
 282                 vm->ids[ring->idx] = id;
 283
 284                 *vm_id = id - adev->vm_manager.ids;
 285                 *vm_pd_addr = AMDGPU_VM_NO_FLUSH;
 286                 trace_amdgpu_vm_grab_id(vm, ring->idx, *vm_id, *vm_pd_addr);
 287
 288                 mutex_unlock(&adev->vm_manager.lock);
 289                 return 0;
 290
 291         } while (i != ring->idx);
 292
 293         /* Still no ID to use? Then use the idle one found earlier */
 294         id = idle;
 295
 296         /* Remember this submission as user of the VMID */
 297         r = amdgpu_sync_fence(ring->adev, &id->active, fence);
 298         if (r)
 299                 goto error;
 300
 301         fence_put(id->first);
 302         id->first = fence_get(fence);
 303
 304         fence_put(id->last_flush);
 305         id->last_flush = NULL;
 306
 307         fence_put(id->flushed_updates);
 308         id->flushed_updates = fence_get(updates);
 309
 310         id->pd_gpu_addr = *vm_pd_addr;
 311
 312         list_move_tail(&id->list, &adev->vm_manager.ids_lru);
 313         atomic64_set(&id->owner, vm->client_id);
 314         vm->ids[ring->idx] = id;
 315
 316         *vm_id = id - adev->vm_manager.ids;
 317         trace_amdgpu_vm_grab_id(vm, ring->idx, *vm_id, *vm_pd_addr);
 318
 319 error:
 320         mutex_unlock(&adev->vm_manager.lock);
 321         return r;
 322 }
 323
 324 static bool amdgpu_vm_ring_has_compute_vm_bug(struct amdgpu_ring *ring)
 325 {
 326         struct amdgpu_device *adev = ring->adev;
 327         const struct amdgpu_ip_block_version *ip_block;
 328
 329         if (ring->type != AMDGPU_RING_TYPE_COMPUTE)
 330                 /* only compute rings */
 331                 return false;
 332
 333         ip_block = amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
 334         if (!ip_block)
 335                 return false;
 336
 337         if (ip_block->major <= 7) {
 338                 /* gfx7 has no workaround */
 339                 return true;
 340         } else if (ip_block->major == 8) {
 341                 if (adev->gfx.mec_fw_version >= 673)
 342                         /* gfx8 is fixed in MEC firmware 673 */
 343                         return false;
 344                 else
 345                         return true;
 346         }
 347         return false;
 348 }
 349
 350 /**
 351  * amdgpu_vm_flush - hardware flush the vm
 352  *
 353  * @ring: ring to use for flush
 354  * @vm_id: vmid number to use
 355  * @pd_addr: address of the page directory
 356  *
 357  * Emit a VM flush when it is necessary.
 358  */
 359 int amdgpu_vm_flush(struct amdgpu_ring *ring,
 360                     unsigned vm_id, uint64_t pd_addr,
 361                     uint32_t gds_base, uint32_t gds_size,
 362                     uint32_t gws_base, uint32_t gws_size,
 363                     uint32_t oa_base, uint32_t oa_size)
 364 {
 365         struct amdgpu_device *adev = ring->adev;
 366         struct amdgpu_vm_id *id = &adev->vm_manager.ids[vm_id];
 367         bool gds_switch_needed = ring->funcs->emit_gds_switch && (
 368                 id->gds_base != gds_base ||
 369                 id->gds_size != gds_size ||
 370                 id->gws_base != gws_base ||
 371                 id->gws_size != gws_size ||
 372                 id->oa_base != oa_base ||
 373                 id->oa_size != oa_size);
 374         int r;
 375
 376         if (ring->funcs->emit_pipeline_sync && (
 377             pd_addr != AMDGPU_VM_NO_FLUSH || gds_switch_needed ||
 378             amdgpu_vm_ring_has_compute_vm_bug(ring)))
 379                 amdgpu_ring_emit_pipeline_sync(ring);
 380
 381         if (ring->funcs->emit_vm_flush &&
 382             pd_addr != AMDGPU_VM_NO_FLUSH) {
 383                 struct fence *fence;
 384
 385                 trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id);
 386                 amdgpu_ring_emit_vm_flush(ring, vm_id, pd_addr);
 387
 388                 r = amdgpu_fence_emit(ring, &fence);
 389                 if (r)
 390                         return r;
 391
 392                 mutex_lock(&adev->vm_manager.lock);
 393                 fence_put(id->last_flush);
 394                 id->last_flush = fence;
 395                 mutex_unlock(&adev->vm_manager.lock);
 396         }
 397
 398         if (gds_switch_needed) {
 399                 id->gds_base = gds_base;
 400                 id->gds_size = gds_size;
 401                 id->gws_base = gws_base;
 402                 id->gws_size = gws_size;
 403                 id->oa_base = oa_base;
 404                 id->oa_size = oa_size;
 405                 amdgpu_ring_emit_gds_switch(ring, vm_id,
 406                                             gds_base, gds_size,
 407                                             gws_base, gws_size,
 408                                             oa_base, oa_size);
 409         }
 410
 411         return 0;
 412 }
 413
 414 /**
 415  * amdgpu_vm_reset_id - reset VMID to zero
 416  *
 417  * @adev: amdgpu device structure
 418  * @vm_id: vmid number to use
 419  *
 420  * Reset saved GDW, GWS and OA to force switch on next flush.
 421  */
 422 void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id)
 423 {
 424         struct amdgpu_vm_id *id = &adev->vm_manager.ids[vm_id];
 425
 426         id->gds_base = 0;
 427         id->gds_size = 0;
 428         id->gws_base = 0;
 429         id->gws_size = 0;
 430         id->oa_base = 0;
 431         id->oa_size = 0;
 432 }
 433
 434 /**
 435  * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
 436  *
 437  * @vm: requested vm
 438  * @bo: requested buffer object
 439  *
 440  * Find @bo inside the requested vm.
 441  * Search inside the @bos vm list for the requested vm
 442  * Returns the found bo_va or NULL if none is found
 443  *
 444  * Object has to be reserved!
 445  */
 446 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
 447                                        struct amdgpu_bo *bo)
 448 {
 449         struct amdgpu_bo_va *bo_va;
 450
 451         list_for_each_entry(bo_va, &bo->va, bo_list) {
 452                 if (bo_va->vm == vm) {
 453                         return bo_va;
 454                 }
 455         }
 456         return NULL;
 457 }
 458
 459 /**
 460  * amdgpu_vm_update_pages - helper to call the right asic function
 461  *
 462  * @adev: amdgpu_device pointer
 463  * @vm_update_params: see amdgpu_vm_update_params definition
 464  * @pe: addr of the page entry
 465  * @addr: dst addr to write into pe
 466  * @count: number of page entries to update
 467  * @incr: increase next addr by incr bytes
 468  * @flags: hw access flags
 469  *
 470  * Traces the parameters and calls the right asic functions
 471  * to setup the page table using the DMA.
 472  */
 473 static void amdgpu_vm_update_pages(struct amdgpu_device *adev,
 474                                    struct amdgpu_vm_update_params
 475                                         *vm_update_params,
 476                                    uint64_t pe, uint64_t addr,
 477                                    unsigned count, uint32_t incr,
 478                                    uint32_t flags)
 479 {
 480         trace_amdgpu_vm_set_page(pe, addr, count, incr, flags);
 481
 482         if (vm_update_params->src) {
 483                 amdgpu_vm_copy_pte(adev, vm_update_params->ib,
 484                         pe, (vm_update_params->src + (addr >> 12) * 8), count);
 485
 486         } else if (vm_update_params->pages_addr) {
 487                 amdgpu_vm_write_pte(adev, vm_update_params->ib,
 488                         vm_update_params->pages_addr,
 489                         pe, addr, count, incr, flags);
 490
 491         } else if (count < 3) {
 492                 amdgpu_vm_write_pte(adev, vm_update_params->ib, NULL, pe, addr,
 493                                     count, incr, flags);
 494
 495         } else {
 496                 amdgpu_vm_set_pte_pde(adev, vm_update_params->ib, pe, addr,
 497                                       count, incr, flags);
 498         }
 499 }
 500
 501 /**
 502  * amdgpu_vm_clear_bo - initially clear the page dir/table
 503  *
 504  * @adev: amdgpu_device pointer
 505  * @bo: bo to clear
 506  *
 507  * need to reserve bo first before calling it.
 508  */
 509 static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
 510                               struct amdgpu_vm *vm,
 511                               struct amdgpu_bo *bo)
 512 {
 513         struct amdgpu_ring *ring;
 514         struct fence *fence = NULL;
 515         struct amdgpu_job *job;
 516         struct amdgpu_vm_update_params vm_update_params;
 517         unsigned entries;
 518         uint64_t addr;
 519         int r;
 520
 521         memset(&vm_update_params, 0, sizeof(vm_update_params));
 522         ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
 523
 524         r = reservation_object_reserve_shared(bo->tbo.resv);
 525         if (r)
 526                 return r;
 527
 528         r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 529         if (r)
 530                 goto error;
 531
 532         addr = amdgpu_bo_gpu_offset(bo);
 533         entries = amdgpu_bo_size(bo) / 8;
 534
 535         r = amdgpu_job_alloc_with_ib(adev, 64, &job);
 536         if (r)
 537                 goto error;
 538
 539         vm_update_params.ib = &job->ibs[0];
 540         amdgpu_vm_update_pages(adev, &vm_update_params, addr, 0, entries,
 541                                0, 0);
 542         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
 543
 544         WARN_ON(job->ibs[0].length_dw > 64);
 545         r = amdgpu_job_submit(job, ring, &vm->entity,
 546                               AMDGPU_FENCE_OWNER_VM, &fence);
 547         if (r)
 548                 goto error_free;
 549
 550         amdgpu_bo_fence(bo, fence, true);
 551         fence_put(fence);
 552         return 0;
 553
 554 error_free:
 555         amdgpu_job_free(job);
 556
 557 error:
 558         return r;
 559 }
 560
 561 /**
 562  * amdgpu_vm_map_gart - Resolve gart mapping of addr
 563  *
 564  * @pages_addr: optional DMA address to use for lookup
 565  * @addr: the unmapped addr
 566  *
 567  * Look up the physical address of the page that the pte resolves
 568  * to and return the pointer for the page table entry.
 569  */
 570 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
 571 {
 572         uint64_t result;
 573
 574         if (pages_addr) {
 575                 /* page table offset */
 576                 result = pages_addr[addr >> PAGE_SHIFT];
 577
 578                 /* in case cpu page size != gpu page size*/
 579                 result |= addr & (~PAGE_MASK);
 580
 581         } else {
 582                 /* No mapping required */
 583                 result = addr;
 584         }
 585
 586         result &= 0xFFFFFFFFFFFFF000ULL;
 587
 588         return result;
 589 }
 590
 591 /**
 592  * amdgpu_vm_update_pdes - make sure that page directory is valid
 593  *
 594  * @adev: amdgpu_device pointer
 595  * @vm: requested vm
 596  * @start: start of GPU address range
 597  * @end: end of GPU address range
 598  *
 599  * Allocates new page tables if necessary
 600  * and updates the page directory.
 601  * Returns 0 for success, error for failure.
 602  */
 603 int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
 604                                     struct amdgpu_vm *vm)
 605 {
 606         struct amdgpu_ring *ring;
 607         struct amdgpu_bo *pd = vm->page_directory;
 608         uint64_t pd_addr = amdgpu_bo_gpu_offset(pd);
 609         uint32_t incr = AMDGPU_VM_PTE_COUNT * 8;
 610         uint64_t last_pde = ~0, last_pt = ~0;
 611         unsigned count = 0, pt_idx, ndw;
 612         struct amdgpu_job *job;
 613         struct amdgpu_vm_update_params vm_update_params;
 614         struct fence *fence = NULL;
 615
 616         int r;
 617
 618         memset(&vm_update_params, 0, sizeof(vm_update_params));
 619         ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
 620
 621         /* padding, etc. */
 622         ndw = 64;
 623
 624         /* assume the worst case */
 625         ndw += vm->max_pde_used * 6;
 626
 627         r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
 628         if (r)
 629                 return r;
 630
 631         vm_update_params.ib = &job->ibs[0];
 632
 633         /* walk over the address space and update the page directory */
 634         for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) {
 635                 struct amdgpu_bo *bo = vm->page_tables[pt_idx].entry.robj;
 636                 uint64_t pde, pt;
 637
 638                 if (bo == NULL)
 639                         continue;
 640
 641                 pt = amdgpu_bo_gpu_offset(bo);
 642                 if (vm->page_tables[pt_idx].addr == pt)
 643                         continue;
 644                 vm->page_tables[pt_idx].addr = pt;
 645
 646                 pde = pd_addr + pt_idx * 8;
 647                 if (((last_pde + 8 * count) != pde) ||
 648                     ((last_pt + incr * count) != pt)) {
 649
 650                         if (count) {
 651                                 amdgpu_vm_update_pages(adev, &vm_update_params,
 652                                                        last_pde, last_pt,
 653                                                        count, incr,
 654                                                        AMDGPU_PTE_VALID);
 655                         }
 656
 657                         count = 1;
 658                         last_pde = pde;
 659                         last_pt = pt;
 660                 } else {
 661                         ++count;
 662                 }
 663         }
 664
 665         if (count)
 666                 amdgpu_vm_update_pages(adev, &vm_update_params,
 667                                         last_pde, last_pt,
 668                                         count, incr, AMDGPU_PTE_VALID);
 669
 670         if (vm_update_params.ib->length_dw != 0) {
 671                 amdgpu_ring_pad_ib(ring, vm_update_params.ib);
 672                 amdgpu_sync_resv(adev, &job->sync, pd->tbo.resv,
 673                                  AMDGPU_FENCE_OWNER_VM);
 674                 WARN_ON(vm_update_params.ib->length_dw > ndw);
 675                 r = amdgpu_job_submit(job, ring, &vm->entity,
 676                                       AMDGPU_FENCE_OWNER_VM, &fence);
 677                 if (r)
 678                         goto error_free;
 679
 680                 amdgpu_bo_fence(pd, fence, true);
 681                 fence_put(vm->page_directory_fence);
 682                 vm->page_directory_fence = fence_get(fence);
 683                 fence_put(fence);
 684
 685         } else {
 686                 amdgpu_job_free(job);
 687         }
 688
 689         return 0;
 690
 691 error_free:
 692         amdgpu_job_free(job);
 693         return r;
 694 }
 695
 696 /**
 697  * amdgpu_vm_frag_ptes - add fragment information to PTEs
 698  *
 699  * @adev: amdgpu_device pointer
 700  * @vm_update_params: see amdgpu_vm_update_params definition
 701  * @pe_start: first PTE to handle
 702  * @pe_end: last PTE to handle
 703  * @addr: addr those PTEs should point to
 704  * @flags: hw mapping flags
 705  */
 706 static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev,
 707                                 struct amdgpu_vm_update_params
 708                                         *vm_update_params,
 709                                 uint64_t pe_start, uint64_t pe_end,
 710                                 uint64_t addr, uint32_t flags)
 711 {
 712         /**
 713          * The MC L1 TLB supports variable sized pages, based on a fragment
 714          * field in the PTE. When this field is set to a non-zero value, page
 715          * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
 716          * flags are considered valid for all PTEs within the fragment range
 717          * and corresponding mappings are assumed to be physically contiguous.
 718          *
 719          * The L1 TLB can store a single PTE for the whole fragment,
 720          * significantly increasing the space available for translation
 721          * caching. This leads to large improvements in throughput when the
 722          * TLB is under pressure.
 723          *
 724          * The L2 TLB distributes small and large fragments into two
 725          * asymmetric partitions. The large fragment cache is significantly
 726          * larger. Thus, we try to use large fragments wherever possible.
 727          * Userspace can support this by aligning virtual base address and
 728          * allocation size to the fragment size.
 729          */
 730
 731         /* SI and newer are optimized for 64KB */
 732         uint64_t frag_flags = AMDGPU_PTE_FRAG_64KB;
 733         uint64_t frag_align = 0x80;
 734
 735         uint64_t frag_start = ALIGN(pe_start, frag_align);
 736         uint64_t frag_end = pe_end & ~(frag_align - 1);
 737
 738         unsigned count;
 739
 740         /* Abort early if there isn't anything to do */
 741         if (pe_start == pe_end)
 742                 return;
 743
 744         /* system pages are non continuously */
 745         if (vm_update_params->src || vm_update_params->pages_addr ||
 746                 !(flags & AMDGPU_PTE_VALID) || (frag_start >= frag_end)) {
 747
 748                 count = (pe_end - pe_start) / 8;
 749                 amdgpu_vm_update_pages(adev, vm_update_params, pe_start,
 750                                        addr, count, AMDGPU_GPU_PAGE_SIZE,
 751                                        flags);
 752                 return;
 753         }
 754
 755         /* handle the 4K area at the beginning */
 756         if (pe_start != frag_start) {
 757                 count = (frag_start - pe_start) / 8;
 758                 amdgpu_vm_update_pages(adev, vm_update_params, pe_start, addr,
 759                                        count, AMDGPU_GPU_PAGE_SIZE, flags);
 760                 addr += AMDGPU_GPU_PAGE_SIZE * count;
 761         }
 762
 763         /* handle the area in the middle */
 764         count = (frag_end - frag_start) / 8;
 765         amdgpu_vm_update_pages(adev, vm_update_params, frag_start, addr, count,
 766                                AMDGPU_GPU_PAGE_SIZE, flags | frag_flags);
 767
 768         /* handle the 4K area at the end */
 769         if (frag_end != pe_end) {
 770                 addr += AMDGPU_GPU_PAGE_SIZE * count;
 771                 count = (pe_end - frag_end) / 8;
 772                 amdgpu_vm_update_pages(adev, vm_update_params, frag_end, addr,
 773                                        count, AMDGPU_GPU_PAGE_SIZE, flags);
 774         }
 775 }
 776
 777 /**
 778  * amdgpu_vm_update_ptes - make sure that page tables are valid
 779  *
 780  * @adev: amdgpu_device pointer
 781  * @vm_update_params: see amdgpu_vm_update_params definition
 782  * @vm: requested vm
 783  * @start: start of GPU address range
 784  * @end: end of GPU address range
 785  * @dst: destination address to map to, the next dst inside the function
 786  * @flags: mapping flags
 787  *
 788  * Update the page tables in the range @start - @end.
 789  */
 790 static void amdgpu_vm_update_ptes(struct amdgpu_device *adev,
 791                                   struct amdgpu_vm_update_params
 792                                         *vm_update_params,
 793                                   struct amdgpu_vm *vm,
 794                                   uint64_t start, uint64_t end,
 795                                   uint64_t dst, uint32_t flags)
 796 {
 797         const uint64_t mask = AMDGPU_VM_PTE_COUNT - 1;
 798
 799         uint64_t cur_pe_start, cur_pe_end, cur_dst;
 800         uint64_t addr; /* next GPU address to be updated */
 801         uint64_t pt_idx;
 802         struct amdgpu_bo *pt;
 803         unsigned nptes; /* next number of ptes to be updated */
 804         uint64_t next_pe_start;
 805
 806         /* initialize the variables */
 807         addr = start;
 808         pt_idx = addr >> amdgpu_vm_block_size;
 809         pt = vm->page_tables[pt_idx].entry.robj;
 810
 811         if ((addr & ~mask) == (end & ~mask))
 812                 nptes = end - addr;
 813         else
 814                 nptes = AMDGPU_VM_PTE_COUNT - (addr & mask);
 815
 816         cur_pe_start = amdgpu_bo_gpu_offset(pt);
 817         cur_pe_start += (addr & mask) * 8;
 818         cur_pe_end = cur_pe_start + 8 * nptes;
 819         cur_dst = dst;
 820
 821         /* for next ptb*/
 822         addr += nptes;
 823         dst += nptes * AMDGPU_GPU_PAGE_SIZE;
 824
 825         /* walk over the address space and update the page tables */
 826         while (addr < end) {
 827                 pt_idx = addr >> amdgpu_vm_block_size;
 828                 pt = vm->page_tables[pt_idx].entry.robj;
 829
 830                 if ((addr & ~mask) == (end & ~mask))
 831                         nptes = end - addr;
 832                 else
 833                         nptes = AMDGPU_VM_PTE_COUNT - (addr & mask);
 834
 835                 next_pe_start = amdgpu_bo_gpu_offset(pt);
 836                 next_pe_start += (addr & mask) * 8;
 837
 838                 if (cur_pe_end == next_pe_start) {
 839                         /* The next ptb is consecutive to current ptb.
 840                          * Don't call amdgpu_vm_frag_ptes now.
 841                          * Will update two ptbs together in future.
 842                         */
 843                         cur_pe_end += 8 * nptes;
 844                 } else {
 845                         amdgpu_vm_frag_ptes(adev, vm_update_params,
 846                                             cur_pe_start, cur_pe_end,
 847                                             cur_dst, flags);
 848
 849                         cur_pe_start = next_pe_start;
 850                         cur_pe_end = next_pe_start + 8 * nptes;
 851                         cur_dst = dst;
 852                 }
 853
 854                 /* for next ptb*/
 855                 addr += nptes;
 856                 dst += nptes * AMDGPU_GPU_PAGE_SIZE;
 857         }
 858
 859         amdgpu_vm_frag_ptes(adev, vm_update_params, cur_pe_start,
 860                             cur_pe_end, cur_dst, flags);
 861 }
 862
 863 /**
 864  * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
 865  *
 866  * @adev: amdgpu_device pointer
 867  * @exclusive: fence we need to sync to
 868  * @src: address where to copy page table entries from
 869  * @pages_addr: DMA addresses to use for mapping
 870  * @vm: requested vm
 871  * @start: start of mapped range
 872  * @last: last mapped entry
 873  * @flags: flags for the entries
 874  * @addr: addr to set the area to
 875  * @fence: optional resulting fence
 876  *
 877  * Fill in the page table entries between @start and @last.
 878  * Returns 0 for success, -EINVAL for failure.
 879  */
 880 static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
 881                                        struct fence *exclusive,
 882                                        uint64_t src,
 883                                        dma_addr_t *pages_addr,
 884                                        struct amdgpu_vm *vm,
 885                                        uint64_t start, uint64_t last,
 886                                        uint32_t flags, uint64_t addr,
 887                                        struct fence **fence)
 888 {
 889         struct amdgpu_ring *ring;
 890         void *owner = AMDGPU_FENCE_OWNER_VM;
 891         unsigned nptes, ncmds, ndw;
 892         struct amdgpu_job *job;
 893         struct amdgpu_vm_update_params vm_update_params;
 894         struct fence *f = NULL;
 895         int r;
 896
 897         ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
 898         memset(&vm_update_params, 0, sizeof(vm_update_params));
 899         vm_update_params.src = src;
 900         vm_update_params.pages_addr = pages_addr;
 901
 902         /* sync to everything on unmapping */
 903         if (!(flags & AMDGPU_PTE_VALID))
 904                 owner = AMDGPU_FENCE_OWNER_UNDEFINED;
 905
 906         nptes = last - start + 1;
 907
 908         /*
 909          * reserve space for one command every (1 << BLOCK_SIZE)
 910          *  entries or 2k dwords (whatever is smaller)
 911          */
 912         ncmds = (nptes >> min(amdgpu_vm_block_size, 11)) + 1;
 913
 914         /* padding, etc. */
 915         ndw = 64;
 916
 917         if (vm_update_params.src) {
 918                 /* only copy commands needed */
 919                 ndw += ncmds * 7;
 920
 921         } else if (vm_update_params.pages_addr) {
 922                 /* header for write data commands */
 923                 ndw += ncmds * 4;
 924
 925                 /* body of write data command */
 926                 ndw += nptes * 2;
 927
 928         } else {
 929                 /* set page commands needed */
 930                 ndw += ncmds * 10;
 931
 932                 /* two extra commands for begin/end of fragment */
 933                 ndw += 2 * 10;
 934         }
 935
 936         r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
 937         if (r)
 938                 return r;
 939
 940         vm_update_params.ib = &job->ibs[0];
 941
 942         r = amdgpu_sync_fence(adev, &job->sync, exclusive);
 943         if (r)
 944                 goto error_free;
 945
 946         r = amdgpu_sync_resv(adev, &job->sync, vm->page_directory->tbo.resv,
 947                              owner);
 948         if (r)
 949                 goto error_free;
 950
 951         r = reservation_object_reserve_shared(vm->page_directory->tbo.resv);
 952         if (r)
 953                 goto error_free;
 954
 955         amdgpu_vm_update_ptes(adev, &vm_update_params, vm, start,
 956                               last + 1, addr, flags);
 957
 958         amdgpu_ring_pad_ib(ring, vm_update_params.ib);
 959         WARN_ON(vm_update_params.ib->length_dw > ndw);
 960         r = amdgpu_job_submit(job, ring, &vm->entity,
 961                               AMDGPU_FENCE_OWNER_VM, &f);
 962         if (r)
 963                 goto error_free;
 964
 965         amdgpu_bo_fence(vm->page_directory, f, true);
 966         if (fence) {
 967                 fence_put(*fence);
 968                 *fence = fence_get(f);
 969         }
 970         fence_put(f);
 971         return 0;
 972
 973 error_free:
 974         amdgpu_job_free(job);
 975         return r;
 976 }
 977
 978 /**
 979  * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks
 980  *
 981  * @adev: amdgpu_device pointer
 982  * @exclusive: fence we need to sync to
 983  * @gtt_flags: flags as they are used for GTT
 984  * @pages_addr: DMA addresses to use for mapping
 985  * @vm: requested vm
 986  * @mapping: mapped range and flags to use for the update
 987  * @addr: addr to set the area to
 988  * @flags: HW flags for the mapping
 989  * @fence: optional resulting fence
 990  *
 991  * Split the mapping into smaller chunks so that each update fits
 992  * into a SDMA IB.
 993  * Returns 0 for success, -EINVAL for failure.
 994  */
 995 static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
 996                                       struct fence *exclusive,
 997                                       uint32_t gtt_flags,
 998                                       dma_addr_t *pages_addr,
 999                                       struct amdgpu_vm *vm,
1000                                       struct amdgpu_bo_va_mapping *mapping,
1001                                       uint32_t flags, uint64_t addr,
1002                                       struct fence **fence)
1003 {
1004         const uint64_t max_size = 64ULL * 1024ULL * 1024ULL / AMDGPU_GPU_PAGE_SIZE;
1005
1006         uint64_t src = 0, start = mapping->it.start;
1007         int r;
1008
1009         /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1010          * but in case of something, we filter the flags in first place
1011          */
1012         if (!(mapping->flags & AMDGPU_PTE_READABLE))
1013                 flags &= ~AMDGPU_PTE_READABLE;
1014         if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
1015                 flags &= ~AMDGPU_PTE_WRITEABLE;
1016
1017         trace_amdgpu_vm_bo_update(mapping);
1018
1019         if (pages_addr) {
1020                 if (flags == gtt_flags)
1021                         src = adev->gart.table_addr + (addr >> 12) * 8;
1022                 addr = 0;
1023         }
1024         addr += mapping->offset;
1025
1026         if (!pages_addr || src)
1027                 return amdgpu_vm_bo_update_mapping(adev, exclusive,
1028                                                    src, pages_addr, vm,
1029                                                    start, mapping->it.last,
1030                                                    flags, addr, fence);
1031
1032         while (start != mapping->it.last + 1) {
1033                 uint64_t last;
1034
1035                 last = min((uint64_t)mapping->it.last, start + max_size - 1);
1036                 r = amdgpu_vm_bo_update_mapping(adev, exclusive,
1037                                                 src, pages_addr, vm,
1038                                                 start, last, flags, addr,
1039                                                 fence);
1040                 if (r)
1041                         return r;
1042
1043                 start = last + 1;
1044                 addr += max_size * AMDGPU_GPU_PAGE_SIZE;
1045         }
1046
1047         return 0;
1048 }
1049
1050 /**
1051  * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1052  *
1053  * @adev: amdgpu_device pointer
1054  * @bo_va: requested BO and VM object
1055  * @mem: ttm mem
1056  *
1057  * Fill in the page table entries for @bo_va.
1058  * Returns 0 for success, -EINVAL for failure.
1059  *
1060  * Object have to be reserved and mutex must be locked!
1061  */
1062 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
1063                         struct amdgpu_bo_va *bo_va,
1064                         struct ttm_mem_reg *mem)
1065 {
1066         struct amdgpu_vm *vm = bo_va->vm;
1067         struct amdgpu_bo_va_mapping *mapping;
1068         dma_addr_t *pages_addr = NULL;
1069         uint32_t gtt_flags, flags;
1070         struct fence *exclusive;
1071         uint64_t addr;
1072         int r;
1073
1074         if (mem) {
1075                 struct ttm_dma_tt *ttm;
1076
1077                 addr = (u64)mem->start << PAGE_SHIFT;
1078                 switch (mem->mem_type) {
1079                 case TTM_PL_TT:
1080                         ttm = container_of(bo_va->bo->tbo.ttm, struct
1081                                            ttm_dma_tt, ttm);
1082                         pages_addr = ttm->dma_address;
1083                         break;
1084
1085                 case TTM_PL_VRAM:
1086                         addr += adev->vm_manager.vram_base_offset;
1087                         break;
1088
1089                 default:
1090                         break;
1091                 }
1092
1093                 exclusive = reservation_object_get_excl(bo_va->bo->tbo.resv);
1094         } else {
1095                 addr = 0;
1096                 exclusive = NULL;
1097         }
1098
1099         flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem);
1100         gtt_flags = (adev == bo_va->bo->adev) ? flags : 0;
1101
1102         spin_lock(&vm->status_lock);
1103         if (!list_empty(&bo_va->vm_status))
1104                 list_splice_init(&bo_va->valids, &bo_va->invalids);
1105         spin_unlock(&vm->status_lock);
1106
1107         list_for_each_entry(mapping, &bo_va->invalids, list) {
1108                 r = amdgpu_vm_bo_split_mapping(adev, exclusive,
1109                                                gtt_flags, pages_addr, vm,
1110                                                mapping, flags, addr,
1111                                                &bo_va->last_pt_update);
1112                 if (r)
1113                         return r;
1114         }
1115
1116         if (trace_amdgpu_vm_bo_mapping_enabled()) {
1117                 list_for_each_entry(mapping, &bo_va->valids, list)
1118                         trace_amdgpu_vm_bo_mapping(mapping);
1119
1120                 list_for_each_entry(mapping, &bo_va->invalids, list)
1121                         trace_amdgpu_vm_bo_mapping(mapping);
1122         }
1123
1124         spin_lock(&vm->status_lock);
1125         list_splice_init(&bo_va->invalids, &bo_va->valids);
1126         list_del_init(&bo_va->vm_status);
1127         if (!mem)
1128                 list_add(&bo_va->vm_status, &vm->cleared);
1129         spin_unlock(&vm->status_lock);
1130
1131         return 0;
1132 }
1133
1134 /**
1135  * amdgpu_vm_clear_freed - clear freed BOs in the PT
1136  *
1137  * @adev: amdgpu_device pointer
1138  * @vm: requested vm
1139  *
1140  * Make sure all freed BOs are cleared in the PT.
1141  * Returns 0 for success.
1142  *
1143  * PTs have to be reserved and mutex must be locked!
1144  */
1145 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
1146                           struct amdgpu_vm *vm)
1147 {
1148         struct amdgpu_bo_va_mapping *mapping;
1149         int r;
1150
1151         while (!list_empty(&vm->freed)) {
1152                 mapping = list_first_entry(&vm->freed,
1153                         struct amdgpu_bo_va_mapping, list);
1154                 list_del(&mapping->list);
1155
1156                 r = amdgpu_vm_bo_split_mapping(adev, NULL, 0, NULL, vm, mapping,
1157                                                0, 0, NULL);
1158                 kfree(mapping);
1159                 if (r)
1160                         return r;
1161
1162         }
1163         return 0;
1164
1165 }
1166
1167 /**
1168  * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT
1169  *
1170  * @adev: amdgpu_device pointer
1171  * @vm: requested vm
1172  *
1173  * Make sure all invalidated BOs are cleared in the PT.
1174  * Returns 0 for success.
1175  *
1176  * PTs have to be reserved and mutex must be locked!
1177  */
1178 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev,
1179                              struct amdgpu_vm *vm, struct amdgpu_sync *sync)
1180 {
1181         struct amdgpu_bo_va *bo_va = NULL;
1182         int r = 0;
1183
1184         spin_lock(&vm->status_lock);
1185         while (!list_empty(&vm->invalidated)) {
1186                 bo_va = list_first_entry(&vm->invalidated,
1187                         struct amdgpu_bo_va, vm_status);
1188                 spin_unlock(&vm->status_lock);
1189
1190                 r = amdgpu_vm_bo_update(adev, bo_va, NULL);
1191                 if (r)
1192                         return r;
1193
1194                 spin_lock(&vm->status_lock);
1195         }
1196         spin_unlock(&vm->status_lock);
1197
1198         if (bo_va)
1199                 r = amdgpu_sync_fence(adev, sync, bo_va->last_pt_update);
1200
1201         return r;
1202 }
1203
1204 /**
1205  * amdgpu_vm_bo_add - add a bo to a specific vm
1206  *
1207  * @adev: amdgpu_device pointer
1208  * @vm: requested vm
1209  * @bo: amdgpu buffer object
1210  *
1211  * Add @bo into the requested vm.
1212  * Add @bo to the list of bos associated with the vm
1213  * Returns newly added bo_va or NULL for failure
1214  *
1215  * Object has to be reserved!
1216  */
1217 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
1218                                       struct amdgpu_vm *vm,
1219                                       struct amdgpu_bo *bo)
1220 {
1221         struct amdgpu_bo_va *bo_va;
1222
1223         bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
1224         if (bo_va == NULL) {
1225                 return NULL;
1226         }
1227         bo_va->vm = vm;
1228         bo_va->bo = bo;
1229         bo_va->ref_count = 1;
1230         INIT_LIST_HEAD(&bo_va->bo_list);
1231         INIT_LIST_HEAD(&bo_va->valids);
1232         INIT_LIST_HEAD(&bo_va->invalids);
1233         INIT_LIST_HEAD(&bo_va->vm_status);
1234
1235         list_add_tail(&bo_va->bo_list, &bo->va);
1236
1237         return bo_va;
1238 }
1239
1240 /**
1241  * amdgpu_vm_bo_map - map bo inside a vm
1242  *
1243  * @adev: amdgpu_device pointer
1244  * @bo_va: bo_va to store the address
1245  * @saddr: where to map the BO
1246  * @offset: requested offset in the BO
1247  * @flags: attributes of pages (read/write/valid/etc.)
1248  *
1249  * Add a mapping of the BO at the specefied addr into the VM.
1250  * Returns 0 for success, error for failure.
1251  *
1252  * Object has to be reserved and unreserved outside!
1253  */
1254 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
1255                      struct amdgpu_bo_va *bo_va,
1256                      uint64_t saddr, uint64_t offset,
1257                      uint64_t size, uint32_t flags)
1258 {
1259         struct amdgpu_bo_va_mapping *mapping;
1260         struct amdgpu_vm *vm = bo_va->vm;
1261         struct interval_tree_node *it;
1262         unsigned last_pfn, pt_idx;
1263         uint64_t eaddr;
1264         int r;
1265
1266         /* validate the parameters */
1267         if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
1268             size == 0 || size & AMDGPU_GPU_PAGE_MASK)
1269                 return -EINVAL;
1270
1271         /* make sure object fit at this offset */
1272         eaddr = saddr + size - 1;
1273         if ((saddr >= eaddr) || (offset + size > amdgpu_bo_size(bo_va->bo)))
1274                 return -EINVAL;
1275
1276         last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE;
1277         if (last_pfn >= adev->vm_manager.max_pfn) {
1278                 dev_err(adev->dev, "va above limit (0x%08X >= 0x%08X)\n",
1279                         last_pfn, adev->vm_manager.max_pfn);
1280                 return -EINVAL;
1281         }
1282
1283         saddr /= AMDGPU_GPU_PAGE_SIZE;
1284         eaddr /= AMDGPU_GPU_PAGE_SIZE;
1285
1286         it = interval_tree_iter_first(&vm->va, saddr, eaddr);
1287         if (it) {
1288                 struct amdgpu_bo_va_mapping *tmp;
1289                 tmp = container_of(it, struct amdgpu_bo_va_mapping, it);
1290                 /* bo and tmp overlap, invalid addr */
1291                 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
1292                         "0x%010lx-0x%010lx\n", bo_va->bo, saddr, eaddr,
1293                         tmp->it.start, tmp->it.last + 1);
1294                 r = -EINVAL;
1295                 goto error;
1296         }
1297
1298         mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1299         if (!mapping) {
1300                 r = -ENOMEM;
1301                 goto error;
1302         }
1303
1304         INIT_LIST_HEAD(&mapping->list);
1305         mapping->it.start = saddr;
1306         mapping->it.last = eaddr;
1307         mapping->offset = offset;
1308         mapping->flags = flags;
1309
1310         list_add(&mapping->list, &bo_va->invalids);
1311         interval_tree_insert(&mapping->it, &vm->va);
1312
1313         /* Make sure the page tables are allocated */
1314         saddr >>= amdgpu_vm_block_size;
1315         eaddr >>= amdgpu_vm_block_size;
1316
1317         BUG_ON(eaddr >= amdgpu_vm_num_pdes(adev));
1318
1319         if (eaddr > vm->max_pde_used)
1320                 vm->max_pde_used = eaddr;
1321
1322         /* walk over the address space and allocate the page tables */
1323         for (pt_idx = saddr; pt_idx <= eaddr; ++pt_idx) {
1324                 struct reservation_object *resv = vm->page_directory->tbo.resv;
1325                 struct amdgpu_bo_list_entry *entry;
1326                 struct amdgpu_bo *pt;
1327
1328                 entry = &vm->page_tables[pt_idx].entry;
1329                 if (entry->robj)
1330                         continue;
1331
1332                 r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8,
1333                                      AMDGPU_GPU_PAGE_SIZE, true,
1334                                      AMDGPU_GEM_DOMAIN_VRAM,
1335                                      AMDGPU_GEM_CREATE_NO_CPU_ACCESS,
1336                                      NULL, resv, &pt);
1337                 if (r)
1338                         goto error_free;
1339
1340                 /* Keep a reference to the page table to avoid freeing
1341                  * them up in the wrong order.
1342                  */
1343                 pt->parent = amdgpu_bo_ref(vm->page_directory);
1344
1345                 r = amdgpu_vm_clear_bo(adev, vm, pt);
1346                 if (r) {
1347                         amdgpu_bo_unref(&pt);
1348                         goto error_free;
1349                 }
1350
1351                 entry->robj = pt;
1352                 entry->priority = 0;
1353                 entry->tv.bo = &entry->robj->tbo;
1354                 entry->tv.shared = true;
1355                 entry->user_pages = NULL;
1356                 vm->page_tables[pt_idx].addr = 0;
1357         }
1358
1359         return 0;
1360
1361 error_free:
1362         list_del(&mapping->list);
1363         interval_tree_remove(&mapping->it, &vm->va);
1364         trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1365         kfree(mapping);
1366
1367 error:
1368         return r;
1369 }
1370
1371 /**
1372  * amdgpu_vm_bo_unmap - remove bo mapping from vm
1373  *
1374  * @adev: amdgpu_device pointer
1375  * @bo_va: bo_va to remove the address from
1376  * @saddr: where to the BO is mapped
1377  *
1378  * Remove a mapping of the BO at the specefied addr from the VM.
1379  * Returns 0 for success, error for failure.
1380  *
1381  * Object has to be reserved and unreserved outside!
1382  */
1383 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
1384                        struct amdgpu_bo_va *bo_va,
1385                        uint64_t saddr)
1386 {
1387         struct amdgpu_bo_va_mapping *mapping;
1388         struct amdgpu_vm *vm = bo_va->vm;
1389         bool valid = true;
1390
1391         saddr /= AMDGPU_GPU_PAGE_SIZE;
1392
1393         list_for_each_entry(mapping, &bo_va->valids, list) {
1394                 if (mapping->it.start == saddr)
1395                         break;
1396         }
1397
1398         if (&mapping->list == &bo_va->valids) {
1399                 valid = false;
1400
1401                 list_for_each_entry(mapping, &bo_va->invalids, list) {
1402                         if (mapping->it.start == saddr)
1403                                 break;
1404                 }
1405
1406                 if (&mapping->list == &bo_va->invalids)
1407                         return -ENOENT;
1408         }
1409
1410         list_del(&mapping->list);
1411         interval_tree_remove(&mapping->it, &vm->va);
1412         trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1413
1414         if (valid)
1415                 list_add(&mapping->list, &vm->freed);
1416         else
1417                 kfree(mapping);
1418
1419         return 0;
1420 }
1421
1422 /**
1423  * amdgpu_vm_bo_rmv - remove a bo to a specific vm
1424  *
1425  * @adev: amdgpu_device pointer
1426  * @bo_va: requested bo_va
1427  *
1428  * Remove @bo_va->bo from the requested vm.
1429  *
1430  * Object have to be reserved!
1431  */
1432 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
1433                       struct amdgpu_bo_va *bo_va)
1434 {
1435         struct amdgpu_bo_va_mapping *mapping, *next;
1436         struct amdgpu_vm *vm = bo_va->vm;
1437
1438         list_del(&bo_va->bo_list);
1439
1440         spin_lock(&vm->status_lock);
1441         list_del(&bo_va->vm_status);
1442         spin_unlock(&vm->status_lock);
1443
1444         list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
1445                 list_del(&mapping->list);
1446                 interval_tree_remove(&mapping->it, &vm->va);
1447                 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1448                 list_add(&mapping->list, &vm->freed);
1449         }
1450         list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
1451                 list_del(&mapping->list);
1452                 interval_tree_remove(&mapping->it, &vm->va);
1453                 kfree(mapping);
1454         }
1455
1456         fence_put(bo_va->last_pt_update);
1457         kfree(bo_va);
1458 }
1459
1460 /**
1461  * amdgpu_vm_bo_invalidate - mark the bo as invalid
1462  *
1463  * @adev: amdgpu_device pointer
1464  * @vm: requested vm
1465  * @bo: amdgpu buffer object
1466  *
1467  * Mark @bo as invalid.
1468  */
1469 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
1470                              struct amdgpu_bo *bo)
1471 {
1472         struct amdgpu_bo_va *bo_va;
1473
1474         list_for_each_entry(bo_va, &bo->va, bo_list) {
1475                 spin_lock(&bo_va->vm->status_lock);
1476                 if (list_empty(&bo_va->vm_status))
1477                         list_add(&bo_va->vm_status, &bo_va->vm->invalidated);
1478                 spin_unlock(&bo_va->vm->status_lock);
1479         }
1480 }
1481
1482 /**
1483  * amdgpu_vm_init - initialize a vm instance
1484  *
1485  * @adev: amdgpu_device pointer
1486  * @vm: requested vm
1487  *
1488  * Init @vm fields.
1489  */
1490 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1491 {
1492         const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
1493                 AMDGPU_VM_PTE_COUNT * 8);
1494         unsigned pd_size, pd_entries;
1495         unsigned ring_instance;
1496         struct amdgpu_ring *ring;
1497         struct amd_sched_rq *rq;
1498         int i, r;
1499
1500         for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
1501                 vm->ids[i] = NULL;
1502         vm->va = RB_ROOT;
1503         vm->client_id = atomic64_inc_return(&adev->vm_manager.client_counter);
1504         spin_lock_init(&vm->status_lock);
1505         INIT_LIST_HEAD(&vm->invalidated);
1506         INIT_LIST_HEAD(&vm->cleared);
1507         INIT_LIST_HEAD(&vm->freed);
1508
1509         pd_size = amdgpu_vm_directory_size(adev);
1510         pd_entries = amdgpu_vm_num_pdes(adev);
1511
1512         /* allocate page table array */
1513         vm->page_tables = drm_calloc_large(pd_entries, sizeof(struct amdgpu_vm_pt));
1514         if (vm->page_tables == NULL) {
1515                 DRM_ERROR("Cannot allocate memory for page table array\n");
1516                 return -ENOMEM;
1517         }
1518
1519         /* create scheduler entity for page table updates */
1520
1521         ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring);
1522         ring_instance %= adev->vm_manager.vm_pte_num_rings;
1523         ring = adev->vm_manager.vm_pte_rings[ring_instance];
1524         rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
1525         r = amd_sched_entity_init(&ring->sched, &vm->entity,
1526                                   rq, amdgpu_sched_jobs);
1527         if (r)
1528                 return r;
1529
1530         vm->page_directory_fence = NULL;
1531
1532         r = amdgpu_bo_create(adev, pd_size, align, true,
1533                              AMDGPU_GEM_DOMAIN_VRAM,
1534                              AMDGPU_GEM_CREATE_NO_CPU_ACCESS,
1535                              NULL, NULL, &vm->page_directory);
1536         if (r)
1537                 goto error_free_sched_entity;
1538
1539         r = amdgpu_bo_reserve(vm->page_directory, false);
1540         if (r)
1541                 goto error_free_page_directory;
1542
1543         r = amdgpu_vm_clear_bo(adev, vm, vm->page_directory);
1544         amdgpu_bo_unreserve(vm->page_directory);
1545         if (r)
1546                 goto error_free_page_directory;
1547         vm->last_eviction_counter = atomic64_read(&adev->num_evictions);
1548
1549         return 0;
1550
1551 error_free_page_directory:
1552         amdgpu_bo_unref(&vm->page_directory);
1553         vm->page_directory = NULL;
1554
1555 error_free_sched_entity:
1556         amd_sched_entity_fini(&ring->sched, &vm->entity);
1557
1558         return r;
1559 }
1560
1561 /**
1562  * amdgpu_vm_fini - tear down a vm instance
1563  *
1564  * @adev: amdgpu_device pointer
1565  * @vm: requested vm
1566  *
1567  * Tear down @vm.
1568  * Unbind the VM and remove all bos from the vm bo list
1569  */
1570 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1571 {
1572         struct amdgpu_bo_va_mapping *mapping, *tmp;
1573         int i;
1574
1575         amd_sched_entity_fini(vm->entity.sched, &vm->entity);
1576
1577         if (!RB_EMPTY_ROOT(&vm->va)) {
1578                 dev_err(adev->dev, "still active bo inside vm\n");
1579         }
1580         rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, it.rb) {
1581                 list_del(&mapping->list);
1582                 interval_tree_remove(&mapping->it, &vm->va);
1583                 kfree(mapping);
1584         }
1585         list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
1586                 list_del(&mapping->list);
1587                 kfree(mapping);
1588         }
1589
1590         for (i = 0; i < amdgpu_vm_num_pdes(adev); i++)
1591                 amdgpu_bo_unref(&vm->page_tables[i].entry.robj);
1592         drm_free_large(vm->page_tables);
1593
1594         amdgpu_bo_unref(&vm->page_directory);
1595         fence_put(vm->page_directory_fence);
1596 }
1597
1598 /**
1599  * amdgpu_vm_manager_init - init the VM manager
1600  *
1601  * @adev: amdgpu_device pointer
1602  *
1603  * Initialize the VM manager structures
1604  */
1605 void amdgpu_vm_manager_init(struct amdgpu_device *adev)
1606 {
1607         unsigned i;
1608
1609         INIT_LIST_HEAD(&adev->vm_manager.ids_lru);
1610
1611         /* skip over VMID 0, since it is the system VM */
1612         for (i = 1; i < adev->vm_manager.num_ids; ++i) {
1613                 amdgpu_vm_reset_id(adev, i);
1614                 amdgpu_sync_create(&adev->vm_manager.ids[i].active);
1615                 list_add_tail(&adev->vm_manager.ids[i].list,
1616                               &adev->vm_manager.ids_lru);
1617         }
1618
1619         adev->vm_manager.fence_context = fence_context_alloc(AMDGPU_MAX_RINGS);
1620         for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
1621                 adev->vm_manager.seqno[i] = 0;
1622
1623         atomic_set(&adev->vm_manager.vm_pte_next_ring, 0);
1624         atomic64_set(&adev->vm_manager.client_counter, 0);
1625 }
1626
1627 /**
1628  * amdgpu_vm_manager_fini - cleanup VM manager
1629  *
1630  * @adev: amdgpu_device pointer
1631  *
1632  * Cleanup the VM manager and free resources.
1633  */
1634 void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
1635 {
1636         unsigned i;
1637
1638         for (i = 0; i < AMDGPU_NUM_VM; ++i) {
1639                 struct amdgpu_vm_id *id = &adev->vm_manager.ids[i];
1640
1641                 fence_put(adev->vm_manager.ids[i].first);
1642                 amdgpu_sync_free(&adev->vm_manager.ids[i].active);
1643                 fence_put(id->flushed_updates);
1644         }
1645 }