drivers/gpu/drm/amd/amdgpu/atombios_crtc.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include <drm/amdgpu_drm.h>
  29 #include <drm/drm_fixed.h>
  30 #include "amdgpu.h"
  31 #include "atom.h"
  32 #include "atom-bits.h"
  33 #include "atombios_encoders.h"
  34 #include "amdgpu_atombios.h"
  35 #include "amdgpu_pll.h"
  36 #include "amdgpu_connectors.h"
  37
  38 void amdgpu_atombios_crtc_overscan_setup(struct drm_crtc *crtc,
  39                                   struct drm_display_mode *mode,
  40                                   struct drm_display_mode *adjusted_mode)
  41 {
  42         struct drm_device *dev = crtc->dev;
  43         struct amdgpu_device *adev = dev->dev_private;
  44         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  45         SET_CRTC_OVERSCAN_PS_ALLOCATION args;
  46         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
  47         int a1, a2;
  48
  49         memset(&args, 0, sizeof(args));
  50
  51         args.ucCRTC = amdgpu_crtc->crtc_id;
  52
  53         switch (amdgpu_crtc->rmx_type) {
  54         case RMX_CENTER:
  55                 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
  56                 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
  57                 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
  58                 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
  59                 break;
  60         case RMX_ASPECT:
  61                 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
  62                 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
  63
  64                 if (a1 > a2) {
  65                         args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
  66                         args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
  67                 } else if (a2 > a1) {
  68                         args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
  69                         args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
  70                 }
  71                 break;
  72         case RMX_FULL:
  73         default:
  74                 args.usOverscanRight = cpu_to_le16(amdgpu_crtc->h_border);
  75                 args.usOverscanLeft = cpu_to_le16(amdgpu_crtc->h_border);
  76                 args.usOverscanBottom = cpu_to_le16(amdgpu_crtc->v_border);
  77                 args.usOverscanTop = cpu_to_le16(amdgpu_crtc->v_border);
  78                 break;
  79         }
  80         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
  81 }
  82
  83 void amdgpu_atombios_crtc_scaler_setup(struct drm_crtc *crtc)
  84 {
  85         struct drm_device *dev = crtc->dev;
  86         struct amdgpu_device *adev = dev->dev_private;
  87         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  88         ENABLE_SCALER_PS_ALLOCATION args;
  89         int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
  90
  91         memset(&args, 0, sizeof(args));
  92
  93         args.ucScaler = amdgpu_crtc->crtc_id;
  94
  95         switch (amdgpu_crtc->rmx_type) {
  96         case RMX_FULL:
  97                 args.ucEnable = ATOM_SCALER_EXPANSION;
  98                 break;
  99         case RMX_CENTER:
 100                 args.ucEnable = ATOM_SCALER_CENTER;
 101                 break;
 102         case RMX_ASPECT:
 103                 args.ucEnable = ATOM_SCALER_EXPANSION;
 104                 break;
 105         default:
 106                 args.ucEnable = ATOM_SCALER_DISABLE;
 107                 break;
 108         }
 109         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
 110 }
 111
 112 void amdgpu_atombios_crtc_lock(struct drm_crtc *crtc, int lock)
 113 {
 114         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 115         struct drm_device *dev = crtc->dev;
 116         struct amdgpu_device *adev = dev->dev_private;
 117         int index =
 118             GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
 119         ENABLE_CRTC_PS_ALLOCATION args;
 120
 121         memset(&args, 0, sizeof(args));
 122
 123         args.ucCRTC = amdgpu_crtc->crtc_id;
 124         args.ucEnable = lock;
 125
 126         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
 127 }
 128
 129 void amdgpu_atombios_crtc_enable(struct drm_crtc *crtc, int state)
 130 {
 131         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 132         struct drm_device *dev = crtc->dev;
 133         struct amdgpu_device *adev = dev->dev_private;
 134         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
 135         ENABLE_CRTC_PS_ALLOCATION args;
 136
 137         memset(&args, 0, sizeof(args));
 138
 139         args.ucCRTC = amdgpu_crtc->crtc_id;
 140         args.ucEnable = state;
 141
 142         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
 143 }
 144
 145 void amdgpu_atombios_crtc_blank(struct drm_crtc *crtc, int state)
 146 {
 147         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 148         struct drm_device *dev = crtc->dev;
 149         struct amdgpu_device *adev = dev->dev_private;
 150         int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
 151         BLANK_CRTC_PS_ALLOCATION args;
 152
 153         memset(&args, 0, sizeof(args));
 154
 155         args.ucCRTC = amdgpu_crtc->crtc_id;
 156         args.ucBlanking = state;
 157
 158         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
 159 }
 160
 161 void amdgpu_atombios_crtc_powergate(struct drm_crtc *crtc, int state)
 162 {
 163         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 164         struct drm_device *dev = crtc->dev;
 165         struct amdgpu_device *adev = dev->dev_private;
 166         int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
 167         ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
 168
 169         memset(&args, 0, sizeof(args));
 170
 171         args.ucDispPipeId = amdgpu_crtc->crtc_id;
 172         args.ucEnable = state;
 173
 174         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
 175 }
 176
 177 void amdgpu_atombios_crtc_powergate_init(struct amdgpu_device *adev)
 178 {
 179         int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
 180         ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
 181
 182         memset(&args, 0, sizeof(args));
 183
 184         args.ucEnable = ATOM_INIT;
 185
 186         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
 187 }
 188
 189 void amdgpu_atombios_crtc_set_dtd_timing(struct drm_crtc *crtc,
 190                                   struct drm_display_mode *mode)
 191 {
 192         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 193         struct drm_device *dev = crtc->dev;
 194         struct amdgpu_device *adev = dev->dev_private;
 195         SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
 196         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
 197         u16 misc = 0;
 198
 199         memset(&args, 0, sizeof(args));
 200         args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (amdgpu_crtc->h_border * 2));
 201         args.usH_Blanking_Time =
 202                 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (amdgpu_crtc->h_border * 2));
 203         args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (amdgpu_crtc->v_border * 2));
 204         args.usV_Blanking_Time =
 205                 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (amdgpu_crtc->v_border * 2));
 206         args.usH_SyncOffset =
 207                 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + amdgpu_crtc->h_border);
 208         args.usH_SyncWidth =
 209                 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
 210         args.usV_SyncOffset =
 211                 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + amdgpu_crtc->v_border);
 212         args.usV_SyncWidth =
 213                 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
 214         args.ucH_Border = amdgpu_crtc->h_border;
 215         args.ucV_Border = amdgpu_crtc->v_border;
 216
 217         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 218                 misc |= ATOM_VSYNC_POLARITY;
 219         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 220                 misc |= ATOM_HSYNC_POLARITY;
 221         if (mode->flags & DRM_MODE_FLAG_CSYNC)
 222                 misc |= ATOM_COMPOSITESYNC;
 223         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 224                 misc |= ATOM_INTERLACE;
 225         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 226                 misc |= ATOM_DOUBLE_CLOCK_MODE;
 227
 228         args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
 229         args.ucCRTC = amdgpu_crtc->crtc_id;
 230
 231         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
 232 }
 233
 234 union atom_enable_ss {
 235         ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
 236         ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
 237         ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
 238 };
 239
 240 static void amdgpu_atombios_crtc_program_ss(struct amdgpu_device *adev,
 241                                      int enable,
 242                                      int pll_id,
 243                                      int crtc_id,
 244                                      struct amdgpu_atom_ss *ss)
 245 {
 246         unsigned i;
 247         int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
 248         union atom_enable_ss args;
 249
 250         if (enable) {
 251                 /* Don't mess with SS if percentage is 0 or external ss.
 252                  * SS is already disabled previously, and disabling it
 253                  * again can cause display problems if the pll is already
 254                  * programmed.
 255                  */
 256                 if (ss->percentage == 0)
 257                         return;
 258                 if (ss->type & ATOM_EXTERNAL_SS_MASK)
 259                         return;
 260         } else {
 261                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
 262                         if (adev->mode_info.crtcs[i] &&
 263                             adev->mode_info.crtcs[i]->enabled &&
 264                             i != crtc_id &&
 265                             pll_id == adev->mode_info.crtcs[i]->pll_id) {
 266                                 /* one other crtc is using this pll don't turn
 267                                  * off spread spectrum as it might turn off
 268                                  * display on active crtc
 269                                  */
 270                                 return;
 271                         }
 272                 }
 273         }
 274
 275         memset(&args, 0, sizeof(args));
 276
 277         args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
 278         args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 279         switch (pll_id) {
 280         case ATOM_PPLL1:
 281                 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
 282                 break;
 283         case ATOM_PPLL2:
 284                 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
 285                 break;
 286         case ATOM_DCPLL:
 287                 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
 288                 break;
 289         case ATOM_PPLL_INVALID:
 290                 return;
 291         }
 292         args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
 293         args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
 294         args.v3.ucEnable = enable;
 295
 296         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
 297 }
 298
 299 union adjust_pixel_clock {
 300         ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
 301         ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
 302 };
 303
 304 static u32 amdgpu_atombios_crtc_adjust_pll(struct drm_crtc *crtc,
 305                                     struct drm_display_mode *mode)
 306 {
 307         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 308         struct drm_device *dev = crtc->dev;
 309         struct amdgpu_device *adev = dev->dev_private;
 310         struct drm_encoder *encoder = amdgpu_crtc->encoder;
 311         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 312         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
 313         u32 adjusted_clock = mode->clock;
 314         int encoder_mode = amdgpu_atombios_encoder_get_encoder_mode(encoder);
 315         u32 dp_clock = mode->clock;
 316         u32 clock = mode->clock;
 317         int bpc = amdgpu_crtc->bpc;
 318         bool is_duallink = amdgpu_dig_monitor_is_duallink(encoder, mode->clock);
 319         union adjust_pixel_clock args;
 320         u8 frev, crev;
 321         int index;
 322
 323         amdgpu_crtc->pll_flags = AMDGPU_PLL_USE_FRAC_FB_DIV;
 324
 325         if ((amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
 326             (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
 327                 if (connector) {
 328                         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 329                         struct amdgpu_connector_atom_dig *dig_connector =
 330                                 amdgpu_connector->con_priv;
 331
 332                         dp_clock = dig_connector->dp_clock;
 333                 }
 334         }
 335
 336         /* use recommended ref_div for ss */
 337         if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 338                 if (amdgpu_crtc->ss_enabled) {
 339                         if (amdgpu_crtc->ss.refdiv) {
 340                                 amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_REF_DIV;
 341                                 amdgpu_crtc->pll_reference_div = amdgpu_crtc->ss.refdiv;
 342                                 amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_FRAC_FB_DIV;
 343                         }
 344                 }
 345         }
 346
 347         /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
 348         if (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
 349                 adjusted_clock = mode->clock * 2;
 350         if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
 351                 amdgpu_crtc->pll_flags |= AMDGPU_PLL_PREFER_CLOSEST_LOWER;
 352         if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 353                 amdgpu_crtc->pll_flags |= AMDGPU_PLL_IS_LCD;
 354
 355
 356         /* adjust pll for deep color modes */
 357         if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
 358                 switch (bpc) {
 359                 case 8:
 360                 default:
 361                         break;
 362                 case 10:
 363                         clock = (clock * 5) / 4;
 364                         break;
 365                 case 12:
 366                         clock = (clock * 3) / 2;
 367                         break;
 368                 case 16:
 369                         clock = clock * 2;
 370                         break;
 371                 }
 372         }
 373
 374         /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
 375          * accordingly based on the encoder/transmitter to work around
 376          * special hw requirements.
 377          */
 378         index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
 379         if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev,
 380                                    &crev))
 381                 return adjusted_clock;
 382
 383         memset(&args, 0, sizeof(args));
 384
 385         switch (frev) {
 386         case 1:
 387                 switch (crev) {
 388                 case 1:
 389                 case 2:
 390                         args.v1.usPixelClock = cpu_to_le16(clock / 10);
 391                         args.v1.ucTransmitterID = amdgpu_encoder->encoder_id;
 392                         args.v1.ucEncodeMode = encoder_mode;
 393                         if (amdgpu_crtc->ss_enabled && amdgpu_crtc->ss.percentage)
 394                                 args.v1.ucConfig |=
 395                                         ADJUST_DISPLAY_CONFIG_SS_ENABLE;
 396
 397                         amdgpu_atom_execute_table(adev->mode_info.atom_context,
 398                                            index, (uint32_t *)&args);
 399                         adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
 400                         break;
 401                 case 3:
 402                         args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10);
 403                         args.v3.sInput.ucTransmitterID = amdgpu_encoder->encoder_id;
 404                         args.v3.sInput.ucEncodeMode = encoder_mode;
 405                         args.v3.sInput.ucDispPllConfig = 0;
 406                         if (amdgpu_crtc->ss_enabled && amdgpu_crtc->ss.percentage)
 407                                 args.v3.sInput.ucDispPllConfig |=
 408                                         DISPPLL_CONFIG_SS_ENABLE;
 409                         if (ENCODER_MODE_IS_DP(encoder_mode)) {
 410                                 args.v3.sInput.ucDispPllConfig |=
 411                                         DISPPLL_CONFIG_COHERENT_MODE;
 412                                 /* 16200 or 27000 */
 413                                 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
 414                         } else if (amdgpu_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 415                                 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
 416                                 if (dig->coherent_mode)
 417                                         args.v3.sInput.ucDispPllConfig |=
 418                                                 DISPPLL_CONFIG_COHERENT_MODE;
 419                                 if (is_duallink)
 420                                         args.v3.sInput.ucDispPllConfig |=
 421                                                 DISPPLL_CONFIG_DUAL_LINK;
 422                         }
 423                         if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
 424                             ENCODER_OBJECT_ID_NONE)
 425                                 args.v3.sInput.ucExtTransmitterID =
 426                                         amdgpu_encoder_get_dp_bridge_encoder_id(encoder);
 427                         else
 428                                 args.v3.sInput.ucExtTransmitterID = 0;
 429
 430                         amdgpu_atom_execute_table(adev->mode_info.atom_context,
 431                                            index, (uint32_t *)&args);
 432                         adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
 433                         if (args.v3.sOutput.ucRefDiv) {
 434                                 amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_FRAC_FB_DIV;
 435                                 amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_REF_DIV;
 436                                 amdgpu_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv;
 437                         }
 438                         if (args.v3.sOutput.ucPostDiv) {
 439                                 amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_FRAC_FB_DIV;
 440                                 amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_POST_DIV;
 441                                 amdgpu_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;
 442                         }
 443                         break;
 444                 default:
 445                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 446                         return adjusted_clock;
 447                 }
 448                 break;
 449         default:
 450                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 451                 return adjusted_clock;
 452         }
 453
 454         return adjusted_clock;
 455 }
 456
 457 union set_pixel_clock {
 458         SET_PIXEL_CLOCK_PS_ALLOCATION base;
 459         PIXEL_CLOCK_PARAMETERS v1;
 460         PIXEL_CLOCK_PARAMETERS_V2 v2;
 461         PIXEL_CLOCK_PARAMETERS_V3 v3;
 462         PIXEL_CLOCK_PARAMETERS_V5 v5;
 463         PIXEL_CLOCK_PARAMETERS_V6 v6;
 464         PIXEL_CLOCK_PARAMETERS_V7 v7;
 465 };
 466
 467 /* on DCE5, make sure the voltage is high enough to support the
 468  * required disp clk.
 469  */
 470 void amdgpu_atombios_crtc_set_disp_eng_pll(struct amdgpu_device *adev,
 471                                            u32 dispclk)
 472 {
 473         u8 frev, crev;
 474         int index;
 475         union set_pixel_clock args;
 476
 477         memset(&args, 0, sizeof(args));
 478
 479         index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
 480         if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev,
 481                                    &crev))
 482                 return;
 483
 484         switch (frev) {
 485         case 1:
 486                 switch (crev) {
 487                 case 5:
 488                         /* if the default dcpll clock is specified,
 489                          * SetPixelClock provides the dividers
 490                          */
 491                         args.v5.ucCRTC = ATOM_CRTC_INVALID;
 492                         args.v5.usPixelClock = cpu_to_le16(dispclk);
 493                         args.v5.ucPpll = ATOM_DCPLL;
 494                         break;
 495                 case 6:
 496                         /* if the default dcpll clock is specified,
 497                          * SetPixelClock provides the dividers
 498                          */
 499                         args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
 500                         args.v6.ucPpll = ATOM_EXT_PLL1;
 501                         break;
 502                 default:
 503                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 504                         return;
 505                 }
 506                 break;
 507         default:
 508                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 509                 return;
 510         }
 511         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
 512 }
 513
 514 union set_dce_clock {
 515         SET_DCE_CLOCK_PS_ALLOCATION_V1_1 v1_1;
 516         SET_DCE_CLOCK_PS_ALLOCATION_V2_1 v2_1;
 517 };
 518
 519 u32 amdgpu_atombios_crtc_set_dce_clock(struct amdgpu_device *adev,
 520                                        u32 freq, u8 clk_type, u8 clk_src)
 521 {
 522         u8 frev, crev;
 523         int index;
 524         union set_dce_clock args;
 525         u32 ret_freq = 0;
 526
 527         memset(&args, 0, sizeof(args));
 528
 529         index = GetIndexIntoMasterTable(COMMAND, SetDCEClock);
 530         if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev,
 531                                    &crev))
 532                 return 0;
 533
 534         switch (frev) {
 535         case 2:
 536                 switch (crev) {
 537                 case 1:
 538                         args.v2_1.asParam.ulDCEClkFreq = cpu_to_le32(freq); /* 10kHz units */
 539                         args.v2_1.asParam.ucDCEClkType = clk_type;
 540                         args.v2_1.asParam.ucDCEClkSrc = clk_src;
 541                         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
 542                         ret_freq = le32_to_cpu(args.v2_1.asParam.ulDCEClkFreq) * 10;
 543                         break;
 544                 default:
 545                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 546                         return 0;
 547                 }
 548                 break;
 549         default:
 550                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 551                 return 0;
 552         }
 553
 554         return ret_freq;
 555 }
 556
 557 static bool is_pixel_clock_source_from_pll(u32 encoder_mode, int pll_id)
 558 {
 559         if (ENCODER_MODE_IS_DP(encoder_mode)) {
 560                 if (pll_id < ATOM_EXT_PLL1)
 561                         return true;
 562                 else
 563                         return false;
 564         } else {
 565                 return true;
 566         }
 567 }
 568
 569 void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc,
 570                                       u32 crtc_id,
 571                                       int pll_id,
 572                                       u32 encoder_mode,
 573                                       u32 encoder_id,
 574                                       u32 clock,
 575                                       u32 ref_div,
 576                                       u32 fb_div,
 577                                       u32 frac_fb_div,
 578                                       u32 post_div,
 579                                       int bpc,
 580                                       bool ss_enabled,
 581                                       struct amdgpu_atom_ss *ss)
 582 {
 583         struct drm_device *dev = crtc->dev;
 584         struct amdgpu_device *adev = dev->dev_private;
 585         u8 frev, crev;
 586         int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
 587         union set_pixel_clock args;
 588
 589         memset(&args, 0, sizeof(args));
 590
 591         if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev,
 592                                    &crev))
 593                 return;
 594
 595         switch (frev) {
 596         case 1:
 597                 switch (crev) {
 598                 case 1:
 599                         if (clock == ATOM_DISABLE)
 600                                 return;
 601                         args.v1.usPixelClock = cpu_to_le16(clock / 10);
 602                         args.v1.usRefDiv = cpu_to_le16(ref_div);
 603                         args.v1.usFbDiv = cpu_to_le16(fb_div);
 604                         args.v1.ucFracFbDiv = frac_fb_div;
 605                         args.v1.ucPostDiv = post_div;
 606                         args.v1.ucPpll = pll_id;
 607                         args.v1.ucCRTC = crtc_id;
 608                         args.v1.ucRefDivSrc = 1;
 609                         break;
 610                 case 2:
 611                         args.v2.usPixelClock = cpu_to_le16(clock / 10);
 612                         args.v2.usRefDiv = cpu_to_le16(ref_div);
 613                         args.v2.usFbDiv = cpu_to_le16(fb_div);
 614                         args.v2.ucFracFbDiv = frac_fb_div;
 615                         args.v2.ucPostDiv = post_div;
 616                         args.v2.ucPpll = pll_id;
 617                         args.v2.ucCRTC = crtc_id;
 618                         args.v2.ucRefDivSrc = 1;
 619                         break;
 620                 case 3:
 621                         args.v3.usPixelClock = cpu_to_le16(clock / 10);
 622                         args.v3.usRefDiv = cpu_to_le16(ref_div);
 623                         args.v3.usFbDiv = cpu_to_le16(fb_div);
 624                         args.v3.ucFracFbDiv = frac_fb_div;
 625                         args.v3.ucPostDiv = post_div;
 626                         args.v3.ucPpll = pll_id;
 627                         if (crtc_id == ATOM_CRTC2)
 628                                 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2;
 629                         else
 630                                 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1;
 631                         if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
 632                                 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
 633                         args.v3.ucTransmitterId = encoder_id;
 634                         args.v3.ucEncoderMode = encoder_mode;
 635                         break;
 636                 case 5:
 637                         args.v5.ucCRTC = crtc_id;
 638                         args.v5.usPixelClock = cpu_to_le16(clock / 10);
 639                         args.v5.ucRefDiv = ref_div;
 640                         args.v5.usFbDiv = cpu_to_le16(fb_div);
 641                         args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
 642                         args.v5.ucPostDiv = post_div;
 643                         args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
 644                         if ((ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) &&
 645                             (pll_id < ATOM_EXT_PLL1))
 646                                 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
 647                         if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
 648                                 switch (bpc) {
 649                                 case 8:
 650                                 default:
 651                                         args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
 652                                         break;
 653                                 case 10:
 654                                         /* yes this is correct, the atom define is wrong */
 655                                         args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_32BPP;
 656                                         break;
 657                                 case 12:
 658                                         /* yes this is correct, the atom define is wrong */
 659                                         args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
 660                                         break;
 661                                 }
 662                         }
 663                         args.v5.ucTransmitterID = encoder_id;
 664                         args.v5.ucEncoderMode = encoder_mode;
 665                         args.v5.ucPpll = pll_id;
 666                         break;
 667                 case 6:
 668                         args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
 669                         args.v6.ucRefDiv = ref_div;
 670                         args.v6.usFbDiv = cpu_to_le16(fb_div);
 671                         args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
 672                         args.v6.ucPostDiv = post_div;
 673                         args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
 674                         if ((ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) &&
 675                             (pll_id < ATOM_EXT_PLL1) &&
 676                             !is_pixel_clock_source_from_pll(encoder_mode, pll_id))
 677                                 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
 678                         if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
 679                                 switch (bpc) {
 680                                 case 8:
 681                                 default:
 682                                         args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
 683                                         break;
 684                                 case 10:
 685                                         args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6;
 686                                         break;
 687                                 case 12:
 688                                         args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6;
 689                                         break;
 690                                 case 16:
 691                                         args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
 692                                         break;
 693                                 }
 694                         }
 695                         args.v6.ucTransmitterID = encoder_id;
 696                         args.v6.ucEncoderMode = encoder_mode;
 697                         args.v6.ucPpll = pll_id;
 698                         break;
 699                 case 7:
 700                         args.v7.ulPixelClock = cpu_to_le32(clock * 10); /* 100 hz units */
 701                         args.v7.ucMiscInfo = 0;
 702                         if ((encoder_mode == ATOM_ENCODER_MODE_DVI) &&
 703                             (clock > 165000))
 704                                 args.v7.ucMiscInfo |= PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN;
 705                         args.v7.ucCRTC = crtc_id;
 706                         if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
 707                                 switch (bpc) {
 708                                 case 8:
 709                                 default:
 710                                         args.v7.ucDeepColorRatio = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS;
 711                                         break;
 712                                 case 10:
 713                                         args.v7.ucDeepColorRatio = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4;
 714                                         break;
 715                                 case 12:
 716                                         args.v7.ucDeepColorRatio = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2;
 717                                         break;
 718                                 case 16:
 719                                         args.v7.ucDeepColorRatio = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1;
 720                                         break;
 721                                 }
 722                         }
 723                         args.v7.ucTransmitterID = encoder_id;
 724                         args.v7.ucEncoderMode = encoder_mode;
 725                         args.v7.ucPpll = pll_id;
 726                         break;
 727                 default:
 728                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 729                         return;
 730                 }
 731                 break;
 732         default:
 733                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 734                 return;
 735         }
 736
 737         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
 738 }
 739
 740 int amdgpu_atombios_crtc_prepare_pll(struct drm_crtc *crtc,
 741                               struct drm_display_mode *mode)
 742 {
 743         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 744         struct drm_device *dev = crtc->dev;
 745         struct amdgpu_device *adev = dev->dev_private;
 746         struct amdgpu_encoder *amdgpu_encoder =
 747                 to_amdgpu_encoder(amdgpu_crtc->encoder);
 748         int encoder_mode = amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder);
 749
 750         amdgpu_crtc->bpc = 8;
 751         amdgpu_crtc->ss_enabled = false;
 752
 753         if ((amdgpu_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
 754             (amdgpu_encoder_get_dp_bridge_encoder_id(amdgpu_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) {
 755                 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
 756                 struct drm_connector *connector =
 757                         amdgpu_get_connector_for_encoder(amdgpu_crtc->encoder);
 758                 struct amdgpu_connector *amdgpu_connector =
 759                         to_amdgpu_connector(connector);
 760                 struct amdgpu_connector_atom_dig *dig_connector =
 761                         amdgpu_connector->con_priv;
 762                 int dp_clock;
 763
 764                 /* Assign mode clock for hdmi deep color max clock limit check */
 765                 amdgpu_connector->pixelclock_for_modeset = mode->clock;
 766                 amdgpu_crtc->bpc = amdgpu_connector_get_monitor_bpc(connector);
 767
 768                 switch (encoder_mode) {
 769                 case ATOM_ENCODER_MODE_DP_MST:
 770                 case ATOM_ENCODER_MODE_DP:
 771                         /* DP/eDP */
 772                         dp_clock = dig_connector->dp_clock / 10;
 773                         amdgpu_crtc->ss_enabled =
 774                                 amdgpu_atombios_get_asic_ss_info(adev, &amdgpu_crtc->ss,
 775                                                                  ASIC_INTERNAL_SS_ON_DP,
 776                                                                  dp_clock);
 777                         break;
 778                 case ATOM_ENCODER_MODE_LVDS:
 779                         amdgpu_crtc->ss_enabled =
 780                                 amdgpu_atombios_get_asic_ss_info(adev,
 781                                                                  &amdgpu_crtc->ss,
 782                                                                  dig->lcd_ss_id,
 783                                                                  mode->clock / 10);
 784                         break;
 785                 case ATOM_ENCODER_MODE_DVI:
 786                         amdgpu_crtc->ss_enabled =
 787                                 amdgpu_atombios_get_asic_ss_info(adev,
 788                                                                  &amdgpu_crtc->ss,
 789                                                                  ASIC_INTERNAL_SS_ON_TMDS,
 790                                                                  mode->clock / 10);
 791                         break;
 792                 case ATOM_ENCODER_MODE_HDMI:
 793                         amdgpu_crtc->ss_enabled =
 794                                 amdgpu_atombios_get_asic_ss_info(adev,
 795                                                                  &amdgpu_crtc->ss,
 796                                                                  ASIC_INTERNAL_SS_ON_HDMI,
 797                                                                  mode->clock / 10);
 798                         break;
 799                 default:
 800                         break;
 801                 }
 802         }
 803
 804         /* adjust pixel clock as needed */
 805         amdgpu_crtc->adjusted_clock = amdgpu_atombios_crtc_adjust_pll(crtc, mode);
 806
 807         return 0;
 808 }
 809
 810 void amdgpu_atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 811 {
 812         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 813         struct drm_device *dev = crtc->dev;
 814         struct amdgpu_device *adev = dev->dev_private;
 815         struct amdgpu_encoder *amdgpu_encoder =
 816                 to_amdgpu_encoder(amdgpu_crtc->encoder);
 817         u32 pll_clock = mode->clock;
 818         u32 clock = mode->clock;
 819         u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
 820         struct amdgpu_pll *pll;
 821         int encoder_mode = amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder);
 822
 823         /* pass the actual clock to amdgpu_atombios_crtc_program_pll for HDMI */
 824         if ((encoder_mode == ATOM_ENCODER_MODE_HDMI) &&
 825             (amdgpu_crtc->bpc > 8))
 826                 clock = amdgpu_crtc->adjusted_clock;
 827
 828         switch (amdgpu_crtc->pll_id) {
 829         case ATOM_PPLL1:
 830                 pll = &adev->clock.ppll[0];
 831                 break;
 832         case ATOM_PPLL2:
 833                 pll = &adev->clock.ppll[1];
 834                 break;
 835         case ATOM_PPLL0:
 836         case ATOM_PPLL_INVALID:
 837         default:
 838                 pll = &adev->clock.ppll[2];
 839                 break;
 840         }
 841
 842         /* update pll params */
 843         pll->flags = amdgpu_crtc->pll_flags;
 844         pll->reference_div = amdgpu_crtc->pll_reference_div;
 845         pll->post_div = amdgpu_crtc->pll_post_div;
 846
 847         amdgpu_pll_compute(pll, amdgpu_crtc->adjusted_clock, &pll_clock,
 848                             &fb_div, &frac_fb_div, &ref_div, &post_div);
 849
 850         amdgpu_atombios_crtc_program_ss(adev, ATOM_DISABLE, amdgpu_crtc->pll_id,
 851                                  amdgpu_crtc->crtc_id, &amdgpu_crtc->ss);
 852
 853         amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
 854                                   encoder_mode, amdgpu_encoder->encoder_id, clock,
 855                                   ref_div, fb_div, frac_fb_div, post_div,
 856                                   amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss);
 857
 858         if (amdgpu_crtc->ss_enabled) {
 859                 /* calculate ss amount and step size */
 860                 u32 step_size;
 861                 u32 amount = (((fb_div * 10) + frac_fb_div) *
 862                               (u32)amdgpu_crtc->ss.percentage) /
 863                         (100 * (u32)amdgpu_crtc->ss.percentage_divider);
 864                 amdgpu_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
 865                 amdgpu_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
 866                         ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
 867                 if (amdgpu_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
 868                         step_size = (4 * amount * ref_div * ((u32)amdgpu_crtc->ss.rate * 2048)) /
 869                                 (125 * 25 * pll->reference_freq / 100);
 870                 else
 871                         step_size = (2 * amount * ref_div * ((u32)amdgpu_crtc->ss.rate * 2048)) /
 872                                 (125 * 25 * pll->reference_freq / 100);
 873                 amdgpu_crtc->ss.step = step_size;
 874
 875                 amdgpu_atombios_crtc_program_ss(adev, ATOM_ENABLE, amdgpu_crtc->pll_id,
 876                                          amdgpu_crtc->crtc_id, &amdgpu_crtc->ss);
 877         }
 878 }
 879