drivers/gpu/drm/amd/amdgpu/ci_dpm.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include "drmP.h"
  26 #include "amdgpu.h"
  27 #include "amdgpu_pm.h"
  28 #include "amdgpu_ucode.h"
  29 #include "cikd.h"
  30 #include "amdgpu_dpm.h"
  31 #include "ci_dpm.h"
  32 #include "gfx_v7_0.h"
  33 #include "atom.h"
  34 #include "amd_pcie.h"
  35 #include <linux/seq_file.h>
  36
  37 #include "smu/smu_7_0_1_d.h"
  38 #include "smu/smu_7_0_1_sh_mask.h"
  39
  40 #include "dce/dce_8_0_d.h"
  41 #include "dce/dce_8_0_sh_mask.h"
  42
  43 #include "bif/bif_4_1_d.h"
  44 #include "bif/bif_4_1_sh_mask.h"
  45
  46 #include "gca/gfx_7_2_d.h"
  47 #include "gca/gfx_7_2_sh_mask.h"
  48
  49 #include "gmc/gmc_7_1_d.h"
  50 #include "gmc/gmc_7_1_sh_mask.h"
  51
  52 MODULE_FIRMWARE("radeon/bonaire_smc.bin");
  53 MODULE_FIRMWARE("radeon/bonaire_k_smc.bin");
  54 MODULE_FIRMWARE("radeon/hawaii_smc.bin");
  55 MODULE_FIRMWARE("radeon/hawaii_k_smc.bin");
  56
  57 #define MC_CG_ARB_FREQ_F0           0x0a
  58 #define MC_CG_ARB_FREQ_F1           0x0b
  59 #define MC_CG_ARB_FREQ_F2           0x0c
  60 #define MC_CG_ARB_FREQ_F3           0x0d
  61
  62 #define SMC_RAM_END 0x40000
  63
  64 #define VOLTAGE_SCALE               4
  65 #define VOLTAGE_VID_OFFSET_SCALE1    625
  66 #define VOLTAGE_VID_OFFSET_SCALE2    100
  67
  68 static const struct ci_pt_defaults defaults_hawaii_xt =
  69 {
  70         1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
  71         { 0x2E,  0x00,  0x00,  0x88,  0x00,  0x00,  0x72,  0x60,  0x51,  0xA7,  0x79,  0x6B,  0x90,  0xBD,  0x79  },
  72         { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
  73 };
  74
  75 static const struct ci_pt_defaults defaults_hawaii_pro =
  76 {
  77         1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
  78         { 0x2E,  0x00,  0x00,  0x88,  0x00,  0x00,  0x72,  0x60,  0x51,  0xA7,  0x79,  0x6B,  0x90,  0xBD,  0x79  },
  79         { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
  80 };
  81
  82 static const struct ci_pt_defaults defaults_bonaire_xt =
  83 {
  84         1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
  85         { 0x79,  0x253, 0x25D, 0xAE,  0x72,  0x80,  0x83,  0x86,  0x6F,  0xC8,  0xC9,  0xC9,  0x2F,  0x4D,  0x61  },
  86         { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
  87 };
  88
  89 static const struct ci_pt_defaults defaults_bonaire_pro =
  90 {
  91         1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x65062,
  92         { 0x8C,  0x23F, 0x244, 0xA6,  0x83,  0x85,  0x86,  0x86,  0x83,  0xDB,  0xDB,  0xDA,  0x67,  0x60,  0x5F  },
  93         { 0x187, 0x193, 0x193, 0x1C7, 0x1D1, 0x1D1, 0x210, 0x219, 0x219, 0x266, 0x26C, 0x26C, 0x2C9, 0x2CB, 0x2CB }
  94 };
  95
  96 static const struct ci_pt_defaults defaults_saturn_xt =
  97 {
  98         1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000,
  99         { 0x8C,  0x247, 0x249, 0xA6,  0x80,  0x81,  0x8B,  0x89,  0x86,  0xC9,  0xCA,  0xC9,  0x4D,  0x4D,  0x4D  },
 100         { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 }
 101 };
 102
 103 static const struct ci_pt_defaults defaults_saturn_pro =
 104 {
 105         1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x30000,
 106         { 0x96,  0x21D, 0x23B, 0xA1,  0x85,  0x87,  0x83,  0x84,  0x81,  0xE6,  0xE6,  0xE6,  0x71,  0x6A,  0x6A  },
 107         { 0x193, 0x19E, 0x19E, 0x1D2, 0x1DC, 0x1DC, 0x21A, 0x223, 0x223, 0x26E, 0x27E, 0x274, 0x2CF, 0x2D2, 0x2D2 }
 108 };
 109
 110 static const struct ci_pt_config_reg didt_config_ci[] =
 111 {
 112         { 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 113         { 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 114         { 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 115         { 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 116         { 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 117         { 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 118         { 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 119         { 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 120         { 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 121         { 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 122         { 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 123         { 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 124         { 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 125         { 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 126         { 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 127         { 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 128         { 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 129         { 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 130         { 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 131         { 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 132         { 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 133         { 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 134         { 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 135         { 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 136         { 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 137         { 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 138         { 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 139         { 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 140         { 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 141         { 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 142         { 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 143         { 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 144         { 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 145         { 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 146         { 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 147         { 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 148         { 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 149         { 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 150         { 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 151         { 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 152         { 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 153         { 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 154         { 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 155         { 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 156         { 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 157         { 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 158         { 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 159         { 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 160         { 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 161         { 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 162         { 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 163         { 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 164         { 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 165         { 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 166         { 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 167         { 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 168         { 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 169         { 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 170         { 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 171         { 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 172         { 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 173         { 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 174         { 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 175         { 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 176         { 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 177         { 0x72, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 178         { 0x62, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 179         { 0x62, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 180         { 0x62, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 181         { 0x61, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 182         { 0x61, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 183         { 0x60, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 184         { 0xFFFFFFFF }
 185 };
 186
 187 static u8 ci_get_memory_module_index(struct amdgpu_device *adev)
 188 {
 189         return (u8) ((RREG32(mmBIOS_SCRATCH_4) >> 16) & 0xff);
 190 }
 191
 192 #define MC_CG_ARB_FREQ_F0           0x0a
 193 #define MC_CG_ARB_FREQ_F1           0x0b
 194 #define MC_CG_ARB_FREQ_F2           0x0c
 195 #define MC_CG_ARB_FREQ_F3           0x0d
 196
 197 static int ci_copy_and_switch_arb_sets(struct amdgpu_device *adev,
 198                                        u32 arb_freq_src, u32 arb_freq_dest)
 199 {
 200         u32 mc_arb_dram_timing;
 201         u32 mc_arb_dram_timing2;
 202         u32 burst_time;
 203         u32 mc_cg_config;
 204
 205         switch (arb_freq_src) {
 206         case MC_CG_ARB_FREQ_F0:
 207                 mc_arb_dram_timing  = RREG32(mmMC_ARB_DRAM_TIMING);
 208                 mc_arb_dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2);
 209                 burst_time = (RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE0_MASK) >>
 210                          MC_ARB_BURST_TIME__STATE0__SHIFT;
 211                 break;
 212         case MC_CG_ARB_FREQ_F1:
 213                 mc_arb_dram_timing  = RREG32(mmMC_ARB_DRAM_TIMING_1);
 214                 mc_arb_dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2_1);
 215                 burst_time = (RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE1_MASK) >>
 216                          MC_ARB_BURST_TIME__STATE1__SHIFT;
 217                 break;
 218         default:
 219                 return -EINVAL;
 220         }
 221
 222         switch (arb_freq_dest) {
 223         case MC_CG_ARB_FREQ_F0:
 224                 WREG32(mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
 225                 WREG32(mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
 226                 WREG32_P(mmMC_ARB_BURST_TIME, (burst_time << MC_ARB_BURST_TIME__STATE0__SHIFT),
 227                         ~MC_ARB_BURST_TIME__STATE0_MASK);
 228                 break;
 229         case MC_CG_ARB_FREQ_F1:
 230                 WREG32(mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
 231                 WREG32(mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
 232                 WREG32_P(mmMC_ARB_BURST_TIME, (burst_time << MC_ARB_BURST_TIME__STATE1__SHIFT),
 233                         ~MC_ARB_BURST_TIME__STATE1_MASK);
 234                 break;
 235         default:
 236                 return -EINVAL;
 237         }
 238
 239         mc_cg_config = RREG32(mmMC_CG_CONFIG) | 0x0000000F;
 240         WREG32(mmMC_CG_CONFIG, mc_cg_config);
 241         WREG32_P(mmMC_ARB_CG, (arb_freq_dest) << MC_ARB_CG__CG_ARB_REQ__SHIFT,
 242                 ~MC_ARB_CG__CG_ARB_REQ_MASK);
 243
 244         return 0;
 245 }
 246
 247 static u8 ci_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
 248 {
 249         u8 mc_para_index;
 250
 251         if (memory_clock < 10000)
 252                 mc_para_index = 0;
 253         else if (memory_clock >= 80000)
 254                 mc_para_index = 0x0f;
 255         else
 256                 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
 257         return mc_para_index;
 258 }
 259
 260 static u8 ci_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
 261 {
 262         u8 mc_para_index;
 263
 264         if (strobe_mode) {
 265                 if (memory_clock < 12500)
 266                         mc_para_index = 0x00;
 267                 else if (memory_clock > 47500)
 268                         mc_para_index = 0x0f;
 269                 else
 270                         mc_para_index = (u8)((memory_clock - 10000) / 2500);
 271         } else {
 272                 if (memory_clock < 65000)
 273                         mc_para_index = 0x00;
 274                 else if (memory_clock > 135000)
 275                         mc_para_index = 0x0f;
 276                 else
 277                         mc_para_index = (u8)((memory_clock - 60000) / 5000);
 278         }
 279         return mc_para_index;
 280 }
 281
 282 static void ci_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev,
 283                                                      u32 max_voltage_steps,
 284                                                      struct atom_voltage_table *voltage_table)
 285 {
 286         unsigned int i, diff;
 287
 288         if (voltage_table->count <= max_voltage_steps)
 289                 return;
 290
 291         diff = voltage_table->count - max_voltage_steps;
 292
 293         for (i = 0; i < max_voltage_steps; i++)
 294                 voltage_table->entries[i] = voltage_table->entries[i + diff];
 295
 296         voltage_table->count = max_voltage_steps;
 297 }
 298
 299 static int ci_get_std_voltage_value_sidd(struct amdgpu_device *adev,
 300                                          struct atom_voltage_table_entry *voltage_table,
 301                                          u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd);
 302 static int ci_set_power_limit(struct amdgpu_device *adev, u32 n);
 303 static int ci_set_overdrive_target_tdp(struct amdgpu_device *adev,
 304                                        u32 target_tdp);
 305 static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate);
 306 static void ci_dpm_set_dpm_funcs(struct amdgpu_device *adev);
 307 static void ci_dpm_set_irq_funcs(struct amdgpu_device *adev);
 308
 309 static PPSMC_Result amdgpu_ci_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
 310                                                              PPSMC_Msg msg, u32 parameter);
 311 static void ci_thermal_start_smc_fan_control(struct amdgpu_device *adev);
 312 static void ci_fan_ctrl_set_default_mode(struct amdgpu_device *adev);
 313
 314 static struct ci_power_info *ci_get_pi(struct amdgpu_device *adev)
 315 {
 316         struct ci_power_info *pi = adev->pm.dpm.priv;
 317
 318         return pi;
 319 }
 320
 321 static struct ci_ps *ci_get_ps(struct amdgpu_ps *rps)
 322 {
 323         struct ci_ps *ps = rps->ps_priv;
 324
 325         return ps;
 326 }
 327
 328 static void ci_initialize_powertune_defaults(struct amdgpu_device *adev)
 329 {
 330         struct ci_power_info *pi = ci_get_pi(adev);
 331
 332         switch (adev->pdev->device) {
 333         case 0x6649:
 334         case 0x6650:
 335         case 0x6651:
 336         case 0x6658:
 337         case 0x665C:
 338         case 0x665D:
 339         default:
 340                 pi->powertune_defaults = &defaults_bonaire_xt;
 341                 break;
 342         case 0x6640:
 343         case 0x6641:
 344         case 0x6646:
 345         case 0x6647:
 346                 pi->powertune_defaults = &defaults_saturn_xt;
 347                 break;
 348         case 0x67B8:
 349         case 0x67B0:
 350                 pi->powertune_defaults = &defaults_hawaii_xt;
 351                 break;
 352         case 0x67BA:
 353         case 0x67B1:
 354                 pi->powertune_defaults = &defaults_hawaii_pro;
 355                 break;
 356         case 0x67A0:
 357         case 0x67A1:
 358         case 0x67A2:
 359         case 0x67A8:
 360         case 0x67A9:
 361         case 0x67AA:
 362         case 0x67B9:
 363         case 0x67BE:
 364                 pi->powertune_defaults = &defaults_bonaire_xt;
 365                 break;
 366         }
 367
 368         pi->dte_tj_offset = 0;
 369
 370         pi->caps_power_containment = true;
 371         pi->caps_cac = false;
 372         pi->caps_sq_ramping = false;
 373         pi->caps_db_ramping = false;
 374         pi->caps_td_ramping = false;
 375         pi->caps_tcp_ramping = false;
 376
 377         if (pi->caps_power_containment) {
 378                 pi->caps_cac = true;
 379                 if (adev->asic_type == CHIP_HAWAII)
 380                         pi->enable_bapm_feature = false;
 381                 else
 382                         pi->enable_bapm_feature = true;
 383                 pi->enable_tdc_limit_feature = true;
 384                 pi->enable_pkg_pwr_tracking_feature = true;
 385         }
 386 }
 387
 388 static u8 ci_convert_to_vid(u16 vddc)
 389 {
 390         return (6200 - (vddc * VOLTAGE_SCALE)) / 25;
 391 }
 392
 393 static int ci_populate_bapm_vddc_vid_sidd(struct amdgpu_device *adev)
 394 {
 395         struct ci_power_info *pi = ci_get_pi(adev);
 396         u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
 397         u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
 398         u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2;
 399         u32 i;
 400
 401         if (adev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL)
 402                 return -EINVAL;
 403         if (adev->pm.dpm.dyn_state.cac_leakage_table.count > 8)
 404                 return -EINVAL;
 405         if (adev->pm.dpm.dyn_state.cac_leakage_table.count !=
 406             adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count)
 407                 return -EINVAL;
 408
 409         for (i = 0; i < adev->pm.dpm.dyn_state.cac_leakage_table.count; i++) {
 410                 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
 411                         lo_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1);
 412                         hi_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2);
 413                         hi2_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3);
 414                 } else {
 415                         lo_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc);
 416                         hi_vid[i] = ci_convert_to_vid((u16)adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage);
 417                 }
 418         }
 419         return 0;
 420 }
 421
 422 static int ci_populate_vddc_vid(struct amdgpu_device *adev)
 423 {
 424         struct ci_power_info *pi = ci_get_pi(adev);
 425         u8 *vid = pi->smc_powertune_table.VddCVid;
 426         u32 i;
 427
 428         if (pi->vddc_voltage_table.count > 8)
 429                 return -EINVAL;
 430
 431         for (i = 0; i < pi->vddc_voltage_table.count; i++)
 432                 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value);
 433
 434         return 0;
 435 }
 436
 437 static int ci_populate_svi_load_line(struct amdgpu_device *adev)
 438 {
 439         struct ci_power_info *pi = ci_get_pi(adev);
 440         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 441
 442         pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en;
 443         pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc;
 444         pi->smc_powertune_table.SviLoadLineTrimVddC = 3;
 445         pi->smc_powertune_table.SviLoadLineOffsetVddC = 0;
 446
 447         return 0;
 448 }
 449
 450 static int ci_populate_tdc_limit(struct amdgpu_device *adev)
 451 {
 452         struct ci_power_info *pi = ci_get_pi(adev);
 453         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 454         u16 tdc_limit;
 455
 456         tdc_limit = adev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256;
 457         pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit);
 458         pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
 459                 pt_defaults->tdc_vddc_throttle_release_limit_perc;
 460         pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt;
 461
 462         return 0;
 463 }
 464
 465 static int ci_populate_dw8(struct amdgpu_device *adev)
 466 {
 467         struct ci_power_info *pi = ci_get_pi(adev);
 468         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 469         int ret;
 470
 471         ret = amdgpu_ci_read_smc_sram_dword(adev,
 472                                      SMU7_FIRMWARE_HEADER_LOCATION +
 473                                      offsetof(SMU7_Firmware_Header, PmFuseTable) +
 474                                      offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl),
 475                                      (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl,
 476                                      pi->sram_end);
 477         if (ret)
 478                 return -EINVAL;
 479         else
 480                 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl;
 481
 482         return 0;
 483 }
 484
 485 static int ci_populate_fuzzy_fan(struct amdgpu_device *adev)
 486 {
 487         struct ci_power_info *pi = ci_get_pi(adev);
 488
 489         if ((adev->pm.dpm.fan.fan_output_sensitivity & (1 << 15)) ||
 490             (adev->pm.dpm.fan.fan_output_sensitivity == 0))
 491                 adev->pm.dpm.fan.fan_output_sensitivity =
 492                         adev->pm.dpm.fan.default_fan_output_sensitivity;
 493
 494         pi->smc_powertune_table.FuzzyFan_PwmSetDelta =
 495                 cpu_to_be16(adev->pm.dpm.fan.fan_output_sensitivity);
 496
 497         return 0;
 498 }
 499
 500 static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct amdgpu_device *adev)
 501 {
 502         struct ci_power_info *pi = ci_get_pi(adev);
 503         u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
 504         u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
 505         int i, min, max;
 506
 507         min = max = hi_vid[0];
 508         for (i = 0; i < 8; i++) {
 509                 if (0 != hi_vid[i]) {
 510                         if (min > hi_vid[i])
 511                                 min = hi_vid[i];
 512                         if (max < hi_vid[i])
 513                                 max = hi_vid[i];
 514                 }
 515
 516                 if (0 != lo_vid[i]) {
 517                         if (min > lo_vid[i])
 518                                 min = lo_vid[i];
 519                         if (max < lo_vid[i])
 520                                 max = lo_vid[i];
 521                 }
 522         }
 523
 524         if ((min == 0) || (max == 0))
 525                 return -EINVAL;
 526         pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max;
 527         pi->smc_powertune_table.GnbLPMLMinVid = (u8)min;
 528
 529         return 0;
 530 }
 531
 532 static int ci_populate_bapm_vddc_base_leakage_sidd(struct amdgpu_device *adev)
 533 {
 534         struct ci_power_info *pi = ci_get_pi(adev);
 535         u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd;
 536         u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd;
 537         struct amdgpu_cac_tdp_table *cac_tdp_table =
 538                 adev->pm.dpm.dyn_state.cac_tdp_table;
 539
 540         hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256;
 541         lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256;
 542
 543         pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd);
 544         pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd);
 545
 546         return 0;
 547 }
 548
 549 static int ci_populate_bapm_parameters_in_dpm_table(struct amdgpu_device *adev)
 550 {
 551         struct ci_power_info *pi = ci_get_pi(adev);
 552         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 553         SMU7_Discrete_DpmTable  *dpm_table = &pi->smc_state_table;
 554         struct amdgpu_cac_tdp_table *cac_tdp_table =
 555                 adev->pm.dpm.dyn_state.cac_tdp_table;
 556         struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table;
 557         int i, j, k;
 558         const u16 *def1;
 559         const u16 *def2;
 560
 561         dpm_table->DefaultTdp = cac_tdp_table->tdp * 256;
 562         dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256;
 563
 564         dpm_table->DTETjOffset = (u8)pi->dte_tj_offset;
 565         dpm_table->GpuTjMax =
 566                 (u8)(pi->thermal_temp_setting.temperature_high / 1000);
 567         dpm_table->GpuTjHyst = 8;
 568
 569         dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base;
 570
 571         if (ppm) {
 572                 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000);
 573                 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256);
 574         } else {
 575                 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0);
 576                 dpm_table->PPM_TemperatureLimit = cpu_to_be16(0);
 577         }
 578
 579         dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient);
 580         def1 = pt_defaults->bapmti_r;
 581         def2 = pt_defaults->bapmti_rc;
 582
 583         for (i = 0; i < SMU7_DTE_ITERATIONS; i++) {
 584                 for (j = 0; j < SMU7_DTE_SOURCES; j++) {
 585                         for (k = 0; k < SMU7_DTE_SINKS; k++) {
 586                                 dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1);
 587                                 dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2);
 588                                 def1++;
 589                                 def2++;
 590                         }
 591                 }
 592         }
 593
 594         return 0;
 595 }
 596
 597 static int ci_populate_pm_base(struct amdgpu_device *adev)
 598 {
 599         struct ci_power_info *pi = ci_get_pi(adev);
 600         u32 pm_fuse_table_offset;
 601         int ret;
 602
 603         if (pi->caps_power_containment) {
 604                 ret = amdgpu_ci_read_smc_sram_dword(adev,
 605                                              SMU7_FIRMWARE_HEADER_LOCATION +
 606                                              offsetof(SMU7_Firmware_Header, PmFuseTable),
 607                                              &pm_fuse_table_offset, pi->sram_end);
 608                 if (ret)
 609                         return ret;
 610                 ret = ci_populate_bapm_vddc_vid_sidd(adev);
 611                 if (ret)
 612                         return ret;
 613                 ret = ci_populate_vddc_vid(adev);
 614                 if (ret)
 615                         return ret;
 616                 ret = ci_populate_svi_load_line(adev);
 617                 if (ret)
 618                         return ret;
 619                 ret = ci_populate_tdc_limit(adev);
 620                 if (ret)
 621                         return ret;
 622                 ret = ci_populate_dw8(adev);
 623                 if (ret)
 624                         return ret;
 625                 ret = ci_populate_fuzzy_fan(adev);
 626                 if (ret)
 627                         return ret;
 628                 ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(adev);
 629                 if (ret)
 630                         return ret;
 631                 ret = ci_populate_bapm_vddc_base_leakage_sidd(adev);
 632                 if (ret)
 633                         return ret;
 634                 ret = amdgpu_ci_copy_bytes_to_smc(adev, pm_fuse_table_offset,
 635                                            (u8 *)&pi->smc_powertune_table,
 636                                            sizeof(SMU7_Discrete_PmFuses), pi->sram_end);
 637                 if (ret)
 638                         return ret;
 639         }
 640
 641         return 0;
 642 }
 643
 644 static void ci_do_enable_didt(struct amdgpu_device *adev, const bool enable)
 645 {
 646         struct ci_power_info *pi = ci_get_pi(adev);
 647         u32 data;
 648
 649         if (pi->caps_sq_ramping) {
 650                 data = RREG32_DIDT(ixDIDT_SQ_CTRL0);
 651                 if (enable)
 652                         data |= DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
 653                 else
 654                         data &= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
 655                 WREG32_DIDT(ixDIDT_SQ_CTRL0, data);
 656         }
 657
 658         if (pi->caps_db_ramping) {
 659                 data = RREG32_DIDT(ixDIDT_DB_CTRL0);
 660                 if (enable)
 661                         data |= DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
 662                 else
 663                         data &= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
 664                 WREG32_DIDT(ixDIDT_DB_CTRL0, data);
 665         }
 666
 667         if (pi->caps_td_ramping) {
 668                 data = RREG32_DIDT(ixDIDT_TD_CTRL0);
 669                 if (enable)
 670                         data |= DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
 671                 else
 672                         data &= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
 673                 WREG32_DIDT(ixDIDT_TD_CTRL0, data);
 674         }
 675
 676         if (pi->caps_tcp_ramping) {
 677                 data = RREG32_DIDT(ixDIDT_TCP_CTRL0);
 678                 if (enable)
 679                         data |= DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
 680                 else
 681                         data &= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
 682                 WREG32_DIDT(ixDIDT_TCP_CTRL0, data);
 683         }
 684 }
 685
 686 static int ci_program_pt_config_registers(struct amdgpu_device *adev,
 687                                           const struct ci_pt_config_reg *cac_config_regs)
 688 {
 689         const struct ci_pt_config_reg *config_regs = cac_config_regs;
 690         u32 data;
 691         u32 cache = 0;
 692
 693         if (config_regs == NULL)
 694                 return -EINVAL;
 695
 696         while (config_regs->offset != 0xFFFFFFFF) {
 697                 if (config_regs->type == CISLANDS_CONFIGREG_CACHE) {
 698                         cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
 699                 } else {
 700                         switch (config_regs->type) {
 701                         case CISLANDS_CONFIGREG_SMC_IND:
 702                                 data = RREG32_SMC(config_regs->offset);
 703                                 break;
 704                         case CISLANDS_CONFIGREG_DIDT_IND:
 705                                 data = RREG32_DIDT(config_regs->offset);
 706                                 break;
 707                         default:
 708                                 data = RREG32(config_regs->offset);
 709                                 break;
 710                         }
 711
 712                         data &= ~config_regs->mask;
 713                         data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
 714                         data |= cache;
 715
 716                         switch (config_regs->type) {
 717                         case CISLANDS_CONFIGREG_SMC_IND:
 718                                 WREG32_SMC(config_regs->offset, data);
 719                                 break;
 720                         case CISLANDS_CONFIGREG_DIDT_IND:
 721                                 WREG32_DIDT(config_regs->offset, data);
 722                                 break;
 723                         default:
 724                                 WREG32(config_regs->offset, data);
 725                                 break;
 726                         }
 727                         cache = 0;
 728                 }
 729                 config_regs++;
 730         }
 731         return 0;
 732 }
 733
 734 static int ci_enable_didt(struct amdgpu_device *adev, bool enable)
 735 {
 736         struct ci_power_info *pi = ci_get_pi(adev);
 737         int ret;
 738
 739         if (pi->caps_sq_ramping || pi->caps_db_ramping ||
 740             pi->caps_td_ramping || pi->caps_tcp_ramping) {
 741                 gfx_v7_0_enter_rlc_safe_mode(adev);
 742
 743                 if (enable) {
 744                         ret = ci_program_pt_config_registers(adev, didt_config_ci);
 745                         if (ret) {
 746                                 gfx_v7_0_exit_rlc_safe_mode(adev);
 747                                 return ret;
 748                         }
 749                 }
 750
 751                 ci_do_enable_didt(adev, enable);
 752
 753                 gfx_v7_0_exit_rlc_safe_mode(adev);
 754         }
 755
 756         return 0;
 757 }
 758
 759 static int ci_enable_power_containment(struct amdgpu_device *adev, bool enable)
 760 {
 761         struct ci_power_info *pi = ci_get_pi(adev);
 762         PPSMC_Result smc_result;
 763         int ret = 0;
 764
 765         if (enable) {
 766                 pi->power_containment_features = 0;
 767                 if (pi->caps_power_containment) {
 768                         if (pi->enable_bapm_feature) {
 769                                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE);
 770                                 if (smc_result != PPSMC_Result_OK)
 771                                         ret = -EINVAL;
 772                                 else
 773                                         pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM;
 774                         }
 775
 776                         if (pi->enable_tdc_limit_feature) {
 777                                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_TDCLimitEnable);
 778                                 if (smc_result != PPSMC_Result_OK)
 779                                         ret = -EINVAL;
 780                                 else
 781                                         pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit;
 782                         }
 783
 784                         if (pi->enable_pkg_pwr_tracking_feature) {
 785                                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PkgPwrLimitEnable);
 786                                 if (smc_result != PPSMC_Result_OK) {
 787                                         ret = -EINVAL;
 788                                 } else {
 789                                         struct amdgpu_cac_tdp_table *cac_tdp_table =
 790                                                 adev->pm.dpm.dyn_state.cac_tdp_table;
 791                                         u32 default_pwr_limit =
 792                                                 (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
 793
 794                                         pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit;
 795
 796                                         ci_set_power_limit(adev, default_pwr_limit);
 797                                 }
 798                         }
 799                 }
 800         } else {
 801                 if (pi->caps_power_containment && pi->power_containment_features) {
 802                         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit)
 803                                 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_TDCLimitDisable);
 804
 805                         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)
 806                                 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE);
 807
 808                         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit)
 809                                 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PkgPwrLimitDisable);
 810                         pi->power_containment_features = 0;
 811                 }
 812         }
 813
 814         return ret;
 815 }
 816
 817 static int ci_enable_smc_cac(struct amdgpu_device *adev, bool enable)
 818 {
 819         struct ci_power_info *pi = ci_get_pi(adev);
 820         PPSMC_Result smc_result;
 821         int ret = 0;
 822
 823         if (pi->caps_cac) {
 824                 if (enable) {
 825                         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableCac);
 826                         if (smc_result != PPSMC_Result_OK) {
 827                                 ret = -EINVAL;
 828                                 pi->cac_enabled = false;
 829                         } else {
 830                                 pi->cac_enabled = true;
 831                         }
 832                 } else if (pi->cac_enabled) {
 833                         amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableCac);
 834                         pi->cac_enabled = false;
 835                 }
 836         }
 837
 838         return ret;
 839 }
 840
 841 static int ci_enable_thermal_based_sclk_dpm(struct amdgpu_device *adev,
 842                                             bool enable)
 843 {
 844         struct ci_power_info *pi = ci_get_pi(adev);
 845         PPSMC_Result smc_result = PPSMC_Result_OK;
 846
 847         if (pi->thermal_sclk_dpm_enabled) {
 848                 if (enable)
 849                         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_ENABLE_THERMAL_DPM);
 850                 else
 851                         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DISABLE_THERMAL_DPM);
 852         }
 853
 854         if (smc_result == PPSMC_Result_OK)
 855                 return 0;
 856         else
 857                 return -EINVAL;
 858 }
 859
 860 static int ci_power_control_set_level(struct amdgpu_device *adev)
 861 {
 862         struct ci_power_info *pi = ci_get_pi(adev);
 863         struct amdgpu_cac_tdp_table *cac_tdp_table =
 864                 adev->pm.dpm.dyn_state.cac_tdp_table;
 865         s32 adjust_percent;
 866         s32 target_tdp;
 867         int ret = 0;
 868         bool adjust_polarity = false; /* ??? */
 869
 870         if (pi->caps_power_containment) {
 871                 adjust_percent = adjust_polarity ?
 872                         adev->pm.dpm.tdp_adjustment : (-1 * adev->pm.dpm.tdp_adjustment);
 873                 target_tdp = ((100 + adjust_percent) *
 874                               (s32)cac_tdp_table->configurable_tdp) / 100;
 875
 876                 ret = ci_set_overdrive_target_tdp(adev, (u32)target_tdp);
 877         }
 878
 879         return ret;
 880 }
 881
 882 static void ci_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
 883 {
 884         struct ci_power_info *pi = ci_get_pi(adev);
 885
 886         if (pi->uvd_power_gated == gate)
 887                 return;
 888
 889         pi->uvd_power_gated = gate;
 890
 891         ci_update_uvd_dpm(adev, gate);
 892 }
 893
 894 static bool ci_dpm_vblank_too_short(struct amdgpu_device *adev)
 895 {
 896         u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
 897         u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 300;
 898
 899         if (vblank_time < switch_limit)
 900                 return true;
 901         else
 902                 return false;
 903
 904 }
 905
 906 static void ci_apply_state_adjust_rules(struct amdgpu_device *adev,
 907                                         struct amdgpu_ps *rps)
 908 {
 909         struct ci_ps *ps = ci_get_ps(rps);
 910         struct ci_power_info *pi = ci_get_pi(adev);
 911         struct amdgpu_clock_and_voltage_limits *max_limits;
 912         bool disable_mclk_switching;
 913         u32 sclk, mclk;
 914         int i;
 915
 916         if (rps->vce_active) {
 917                 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
 918                 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
 919         } else {
 920                 rps->evclk = 0;
 921                 rps->ecclk = 0;
 922         }
 923
 924         if ((adev->pm.dpm.new_active_crtc_count > 1) ||
 925             ci_dpm_vblank_too_short(adev))
 926                 disable_mclk_switching = true;
 927         else
 928                 disable_mclk_switching = false;
 929
 930         if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
 931                 pi->battery_state = true;
 932         else
 933                 pi->battery_state = false;
 934
 935         if (adev->pm.dpm.ac_power)
 936                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
 937         else
 938                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
 939
 940         if (adev->pm.dpm.ac_power == false) {
 941                 for (i = 0; i < ps->performance_level_count; i++) {
 942                         if (ps->performance_levels[i].mclk > max_limits->mclk)
 943                                 ps->performance_levels[i].mclk = max_limits->mclk;
 944                         if (ps->performance_levels[i].sclk > max_limits->sclk)
 945                                 ps->performance_levels[i].sclk = max_limits->sclk;
 946                 }
 947         }
 948
 949         /* XXX validate the min clocks required for display */
 950
 951         if (disable_mclk_switching) {
 952                 mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;
 953                 sclk = ps->performance_levels[0].sclk;
 954         } else {
 955                 mclk = ps->performance_levels[0].mclk;
 956                 sclk = ps->performance_levels[0].sclk;
 957         }
 958
 959         if (rps->vce_active) {
 960                 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
 961                         sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
 962                 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk)
 963                         mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk;
 964         }
 965
 966         ps->performance_levels[0].sclk = sclk;
 967         ps->performance_levels[0].mclk = mclk;
 968
 969         if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk)
 970                 ps->performance_levels[1].sclk = ps->performance_levels[0].sclk;
 971
 972         if (disable_mclk_switching) {
 973                 if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk)
 974                         ps->performance_levels[0].mclk = ps->performance_levels[1].mclk;
 975         } else {
 976                 if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk)
 977                         ps->performance_levels[1].mclk = ps->performance_levels[0].mclk;
 978         }
 979 }
 980
 981 static int ci_thermal_set_temperature_range(struct amdgpu_device *adev,
 982                                             int min_temp, int max_temp)
 983 {
 984         int low_temp = 0 * 1000;
 985         int high_temp = 255 * 1000;
 986         u32 tmp;
 987
 988         if (low_temp < min_temp)
 989                 low_temp = min_temp;
 990         if (high_temp > max_temp)
 991                 high_temp = max_temp;
 992         if (high_temp < low_temp) {
 993                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
 994                 return -EINVAL;
 995         }
 996
 997         tmp = RREG32_SMC(ixCG_THERMAL_INT);
 998         tmp &= ~(CG_THERMAL_INT__DIG_THERM_INTH_MASK | CG_THERMAL_INT__DIG_THERM_INTL_MASK);
 999         tmp |= ((high_temp / 1000) << CG_THERMAL_INT__DIG_THERM_INTH__SHIFT) |
1000                 ((low_temp / 1000)) << CG_THERMAL_INT__DIG_THERM_INTL__SHIFT;
1001         WREG32_SMC(ixCG_THERMAL_INT, tmp);
1002
1003 #if 0
1004         /* XXX: need to figure out how to handle this properly */
1005         tmp = RREG32_SMC(ixCG_THERMAL_CTRL);
1006         tmp &= DIG_THERM_DPM_MASK;
1007         tmp |= DIG_THERM_DPM(high_temp / 1000);
1008         WREG32_SMC(ixCG_THERMAL_CTRL, tmp);
1009 #endif
1010
1011         adev->pm.dpm.thermal.min_temp = low_temp;
1012         adev->pm.dpm.thermal.max_temp = high_temp;
1013         return 0;
1014 }
1015
1016 static int ci_thermal_enable_alert(struct amdgpu_device *adev,
1017                                    bool enable)
1018 {
1019         u32 thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
1020         PPSMC_Result result;
1021
1022         if (enable) {
1023                 thermal_int &= ~(CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK |
1024                                  CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK);
1025                 WREG32_SMC(ixCG_THERMAL_INT, thermal_int);
1026                 result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Thermal_Cntl_Enable);
1027                 if (result != PPSMC_Result_OK) {
1028                         DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
1029                         return -EINVAL;
1030                 }
1031         } else {
1032                 thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK |
1033                         CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
1034                 WREG32_SMC(ixCG_THERMAL_INT, thermal_int);
1035                 result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Thermal_Cntl_Disable);
1036                 if (result != PPSMC_Result_OK) {
1037                         DRM_DEBUG_KMS("Could not disable thermal interrupts.\n");
1038                         return -EINVAL;
1039                 }
1040         }
1041
1042         return 0;
1043 }
1044
1045 static void ci_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode)
1046 {
1047         struct ci_power_info *pi = ci_get_pi(adev);
1048         u32 tmp;
1049
1050         if (pi->fan_ctrl_is_in_default_mode) {
1051                 tmp = (RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK)
1052                         >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
1053                 pi->fan_ctrl_default_mode = tmp;
1054                 tmp = (RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__TMIN_MASK)
1055                         >> CG_FDO_CTRL2__TMIN__SHIFT;
1056                 pi->t_min = tmp;
1057                 pi->fan_ctrl_is_in_default_mode = false;
1058         }
1059
1060         tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;
1061         tmp |= 0 << CG_FDO_CTRL2__TMIN__SHIFT;
1062         WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1063
1064         tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
1065         tmp |= mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
1066         WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1067 }
1068
1069 static int ci_thermal_setup_fan_table(struct amdgpu_device *adev)
1070 {
1071         struct ci_power_info *pi = ci_get_pi(adev);
1072         SMU7_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
1073         u32 duty100;
1074         u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
1075         u16 fdo_min, slope1, slope2;
1076         u32 reference_clock, tmp;
1077         int ret;
1078         u64 tmp64;
1079
1080         if (!pi->fan_table_start) {
1081                 adev->pm.dpm.fan.ucode_fan_control = false;
1082                 return 0;
1083         }
1084
1085         duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK)
1086                 >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
1087
1088         if (duty100 == 0) {
1089                 adev->pm.dpm.fan.ucode_fan_control = false;
1090                 return 0;
1091         }
1092
1093         tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100;
1094         do_div(tmp64, 10000);
1095         fdo_min = (u16)tmp64;
1096
1097         t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min;
1098         t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med;
1099
1100         pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min;
1101         pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med;
1102
1103         slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
1104         slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
1105
1106         fan_table.TempMin = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100);
1107         fan_table.TempMed = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100);
1108         fan_table.TempMax = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100);
1109
1110         fan_table.Slope1 = cpu_to_be16(slope1);
1111         fan_table.Slope2 = cpu_to_be16(slope2);
1112
1113         fan_table.FdoMin = cpu_to_be16(fdo_min);
1114
1115         fan_table.HystDown = cpu_to_be16(adev->pm.dpm.fan.t_hyst);
1116
1117         fan_table.HystUp = cpu_to_be16(1);
1118
1119         fan_table.HystSlope = cpu_to_be16(1);
1120
1121         fan_table.TempRespLim = cpu_to_be16(5);
1122
1123         reference_clock = amdgpu_asic_get_xclk(adev);
1124
1125         fan_table.RefreshPeriod = cpu_to_be32((adev->pm.dpm.fan.cycle_delay *
1126                                                reference_clock) / 1600);
1127
1128         fan_table.FdoMax = cpu_to_be16((u16)duty100);
1129
1130         tmp = (RREG32_SMC(ixCG_MULT_THERMAL_CTRL) & CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK)
1131                 >> CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT;
1132         fan_table.TempSrc = (uint8_t)tmp;
1133
1134         ret = amdgpu_ci_copy_bytes_to_smc(adev,
1135                                           pi->fan_table_start,
1136                                           (u8 *)(&fan_table),
1137                                           sizeof(fan_table),
1138                                           pi->sram_end);
1139
1140         if (ret) {
1141                 DRM_ERROR("Failed to load fan table to the SMC.");
1142                 adev->pm.dpm.fan.ucode_fan_control = false;
1143         }
1144
1145         return 0;
1146 }
1147
1148 static int ci_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev)
1149 {
1150         struct ci_power_info *pi = ci_get_pi(adev);
1151         PPSMC_Result ret;
1152
1153         if (pi->caps_od_fuzzy_fan_control_support) {
1154                 ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
1155                                                                PPSMC_StartFanControl,
1156                                                                FAN_CONTROL_FUZZY);
1157                 if (ret != PPSMC_Result_OK)
1158                         return -EINVAL;
1159                 ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
1160                                                                PPSMC_MSG_SetFanPwmMax,
1161                                                                adev->pm.dpm.fan.default_max_fan_pwm);
1162                 if (ret != PPSMC_Result_OK)
1163                         return -EINVAL;
1164         } else {
1165                 ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
1166                                                                PPSMC_StartFanControl,
1167                                                                FAN_CONTROL_TABLE);
1168                 if (ret != PPSMC_Result_OK)
1169                         return -EINVAL;
1170         }
1171
1172         pi->fan_is_controlled_by_smc = true;
1173         return 0;
1174 }
1175
1176
1177 static int ci_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev)
1178 {
1179         PPSMC_Result ret;
1180         struct ci_power_info *pi = ci_get_pi(adev);
1181
1182         ret = amdgpu_ci_send_msg_to_smc(adev, PPSMC_StopFanControl);
1183         if (ret == PPSMC_Result_OK) {
1184                 pi->fan_is_controlled_by_smc = false;
1185                 return 0;
1186         } else {
1187                 return -EINVAL;
1188         }
1189 }
1190
1191 static int ci_dpm_get_fan_speed_percent(struct amdgpu_device *adev,
1192                                         u32 *speed)
1193 {
1194         u32 duty, duty100;
1195         u64 tmp64;
1196
1197         if (adev->pm.no_fan)
1198                 return -ENOENT;
1199
1200         duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK)
1201                 >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
1202         duty = (RREG32_SMC(ixCG_THERMAL_STATUS) & CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK)
1203                 >> CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT;
1204
1205         if (duty100 == 0)
1206                 return -EINVAL;
1207
1208         tmp64 = (u64)duty * 100;
1209         do_div(tmp64, duty100);
1210         *speed = (u32)tmp64;
1211
1212         if (*speed > 100)
1213                 *speed = 100;
1214
1215         return 0;
1216 }
1217
1218 static int ci_dpm_set_fan_speed_percent(struct amdgpu_device *adev,
1219                                         u32 speed)
1220 {
1221         u32 tmp;
1222         u32 duty, duty100;
1223         u64 tmp64;
1224         struct ci_power_info *pi = ci_get_pi(adev);
1225
1226         if (adev->pm.no_fan)
1227                 return -ENOENT;
1228
1229         if (pi->fan_is_controlled_by_smc)
1230                 return -EINVAL;
1231
1232         if (speed > 100)
1233                 return -EINVAL;
1234
1235         duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK)
1236                 >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
1237
1238         if (duty100 == 0)
1239                 return -EINVAL;
1240
1241         tmp64 = (u64)speed * duty100;
1242         do_div(tmp64, 100);
1243         duty = (u32)tmp64;
1244
1245         tmp = RREG32_SMC(ixCG_FDO_CTRL0) & ~CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK;
1246         tmp |= duty << CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT;
1247         WREG32_SMC(ixCG_FDO_CTRL0, tmp);
1248
1249         return 0;
1250 }
1251
1252 static void ci_dpm_set_fan_control_mode(struct amdgpu_device *adev, u32 mode)
1253 {
1254         if (mode) {
1255                 /* stop auto-manage */
1256                 if (adev->pm.dpm.fan.ucode_fan_control)
1257                         ci_fan_ctrl_stop_smc_fan_control(adev);
1258                 ci_fan_ctrl_set_static_mode(adev, mode);
1259         } else {
1260                 /* restart auto-manage */
1261                 if (adev->pm.dpm.fan.ucode_fan_control)
1262                         ci_thermal_start_smc_fan_control(adev);
1263                 else
1264                         ci_fan_ctrl_set_default_mode(adev);
1265         }
1266 }
1267
1268 static u32 ci_dpm_get_fan_control_mode(struct amdgpu_device *adev)
1269 {
1270         struct ci_power_info *pi = ci_get_pi(adev);
1271         u32 tmp;
1272
1273         if (pi->fan_is_controlled_by_smc)
1274                 return 0;
1275
1276         tmp = RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
1277         return (tmp >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT);
1278 }
1279
1280 #if 0
1281 static int ci_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev,
1282                                          u32 *speed)
1283 {
1284         u32 tach_period;
1285         u32 xclk = amdgpu_asic_get_xclk(adev);
1286
1287         if (adev->pm.no_fan)
1288                 return -ENOENT;
1289
1290         if (adev->pm.fan_pulses_per_revolution == 0)
1291                 return -ENOENT;
1292
1293         tach_period = (RREG32_SMC(ixCG_TACH_STATUS) & CG_TACH_STATUS__TACH_PERIOD_MASK)
1294                 >> CG_TACH_STATUS__TACH_PERIOD__SHIFT;
1295         if (tach_period == 0)
1296                 return -ENOENT;
1297
1298         *speed = 60 * xclk * 10000 / tach_period;
1299
1300         return 0;
1301 }
1302
1303 static int ci_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev,
1304                                          u32 speed)
1305 {
1306         u32 tach_period, tmp;
1307         u32 xclk = amdgpu_asic_get_xclk(adev);
1308
1309         if (adev->pm.no_fan)
1310                 return -ENOENT;
1311
1312         if (adev->pm.fan_pulses_per_revolution == 0)
1313                 return -ENOENT;
1314
1315         if ((speed < adev->pm.fan_min_rpm) ||
1316             (speed > adev->pm.fan_max_rpm))
1317                 return -EINVAL;
1318
1319         if (adev->pm.dpm.fan.ucode_fan_control)
1320                 ci_fan_ctrl_stop_smc_fan_control(adev);
1321
1322         tach_period = 60 * xclk * 10000 / (8 * speed);
1323         tmp = RREG32_SMC(ixCG_TACH_CTRL) & ~CG_TACH_CTRL__TARGET_PERIOD_MASK;
1324         tmp |= tach_period << CG_TACH_CTRL__TARGET_PERIOD__SHIFT;
1325         WREG32_SMC(CG_TACH_CTRL, tmp);
1326
1327         ci_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM);
1328
1329         return 0;
1330 }
1331 #endif
1332
1333 static void ci_fan_ctrl_set_default_mode(struct amdgpu_device *adev)
1334 {
1335         struct ci_power_info *pi = ci_get_pi(adev);
1336         u32 tmp;
1337
1338         if (!pi->fan_ctrl_is_in_default_mode) {
1339                 tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
1340                 tmp |= pi->fan_ctrl_default_mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
1341                 WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1342
1343                 tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;
1344                 tmp |= pi->t_min << CG_FDO_CTRL2__TMIN__SHIFT;
1345                 WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1346                 pi->fan_ctrl_is_in_default_mode = true;
1347         }
1348 }
1349
1350 static void ci_thermal_start_smc_fan_control(struct amdgpu_device *adev)
1351 {
1352         if (adev->pm.dpm.fan.ucode_fan_control) {
1353                 ci_fan_ctrl_start_smc_fan_control(adev);
1354                 ci_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC);
1355         }
1356 }
1357
1358 static void ci_thermal_initialize(struct amdgpu_device *adev)
1359 {
1360         u32 tmp;
1361
1362         if (adev->pm.fan_pulses_per_revolution) {
1363                 tmp = RREG32_SMC(ixCG_TACH_CTRL) & ~CG_TACH_CTRL__EDGE_PER_REV_MASK;
1364                 tmp |= (adev->pm.fan_pulses_per_revolution - 1)
1365                         << CG_TACH_CTRL__EDGE_PER_REV__SHIFT;
1366                 WREG32_SMC(ixCG_TACH_CTRL, tmp);
1367         }
1368
1369         tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK;
1370         tmp |= 0x28 << CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT;
1371         WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1372 }
1373
1374 static int ci_thermal_start_thermal_controller(struct amdgpu_device *adev)
1375 {
1376         int ret;
1377
1378         ci_thermal_initialize(adev);
1379         ret = ci_thermal_set_temperature_range(adev, CISLANDS_TEMP_RANGE_MIN, CISLANDS_TEMP_RANGE_MAX);
1380         if (ret)
1381                 return ret;
1382         ret = ci_thermal_enable_alert(adev, true);
1383         if (ret)
1384                 return ret;
1385         if (adev->pm.dpm.fan.ucode_fan_control) {
1386                 ret = ci_thermal_setup_fan_table(adev);
1387                 if (ret)
1388                         return ret;
1389                 ci_thermal_start_smc_fan_control(adev);
1390         }
1391
1392         return 0;
1393 }
1394
1395 static void ci_thermal_stop_thermal_controller(struct amdgpu_device *adev)
1396 {
1397         if (!adev->pm.no_fan)
1398                 ci_fan_ctrl_set_default_mode(adev);
1399 }
1400
1401 static int ci_read_smc_soft_register(struct amdgpu_device *adev,
1402                                      u16 reg_offset, u32 *value)
1403 {
1404         struct ci_power_info *pi = ci_get_pi(adev);
1405
1406         return amdgpu_ci_read_smc_sram_dword(adev,
1407                                       pi->soft_regs_start + reg_offset,
1408                                       value, pi->sram_end);
1409 }
1410
1411 static int ci_write_smc_soft_register(struct amdgpu_device *adev,
1412                                       u16 reg_offset, u32 value)
1413 {
1414         struct ci_power_info *pi = ci_get_pi(adev);
1415
1416         return amdgpu_ci_write_smc_sram_dword(adev,
1417                                        pi->soft_regs_start + reg_offset,
1418                                        value, pi->sram_end);
1419 }
1420
1421 static void ci_init_fps_limits(struct amdgpu_device *adev)
1422 {
1423         struct ci_power_info *pi = ci_get_pi(adev);
1424         SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
1425
1426         if (pi->caps_fps) {
1427                 u16 tmp;
1428
1429                 tmp = 45;
1430                 table->FpsHighT = cpu_to_be16(tmp);
1431
1432                 tmp = 30;
1433                 table->FpsLowT = cpu_to_be16(tmp);
1434         }
1435 }
1436
1437 static int ci_update_sclk_t(struct amdgpu_device *adev)
1438 {
1439         struct ci_power_info *pi = ci_get_pi(adev);
1440         int ret = 0;
1441         u32 low_sclk_interrupt_t = 0;
1442
1443         if (pi->caps_sclk_throttle_low_notification) {
1444                 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
1445
1446                 ret = amdgpu_ci_copy_bytes_to_smc(adev,
1447                                            pi->dpm_table_start +
1448                                            offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT),
1449                                            (u8 *)&low_sclk_interrupt_t,
1450                                            sizeof(u32), pi->sram_end);
1451
1452         }
1453
1454         return ret;
1455 }
1456
1457 static void ci_get_leakage_voltages(struct amdgpu_device *adev)
1458 {
1459         struct ci_power_info *pi = ci_get_pi(adev);
1460         u16 leakage_id, virtual_voltage_id;
1461         u16 vddc, vddci;
1462         int i;
1463
1464         pi->vddc_leakage.count = 0;
1465         pi->vddci_leakage.count = 0;
1466
1467         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
1468                 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
1469                         virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1470                         if (amdgpu_atombios_get_voltage_evv(adev, virtual_voltage_id, &vddc) != 0)
1471                                 continue;
1472                         if (vddc != 0 && vddc != virtual_voltage_id) {
1473                                 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
1474                                 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
1475                                 pi->vddc_leakage.count++;
1476                         }
1477                 }
1478         } else if (amdgpu_atombios_get_leakage_id_from_vbios(adev, &leakage_id) == 0) {
1479                 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
1480                         virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1481                         if (amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(adev, &vddc, &vddci,
1482                                                                                      virtual_voltage_id,
1483                                                                                      leakage_id) == 0) {
1484                                 if (vddc != 0 && vddc != virtual_voltage_id) {
1485                                         pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
1486                                         pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
1487                                         pi->vddc_leakage.count++;
1488                                 }
1489                                 if (vddci != 0 && vddci != virtual_voltage_id) {
1490                                         pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci;
1491                                         pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id;
1492                                         pi->vddci_leakage.count++;
1493                                 }
1494                         }
1495                 }
1496         }
1497 }
1498
1499 static void ci_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources)
1500 {
1501         struct ci_power_info *pi = ci_get_pi(adev);
1502         bool want_thermal_protection;
1503         enum amdgpu_dpm_event_src dpm_event_src;
1504         u32 tmp;
1505
1506         switch (sources) {
1507         case 0:
1508         default:
1509                 want_thermal_protection = false;
1510                 break;
1511         case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL):
1512                 want_thermal_protection = true;
1513                 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGITAL;
1514                 break;
1515         case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
1516                 want_thermal_protection = true;
1517                 dpm_event_src = AMDGPU_DPM_EVENT_SRC_EXTERNAL;
1518                 break;
1519         case ((1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
1520               (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL)):
1521                 want_thermal_protection = true;
1522                 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
1523                 break;
1524         }
1525
1526         if (want_thermal_protection) {
1527 #if 0
1528                 /* XXX: need to figure out how to handle this properly */
1529                 tmp = RREG32_SMC(ixCG_THERMAL_CTRL);
1530                 tmp &= DPM_EVENT_SRC_MASK;
1531                 tmp |= DPM_EVENT_SRC(dpm_event_src);
1532                 WREG32_SMC(ixCG_THERMAL_CTRL, tmp);
1533 #endif
1534
1535                 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
1536                 if (pi->thermal_protection)
1537                         tmp &= ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
1538                 else
1539                         tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
1540                 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
1541         } else {
1542                 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
1543                 tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
1544                 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
1545         }
1546 }
1547
1548 static void ci_enable_auto_throttle_source(struct amdgpu_device *adev,
1549                                            enum amdgpu_dpm_auto_throttle_src source,
1550                                            bool enable)
1551 {
1552         struct ci_power_info *pi = ci_get_pi(adev);
1553
1554         if (enable) {
1555                 if (!(pi->active_auto_throttle_sources & (1 << source))) {
1556                         pi->active_auto_throttle_sources |= 1 << source;
1557                         ci_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
1558                 }
1559         } else {
1560                 if (pi->active_auto_throttle_sources & (1 << source)) {
1561                         pi->active_auto_throttle_sources &= ~(1 << source);
1562                         ci_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
1563                 }
1564         }
1565 }
1566
1567 static void ci_enable_vr_hot_gpio_interrupt(struct amdgpu_device *adev)
1568 {
1569         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1570                 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableVRHotGPIOInterrupt);
1571 }
1572
1573 static int ci_unfreeze_sclk_mclk_dpm(struct amdgpu_device *adev)
1574 {
1575         struct ci_power_info *pi = ci_get_pi(adev);
1576         PPSMC_Result smc_result;
1577
1578         if (!pi->need_update_smu7_dpm_table)
1579                 return 0;
1580
1581         if ((!pi->sclk_dpm_key_disabled) &&
1582             (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1583                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
1584                 if (smc_result != PPSMC_Result_OK)
1585                         return -EINVAL;
1586         }
1587
1588         if ((!pi->mclk_dpm_key_disabled) &&
1589             (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1590                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
1591                 if (smc_result != PPSMC_Result_OK)
1592                         return -EINVAL;
1593         }
1594
1595         pi->need_update_smu7_dpm_table = 0;
1596         return 0;
1597 }
1598
1599 static int ci_enable_sclk_mclk_dpm(struct amdgpu_device *adev, bool enable)
1600 {
1601         struct ci_power_info *pi = ci_get_pi(adev);
1602         PPSMC_Result smc_result;
1603
1604         if (enable) {
1605                 if (!pi->sclk_dpm_key_disabled) {
1606                         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DPM_Enable);
1607                         if (smc_result != PPSMC_Result_OK)
1608                                 return -EINVAL;
1609                 }
1610
1611                 if (!pi->mclk_dpm_key_disabled) {
1612                         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_Enable);
1613                         if (smc_result != PPSMC_Result_OK)
1614                                 return -EINVAL;
1615
1616                         WREG32_P(mmMC_SEQ_CNTL_3, MC_SEQ_CNTL_3__CAC_EN_MASK,
1617                                         ~MC_SEQ_CNTL_3__CAC_EN_MASK);
1618
1619                         WREG32_SMC(ixLCAC_MC0_CNTL, 0x05);
1620                         WREG32_SMC(ixLCAC_MC1_CNTL, 0x05);
1621                         WREG32_SMC(ixLCAC_CPL_CNTL, 0x100005);
1622
1623                         udelay(10);
1624
1625                         WREG32_SMC(ixLCAC_MC0_CNTL, 0x400005);
1626                         WREG32_SMC(ixLCAC_MC1_CNTL, 0x400005);
1627                         WREG32_SMC(ixLCAC_CPL_CNTL, 0x500005);
1628                 }
1629         } else {
1630                 if (!pi->sclk_dpm_key_disabled) {
1631                         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DPM_Disable);
1632                         if (smc_result != PPSMC_Result_OK)
1633                                 return -EINVAL;
1634                 }
1635
1636                 if (!pi->mclk_dpm_key_disabled) {
1637                         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_Disable);
1638                         if (smc_result != PPSMC_Result_OK)
1639                                 return -EINVAL;
1640                 }
1641         }
1642
1643         return 0;
1644 }
1645
1646 static int ci_start_dpm(struct amdgpu_device *adev)
1647 {
1648         struct ci_power_info *pi = ci_get_pi(adev);
1649         PPSMC_Result smc_result;
1650         int ret;
1651         u32 tmp;
1652
1653         tmp = RREG32_SMC(ixGENERAL_PWRMGT);
1654         tmp |= GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK;
1655         WREG32_SMC(ixGENERAL_PWRMGT, tmp);
1656
1657         tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
1658         tmp |= SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK;
1659         WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
1660
1661         ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000);
1662
1663         WREG32_P(mmBIF_LNCNT_RESET, 0, ~BIF_LNCNT_RESET__RESET_LNCNT_EN_MASK);
1664
1665         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Voltage_Cntl_Enable);
1666         if (smc_result != PPSMC_Result_OK)
1667                 return -EINVAL;
1668
1669         ret = ci_enable_sclk_mclk_dpm(adev, true);
1670         if (ret)
1671                 return ret;
1672
1673         if (!pi->pcie_dpm_key_disabled) {
1674                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PCIeDPM_Enable);
1675                 if (smc_result != PPSMC_Result_OK)
1676                         return -EINVAL;
1677         }
1678
1679         return 0;
1680 }
1681
1682 static int ci_freeze_sclk_mclk_dpm(struct amdgpu_device *adev)
1683 {
1684         struct ci_power_info *pi = ci_get_pi(adev);
1685         PPSMC_Result smc_result;
1686
1687         if (!pi->need_update_smu7_dpm_table)
1688                 return 0;
1689
1690         if ((!pi->sclk_dpm_key_disabled) &&
1691             (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1692                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_SCLKDPM_FreezeLevel);
1693                 if (smc_result != PPSMC_Result_OK)
1694                         return -EINVAL;
1695         }
1696
1697         if ((!pi->mclk_dpm_key_disabled) &&
1698             (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1699                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_FreezeLevel);
1700                 if (smc_result != PPSMC_Result_OK)
1701                         return -EINVAL;
1702         }
1703
1704         return 0;
1705 }
1706
1707 static int ci_stop_dpm(struct amdgpu_device *adev)
1708 {
1709         struct ci_power_info *pi = ci_get_pi(adev);
1710         PPSMC_Result smc_result;
1711         int ret;
1712         u32 tmp;
1713
1714         tmp = RREG32_SMC(ixGENERAL_PWRMGT);
1715         tmp &= ~GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK;
1716         WREG32_SMC(ixGENERAL_PWRMGT, tmp);
1717
1718         tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
1719         tmp &= ~SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK;
1720         WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
1721
1722         if (!pi->pcie_dpm_key_disabled) {
1723                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PCIeDPM_Disable);
1724                 if (smc_result != PPSMC_Result_OK)
1725                         return -EINVAL;
1726         }
1727
1728         ret = ci_enable_sclk_mclk_dpm(adev, false);
1729         if (ret)
1730                 return ret;
1731
1732         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Voltage_Cntl_Disable);
1733         if (smc_result != PPSMC_Result_OK)
1734                 return -EINVAL;
1735
1736         return 0;
1737 }
1738
1739 static void ci_enable_sclk_control(struct amdgpu_device *adev, bool enable)
1740 {
1741         u32 tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
1742
1743         if (enable)
1744                 tmp &= ~SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK;
1745         else
1746                 tmp |= SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK;
1747         WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
1748 }
1749
1750 #if 0
1751 static int ci_notify_hw_of_power_source(struct amdgpu_device *adev,
1752                                         bool ac_power)
1753 {
1754         struct ci_power_info *pi = ci_get_pi(adev);
1755         struct amdgpu_cac_tdp_table *cac_tdp_table =
1756                 adev->pm.dpm.dyn_state.cac_tdp_table;
1757         u32 power_limit;
1758
1759         if (ac_power)
1760                 power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
1761         else
1762                 power_limit = (u32)(cac_tdp_table->battery_power_limit * 256);
1763
1764         ci_set_power_limit(adev, power_limit);
1765
1766         if (pi->caps_automatic_dc_transition) {
1767                 if (ac_power)
1768                         amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC);
1769                 else
1770                         amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Remove_DC_Clamp);
1771         }
1772
1773         return 0;
1774 }
1775 #endif
1776
1777 static PPSMC_Result amdgpu_ci_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
1778                                                       PPSMC_Msg msg, u32 parameter)
1779 {
1780         WREG32(mmSMC_MSG_ARG_0, parameter);
1781         return amdgpu_ci_send_msg_to_smc(adev, msg);
1782 }
1783
1784 static PPSMC_Result amdgpu_ci_send_msg_to_smc_return_parameter(struct amdgpu_device *adev,
1785                                                         PPSMC_Msg msg, u32 *parameter)
1786 {
1787         PPSMC_Result smc_result;
1788
1789         smc_result = amdgpu_ci_send_msg_to_smc(adev, msg);
1790
1791         if ((smc_result == PPSMC_Result_OK) && parameter)
1792                 *parameter = RREG32(mmSMC_MSG_ARG_0);
1793
1794         return smc_result;
1795 }
1796
1797 static int ci_dpm_force_state_sclk(struct amdgpu_device *adev, u32 n)
1798 {
1799         struct ci_power_info *pi = ci_get_pi(adev);
1800
1801         if (!pi->sclk_dpm_key_disabled) {
1802                 PPSMC_Result smc_result =
1803                         amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SCLKDPM_SetEnabledMask, 1 << n);
1804                 if (smc_result != PPSMC_Result_OK)
1805                         return -EINVAL;
1806         }
1807
1808         return 0;
1809 }
1810
1811 static int ci_dpm_force_state_mclk(struct amdgpu_device *adev, u32 n)
1812 {
1813         struct ci_power_info *pi = ci_get_pi(adev);
1814
1815         if (!pi->mclk_dpm_key_disabled) {
1816                 PPSMC_Result smc_result =
1817                         amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_MCLKDPM_SetEnabledMask, 1 << n);
1818                 if (smc_result != PPSMC_Result_OK)
1819                         return -EINVAL;
1820         }
1821
1822         return 0;
1823 }
1824
1825 static int ci_dpm_force_state_pcie(struct amdgpu_device *adev, u32 n)
1826 {
1827         struct ci_power_info *pi = ci_get_pi(adev);
1828
1829         if (!pi->pcie_dpm_key_disabled) {
1830                 PPSMC_Result smc_result =
1831                         amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_PCIeDPM_ForceLevel, n);
1832                 if (smc_result != PPSMC_Result_OK)
1833                         return -EINVAL;
1834         }
1835
1836         return 0;
1837 }
1838
1839 static int ci_set_power_limit(struct amdgpu_device *adev, u32 n)
1840 {
1841         struct ci_power_info *pi = ci_get_pi(adev);
1842
1843         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
1844                 PPSMC_Result smc_result =
1845                         amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_PkgPwrSetLimit, n);
1846                 if (smc_result != PPSMC_Result_OK)
1847                         return -EINVAL;
1848         }
1849
1850         return 0;
1851 }
1852
1853 static int ci_set_overdrive_target_tdp(struct amdgpu_device *adev,
1854                                        u32 target_tdp)
1855 {
1856         PPSMC_Result smc_result =
1857                 amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
1858         if (smc_result != PPSMC_Result_OK)
1859                 return -EINVAL;
1860         return 0;
1861 }
1862
1863 #if 0
1864 static int ci_set_boot_state(struct amdgpu_device *adev)
1865 {
1866         return ci_enable_sclk_mclk_dpm(adev, false);
1867 }
1868 #endif
1869
1870 static u32 ci_get_average_sclk_freq(struct amdgpu_device *adev)
1871 {
1872         u32 sclk_freq;
1873         PPSMC_Result smc_result =
1874                 amdgpu_ci_send_msg_to_smc_return_parameter(adev,
1875                                                     PPSMC_MSG_API_GetSclkFrequency,
1876                                                     &sclk_freq);
1877         if (smc_result != PPSMC_Result_OK)
1878                 sclk_freq = 0;
1879
1880         return sclk_freq;
1881 }
1882
1883 static u32 ci_get_average_mclk_freq(struct amdgpu_device *adev)
1884 {
1885         u32 mclk_freq;
1886         PPSMC_Result smc_result =
1887                 amdgpu_ci_send_msg_to_smc_return_parameter(adev,
1888                                                     PPSMC_MSG_API_GetMclkFrequency,
1889                                                     &mclk_freq);
1890         if (smc_result != PPSMC_Result_OK)
1891                 mclk_freq = 0;
1892
1893         return mclk_freq;
1894 }
1895
1896 static void ci_dpm_start_smc(struct amdgpu_device *adev)
1897 {
1898         int i;
1899
1900         amdgpu_ci_program_jump_on_start(adev);
1901         amdgpu_ci_start_smc_clock(adev);
1902         amdgpu_ci_start_smc(adev);
1903         for (i = 0; i < adev->usec_timeout; i++) {
1904                 if (RREG32_SMC(ixFIRMWARE_FLAGS) & FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK)
1905                         break;
1906         }
1907 }
1908
1909 static void ci_dpm_stop_smc(struct amdgpu_device *adev)
1910 {
1911         amdgpu_ci_reset_smc(adev);
1912         amdgpu_ci_stop_smc_clock(adev);
1913 }
1914
1915 static int ci_process_firmware_header(struct amdgpu_device *adev)
1916 {
1917         struct ci_power_info *pi = ci_get_pi(adev);
1918         u32 tmp;
1919         int ret;
1920
1921         ret = amdgpu_ci_read_smc_sram_dword(adev,
1922                                      SMU7_FIRMWARE_HEADER_LOCATION +
1923                                      offsetof(SMU7_Firmware_Header, DpmTable),
1924                                      &tmp, pi->sram_end);
1925         if (ret)
1926                 return ret;
1927
1928         pi->dpm_table_start = tmp;
1929
1930         ret = amdgpu_ci_read_smc_sram_dword(adev,
1931                                      SMU7_FIRMWARE_HEADER_LOCATION +
1932                                      offsetof(SMU7_Firmware_Header, SoftRegisters),
1933                                      &tmp, pi->sram_end);
1934         if (ret)
1935                 return ret;
1936
1937         pi->soft_regs_start = tmp;
1938
1939         ret = amdgpu_ci_read_smc_sram_dword(adev,
1940                                      SMU7_FIRMWARE_HEADER_LOCATION +
1941                                      offsetof(SMU7_Firmware_Header, mcRegisterTable),
1942                                      &tmp, pi->sram_end);
1943         if (ret)
1944                 return ret;
1945
1946         pi->mc_reg_table_start = tmp;
1947
1948         ret = amdgpu_ci_read_smc_sram_dword(adev,
1949                                      SMU7_FIRMWARE_HEADER_LOCATION +
1950                                      offsetof(SMU7_Firmware_Header, FanTable),
1951                                      &tmp, pi->sram_end);
1952         if (ret)
1953                 return ret;
1954
1955         pi->fan_table_start = tmp;
1956
1957         ret = amdgpu_ci_read_smc_sram_dword(adev,
1958                                      SMU7_FIRMWARE_HEADER_LOCATION +
1959                                      offsetof(SMU7_Firmware_Header, mcArbDramTimingTable),
1960                                      &tmp, pi->sram_end);
1961         if (ret)
1962                 return ret;
1963
1964         pi->arb_table_start = tmp;
1965
1966         return 0;
1967 }
1968
1969 static void ci_read_clock_registers(struct amdgpu_device *adev)
1970 {
1971         struct ci_power_info *pi = ci_get_pi(adev);
1972
1973         pi->clock_registers.cg_spll_func_cntl =
1974                 RREG32_SMC(ixCG_SPLL_FUNC_CNTL);
1975         pi->clock_registers.cg_spll_func_cntl_2 =
1976                 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_2);
1977         pi->clock_registers.cg_spll_func_cntl_3 =
1978                 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_3);
1979         pi->clock_registers.cg_spll_func_cntl_4 =
1980                 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_4);
1981         pi->clock_registers.cg_spll_spread_spectrum =
1982                 RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM);
1983         pi->clock_registers.cg_spll_spread_spectrum_2 =
1984                 RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM_2);
1985         pi->clock_registers.dll_cntl = RREG32(mmDLL_CNTL);
1986         pi->clock_registers.mclk_pwrmgt_cntl = RREG32(mmMCLK_PWRMGT_CNTL);
1987         pi->clock_registers.mpll_ad_func_cntl = RREG32(mmMPLL_AD_FUNC_CNTL);
1988         pi->clock_registers.mpll_dq_func_cntl = RREG32(mmMPLL_DQ_FUNC_CNTL);
1989         pi->clock_registers.mpll_func_cntl = RREG32(mmMPLL_FUNC_CNTL);
1990         pi->clock_registers.mpll_func_cntl_1 = RREG32(mmMPLL_FUNC_CNTL_1);
1991         pi->clock_registers.mpll_func_cntl_2 = RREG32(mmMPLL_FUNC_CNTL_2);
1992         pi->clock_registers.mpll_ss1 = RREG32(mmMPLL_SS1);
1993         pi->clock_registers.mpll_ss2 = RREG32(mmMPLL_SS2);
1994 }
1995
1996 static void ci_init_sclk_t(struct amdgpu_device *adev)
1997 {
1998         struct ci_power_info *pi = ci_get_pi(adev);
1999
2000         pi->low_sclk_interrupt_t = 0;
2001 }
2002
2003 static void ci_enable_thermal_protection(struct amdgpu_device *adev,
2004                                          bool enable)
2005 {
2006         u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
2007
2008         if (enable)
2009                 tmp &= ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
2010         else
2011                 tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
2012         WREG32_SMC(ixGENERAL_PWRMGT, tmp);
2013 }
2014
2015 static void ci_enable_acpi_power_management(struct amdgpu_device *adev)
2016 {
2017         u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
2018
2019         tmp |= GENERAL_PWRMGT__STATIC_PM_EN_MASK;
2020
2021         WREG32_SMC(ixGENERAL_PWRMGT, tmp);
2022 }
2023
2024 #if 0
2025 static int ci_enter_ulp_state(struct amdgpu_device *adev)
2026 {
2027
2028         WREG32(mmSMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
2029
2030         udelay(25000);
2031
2032         return 0;
2033 }
2034
2035 static int ci_exit_ulp_state(struct amdgpu_device *adev)
2036 {
2037         int i;
2038
2039         WREG32(mmSMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
2040
2041         udelay(7000);
2042
2043         for (i = 0; i < adev->usec_timeout; i++) {
2044                 if (RREG32(mmSMC_RESP_0) == 1)
2045                         break;
2046                 udelay(1000);
2047         }
2048
2049         return 0;
2050 }
2051 #endif
2052
2053 static int ci_notify_smc_display_change(struct amdgpu_device *adev,
2054                                         bool has_display)
2055 {
2056         PPSMC_Msg msg = has_display ? PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
2057
2058         return (amdgpu_ci_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ?  0 : -EINVAL;
2059 }
2060
2061 static int ci_enable_ds_master_switch(struct amdgpu_device *adev,
2062                                       bool enable)
2063 {
2064         struct ci_power_info *pi = ci_get_pi(adev);
2065
2066         if (enable) {
2067                 if (pi->caps_sclk_ds) {
2068                         if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK)
2069                                 return -EINVAL;
2070                 } else {
2071                         if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
2072                                 return -EINVAL;
2073                 }
2074         } else {
2075                 if (pi->caps_sclk_ds) {
2076                         if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
2077                                 return -EINVAL;
2078                 }
2079         }
2080
2081         return 0;
2082 }
2083
2084 static void ci_program_display_gap(struct amdgpu_device *adev)
2085 {
2086         u32 tmp = RREG32_SMC(ixCG_DISPLAY_GAP_CNTL);
2087         u32 pre_vbi_time_in_us;
2088         u32 frame_time_in_us;
2089         u32 ref_clock = adev->clock.spll.reference_freq;
2090         u32 refresh_rate = amdgpu_dpm_get_vrefresh(adev);
2091         u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
2092
2093         tmp &= ~CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK;
2094         if (adev->pm.dpm.new_active_crtc_count > 0)
2095                 tmp |= (AMDGPU_PM_DISPLAY_GAP_VBLANK_OR_WM << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT);
2096         else
2097                 tmp |= (AMDGPU_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT);
2098         WREG32_SMC(ixCG_DISPLAY_GAP_CNTL, tmp);
2099
2100         if (refresh_rate == 0)
2101                 refresh_rate = 60;
2102         if (vblank_time == 0xffffffff)
2103                 vblank_time = 500;
2104         frame_time_in_us = 1000000 / refresh_rate;
2105         pre_vbi_time_in_us =
2106                 frame_time_in_us - 200 - vblank_time;
2107         tmp = pre_vbi_time_in_us * (ref_clock / 100);
2108
2109         WREG32_SMC(ixCG_DISPLAY_GAP_CNTL2, tmp);
2110         ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64);
2111         ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
2112
2113
2114         ci_notify_smc_display_change(adev, (adev->pm.dpm.new_active_crtc_count == 1));
2115
2116 }
2117
2118 static void ci_enable_spread_spectrum(struct amdgpu_device *adev, bool enable)
2119 {
2120         struct ci_power_info *pi = ci_get_pi(adev);
2121         u32 tmp;
2122
2123         if (enable) {
2124                 if (pi->caps_sclk_ss_support) {
2125                         tmp = RREG32_SMC(ixGENERAL_PWRMGT);
2126                         tmp |= GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK;
2127                         WREG32_SMC(ixGENERAL_PWRMGT, tmp);
2128                 }
2129         } else {
2130                 tmp = RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM);
2131                 tmp &= ~CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK;
2132                 WREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM, tmp);
2133
2134                 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
2135                 tmp &= ~GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK;
2136                 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
2137         }
2138 }
2139
2140 static void ci_program_sstp(struct amdgpu_device *adev)
2141 {
2142         WREG32_SMC(ixCG_STATIC_SCREEN_PARAMETER,
2143         ((CISLANDS_SSTU_DFLT << CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT) |
2144          (CISLANDS_SST_DFLT << CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT)));
2145 }
2146
2147 static void ci_enable_display_gap(struct amdgpu_device *adev)
2148 {
2149         u32 tmp = RREG32_SMC(ixCG_DISPLAY_GAP_CNTL);
2150
2151         tmp &= ~(CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK |
2152                         CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG_MASK);
2153         tmp |= ((AMDGPU_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT) |
2154                 (AMDGPU_PM_DISPLAY_GAP_VBLANK << CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG__SHIFT));
2155
2156         WREG32_SMC(ixCG_DISPLAY_GAP_CNTL, tmp);
2157 }
2158
2159 static void ci_program_vc(struct amdgpu_device *adev)
2160 {
2161         u32 tmp;
2162
2163         tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
2164         tmp &= ~(SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK | SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
2165         WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
2166
2167         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, CISLANDS_VRC_DFLT0);
2168         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_1, CISLANDS_VRC_DFLT1);
2169         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_2, CISLANDS_VRC_DFLT2);
2170         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_3, CISLANDS_VRC_DFLT3);
2171         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_4, CISLANDS_VRC_DFLT4);
2172         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_5, CISLANDS_VRC_DFLT5);
2173         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_6, CISLANDS_VRC_DFLT6);
2174         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_7, CISLANDS_VRC_DFLT7);
2175 }
2176
2177 static void ci_clear_vc(struct amdgpu_device *adev)
2178 {
2179         u32 tmp;
2180
2181         tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
2182         tmp |= (SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK | SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
2183         WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
2184
2185         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0);
2186         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_1, 0);
2187         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_2, 0);
2188         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_3, 0);
2189         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_4, 0);
2190         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_5, 0);
2191         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_6, 0);
2192         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_7, 0);
2193 }
2194
2195 static int ci_upload_firmware(struct amdgpu_device *adev)
2196 {
2197         struct ci_power_info *pi = ci_get_pi(adev);
2198         int i, ret;
2199
2200         for (i = 0; i < adev->usec_timeout; i++) {
2201                 if (RREG32_SMC(ixRCU_UC_EVENTS) & RCU_UC_EVENTS__boot_seq_done_MASK)
2202                         break;
2203         }
2204         WREG32_SMC(ixSMC_SYSCON_MISC_CNTL, 1);
2205
2206         amdgpu_ci_stop_smc_clock(adev);
2207         amdgpu_ci_reset_smc(adev);
2208
2209         ret = amdgpu_ci_load_smc_ucode(adev, pi->sram_end);
2210
2211         return ret;
2212
2213 }
2214
2215 static int ci_get_svi2_voltage_table(struct amdgpu_device *adev,
2216                                      struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table,
2217                                      struct atom_voltage_table *voltage_table)
2218 {
2219         u32 i;
2220
2221         if (voltage_dependency_table == NULL)
2222                 return -EINVAL;
2223
2224         voltage_table->mask_low = 0;
2225         voltage_table->phase_delay = 0;
2226
2227         voltage_table->count = voltage_dependency_table->count;
2228         for (i = 0; i < voltage_table->count; i++) {
2229                 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
2230                 voltage_table->entries[i].smio_low = 0;
2231         }
2232
2233         return 0;
2234 }
2235
2236 static int ci_construct_voltage_tables(struct amdgpu_device *adev)
2237 {
2238         struct ci_power_info *pi = ci_get_pi(adev);
2239         int ret;
2240
2241         if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2242                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
2243                                                         VOLTAGE_OBJ_GPIO_LUT,
2244                                                         &pi->vddc_voltage_table);
2245                 if (ret)
2246                         return ret;
2247         } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2248                 ret = ci_get_svi2_voltage_table(adev,
2249                                                 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2250                                                 &pi->vddc_voltage_table);
2251                 if (ret)
2252                         return ret;
2253         }
2254
2255         if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC)
2256                 ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_VDDC,
2257                                                          &pi->vddc_voltage_table);
2258
2259         if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2260                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI,
2261                                                         VOLTAGE_OBJ_GPIO_LUT,
2262                                                         &pi->vddci_voltage_table);
2263                 if (ret)
2264                         return ret;
2265         } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2266                 ret = ci_get_svi2_voltage_table(adev,
2267                                                 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2268                                                 &pi->vddci_voltage_table);
2269                 if (ret)
2270                         return ret;
2271         }
2272
2273         if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI)
2274                 ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_VDDCI,
2275                                                          &pi->vddci_voltage_table);
2276
2277         if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2278                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC,
2279                                                         VOLTAGE_OBJ_GPIO_LUT,
2280                                                         &pi->mvdd_voltage_table);
2281                 if (ret)
2282                         return ret;
2283         } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2284                 ret = ci_get_svi2_voltage_table(adev,
2285                                                 &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
2286                                                 &pi->mvdd_voltage_table);
2287                 if (ret)
2288                         return ret;
2289         }
2290
2291         if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD)
2292                 ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_MVDD,
2293                                                          &pi->mvdd_voltage_table);
2294
2295         return 0;
2296 }
2297
2298 static void ci_populate_smc_voltage_table(struct amdgpu_device *adev,
2299                                           struct atom_voltage_table_entry *voltage_table,
2300                                           SMU7_Discrete_VoltageLevel *smc_voltage_table)
2301 {
2302         int ret;
2303
2304         ret = ci_get_std_voltage_value_sidd(adev, voltage_table,
2305                                             &smc_voltage_table->StdVoltageHiSidd,
2306                                             &smc_voltage_table->StdVoltageLoSidd);
2307
2308         if (ret) {
2309                 smc_voltage_table->StdVoltageHiSidd = voltage_table->value * VOLTAGE_SCALE;
2310                 smc_voltage_table->StdVoltageLoSidd = voltage_table->value * VOLTAGE_SCALE;
2311         }
2312
2313         smc_voltage_table->Voltage = cpu_to_be16(voltage_table->value * VOLTAGE_SCALE);
2314         smc_voltage_table->StdVoltageHiSidd =
2315                 cpu_to_be16(smc_voltage_table->StdVoltageHiSidd);
2316         smc_voltage_table->StdVoltageLoSidd =
2317                 cpu_to_be16(smc_voltage_table->StdVoltageLoSidd);
2318 }
2319
2320 static int ci_populate_smc_vddc_table(struct amdgpu_device *adev,
2321                                       SMU7_Discrete_DpmTable *table)
2322 {
2323         struct ci_power_info *pi = ci_get_pi(adev);
2324         unsigned int count;
2325
2326         table->VddcLevelCount = pi->vddc_voltage_table.count;
2327         for (count = 0; count < table->VddcLevelCount; count++) {
2328                 ci_populate_smc_voltage_table(adev,
2329                                               &pi->vddc_voltage_table.entries[count],
2330                                               &table->VddcLevel[count]);
2331
2332                 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2333                         table->VddcLevel[count].Smio |=
2334                                 pi->vddc_voltage_table.entries[count].smio_low;
2335                 else
2336                         table->VddcLevel[count].Smio = 0;
2337         }
2338         table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount);
2339
2340         return 0;
2341 }
2342
2343 static int ci_populate_smc_vddci_table(struct amdgpu_device *adev,
2344                                        SMU7_Discrete_DpmTable *table)
2345 {
2346         unsigned int count;
2347         struct ci_power_info *pi = ci_get_pi(adev);
2348
2349         table->VddciLevelCount = pi->vddci_voltage_table.count;
2350         for (count = 0; count < table->VddciLevelCount; count++) {
2351                 ci_populate_smc_voltage_table(adev,
2352                                               &pi->vddci_voltage_table.entries[count],
2353                                               &table->VddciLevel[count]);
2354
2355                 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2356                         table->VddciLevel[count].Smio |=
2357                                 pi->vddci_voltage_table.entries[count].smio_low;
2358                 else
2359                         table->VddciLevel[count].Smio = 0;
2360         }
2361         table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount);
2362
2363         return 0;
2364 }
2365
2366 static int ci_populate_smc_mvdd_table(struct amdgpu_device *adev,
2367                                       SMU7_Discrete_DpmTable *table)
2368 {
2369         struct ci_power_info *pi = ci_get_pi(adev);
2370         unsigned int count;
2371
2372         table->MvddLevelCount = pi->mvdd_voltage_table.count;
2373         for (count = 0; count < table->MvddLevelCount; count++) {
2374                 ci_populate_smc_voltage_table(adev,
2375                                               &pi->mvdd_voltage_table.entries[count],
2376                                               &table->MvddLevel[count]);
2377
2378                 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2379                         table->MvddLevel[count].Smio |=
2380                                 pi->mvdd_voltage_table.entries[count].smio_low;
2381                 else
2382                         table->MvddLevel[count].Smio = 0;
2383         }
2384         table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount);
2385
2386         return 0;
2387 }
2388
2389 static int ci_populate_smc_voltage_tables(struct amdgpu_device *adev,
2390                                           SMU7_Discrete_DpmTable *table)
2391 {
2392         int ret;
2393
2394         ret = ci_populate_smc_vddc_table(adev, table);
2395         if (ret)
2396                 return ret;
2397
2398         ret = ci_populate_smc_vddci_table(adev, table);
2399         if (ret)
2400                 return ret;
2401
2402         ret = ci_populate_smc_mvdd_table(adev, table);
2403         if (ret)
2404                 return ret;
2405
2406         return 0;
2407 }
2408
2409 static int ci_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk,
2410                                   SMU7_Discrete_VoltageLevel *voltage)
2411 {
2412         struct ci_power_info *pi = ci_get_pi(adev);
2413         u32 i = 0;
2414
2415         if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
2416                 for (i = 0; i < adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) {
2417                         if (mclk <= adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) {
2418                                 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value;
2419                                 break;
2420                         }
2421                 }
2422
2423                 if (i >= adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count)
2424                         return -EINVAL;
2425         }
2426
2427         return -EINVAL;
2428 }
2429
2430 static int ci_get_std_voltage_value_sidd(struct amdgpu_device *adev,
2431                                          struct atom_voltage_table_entry *voltage_table,
2432                                          u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd)
2433 {
2434         u16 v_index, idx;
2435         bool voltage_found = false;
2436         *std_voltage_hi_sidd = voltage_table->value * VOLTAGE_SCALE;
2437         *std_voltage_lo_sidd = voltage_table->value * VOLTAGE_SCALE;
2438
2439         if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
2440                 return -EINVAL;
2441
2442         if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) {
2443                 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
2444                         if (voltage_table->value ==
2445                             adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
2446                                 voltage_found = true;
2447                                 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
2448                                         idx = v_index;
2449                                 else
2450                                         idx = adev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
2451                                 *std_voltage_lo_sidd =
2452                                         adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
2453                                 *std_voltage_hi_sidd =
2454                                         adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
2455                                 break;
2456                         }
2457                 }
2458
2459                 if (!voltage_found) {
2460                         for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
2461                                 if (voltage_table->value <=
2462                                     adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
2463                                         voltage_found = true;
2464                                         if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
2465                                                 idx = v_index;
2466                                         else
2467                                                 idx = adev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
2468                                         *std_voltage_lo_sidd =
2469                                                 adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
2470                                         *std_voltage_hi_sidd =
2471                                                 adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
2472                                         break;
2473                                 }
2474                         }
2475                 }
2476         }
2477
2478         return 0;
2479 }
2480
2481 static void ci_populate_phase_value_based_on_sclk(struct amdgpu_device *adev,
2482                                                   const struct amdgpu_phase_shedding_limits_table *limits,
2483                                                   u32 sclk,
2484                                                   u32 *phase_shedding)
2485 {
2486         unsigned int i;
2487
2488         *phase_shedding = 1;
2489
2490         for (i = 0; i < limits->count; i++) {
2491                 if (sclk < limits->entries[i].sclk) {
2492                         *phase_shedding = i;
2493                         break;
2494                 }
2495         }
2496 }
2497
2498 static void ci_populate_phase_value_based_on_mclk(struct amdgpu_device *adev,
2499                                                   const struct amdgpu_phase_shedding_limits_table *limits,
2500                                                   u32 mclk,
2501                                                   u32 *phase_shedding)
2502 {
2503         unsigned int i;
2504
2505         *phase_shedding = 1;
2506
2507         for (i = 0; i < limits->count; i++) {
2508                 if (mclk < limits->entries[i].mclk) {
2509                         *phase_shedding = i;
2510                         break;
2511                 }
2512         }
2513 }
2514
2515 static int ci_init_arb_table_index(struct amdgpu_device *adev)
2516 {
2517         struct ci_power_info *pi = ci_get_pi(adev);
2518         u32 tmp;
2519         int ret;
2520
2521         ret = amdgpu_ci_read_smc_sram_dword(adev, pi->arb_table_start,
2522                                      &tmp, pi->sram_end);
2523         if (ret)
2524                 return ret;
2525
2526         tmp &= 0x00FFFFFF;
2527         tmp |= MC_CG_ARB_FREQ_F1 << 24;
2528
2529         return amdgpu_ci_write_smc_sram_dword(adev, pi->arb_table_start,
2530                                        tmp, pi->sram_end);
2531 }
2532
2533 static int ci_get_dependency_volt_by_clk(struct amdgpu_device *adev,
2534                                          struct amdgpu_clock_voltage_dependency_table *allowed_clock_voltage_table,
2535                                          u32 clock, u32 *voltage)
2536 {
2537         u32 i = 0;
2538
2539         if (allowed_clock_voltage_table->count == 0)
2540                 return -EINVAL;
2541
2542         for (i = 0; i < allowed_clock_voltage_table->count; i++) {
2543                 if (allowed_clock_voltage_table->entries[i].clk >= clock) {
2544                         *voltage = allowed_clock_voltage_table->entries[i].v;
2545                         return 0;
2546                 }
2547         }
2548
2549         *voltage = allowed_clock_voltage_table->entries[i-1].v;
2550
2551         return 0;
2552 }
2553
2554 static u8 ci_get_sleep_divider_id_from_clock(u32 sclk, u32 min_sclk_in_sr)
2555 {
2556         u32 i;
2557         u32 tmp;
2558         u32 min = max(min_sclk_in_sr, (u32)CISLAND_MINIMUM_ENGINE_CLOCK);
2559
2560         if (sclk < min)
2561                 return 0;
2562
2563         for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
2564                 tmp = sclk >> i;
2565                 if (tmp >= min || i == 0)
2566                         break;
2567         }
2568
2569         return (u8)i;
2570 }
2571
2572 static int ci_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev)
2573 {
2574         return ci_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
2575 }
2576
2577 static int ci_reset_to_default(struct amdgpu_device *adev)
2578 {
2579         return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
2580                 0 : -EINVAL;
2581 }
2582
2583 static int ci_force_switch_to_arb_f0(struct amdgpu_device *adev)
2584 {
2585         u32 tmp;
2586
2587         tmp = (RREG32_SMC(ixSMC_SCRATCH9) & 0x0000ff00) >> 8;
2588
2589         if (tmp == MC_CG_ARB_FREQ_F0)
2590                 return 0;
2591
2592         return ci_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0);
2593 }
2594
2595 static void ci_register_patching_mc_arb(struct amdgpu_device *adev,
2596                                         const u32 engine_clock,
2597                                         const u32 memory_clock,
2598                                         u32 *dram_timimg2)
2599 {
2600         bool patch;
2601         u32 tmp, tmp2;
2602
2603         tmp = RREG32(mmMC_SEQ_MISC0);
2604         patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
2605
2606         if (patch &&
2607             ((adev->pdev->device == 0x67B0) ||
2608              (adev->pdev->device == 0x67B1))) {
2609                 if ((memory_clock > 100000) && (memory_clock <= 125000)) {
2610                         tmp2 = (((0x31 * engine_clock) / 125000) - 1) & 0xff;
2611                         *dram_timimg2 &= ~0x00ff0000;
2612                         *dram_timimg2 |= tmp2 << 16;
2613                 } else if ((memory_clock > 125000) && (memory_clock <= 137500)) {
2614                         tmp2 = (((0x36 * engine_clock) / 137500) - 1) & 0xff;
2615                         *dram_timimg2 &= ~0x00ff0000;
2616                         *dram_timimg2 |= tmp2 << 16;
2617                 }
2618         }
2619 }
2620
2621 static int ci_populate_memory_timing_parameters(struct amdgpu_device *adev,
2622                                                 u32 sclk,
2623                                                 u32 mclk,
2624                                                 SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs)
2625 {
2626         u32 dram_timing;
2627         u32 dram_timing2;
2628         u32 burst_time;
2629
2630         amdgpu_atombios_set_engine_dram_timings(adev, sclk, mclk);
2631
2632         dram_timing  = RREG32(mmMC_ARB_DRAM_TIMING);
2633         dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2);
2634         burst_time = RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE0_MASK;
2635
2636         ci_register_patching_mc_arb(adev, sclk, mclk, &dram_timing2);
2637
2638         arb_regs->McArbDramTiming  = cpu_to_be32(dram_timing);
2639         arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2);
2640         arb_regs->McArbBurstTime = (u8)burst_time;
2641
2642         return 0;
2643 }
2644
2645 static int ci_do_program_memory_timing_parameters(struct amdgpu_device *adev)
2646 {
2647         struct ci_power_info *pi = ci_get_pi(adev);
2648         SMU7_Discrete_MCArbDramTimingTable arb_regs;
2649         u32 i, j;
2650         int ret =  0;
2651
2652         memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable));
2653
2654         for (i = 0; i < pi->dpm_table.sclk_table.count; i++) {
2655                 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) {
2656                         ret = ci_populate_memory_timing_parameters(adev,
2657                                                                    pi->dpm_table.sclk_table.dpm_levels[i].value,
2658                                                                    pi->dpm_table.mclk_table.dpm_levels[j].value,
2659                                                                    &arb_regs.entries[i][j]);
2660                         if (ret)
2661                                 break;
2662                 }
2663         }
2664
2665         if (ret == 0)
2666                 ret = amdgpu_ci_copy_bytes_to_smc(adev,
2667                                            pi->arb_table_start,
2668                                            (u8 *)&arb_regs,
2669                                            sizeof(SMU7_Discrete_MCArbDramTimingTable),
2670                                            pi->sram_end);
2671
2672         return ret;
2673 }
2674
2675 static int ci_program_memory_timing_parameters(struct amdgpu_device *adev)
2676 {
2677         struct ci_power_info *pi = ci_get_pi(adev);
2678
2679         if (pi->need_update_smu7_dpm_table == 0)
2680                 return 0;
2681
2682         return ci_do_program_memory_timing_parameters(adev);
2683 }
2684
2685 static void ci_populate_smc_initial_state(struct amdgpu_device *adev,
2686                                           struct amdgpu_ps *amdgpu_boot_state)
2687 {
2688         struct ci_ps *boot_state = ci_get_ps(amdgpu_boot_state);
2689         struct ci_power_info *pi = ci_get_pi(adev);
2690         u32 level = 0;
2691
2692         for (level = 0; level < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) {
2693                 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >=
2694                     boot_state->performance_levels[0].sclk) {
2695                         pi->smc_state_table.GraphicsBootLevel = level;
2696                         break;
2697                 }
2698         }
2699
2700         for (level = 0; level < adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) {
2701                 if (adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >=
2702                     boot_state->performance_levels[0].mclk) {
2703                         pi->smc_state_table.MemoryBootLevel = level;
2704                         break;
2705                 }
2706         }
2707 }
2708
2709 static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table)
2710 {
2711         u32 i;
2712         u32 mask_value = 0;
2713
2714         for (i = dpm_table->count; i > 0; i--) {
2715                 mask_value = mask_value << 1;
2716                 if (dpm_table->dpm_levels[i-1].enabled)
2717                         mask_value |= 0x1;
2718                 else
2719                         mask_value &= 0xFFFFFFFE;
2720         }
2721
2722         return mask_value;
2723 }
2724
2725 static void ci_populate_smc_link_level(struct amdgpu_device *adev,
2726                                        SMU7_Discrete_DpmTable *table)
2727 {
2728         struct ci_power_info *pi = ci_get_pi(adev);
2729         struct ci_dpm_table *dpm_table = &pi->dpm_table;
2730         u32 i;
2731
2732         for (i = 0; i < dpm_table->pcie_speed_table.count; i++) {
2733                 table->LinkLevel[i].PcieGenSpeed =
2734                         (u8)dpm_table->pcie_speed_table.dpm_levels[i].value;
2735                 table->LinkLevel[i].PcieLaneCount =
2736                         amdgpu_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
2737                 table->LinkLevel[i].EnabledForActivity = 1;
2738                 table->LinkLevel[i].DownT = cpu_to_be32(5);
2739                 table->LinkLevel[i].UpT = cpu_to_be32(30);
2740         }
2741
2742         pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;
2743         pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
2744                 ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
2745 }
2746
2747 static int ci_populate_smc_uvd_level(struct amdgpu_device *adev,
2748                                      SMU7_Discrete_DpmTable *table)
2749 {
2750         u32 count;
2751         struct atom_clock_dividers dividers;
2752         int ret = -EINVAL;
2753
2754         table->UvdLevelCount =
2755                 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count;
2756
2757         for (count = 0; count < table->UvdLevelCount; count++) {
2758                 table->UvdLevel[count].VclkFrequency =
2759                         adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk;
2760                 table->UvdLevel[count].DclkFrequency =
2761                         adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk;
2762                 table->UvdLevel[count].MinVddc =
2763                         adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2764                 table->UvdLevel[count].MinVddcPhases = 1;
2765
2766                 ret = amdgpu_atombios_get_clock_dividers(adev,
2767                                                          COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2768                                                          table->UvdLevel[count].VclkFrequency, false, &dividers);
2769                 if (ret)
2770                         return ret;
2771
2772                 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;
2773
2774                 ret = amdgpu_atombios_get_clock_dividers(adev,
2775                                                          COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2776                                                          table->UvdLevel[count].DclkFrequency, false, &dividers);
2777                 if (ret)
2778                         return ret;
2779
2780                 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;
2781
2782                 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency);
2783                 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency);
2784                 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc);
2785         }
2786
2787         return ret;
2788 }
2789
2790 static int ci_populate_smc_vce_level(struct amdgpu_device *adev,
2791                                      SMU7_Discrete_DpmTable *table)
2792 {
2793         u32 count;
2794         struct atom_clock_dividers dividers;
2795         int ret = -EINVAL;
2796
2797         table->VceLevelCount =
2798                 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count;
2799
2800         for (count = 0; count < table->VceLevelCount; count++) {
2801                 table->VceLevel[count].Frequency =
2802                         adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk;
2803                 table->VceLevel[count].MinVoltage =
2804                         (u16)adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2805                 table->VceLevel[count].MinPhases = 1;
2806
2807                 ret = amdgpu_atombios_get_clock_dividers(adev,
2808                                                          COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2809                                                          table->VceLevel[count].Frequency, false, &dividers);
2810                 if (ret)
2811                         return ret;
2812
2813                 table->VceLevel[count].Divider = (u8)dividers.post_divider;
2814
2815                 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency);
2816                 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage);
2817         }
2818
2819         return ret;
2820
2821 }
2822
2823 static int ci_populate_smc_acp_level(struct amdgpu_device *adev,
2824                                      SMU7_Discrete_DpmTable *table)
2825 {
2826         u32 count;
2827         struct atom_clock_dividers dividers;
2828         int ret = -EINVAL;
2829
2830         table->AcpLevelCount = (u8)
2831                 (adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count);
2832
2833         for (count = 0; count < table->AcpLevelCount; count++) {
2834                 table->AcpLevel[count].Frequency =
2835                         adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk;
2836                 table->AcpLevel[count].MinVoltage =
2837                         adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v;
2838                 table->AcpLevel[count].MinPhases = 1;
2839
2840                 ret = amdgpu_atombios_get_clock_dividers(adev,
2841                                                          COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2842                                                          table->AcpLevel[count].Frequency, false, &dividers);
2843                 if (ret)
2844                         return ret;
2845
2846                 table->AcpLevel[count].Divider = (u8)dividers.post_divider;
2847
2848                 table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency);
2849                 table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage);
2850         }
2851
2852         return ret;
2853 }
2854
2855 static int ci_populate_smc_samu_level(struct amdgpu_device *adev,
2856                                       SMU7_Discrete_DpmTable *table)
2857 {
2858         u32 count;
2859         struct atom_clock_dividers dividers;
2860         int ret = -EINVAL;
2861
2862         table->SamuLevelCount =
2863                 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count;
2864
2865         for (count = 0; count < table->SamuLevelCount; count++) {
2866                 table->SamuLevel[count].Frequency =
2867                         adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk;
2868                 table->SamuLevel[count].MinVoltage =
2869                         adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2870                 table->SamuLevel[count].MinPhases = 1;
2871
2872                 ret = amdgpu_atombios_get_clock_dividers(adev,
2873                                                          COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2874                                                          table->SamuLevel[count].Frequency, false, &dividers);
2875                 if (ret)
2876                         return ret;
2877
2878                 table->SamuLevel[count].Divider = (u8)dividers.post_divider;
2879
2880                 table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency);
2881                 table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage);
2882         }
2883
2884         return ret;
2885 }
2886
2887 static int ci_calculate_mclk_params(struct amdgpu_device *adev,
2888                                     u32 memory_clock,
2889                                     SMU7_Discrete_MemoryLevel *mclk,
2890                                     bool strobe_mode,
2891                                     bool dll_state_on)
2892 {
2893         struct ci_power_info *pi = ci_get_pi(adev);
2894         u32  dll_cntl = pi->clock_registers.dll_cntl;
2895         u32  mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2896         u32  mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl;
2897         u32  mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl;
2898         u32  mpll_func_cntl = pi->clock_registers.mpll_func_cntl;
2899         u32  mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1;
2900         u32  mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2;
2901         u32  mpll_ss1 = pi->clock_registers.mpll_ss1;
2902         u32  mpll_ss2 = pi->clock_registers.mpll_ss2;
2903         struct atom_mpll_param mpll_param;
2904         int ret;
2905
2906         ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param);
2907         if (ret)
2908                 return ret;
2909
2910         mpll_func_cntl &= ~MPLL_FUNC_CNTL__BWCTRL_MASK;
2911         mpll_func_cntl |= (mpll_param.bwcntl << MPLL_FUNC_CNTL__BWCTRL__SHIFT);
2912
2913         mpll_func_cntl_1 &= ~(MPLL_FUNC_CNTL_1__CLKF_MASK | MPLL_FUNC_CNTL_1__CLKFRAC_MASK |
2914                         MPLL_FUNC_CNTL_1__VCO_MODE_MASK);
2915         mpll_func_cntl_1 |= (mpll_param.clkf) << MPLL_FUNC_CNTL_1__CLKF__SHIFT |
2916                 (mpll_param.clkfrac << MPLL_FUNC_CNTL_1__CLKFRAC__SHIFT) |
2917                 (mpll_param.vco_mode << MPLL_FUNC_CNTL_1__VCO_MODE__SHIFT);
2918
2919         mpll_ad_func_cntl &= ~MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK;
2920         mpll_ad_func_cntl |= (mpll_param.post_div << MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT);
2921
2922         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
2923                 mpll_dq_func_cntl &= ~(MPLL_DQ_FUNC_CNTL__YCLK_SEL_MASK |
2924                                 MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK);
2925                 mpll_dq_func_cntl |= (mpll_param.yclk_sel << MPLL_DQ_FUNC_CNTL__YCLK_SEL__SHIFT) |
2926                                 (mpll_param.post_div << MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT);
2927         }
2928
2929         if (pi->caps_mclk_ss_support) {
2930                 struct amdgpu_atom_ss ss;
2931                 u32 freq_nom;
2932                 u32 tmp;
2933                 u32 reference_clock = adev->clock.mpll.reference_freq;
2934
2935                 if (mpll_param.qdr == 1)
2936                         freq_nom = memory_clock * 4 * (1 << mpll_param.post_div);
2937                 else
2938                         freq_nom = memory_clock * 2 * (1 << mpll_param.post_div);
2939
2940                 tmp = (freq_nom / reference_clock);
2941                 tmp = tmp * tmp;
2942                 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
2943                                                      ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
2944                         u32 clks = reference_clock * 5 / ss.rate;
2945                         u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
2946
2947                         mpll_ss1 &= ~MPLL_SS1__CLKV_MASK;
2948                         mpll_ss1 |= (clkv << MPLL_SS1__CLKV__SHIFT);
2949
2950                         mpll_ss2 &= ~MPLL_SS2__CLKS_MASK;
2951                         mpll_ss2 |= (clks << MPLL_SS2__CLKS__SHIFT);
2952                 }
2953         }
2954
2955         mclk_pwrmgt_cntl &= ~MCLK_PWRMGT_CNTL__DLL_SPEED_MASK;
2956         mclk_pwrmgt_cntl |= (mpll_param.dll_speed << MCLK_PWRMGT_CNTL__DLL_SPEED__SHIFT);
2957
2958         if (dll_state_on)
2959                 mclk_pwrmgt_cntl |= MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK |
2960                         MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK;
2961         else
2962                 mclk_pwrmgt_cntl &= ~(MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK |
2963                         MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK);
2964
2965         mclk->MclkFrequency = memory_clock;
2966         mclk->MpllFuncCntl = mpll_func_cntl;
2967         mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
2968         mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
2969         mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
2970         mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
2971         mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
2972         mclk->DllCntl = dll_cntl;
2973         mclk->MpllSs1 = mpll_ss1;
2974         mclk->MpllSs2 = mpll_ss2;
2975
2976         return 0;
2977 }
2978
2979 static int ci_populate_single_memory_level(struct amdgpu_device *adev,
2980                                            u32 memory_clock,
2981                                            SMU7_Discrete_MemoryLevel *memory_level)
2982 {
2983         struct ci_power_info *pi = ci_get_pi(adev);
2984         int ret;
2985         bool dll_state_on;
2986
2987         if (adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) {
2988                 ret = ci_get_dependency_volt_by_clk(adev,
2989                                                     &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2990                                                     memory_clock, &memory_level->MinVddc);
2991                 if (ret)
2992                         return ret;
2993         }
2994
2995         if (adev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) {
2996                 ret = ci_get_dependency_volt_by_clk(adev,
2997                                                     &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2998                                                     memory_clock, &memory_level->MinVddci);
2999                 if (ret)
3000                         return ret;
3001         }
3002
3003         if (adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) {
3004                 ret = ci_get_dependency_volt_by_clk(adev,
3005                                                     &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
3006                                                     memory_clock, &memory_level->MinMvdd);
3007                 if (ret)
3008                         return ret;
3009         }
3010
3011         memory_level->MinVddcPhases = 1;
3012
3013         if (pi->vddc_phase_shed_control)
3014                 ci_populate_phase_value_based_on_mclk(adev,
3015                                                       &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
3016                                                       memory_clock,
3017                                                       &memory_level->MinVddcPhases);
3018
3019         memory_level->EnabledForThrottle = 1;
3020         memory_level->UpH = 0;
3021         memory_level->DownH = 100;
3022         memory_level->VoltageDownH = 0;
3023         memory_level->ActivityLevel = (u16)pi->mclk_activity_target;
3024
3025         memory_level->StutterEnable = false;
3026         memory_level->StrobeEnable = false;
3027         memory_level->EdcReadEnable = false;
3028         memory_level->EdcWriteEnable = false;
3029         memory_level->RttEnable = false;
3030
3031         memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
3032
3033         if (pi->mclk_stutter_mode_threshold &&
3034             (memory_clock <= pi->mclk_stutter_mode_threshold) &&
3035             (pi->uvd_enabled == false) &&
3036             (RREG32(mmDPG_PIPE_STUTTER_CONTROL) & DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK) &&
3037             (adev->pm.dpm.new_active_crtc_count <= 2))
3038                 memory_level->StutterEnable = true;
3039
3040         if (pi->mclk_strobe_mode_threshold &&
3041             (memory_clock <= pi->mclk_strobe_mode_threshold))
3042                 memory_level->StrobeEnable = 1;
3043
3044         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
3045                 memory_level->StrobeRatio =
3046                         ci_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable);
3047                 if (pi->mclk_edc_enable_threshold &&
3048                     (memory_clock > pi->mclk_edc_enable_threshold))
3049                         memory_level->EdcReadEnable = true;
3050
3051                 if (pi->mclk_edc_wr_enable_threshold &&
3052                     (memory_clock > pi->mclk_edc_wr_enable_threshold))
3053                         memory_level->EdcWriteEnable = true;
3054
3055                 if (memory_level->StrobeEnable) {
3056                         if (ci_get_mclk_frequency_ratio(memory_clock, true) >=
3057                             ((RREG32(mmMC_SEQ_MISC7) >> 16) & 0xf))
3058                                 dll_state_on = ((RREG32(mmMC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
3059                         else
3060                                 dll_state_on = ((RREG32(mmMC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
3061                 } else {
3062                         dll_state_on = pi->dll_default_on;
3063                 }
3064         } else {
3065                 memory_level->StrobeRatio = ci_get_ddr3_mclk_frequency_ratio(memory_clock);
3066                 dll_state_on = ((RREG32(mmMC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
3067         }
3068
3069         ret = ci_calculate_mclk_params(adev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
3070         if (ret)
3071                 return ret;
3072
3073         memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE);
3074         memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases);
3075         memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE);
3076         memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE);
3077
3078         memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency);
3079         memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel);
3080         memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl);
3081         memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1);
3082         memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2);
3083         memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl);
3084         memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl);
3085         memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl);
3086         memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl);
3087         memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1);
3088         memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2);
3089
3090         return 0;
3091 }
3092
3093 static int ci_populate_smc_acpi_level(struct amdgpu_device *adev,
3094                                       SMU7_Discrete_DpmTable *table)
3095 {
3096         struct ci_power_info *pi = ci_get_pi(adev);
3097         struct atom_clock_dividers dividers;
3098         SMU7_Discrete_VoltageLevel voltage_level;
3099         u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl;
3100         u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2;
3101         u32 dll_cntl = pi->clock_registers.dll_cntl;
3102         u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
3103         int ret;
3104
3105         table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
3106
3107         if (pi->acpi_vddc)
3108                 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE);
3109         else
3110                 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE);
3111
3112         table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1;
3113
3114         table->ACPILevel.SclkFrequency = adev->clock.spll.reference_freq;
3115
3116         ret = amdgpu_atombios_get_clock_dividers(adev,
3117                                                  COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
3118                                                  table->ACPILevel.SclkFrequency, false, &dividers);
3119         if (ret)
3120                 return ret;
3121
3122         table->ACPILevel.SclkDid = (u8)dividers.post_divider;
3123         table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
3124         table->ACPILevel.DeepSleepDivId = 0;
3125
3126         spll_func_cntl &= ~CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK;
3127         spll_func_cntl |= CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK;
3128
3129         spll_func_cntl_2 &= ~CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
3130         spll_func_cntl_2 |= (4 << CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT);
3131
3132         table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
3133         table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
3134         table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3;
3135         table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4;
3136         table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum;
3137         table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2;
3138         table->ACPILevel.CcPwrDynRm = 0;
3139         table->ACPILevel.CcPwrDynRm1 = 0;
3140
3141         table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags);
3142         table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases);
3143         table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency);
3144         table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl);
3145         table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2);
3146         table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3);
3147         table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4);
3148         table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum);
3149         table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2);
3150         table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm);
3151         table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1);
3152
3153         table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
3154         table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
3155
3156         if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
3157                 if (pi->acpi_vddci)
3158                         table->MemoryACPILevel.MinVddci =
3159                                 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE);
3160                 else
3161                         table->MemoryACPILevel.MinVddci =
3162                                 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE);
3163         }
3164
3165         if (ci_populate_mvdd_value(adev, 0, &voltage_level))
3166                 table->MemoryACPILevel.MinMvdd = 0;
3167         else
3168                 table->MemoryACPILevel.MinMvdd =
3169                         cpu_to_be32(voltage_level.Voltage * VOLTAGE_SCALE);
3170
3171         mclk_pwrmgt_cntl |= MCLK_PWRMGT_CNTL__MRDCK0_RESET_MASK |
3172                 MCLK_PWRMGT_CNTL__MRDCK1_RESET_MASK;
3173         mclk_pwrmgt_cntl &= ~(MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK |
3174                         MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK);
3175
3176         dll_cntl &= ~(DLL_CNTL__MRDCK0_BYPASS_MASK | DLL_CNTL__MRDCK1_BYPASS_MASK);
3177
3178         table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl);
3179         table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl);
3180         table->MemoryACPILevel.MpllAdFuncCntl =
3181                 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl);
3182         table->MemoryACPILevel.MpllDqFuncCntl =
3183                 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl);
3184         table->MemoryACPILevel.MpllFuncCntl =
3185                 cpu_to_be32(pi->clock_registers.mpll_func_cntl);
3186         table->MemoryACPILevel.MpllFuncCntl_1 =
3187                 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1);
3188         table->MemoryACPILevel.MpllFuncCntl_2 =
3189                 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2);
3190         table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1);
3191         table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2);
3192
3193         table->MemoryACPILevel.EnabledForThrottle = 0;
3194         table->MemoryACPILevel.EnabledForActivity = 0;
3195         table->MemoryACPILevel.UpH = 0;
3196         table->MemoryACPILevel.DownH = 100;
3197         table->MemoryACPILevel.VoltageDownH = 0;
3198         table->MemoryACPILevel.ActivityLevel =
3199                 cpu_to_be16((u16)pi->mclk_activity_target);
3200
3201         table->MemoryACPILevel.StutterEnable = false;
3202         table->MemoryACPILevel.StrobeEnable = false;
3203         table->MemoryACPILevel.EdcReadEnable = false;
3204         table->MemoryACPILevel.EdcWriteEnable = false;
3205         table->MemoryACPILevel.RttEnable = false;
3206
3207         return 0;
3208 }
3209
3210
3211 static int ci_enable_ulv(struct amdgpu_device *adev, bool enable)
3212 {
3213         struct ci_power_info *pi = ci_get_pi(adev);
3214         struct ci_ulv_parm *ulv = &pi->ulv;
3215
3216         if (ulv->supported) {
3217                 if (enable)
3218                         return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
3219                                 0 : -EINVAL;
3220                 else
3221                         return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
3222                                 0 : -EINVAL;
3223         }
3224
3225         return 0;
3226 }
3227
3228 static int ci_populate_ulv_level(struct amdgpu_device *adev,
3229                                  SMU7_Discrete_Ulv *state)
3230 {
3231         struct ci_power_info *pi = ci_get_pi(adev);
3232         u16 ulv_voltage = adev->pm.dpm.backbias_response_time;
3233
3234         state->CcPwrDynRm = 0;
3235         state->CcPwrDynRm1 = 0;
3236
3237         if (ulv_voltage == 0) {
3238                 pi->ulv.supported = false;
3239                 return 0;
3240         }
3241
3242         if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
3243                 if (ulv_voltage > adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
3244                         state->VddcOffset = 0;
3245                 else
3246                         state->VddcOffset =
3247                                 adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage;
3248         } else {
3249                 if (ulv_voltage > adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
3250                         state->VddcOffsetVid = 0;
3251                 else
3252                         state->VddcOffsetVid = (u8)
3253                                 ((adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) *
3254                                  VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
3255         }
3256         state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1;
3257
3258         state->CcPwrDynRm = cpu_to_be32(state->CcPwrDynRm);
3259         state->CcPwrDynRm1 = cpu_to_be32(state->CcPwrDynRm1);
3260         state->VddcOffset = cpu_to_be16(state->VddcOffset);
3261
3262         return 0;
3263 }
3264
3265 static int ci_calculate_sclk_params(struct amdgpu_device *adev,
3266                                     u32 engine_clock,
3267                                     SMU7_Discrete_GraphicsLevel *sclk)
3268 {
3269         struct ci_power_info *pi = ci_get_pi(adev);
3270         struct atom_clock_dividers dividers;
3271         u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3;
3272         u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4;
3273         u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum;
3274         u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2;
3275         u32 reference_clock = adev->clock.spll.reference_freq;
3276         u32 reference_divider;
3277         u32 fbdiv;
3278         int ret;
3279
3280         ret = amdgpu_atombios_get_clock_dividers(adev,
3281                                                  COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
3282                                                  engine_clock, false, &dividers);
3283         if (ret)
3284                 return ret;
3285
3286         reference_divider = 1 + dividers.ref_div;
3287         fbdiv = dividers.fb_div & 0x3FFFFFF;
3288
3289         spll_func_cntl_3 &= ~CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK;
3290         spll_func_cntl_3 |= (fbdiv << CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT);
3291         spll_func_cntl_3 |= CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK;
3292
3293         if (pi->caps_sclk_ss_support) {
3294                 struct amdgpu_atom_ss ss;
3295                 u32 vco_freq = engine_clock * dividers.post_div;
3296
3297                 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
3298                                                      ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
3299                         u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
3300                         u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
3301
3302                         cg_spll_spread_spectrum &= ~(CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK | CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK);
3303                         cg_spll_spread_spectrum |= (clk_s << CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT);
3304                         cg_spll_spread_spectrum |= (1 << CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT);
3305
3306                         cg_spll_spread_spectrum_2 &= ~CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK;
3307                         cg_spll_spread_spectrum_2 |= (clk_v << CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT);
3308                 }
3309         }
3310
3311         sclk->SclkFrequency = engine_clock;
3312         sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
3313         sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
3314         sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
3315         sclk->SpllSpreadSpectrum2  = cg_spll_spread_spectrum_2;
3316         sclk->SclkDid = (u8)dividers.post_divider;
3317
3318         return 0;
3319 }
3320
3321 static int ci_populate_single_graphic_level(struct amdgpu_device *adev,
3322                                             u32 engine_clock,
3323                                             u16 sclk_activity_level_t,
3324                                             SMU7_Discrete_GraphicsLevel *graphic_level)
3325 {
3326         struct ci_power_info *pi = ci_get_pi(adev);
3327         int ret;
3328
3329         ret = ci_calculate_sclk_params(adev, engine_clock, graphic_level);
3330         if (ret)
3331                 return ret;
3332
3333         ret = ci_get_dependency_volt_by_clk(adev,
3334                                             &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3335                                             engine_clock, &graphic_level->MinVddc);
3336         if (ret)
3337                 return ret;
3338
3339         graphic_level->SclkFrequency = engine_clock;
3340
3341         graphic_level->Flags =  0;
3342         graphic_level->MinVddcPhases = 1;
3343
3344         if (pi->vddc_phase_shed_control)
3345                 ci_populate_phase_value_based_on_sclk(adev,
3346                                                       &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
3347                                                       engine_clock,
3348                                                       &graphic_level->MinVddcPhases);
3349
3350         graphic_level->ActivityLevel = sclk_activity_level_t;
3351
3352         graphic_level->CcPwrDynRm = 0;
3353         graphic_level->CcPwrDynRm1 = 0;
3354         graphic_level->EnabledForThrottle = 1;
3355         graphic_level->UpH = 0;
3356         graphic_level->DownH = 0;
3357         graphic_level->VoltageDownH = 0;
3358         graphic_level->PowerThrottle = 0;
3359
3360         if (pi->caps_sclk_ds)
3361                 graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(engine_clock,
3362                                                                                    CISLAND_MINIMUM_ENGINE_CLOCK);
3363
3364         graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
3365
3366         graphic_level->Flags = cpu_to_be32(graphic_level->Flags);
3367         graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE);
3368         graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases);
3369         graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency);
3370         graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel);
3371         graphic_level->CgSpllFuncCntl3 = cpu_to_be32(graphic_level->CgSpllFuncCntl3);
3372         graphic_level->CgSpllFuncCntl4 = cpu_to_be32(graphic_level->CgSpllFuncCntl4);
3373         graphic_level->SpllSpreadSpectrum = cpu_to_be32(graphic_level->SpllSpreadSpectrum);
3374         graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2);
3375         graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm);
3376         graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1);
3377
3378         return 0;
3379 }
3380
3381 static int ci_populate_all_graphic_levels(struct amdgpu_device *adev)
3382 {
3383         struct ci_power_info *pi = ci_get_pi(adev);
3384         struct ci_dpm_table *dpm_table = &pi->dpm_table;
3385         u32 level_array_address = pi->dpm_table_start +
3386                 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
3387         u32 level_array_size = sizeof(SMU7_Discrete_GraphicsLevel) *
3388                 SMU7_MAX_LEVELS_GRAPHICS;
3389         SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel;
3390         u32 i, ret;
3391
3392         memset(levels, 0, level_array_size);
3393
3394         for (i = 0; i < dpm_table->sclk_table.count; i++) {
3395                 ret = ci_populate_single_graphic_level(adev,
3396                                                        dpm_table->sclk_table.dpm_levels[i].value,
3397                                                        (u16)pi->activity_target[i],
3398                                                        &pi->smc_state_table.GraphicsLevel[i]);
3399                 if (ret)
3400                         return ret;
3401                 if (i > 1)
3402                         pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
3403                 if (i == (dpm_table->sclk_table.count - 1))
3404                         pi->smc_state_table.GraphicsLevel[i].DisplayWatermark =
3405                                 PPSMC_DISPLAY_WATERMARK_HIGH;
3406         }
3407         pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
3408
3409         pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
3410         pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
3411                 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
3412
3413         ret = amdgpu_ci_copy_bytes_to_smc(adev, level_array_address,
3414                                    (u8 *)levels, level_array_size,
3415                                    pi->sram_end);
3416         if (ret)
3417                 return ret;
3418
3419         return 0;
3420 }
3421
3422 static int ci_populate_ulv_state(struct amdgpu_device *adev,
3423                                  SMU7_Discrete_Ulv *ulv_level)
3424 {
3425         return ci_populate_ulv_level(adev, ulv_level);
3426 }
3427
3428 static int ci_populate_all_memory_levels(struct amdgpu_device *adev)
3429 {
3430         struct ci_power_info *pi = ci_get_pi(adev);
3431         struct ci_dpm_table *dpm_table = &pi->dpm_table;
3432         u32 level_array_address = pi->dpm_table_start +
3433                 offsetof(SMU7_Discrete_DpmTable, MemoryLevel);
3434         u32 level_array_size = sizeof(SMU7_Discrete_MemoryLevel) *
3435                 SMU7_MAX_LEVELS_MEMORY;
3436         SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel;
3437         u32 i, ret;
3438
3439         memset(levels, 0, level_array_size);
3440
3441         for (i = 0; i < dpm_table->mclk_table.count; i++) {
3442                 if (dpm_table->mclk_table.dpm_levels[i].value == 0)
3443                         return -EINVAL;
3444                 ret = ci_populate_single_memory_level(adev,
3445                                                       dpm_table->mclk_table.dpm_levels[i].value,
3446                                                       &pi->smc_state_table.MemoryLevel[i]);
3447                 if (ret)
3448                         return ret;
3449         }
3450
3451         pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
3452
3453         if ((dpm_table->mclk_table.count >= 2) &&
3454             ((adev->pdev->device == 0x67B0) || (adev->pdev->device == 0x67B1))) {
3455                 pi->smc_state_table.MemoryLevel[1].MinVddc =
3456                         pi->smc_state_table.MemoryLevel[0].MinVddc;
3457                 pi->smc_state_table.MemoryLevel[1].MinVddcPhases =
3458                         pi->smc_state_table.MemoryLevel[0].MinVddcPhases;
3459         }
3460
3461         pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F);
3462
3463         pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count;
3464         pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
3465                 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
3466
3467         pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark =
3468                 PPSMC_DISPLAY_WATERMARK_HIGH;
3469
3470         ret = amdgpu_ci_copy_bytes_to_smc(adev, level_array_address,
3471                                    (u8 *)levels, level_array_size,
3472                                    pi->sram_end);
3473         if (ret)
3474                 return ret;
3475
3476         return 0;
3477 }
3478
3479 static void ci_reset_single_dpm_table(struct amdgpu_device *adev,
3480                                       struct ci_single_dpm_table* dpm_table,
3481                                       u32 count)
3482 {
3483         u32 i;
3484
3485         dpm_table->count = count;
3486         for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
3487                 dpm_table->dpm_levels[i].enabled = false;
3488 }
3489
3490 static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table,
3491                                       u32 index, u32 pcie_gen, u32 pcie_lanes)
3492 {
3493         dpm_table->dpm_levels[index].value = pcie_gen;
3494         dpm_table->dpm_levels[index].param1 = pcie_lanes;
3495         dpm_table->dpm_levels[index].enabled = true;
3496 }
3497
3498 static int ci_setup_default_pcie_tables(struct amdgpu_device *adev)
3499 {
3500         struct ci_power_info *pi = ci_get_pi(adev);
3501
3502         if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels)
3503                 return -EINVAL;
3504
3505         if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) {
3506                 pi->pcie_gen_powersaving = pi->pcie_gen_performance;
3507                 pi->pcie_lane_powersaving = pi->pcie_lane_performance;
3508         } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) {
3509                 pi->pcie_gen_performance = pi->pcie_gen_powersaving;
3510                 pi->pcie_lane_performance = pi->pcie_lane_powersaving;
3511         }
3512
3513         ci_reset_single_dpm_table(adev,
3514                                   &pi->dpm_table.pcie_speed_table,
3515                                   SMU7_MAX_LEVELS_LINK);
3516
3517         if (adev->asic_type == CHIP_BONAIRE)
3518                 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
3519                                           pi->pcie_gen_powersaving.min,
3520                                           pi->pcie_lane_powersaving.max);
3521         else
3522                 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
3523                                           pi->pcie_gen_powersaving.min,
3524                                           pi->pcie_lane_powersaving.min);
3525         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1,
3526                                   pi->pcie_gen_performance.min,
3527                                   pi->pcie_lane_performance.min);
3528         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2,
3529                                   pi->pcie_gen_powersaving.min,
3530                                   pi->pcie_lane_powersaving.max);
3531         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3,
3532                                   pi->pcie_gen_performance.min,
3533                                   pi->pcie_lane_performance.max);
3534         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4,
3535                                   pi->pcie_gen_powersaving.max,
3536                                   pi->pcie_lane_powersaving.max);
3537         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5,
3538                                   pi->pcie_gen_performance.max,
3539                                   pi->pcie_lane_performance.max);
3540
3541         pi->dpm_table.pcie_speed_table.count = 6;
3542
3543         return 0;
3544 }
3545
3546 static int ci_setup_default_dpm_tables(struct amdgpu_device *adev)
3547 {
3548         struct ci_power_info *pi = ci_get_pi(adev);
3549         struct amdgpu_clock_voltage_dependency_table *allowed_sclk_vddc_table =
3550                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3551         struct amdgpu_clock_voltage_dependency_table *allowed_mclk_table =
3552                 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
3553         struct amdgpu_cac_leakage_table *std_voltage_table =
3554                 &adev->pm.dpm.dyn_state.cac_leakage_table;
3555         u32 i;
3556
3557         if (allowed_sclk_vddc_table == NULL)
3558                 return -EINVAL;
3559         if (allowed_sclk_vddc_table->count < 1)
3560                 return -EINVAL;
3561         if (allowed_mclk_table == NULL)
3562                 return -EINVAL;
3563         if (allowed_mclk_table->count < 1)
3564                 return -EINVAL;
3565
3566         memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table));
3567
3568         ci_reset_single_dpm_table(adev,
3569                                   &pi->dpm_table.sclk_table,
3570                                   SMU7_MAX_LEVELS_GRAPHICS);
3571         ci_reset_single_dpm_table(adev,
3572                                   &pi->dpm_table.mclk_table,
3573                                   SMU7_MAX_LEVELS_MEMORY);
3574         ci_reset_single_dpm_table(adev,
3575                                   &pi->dpm_table.vddc_table,
3576                                   SMU7_MAX_LEVELS_VDDC);
3577         ci_reset_single_dpm_table(adev,
3578                                   &pi->dpm_table.vddci_table,
3579                                   SMU7_MAX_LEVELS_VDDCI);
3580         ci_reset_single_dpm_table(adev,
3581                                   &pi->dpm_table.mvdd_table,
3582                                   SMU7_MAX_LEVELS_MVDD);
3583
3584         pi->dpm_table.sclk_table.count = 0;
3585         for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3586                 if ((i == 0) ||
3587                     (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value !=
3588                      allowed_sclk_vddc_table->entries[i].clk)) {
3589                         pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value =
3590                                 allowed_sclk_vddc_table->entries[i].clk;
3591                         pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled =
3592                                 (i == 0) ? true : false;
3593                         pi->dpm_table.sclk_table.count++;
3594                 }
3595         }
3596
3597         pi->dpm_table.mclk_table.count = 0;
3598         for (i = 0; i < allowed_mclk_table->count; i++) {
3599                 if ((i == 0) ||
3600                     (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value !=
3601                      allowed_mclk_table->entries[i].clk)) {
3602                         pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value =
3603                                 allowed_mclk_table->entries[i].clk;
3604                         pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled =
3605                                 (i == 0) ? true : false;
3606                         pi->dpm_table.mclk_table.count++;
3607                 }
3608         }
3609
3610         for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3611                 pi->dpm_table.vddc_table.dpm_levels[i].value =
3612                         allowed_sclk_vddc_table->entries[i].v;
3613                 pi->dpm_table.vddc_table.dpm_levels[i].param1 =
3614                         std_voltage_table->entries[i].leakage;
3615                 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true;
3616         }
3617         pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count;
3618
3619         allowed_mclk_table = &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
3620         if (allowed_mclk_table) {
3621                 for (i = 0; i < allowed_mclk_table->count; i++) {
3622                         pi->dpm_table.vddci_table.dpm_levels[i].value =
3623                                 allowed_mclk_table->entries[i].v;
3624                         pi->dpm_table.vddci_table.dpm_levels[i].enabled = true;
3625                 }
3626                 pi->dpm_table.vddci_table.count = allowed_mclk_table->count;
3627         }
3628
3629         allowed_mclk_table = &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk;
3630         if (allowed_mclk_table) {
3631                 for (i = 0; i < allowed_mclk_table->count; i++) {
3632                         pi->dpm_table.mvdd_table.dpm_levels[i].value =
3633                                 allowed_mclk_table->entries[i].v;
3634                         pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true;
3635                 }
3636                 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count;
3637         }
3638
3639         ci_setup_default_pcie_tables(adev);
3640
3641         return 0;
3642 }
3643
3644 static int ci_find_boot_level(struct ci_single_dpm_table *table,
3645                               u32 value, u32 *boot_level)
3646 {
3647         u32 i;
3648         int ret = -EINVAL;
3649
3650         for(i = 0; i < table->count; i++) {
3651                 if (value == table->dpm_levels[i].value) {
3652                         *boot_level = i;
3653                         ret = 0;
3654                 }
3655         }
3656
3657         return ret;
3658 }
3659
3660 static int ci_init_smc_table(struct amdgpu_device *adev)
3661 {
3662         struct ci_power_info *pi = ci_get_pi(adev);
3663         struct ci_ulv_parm *ulv = &pi->ulv;
3664         struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps;
3665         SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
3666         int ret;
3667
3668         ret = ci_setup_default_dpm_tables(adev);
3669         if (ret)
3670                 return ret;
3671
3672         if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE)
3673                 ci_populate_smc_voltage_tables(adev, table);
3674
3675         ci_init_fps_limits(adev);
3676
3677         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
3678                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
3679
3680         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
3681                 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
3682
3683         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
3684                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
3685
3686         if (ulv->supported) {
3687                 ret = ci_populate_ulv_state(adev, &pi->smc_state_table.Ulv);
3688                 if (ret)
3689                         return ret;
3690                 WREG32_SMC(ixCG_ULV_PARAMETER, ulv->cg_ulv_parameter);
3691         }
3692
3693         ret = ci_populate_all_graphic_levels(adev);
3694         if (ret)
3695                 return ret;
3696
3697         ret = ci_populate_all_memory_levels(adev);
3698         if (ret)
3699                 return ret;
3700
3701         ci_populate_smc_link_level(adev, table);
3702
3703         ret = ci_populate_smc_acpi_level(adev, table);
3704         if (ret)
3705                 return ret;
3706
3707         ret = ci_populate_smc_vce_level(adev, table);
3708         if (ret)
3709                 return ret;
3710
3711         ret = ci_populate_smc_acp_level(adev, table);
3712         if (ret)
3713                 return ret;
3714
3715         ret = ci_populate_smc_samu_level(adev, table);
3716         if (ret)
3717                 return ret;
3718
3719         ret = ci_do_program_memory_timing_parameters(adev);
3720         if (ret)
3721                 return ret;
3722
3723         ret = ci_populate_smc_uvd_level(adev, table);
3724         if (ret)
3725                 return ret;
3726
3727         table->UvdBootLevel  = 0;
3728         table->VceBootLevel  = 0;
3729         table->AcpBootLevel  = 0;
3730         table->SamuBootLevel  = 0;
3731         table->GraphicsBootLevel  = 0;
3732         table->MemoryBootLevel  = 0;
3733
3734         ret = ci_find_boot_level(&pi->dpm_table.sclk_table,
3735                                  pi->vbios_boot_state.sclk_bootup_value,
3736                                  (u32 *)&pi->smc_state_table.GraphicsBootLevel);
3737
3738         ret = ci_find_boot_level(&pi->dpm_table.mclk_table,
3739                                  pi->vbios_boot_state.mclk_bootup_value,
3740                                  (u32 *)&pi->smc_state_table.MemoryBootLevel);
3741
3742         table->BootVddc = pi->vbios_boot_state.vddc_bootup_value;
3743         table->BootVddci = pi->vbios_boot_state.vddci_bootup_value;
3744         table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value;
3745
3746         ci_populate_smc_initial_state(adev, amdgpu_boot_state);
3747
3748         ret = ci_populate_bapm_parameters_in_dpm_table(adev);
3749         if (ret)
3750                 return ret;
3751
3752         table->UVDInterval = 1;
3753         table->VCEInterval = 1;
3754         table->ACPInterval = 1;
3755         table->SAMUInterval = 1;
3756         table->GraphicsVoltageChangeEnable = 1;
3757         table->GraphicsThermThrottleEnable = 1;
3758         table->GraphicsInterval = 1;
3759         table->VoltageInterval = 1;
3760         table->ThermalInterval = 1;
3761         table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high *
3762                                              CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3763         table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low *
3764                                             CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3765         table->MemoryVoltageChangeEnable = 1;
3766         table->MemoryInterval = 1;
3767         table->VoltageResponseTime = 0;
3768         table->VddcVddciDelta = 4000;
3769         table->PhaseResponseTime = 0;
3770         table->MemoryThermThrottleEnable = 1;
3771         table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1;
3772         table->PCIeGenInterval = 1;
3773         if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2)
3774                 table->SVI2Enable  = 1;
3775         else
3776                 table->SVI2Enable  = 0;
3777
3778         table->ThermGpio = 17;
3779         table->SclkStepSize = 0x4000;
3780
3781         table->SystemFlags = cpu_to_be32(table->SystemFlags);
3782         table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid);
3783         table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase);
3784         table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid);
3785         table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid);
3786         table->SclkStepSize = cpu_to_be32(table->SclkStepSize);
3787         table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh);
3788         table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow);
3789         table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta);
3790         table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime);
3791         table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime);
3792         table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE);
3793         table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE);
3794         table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE);
3795
3796         ret = amdgpu_ci_copy_bytes_to_smc(adev,
3797                                    pi->dpm_table_start +
3798                                    offsetof(SMU7_Discrete_DpmTable, SystemFlags),
3799                                    (u8 *)&table->SystemFlags,
3800                                    sizeof(SMU7_Discrete_DpmTable) - 3 * sizeof(SMU7_PIDController),
3801                                    pi->sram_end);
3802         if (ret)
3803                 return ret;
3804
3805         return 0;
3806 }
3807
3808 static void ci_trim_single_dpm_states(struct amdgpu_device *adev,
3809                                       struct ci_single_dpm_table *dpm_table,
3810                                       u32 low_limit, u32 high_limit)
3811 {
3812         u32 i;
3813
3814         for (i = 0; i < dpm_table->count; i++) {
3815                 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3816                     (dpm_table->dpm_levels[i].value > high_limit))
3817                         dpm_table->dpm_levels[i].enabled = false;
3818                 else
3819                         dpm_table->dpm_levels[i].enabled = true;
3820         }
3821 }
3822
3823 static void ci_trim_pcie_dpm_states(struct amdgpu_device *adev,
3824                                     u32 speed_low, u32 lanes_low,
3825                                     u32 speed_high, u32 lanes_high)
3826 {
3827         struct ci_power_info *pi = ci_get_pi(adev);
3828         struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;
3829         u32 i, j;
3830
3831         for (i = 0; i < pcie_table->count; i++) {
3832                 if ((pcie_table->dpm_levels[i].value < speed_low) ||
3833                     (pcie_table->dpm_levels[i].param1 < lanes_low) ||
3834                     (pcie_table->dpm_levels[i].value > speed_high) ||
3835                     (pcie_table->dpm_levels[i].param1 > lanes_high))
3836                         pcie_table->dpm_levels[i].enabled = false;
3837                 else
3838                         pcie_table->dpm_levels[i].enabled = true;
3839         }
3840
3841         for (i = 0; i < pcie_table->count; i++) {
3842                 if (pcie_table->dpm_levels[i].enabled) {
3843                         for (j = i + 1; j < pcie_table->count; j++) {
3844                                 if (pcie_table->dpm_levels[j].enabled) {
3845                                         if ((pcie_table->dpm_levels[i].value == pcie_table->dpm_levels[j].value) &&
3846                                             (pcie_table->dpm_levels[i].param1 == pcie_table->dpm_levels[j].param1))
3847                                                 pcie_table->dpm_levels[j].enabled = false;
3848                                 }
3849                         }
3850                 }
3851         }
3852 }
3853
3854 static int ci_trim_dpm_states(struct amdgpu_device *adev,
3855                               struct amdgpu_ps *amdgpu_state)
3856 {
3857         struct ci_ps *state = ci_get_ps(amdgpu_state);
3858         struct ci_power_info *pi = ci_get_pi(adev);
3859         u32 high_limit_count;
3860
3861         if (state->performance_level_count < 1)
3862                 return -EINVAL;
3863
3864         if (state->performance_level_count == 1)
3865                 high_limit_count = 0;
3866         else
3867                 high_limit_count = 1;
3868
3869         ci_trim_single_dpm_states(adev,
3870                                   &pi->dpm_table.sclk_table,
3871                                   state->performance_levels[0].sclk,
3872                                   state->performance_levels[high_limit_count].sclk);
3873
3874         ci_trim_single_dpm_states(adev,
3875                                   &pi->dpm_table.mclk_table,
3876                                   state->performance_levels[0].mclk,
3877                                   state->performance_levels[high_limit_count].mclk);
3878
3879         ci_trim_pcie_dpm_states(adev,
3880                                 state->performance_levels[0].pcie_gen,
3881                                 state->performance_levels[0].pcie_lane,
3882                                 state->performance_levels[high_limit_count].pcie_gen,
3883                                 state->performance_levels[high_limit_count].pcie_lane);
3884
3885         return 0;
3886 }
3887
3888 static int ci_apply_disp_minimum_voltage_request(struct amdgpu_device *adev)
3889 {
3890         struct amdgpu_clock_voltage_dependency_table *disp_voltage_table =
3891                 &adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk;
3892         struct amdgpu_clock_voltage_dependency_table *vddc_table =
3893                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3894         u32 requested_voltage = 0;
3895         u32 i;
3896
3897         if (disp_voltage_table == NULL)
3898                 return -EINVAL;
3899         if (!disp_voltage_table->count)
3900                 return -EINVAL;
3901
3902         for (i = 0; i < disp_voltage_table->count; i++) {
3903                 if (adev->clock.current_dispclk == disp_voltage_table->entries[i].clk)
3904                         requested_voltage = disp_voltage_table->entries[i].v;
3905         }
3906
3907         for (i = 0; i < vddc_table->count; i++) {
3908                 if (requested_voltage <= vddc_table->entries[i].v) {
3909                         requested_voltage = vddc_table->entries[i].v;
3910                         return (amdgpu_ci_send_msg_to_smc_with_parameter(adev,
3911                                                                   PPSMC_MSG_VddC_Request,
3912                                                                   requested_voltage * VOLTAGE_SCALE) == PPSMC_Result_OK) ?
3913                                 0 : -EINVAL;
3914                 }
3915         }
3916
3917         return -EINVAL;
3918 }
3919
3920 static int ci_upload_dpm_level_enable_mask(struct amdgpu_device *adev)
3921 {
3922         struct ci_power_info *pi = ci_get_pi(adev);
3923         PPSMC_Result result;
3924
3925         ci_apply_disp_minimum_voltage_request(adev);
3926
3927         if (!pi->sclk_dpm_key_disabled) {
3928                 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3929                         result = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
3930                                                                    PPSMC_MSG_SCLKDPM_SetEnabledMask,
3931                                                                    pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
3932                         if (result != PPSMC_Result_OK)
3933                                 return -EINVAL;
3934                 }
3935         }
3936
3937         if (!pi->mclk_dpm_key_disabled) {
3938                 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3939                         result = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
3940                                                                    PPSMC_MSG_MCLKDPM_SetEnabledMask,
3941                                                                    pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3942                         if (result != PPSMC_Result_OK)
3943                                 return -EINVAL;
3944                 }
3945         }
3946
3947 #if 0
3948         if (!pi->pcie_dpm_key_disabled) {
3949                 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3950                         result = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
3951                                                                    PPSMC_MSG_PCIeDPM_SetEnabledMask,
3952                                                                    pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
3953                         if (result != PPSMC_Result_OK)
3954                                 return -EINVAL;
3955                 }
3956         }
3957 #endif
3958
3959         return 0;
3960 }
3961
3962 static void ci_find_dpm_states_clocks_in_dpm_table(struct amdgpu_device *adev,
3963                                                    struct amdgpu_ps *amdgpu_state)
3964 {
3965         struct ci_power_info *pi = ci_get_pi(adev);
3966         struct ci_ps *state = ci_get_ps(amdgpu_state);
3967         struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;
3968         u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3969         struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;
3970         u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3971         u32 i;
3972
3973         pi->need_update_smu7_dpm_table = 0;
3974
3975         for (i = 0; i < sclk_table->count; i++) {
3976                 if (sclk == sclk_table->dpm_levels[i].value)
3977                         break;
3978         }
3979
3980         if (i >= sclk_table->count) {
3981                 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3982         } else {
3983                 /* XXX check display min clock requirements */
3984                 if (CISLAND_MINIMUM_ENGINE_CLOCK != CISLAND_MINIMUM_ENGINE_CLOCK)
3985                         pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3986         }
3987
3988         for (i = 0; i < mclk_table->count; i++) {
3989                 if (mclk == mclk_table->dpm_levels[i].value)
3990                         break;
3991         }
3992
3993         if (i >= mclk_table->count)
3994                 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3995
3996         if (adev->pm.dpm.current_active_crtc_count !=
3997             adev->pm.dpm.new_active_crtc_count)
3998                 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
3999 }
4000
4001 static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct amdgpu_device *adev,
4002                                                        struct amdgpu_ps *amdgpu_state)
4003 {
4004         struct ci_power_info *pi = ci_get_pi(adev);
4005         struct ci_ps *state = ci_get_ps(amdgpu_state);
4006         u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
4007         u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
4008         struct ci_dpm_table *dpm_table = &pi->dpm_table;
4009         int ret;
4010
4011         if (!pi->need_update_smu7_dpm_table)
4012                 return 0;
4013
4014         if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK)
4015                 dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk;
4016
4017         if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)
4018                 dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk;
4019
4020         if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) {
4021                 ret = ci_populate_all_graphic_levels(adev);
4022                 if (ret)
4023                         return ret;
4024         }
4025
4026         if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) {
4027                 ret = ci_populate_all_memory_levels(adev);
4028                 if (ret)
4029                         return ret;
4030         }
4031
4032         return 0;
4033 }
4034
4035 static int ci_enable_uvd_dpm(struct amdgpu_device *adev, bool enable)
4036 {
4037         struct ci_power_info *pi = ci_get_pi(adev);
4038         const struct amdgpu_clock_and_voltage_limits *max_limits;
4039         int i;
4040
4041         if (adev->pm.dpm.ac_power)
4042                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4043         else
4044                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4045
4046         if (enable) {
4047                 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0;
4048
4049                 for (i = adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4050                         if (adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4051                                 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i;
4052
4053                                 if (!pi->caps_uvd_dpm)
4054                                         break;
4055                         }
4056                 }
4057
4058                 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4059                                                   PPSMC_MSG_UVDDPM_SetEnabledMask,
4060                                                   pi->dpm_level_enable_mask.uvd_dpm_enable_mask);
4061
4062                 if (pi->last_mclk_dpm_enable_mask & 0x1) {
4063                         pi->uvd_enabled = true;
4064                         pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
4065                         amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4066                                                           PPSMC_MSG_MCLKDPM_SetEnabledMask,
4067                                                           pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
4068                 }
4069         } else {
4070                 if (pi->last_mclk_dpm_enable_mask & 0x1) {
4071                         pi->uvd_enabled = false;
4072                         pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1;
4073                         amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4074                                                           PPSMC_MSG_MCLKDPM_SetEnabledMask,
4075                                                           pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
4076                 }
4077         }
4078
4079         return (amdgpu_ci_send_msg_to_smc(adev, enable ?
4080                                    PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable) == PPSMC_Result_OK) ?
4081                 0 : -EINVAL;
4082 }
4083
4084 static int ci_enable_vce_dpm(struct amdgpu_device *adev, bool enable)
4085 {
4086         struct ci_power_info *pi = ci_get_pi(adev);
4087         const struct amdgpu_clock_and_voltage_limits *max_limits;
4088         int i;
4089
4090         if (adev->pm.dpm.ac_power)
4091                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4092         else
4093                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4094
4095         if (enable) {
4096                 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0;
4097                 for (i = adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4098                         if (adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4099                                 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i;
4100
4101                                 if (!pi->caps_vce_dpm)
4102                                         break;
4103                         }
4104                 }
4105
4106                 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4107                                                   PPSMC_MSG_VCEDPM_SetEnabledMask,
4108                                                   pi->dpm_level_enable_mask.vce_dpm_enable_mask);
4109         }
4110
4111         return (amdgpu_ci_send_msg_to_smc(adev, enable ?
4112                                    PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable) == PPSMC_Result_OK) ?
4113                 0 : -EINVAL;
4114 }
4115
4116 #if 0
4117 static int ci_enable_samu_dpm(struct amdgpu_device *adev, bool enable)
4118 {
4119         struct ci_power_info *pi = ci_get_pi(adev);
4120         const struct amdgpu_clock_and_voltage_limits *max_limits;
4121         int i;
4122
4123         if (adev->pm.dpm.ac_power)
4124                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4125         else
4126                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4127
4128         if (enable) {
4129                 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
4130                 for (i = adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4131                         if (adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4132                                 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
4133
4134                                 if (!pi->caps_samu_dpm)
4135                                         break;
4136                         }
4137                 }
4138
4139                 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4140                                                   PPSMC_MSG_SAMUDPM_SetEnabledMask,
4141                                                   pi->dpm_level_enable_mask.samu_dpm_enable_mask);
4142         }
4143         return (amdgpu_ci_send_msg_to_smc(adev, enable ?
4144                                    PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable) == PPSMC_Result_OK) ?
4145                 0 : -EINVAL;
4146 }
4147
4148 static int ci_enable_acp_dpm(struct amdgpu_device *adev, bool enable)
4149 {
4150         struct ci_power_info *pi = ci_get_pi(adev);
4151         const struct amdgpu_clock_and_voltage_limits *max_limits;
4152         int i;
4153
4154         if (adev->pm.dpm.ac_power)
4155                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4156         else
4157                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4158
4159         if (enable) {
4160                 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
4161                 for (i = adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4162                         if (adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4163                                 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
4164
4165                                 if (!pi->caps_acp_dpm)
4166                                         break;
4167                         }
4168                 }
4169
4170                 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4171                                                   PPSMC_MSG_ACPDPM_SetEnabledMask,
4172                                                   pi->dpm_level_enable_mask.acp_dpm_enable_mask);
4173         }
4174
4175         return (amdgpu_ci_send_msg_to_smc(adev, enable ?
4176                                    PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable) == PPSMC_Result_OK) ?
4177                 0 : -EINVAL;
4178 }
4179 #endif
4180
4181 static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate)
4182 {
4183         struct ci_power_info *pi = ci_get_pi(adev);
4184         u32 tmp;
4185
4186         if (!gate) {
4187                 if (pi->caps_uvd_dpm ||
4188                     (adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0))
4189                         pi->smc_state_table.UvdBootLevel = 0;
4190                 else
4191                         pi->smc_state_table.UvdBootLevel =
4192                                 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1;
4193
4194                 tmp = RREG32_SMC(ixDPM_TABLE_475);
4195                 tmp &= ~DPM_TABLE_475__UvdBootLevel_MASK;
4196                 tmp |= (pi->smc_state_table.UvdBootLevel << DPM_TABLE_475__UvdBootLevel__SHIFT);
4197                 WREG32_SMC(ixDPM_TABLE_475, tmp);
4198         }
4199
4200         return ci_enable_uvd_dpm(adev, !gate);
4201 }
4202
4203 static u8 ci_get_vce_boot_level(struct amdgpu_device *adev)
4204 {
4205         u8 i;
4206         u32 min_evclk = 30000; /* ??? */
4207         struct amdgpu_vce_clock_voltage_dependency_table *table =
4208                 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
4209
4210         for (i = 0; i < table->count; i++) {
4211                 if (table->entries[i].evclk >= min_evclk)
4212                         return i;
4213         }
4214
4215         return table->count - 1;
4216 }
4217
4218 static int ci_update_vce_dpm(struct amdgpu_device *adev,
4219                              struct amdgpu_ps *amdgpu_new_state,
4220                              struct amdgpu_ps *amdgpu_current_state)
4221 {
4222         struct ci_power_info *pi = ci_get_pi(adev);
4223         int ret = 0;
4224         u32 tmp;
4225
4226         if (amdgpu_current_state->evclk != amdgpu_new_state->evclk) {
4227                 if (amdgpu_new_state->evclk) {
4228                         /* turn the clocks on when encoding */
4229                         ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
4230                                                             AMD_CG_STATE_UNGATE);
4231                         if (ret)
4232                                 return ret;
4233
4234                         pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(adev);
4235                         tmp = RREG32_SMC(ixDPM_TABLE_475);
4236                         tmp &= ~DPM_TABLE_475__VceBootLevel_MASK;
4237                         tmp |= (pi->smc_state_table.VceBootLevel << DPM_TABLE_475__VceBootLevel__SHIFT);
4238                         WREG32_SMC(ixDPM_TABLE_475, tmp);
4239
4240                         ret = ci_enable_vce_dpm(adev, true);
4241                 } else {
4242                         /* turn the clocks off when not encoding */
4243                         ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
4244                                                             AMD_CG_STATE_GATE);
4245                         if (ret)
4246                                 return ret;
4247
4248                         ret = ci_enable_vce_dpm(adev, false);
4249                 }
4250         }
4251         return ret;
4252 }
4253
4254 #if 0
4255 static int ci_update_samu_dpm(struct amdgpu_device *adev, bool gate)
4256 {
4257         return ci_enable_samu_dpm(adev, gate);
4258 }
4259
4260 static int ci_update_acp_dpm(struct amdgpu_device *adev, bool gate)
4261 {
4262         struct ci_power_info *pi = ci_get_pi(adev);
4263         u32 tmp;
4264
4265         if (!gate) {
4266                 pi->smc_state_table.AcpBootLevel = 0;
4267
4268                 tmp = RREG32_SMC(ixDPM_TABLE_475);
4269                 tmp &= ~AcpBootLevel_MASK;
4270                 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
4271                 WREG32_SMC(ixDPM_TABLE_475, tmp);
4272         }
4273
4274         return ci_enable_acp_dpm(adev, !gate);
4275 }
4276 #endif
4277
4278 static int ci_generate_dpm_level_enable_mask(struct amdgpu_device *adev,
4279                                              struct amdgpu_ps *amdgpu_state)
4280 {
4281         struct ci_power_info *pi = ci_get_pi(adev);
4282         int ret;
4283
4284         ret = ci_trim_dpm_states(adev, amdgpu_state);
4285         if (ret)
4286                 return ret;
4287
4288         pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
4289                 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table);
4290         pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
4291                 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table);
4292         pi->last_mclk_dpm_enable_mask =
4293                 pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
4294         if (pi->uvd_enabled) {
4295                 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)
4296                         pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
4297         }
4298         pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
4299                 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table);
4300
4301         return 0;
4302 }
4303
4304 static u32 ci_get_lowest_enabled_level(struct amdgpu_device *adev,
4305                                        u32 level_mask)
4306 {
4307         u32 level = 0;
4308
4309         while ((level_mask & (1 << level)) == 0)
4310                 level++;
4311
4312         return level;
4313 }
4314
4315
4316 static int ci_dpm_force_performance_level(struct amdgpu_device *adev,
4317                                           enum amdgpu_dpm_forced_level level)
4318 {
4319         struct ci_power_info *pi = ci_get_pi(adev);
4320         u32 tmp, levels, i;
4321         int ret;
4322
4323         if (level == AMDGPU_DPM_FORCED_LEVEL_HIGH) {
4324                 if ((!pi->pcie_dpm_key_disabled) &&
4325                     pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
4326                         levels = 0;
4327                         tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
4328                         while (tmp >>= 1)
4329                                 levels++;
4330                         if (levels) {
4331                                 ret = ci_dpm_force_state_pcie(adev, level);
4332                                 if (ret)
4333                                         return ret;
4334                                 for (i = 0; i < adev->usec_timeout; i++) {
4335                                         tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_1) &
4336                                         TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK) >>
4337                                         TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT;
4338                                         if (tmp == levels)
4339                                                 break;
4340                                         udelay(1);
4341                                 }
4342                         }
4343                 }
4344                 if ((!pi->sclk_dpm_key_disabled) &&
4345                     pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4346                         levels = 0;
4347                         tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;
4348                         while (tmp >>= 1)
4349                                 levels++;
4350                         if (levels) {
4351                                 ret = ci_dpm_force_state_sclk(adev, levels);
4352                                 if (ret)
4353                                         return ret;
4354                                 for (i = 0; i < adev->usec_timeout; i++) {
4355                                         tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
4356                                         TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
4357                                         TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
4358                                         if (tmp == levels)
4359                                                 break;
4360                                         udelay(1);
4361                                 }
4362                         }
4363                 }
4364                 if ((!pi->mclk_dpm_key_disabled) &&
4365                     pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4366                         levels = 0;
4367                         tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
4368                         while (tmp >>= 1)
4369                                 levels++;
4370                         if (levels) {
4371                                 ret = ci_dpm_force_state_mclk(adev, levels);
4372                                 if (ret)
4373                                         return ret;
4374                                 for (i = 0; i < adev->usec_timeout; i++) {
4375                                         tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
4376                                         TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK) >>
4377                                         TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT;
4378                                         if (tmp == levels)
4379                                                 break;
4380                                         udelay(1);
4381                                 }
4382                         }
4383                 }
4384         } else if (level == AMDGPU_DPM_FORCED_LEVEL_LOW) {
4385                 if ((!pi->sclk_dpm_key_disabled) &&
4386                     pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4387                         levels = ci_get_lowest_enabled_level(adev,
4388                                                              pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
4389                         ret = ci_dpm_force_state_sclk(adev, levels);
4390                         if (ret)
4391                                 return ret;
4392                         for (i = 0; i < adev->usec_timeout; i++) {
4393                                 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
4394                                 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
4395                                 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
4396                                 if (tmp == levels)
4397                                         break;
4398                                 udelay(1);
4399                         }
4400                 }
4401                 if ((!pi->mclk_dpm_key_disabled) &&
4402                     pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4403                         levels = ci_get_lowest_enabled_level(adev,
4404                                                              pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
4405                         ret = ci_dpm_force_state_mclk(adev, levels);
4406                         if (ret)
4407                                 return ret;
4408                         for (i = 0; i < adev->usec_timeout; i++) {
4409                                 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
4410                                 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK) >>
4411                                 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT;
4412                                 if (tmp == levels)
4413                                         break;
4414                                 udelay(1);
4415                         }
4416                 }
4417                 if ((!pi->pcie_dpm_key_disabled) &&
4418                     pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
4419                         levels = ci_get_lowest_enabled_level(adev,
4420                                                              pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
4421                         ret = ci_dpm_force_state_pcie(adev, levels);
4422                         if (ret)
4423                                 return ret;
4424                         for (i = 0; i < adev->usec_timeout; i++) {
4425                                 tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_1) &
4426                                 TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK) >>
4427                                 TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT;
4428                                 if (tmp == levels)
4429                                         break;
4430                                 udelay(1);
4431                         }
4432                 }
4433         } else if (level == AMDGPU_DPM_FORCED_LEVEL_AUTO) {
4434                 if (!pi->pcie_dpm_key_disabled) {
4435                         PPSMC_Result smc_result;
4436
4437                         smc_result = amdgpu_ci_send_msg_to_smc(adev,
4438                                                                PPSMC_MSG_PCIeDPM_UnForceLevel);
4439                         if (smc_result != PPSMC_Result_OK)
4440                                 return -EINVAL;
4441                 }
4442                 ret = ci_upload_dpm_level_enable_mask(adev);
4443                 if (ret)
4444                         return ret;
4445         }
4446
4447         adev->pm.dpm.forced_level = level;
4448
4449         return 0;
4450 }
4451
4452 static int ci_set_mc_special_registers(struct amdgpu_device *adev,
4453                                        struct ci_mc_reg_table *table)
4454 {
4455         u8 i, j, k;
4456         u32 temp_reg;
4457
4458         for (i = 0, j = table->last; i < table->last; i++) {
4459                 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4460                         return -EINVAL;
4461                 switch(table->mc_reg_address[i].s1) {
4462                 case mmMC_SEQ_MISC1:
4463                         temp_reg = RREG32(mmMC_PMG_CMD_EMRS);
4464                         table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
4465                         table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP;
4466                         for (k = 0; k < table->num_entries; k++) {
4467                                 table->mc_reg_table_entry[k].mc_data[j] =
4468                                         ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
4469                         }
4470                         j++;
4471                         if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4472                                 return -EINVAL;
4473
4474                         temp_reg = RREG32(mmMC_PMG_CMD_MRS);
4475                         table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
4476                         table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
4477                         for (k = 0; k < table->num_entries; k++) {
4478                                 table->mc_reg_table_entry[k].mc_data[j] =
4479                                         (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
4480                                 if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5)
4481                                         table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
4482                         }
4483                         j++;
4484                         if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4485                                 return -EINVAL;
4486
4487                         if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
4488                                 table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
4489                                 table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
4490                                 for (k = 0; k < table->num_entries; k++) {
4491                                         table->mc_reg_table_entry[k].mc_data[j] =
4492                                                 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
4493                                 }
4494                                 j++;
4495                                 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4496                                         return -EINVAL;
4497                         }
4498                         break;
4499                 case mmMC_SEQ_RESERVE_M:
4500                         temp_reg = RREG32(mmMC_PMG_CMD_MRS1);
4501                         table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1;
4502                         table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP;
4503                         for (k = 0; k < table->num_entries; k++) {
4504                                 table->mc_reg_table_entry[k].mc_data[j] =
4505                                         (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
4506                         }
4507                         j++;
4508                         if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4509                                 return -EINVAL;
4510                         break;
4511                 default:
4512                         break;
4513                 }
4514
4515         }
4516
4517         table->last = j;
4518
4519         return 0;
4520 }
4521
4522 static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
4523 {
4524         bool result = true;
4525
4526         switch(in_reg) {
4527         case mmMC_SEQ_RAS_TIMING:
4528                 *out_reg = mmMC_SEQ_RAS_TIMING_LP;
4529                 break;
4530         case mmMC_SEQ_DLL_STBY:
4531                 *out_reg = mmMC_SEQ_DLL_STBY_LP;
4532                 break;
4533         case mmMC_SEQ_G5PDX_CMD0:
4534                 *out_reg = mmMC_SEQ_G5PDX_CMD0_LP;
4535                 break;
4536         case mmMC_SEQ_G5PDX_CMD1:
4537                 *out_reg = mmMC_SEQ_G5PDX_CMD1_LP;
4538                 break;
4539         case mmMC_SEQ_G5PDX_CTRL:
4540                 *out_reg = mmMC_SEQ_G5PDX_CTRL_LP;
4541                 break;
4542         case mmMC_SEQ_CAS_TIMING:
4543                 *out_reg = mmMC_SEQ_CAS_TIMING_LP;
4544             break;
4545         case mmMC_SEQ_MISC_TIMING:
4546                 *out_reg = mmMC_SEQ_MISC_TIMING_LP;
4547                 break;
4548         case mmMC_SEQ_MISC_TIMING2:
4549                 *out_reg = mmMC_SEQ_MISC_TIMING2_LP;
4550                 break;
4551         case mmMC_SEQ_PMG_DVS_CMD:
4552                 *out_reg = mmMC_SEQ_PMG_DVS_CMD_LP;
4553                 break;
4554         case mmMC_SEQ_PMG_DVS_CTL:
4555                 *out_reg = mmMC_SEQ_PMG_DVS_CTL_LP;
4556                 break;
4557         case mmMC_SEQ_RD_CTL_D0:
4558                 *out_reg = mmMC_SEQ_RD_CTL_D0_LP;
4559                 break;
4560         case mmMC_SEQ_RD_CTL_D1:
4561                 *out_reg = mmMC_SEQ_RD_CTL_D1_LP;
4562                 break;
4563         case mmMC_SEQ_WR_CTL_D0:
4564                 *out_reg = mmMC_SEQ_WR_CTL_D0_LP;
4565                 break;
4566         case mmMC_SEQ_WR_CTL_D1:
4567                 *out_reg = mmMC_SEQ_WR_CTL_D1_LP;
4568                 break;
4569         case mmMC_PMG_CMD_EMRS:
4570                 *out_reg = mmMC_SEQ_PMG_CMD_EMRS_LP;
4571                 break;
4572         case mmMC_PMG_CMD_MRS:
4573                 *out_reg = mmMC_SEQ_PMG_CMD_MRS_LP;
4574                 break;
4575         case mmMC_PMG_CMD_MRS1:
4576                 *out_reg = mmMC_SEQ_PMG_CMD_MRS1_LP;
4577                 break;
4578         case mmMC_SEQ_PMG_TIMING:
4579                 *out_reg = mmMC_SEQ_PMG_TIMING_LP;
4580                 break;
4581         case mmMC_PMG_CMD_MRS2:
4582                 *out_reg = mmMC_SEQ_PMG_CMD_MRS2_LP;
4583                 break;
4584         case mmMC_SEQ_WR_CTL_2:
4585                 *out_reg = mmMC_SEQ_WR_CTL_2_LP;
4586                 break;
4587         default:
4588                 result = false;
4589                 break;
4590         }
4591
4592         return result;
4593 }
4594
4595 static void ci_set_valid_flag(struct ci_mc_reg_table *table)
4596 {
4597         u8 i, j;
4598
4599         for (i = 0; i < table->last; i++) {
4600                 for (j = 1; j < table->num_entries; j++) {
4601                         if (table->mc_reg_table_entry[j-1].mc_data[i] !=
4602                             table->mc_reg_table_entry[j].mc_data[i]) {
4603                                 table->valid_flag |= 1 << i;
4604                                 break;
4605                         }
4606                 }
4607         }
4608 }
4609
4610 static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table)
4611 {
4612         u32 i;
4613         u16 address;
4614
4615         for (i = 0; i < table->last; i++) {
4616                 table->mc_reg_address[i].s0 =
4617                         ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
4618                         address : table->mc_reg_address[i].s1;
4619         }
4620 }
4621
4622 static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table,
4623                                       struct ci_mc_reg_table *ci_table)
4624 {
4625         u8 i, j;
4626
4627         if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4628                 return -EINVAL;
4629         if (table->num_entries > MAX_AC_TIMING_ENTRIES)
4630                 return -EINVAL;
4631
4632         for (i = 0; i < table->last; i++)
4633                 ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
4634
4635         ci_table->last = table->last;
4636
4637         for (i = 0; i < table->num_entries; i++) {
4638                 ci_table->mc_reg_table_entry[i].mclk_max =
4639                         table->mc_reg_table_entry[i].mclk_max;
4640                 for (j = 0; j < table->last; j++)
4641                         ci_table->mc_reg_table_entry[i].mc_data[j] =
4642                                 table->mc_reg_table_entry[i].mc_data[j];
4643         }
4644         ci_table->num_entries = table->num_entries;
4645
4646         return 0;
4647 }
4648
4649 static int ci_register_patching_mc_seq(struct amdgpu_device *adev,
4650                                        struct ci_mc_reg_table *table)
4651 {
4652         u8 i, k;
4653         u32 tmp;
4654         bool patch;
4655
4656         tmp = RREG32(mmMC_SEQ_MISC0);
4657         patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
4658
4659         if (patch &&
4660             ((adev->pdev->device == 0x67B0) ||
4661              (adev->pdev->device == 0x67B1))) {
4662                 for (i = 0; i < table->last; i++) {
4663                         if (table->last >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4664                                 return -EINVAL;
4665                         switch (table->mc_reg_address[i].s1) {
4666                         case mmMC_SEQ_MISC1:
4667                                 for (k = 0; k < table->num_entries; k++) {
4668                                         if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4669                                             (table->mc_reg_table_entry[k].mclk_max == 137500))
4670                                                 table->mc_reg_table_entry[k].mc_data[i] =
4671                                                         (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFF8) |
4672                                                         0x00000007;
4673                                 }
4674                                 break;
4675                         case mmMC_SEQ_WR_CTL_D0:
4676                                 for (k = 0; k < table->num_entries; k++) {
4677                                         if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4678                                             (table->mc_reg_table_entry[k].mclk_max == 137500))
4679                                                 table->mc_reg_table_entry[k].mc_data[i] =
4680                                                         (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
4681                                                         0x0000D0DD;
4682                                 }
4683                                 break;
4684                         case mmMC_SEQ_WR_CTL_D1:
4685                                 for (k = 0; k < table->num_entries; k++) {
4686                                         if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4687                                             (table->mc_reg_table_entry[k].mclk_max == 137500))
4688                                                 table->mc_reg_table_entry[k].mc_data[i] =
4689                                                         (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
4690                                                         0x0000D0DD;
4691                                 }
4692                                 break;
4693                         case mmMC_SEQ_WR_CTL_2:
4694                                 for (k = 0; k < table->num_entries; k++) {
4695                                         if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4696                                             (table->mc_reg_table_entry[k].mclk_max == 137500))
4697                                                 table->mc_reg_table_entry[k].mc_data[i] = 0;
4698                                 }
4699                                 break;
4700                         case mmMC_SEQ_CAS_TIMING:
4701                                 for (k = 0; k < table->num_entries; k++) {
4702                                         if (table->mc_reg_table_entry[k].mclk_max == 125000)
4703                                                 table->mc_reg_table_entry[k].mc_data[i] =
4704                                                         (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
4705                                                         0x000C0140;
4706                                         else if (table->mc_reg_table_entry[k].mclk_max == 137500)
4707                                                 table->mc_reg_table_entry[k].mc_data[i] =
4708                                                         (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
4709                                                         0x000C0150;
4710                                 }
4711                                 break;
4712                         case mmMC_SEQ_MISC_TIMING:
4713                                 for (k = 0; k < table->num_entries; k++) {
4714                                         if (table->mc_reg_table_entry[k].mclk_max == 125000)
4715                                                 table->mc_reg_table_entry[k].mc_data[i] =
4716                                                         (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
4717                                                         0x00000030;
4718                                         else if (table->mc_reg_table_entry[k].mclk_max == 137500)
4719                                                 table->mc_reg_table_entry[k].mc_data[i] =
4720                                                         (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
4721                                                         0x00000035;
4722                                 }
4723                                 break;
4724                         default:
4725                                 break;
4726                         }
4727                 }
4728
4729                 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 3);
4730                 tmp = RREG32(mmMC_SEQ_IO_DEBUG_DATA);
4731                 tmp = (tmp & 0xFFF8FFFF) | (1 << 16);
4732                 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 3);
4733                 WREG32(mmMC_SEQ_IO_DEBUG_DATA, tmp);
4734         }
4735
4736         return 0;
4737 }
4738
4739 static int ci_initialize_mc_reg_table(struct amdgpu_device *adev)
4740 {
4741         struct ci_power_info *pi = ci_get_pi(adev);
4742         struct atom_mc_reg_table *table;
4743         struct ci_mc_reg_table *ci_table = &pi->mc_reg_table;
4744         u8 module_index = ci_get_memory_module_index(adev);
4745         int ret;
4746
4747         table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
4748         if (!table)
4749                 return -ENOMEM;
4750
4751         WREG32(mmMC_SEQ_RAS_TIMING_LP, RREG32(mmMC_SEQ_RAS_TIMING));
4752         WREG32(mmMC_SEQ_CAS_TIMING_LP, RREG32(mmMC_SEQ_CAS_TIMING));
4753         WREG32(mmMC_SEQ_DLL_STBY_LP, RREG32(mmMC_SEQ_DLL_STBY));
4754         WREG32(mmMC_SEQ_G5PDX_CMD0_LP, RREG32(mmMC_SEQ_G5PDX_CMD0));
4755         WREG32(mmMC_SEQ_G5PDX_CMD1_LP, RREG32(mmMC_SEQ_G5PDX_CMD1));
4756         WREG32(mmMC_SEQ_G5PDX_CTRL_LP, RREG32(mmMC_SEQ_G5PDX_CTRL));
4757         WREG32(mmMC_SEQ_PMG_DVS_CMD_LP, RREG32(mmMC_SEQ_PMG_DVS_CMD));
4758         WREG32(mmMC_SEQ_PMG_DVS_CTL_LP, RREG32(mmMC_SEQ_PMG_DVS_CTL));
4759         WREG32(mmMC_SEQ_MISC_TIMING_LP, RREG32(mmMC_SEQ_MISC_TIMING));
4760         WREG32(mmMC_SEQ_MISC_TIMING2_LP, RREG32(mmMC_SEQ_MISC_TIMING2));
4761         WREG32(mmMC_SEQ_PMG_CMD_EMRS_LP, RREG32(mmMC_PMG_CMD_EMRS));
4762         WREG32(mmMC_SEQ_PMG_CMD_MRS_LP, RREG32(mmMC_PMG_CMD_MRS));
4763         WREG32(mmMC_SEQ_PMG_CMD_MRS1_LP, RREG32(mmMC_PMG_CMD_MRS1));
4764         WREG32(mmMC_SEQ_WR_CTL_D0_LP, RREG32(mmMC_SEQ_WR_CTL_D0));
4765         WREG32(mmMC_SEQ_WR_CTL_D1_LP, RREG32(mmMC_SEQ_WR_CTL_D1));
4766         WREG32(mmMC_SEQ_RD_CTL_D0_LP, RREG32(mmMC_SEQ_RD_CTL_D0));
4767         WREG32(mmMC_SEQ_RD_CTL_D1_LP, RREG32(mmMC_SEQ_RD_CTL_D1));
4768         WREG32(mmMC_SEQ_PMG_TIMING_LP, RREG32(mmMC_SEQ_PMG_TIMING));
4769         WREG32(mmMC_SEQ_PMG_CMD_MRS2_LP, RREG32(mmMC_PMG_CMD_MRS2));
4770         WREG32(mmMC_SEQ_WR_CTL_2_LP, RREG32(mmMC_SEQ_WR_CTL_2));
4771
4772         ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table);
4773         if (ret)
4774                 goto init_mc_done;
4775
4776         ret = ci_copy_vbios_mc_reg_table(table, ci_table);
4777         if (ret)
4778                 goto init_mc_done;
4779
4780         ci_set_s0_mc_reg_index(ci_table);
4781
4782         ret = ci_register_patching_mc_seq(adev, ci_table);
4783         if (ret)
4784                 goto init_mc_done;
4785
4786         ret = ci_set_mc_special_registers(adev, ci_table);
4787         if (ret)
4788                 goto init_mc_done;
4789
4790         ci_set_valid_flag(ci_table);
4791
4792 init_mc_done:
4793         kfree(table);
4794
4795         return ret;
4796 }
4797
4798 static int ci_populate_mc_reg_addresses(struct amdgpu_device *adev,
4799                                         SMU7_Discrete_MCRegisters *mc_reg_table)
4800 {
4801         struct ci_power_info *pi = ci_get_pi(adev);
4802         u32 i, j;
4803
4804         for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) {
4805                 if (pi->mc_reg_table.valid_flag & (1 << j)) {
4806                         if (i >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4807                                 return -EINVAL;
4808                         mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0);
4809                         mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1);
4810                         i++;
4811                 }
4812         }
4813
4814         mc_reg_table->last = (u8)i;
4815
4816         return 0;
4817 }
4818
4819 static void ci_convert_mc_registers(const struct ci_mc_reg_entry *entry,
4820                                     SMU7_Discrete_MCRegisterSet *data,
4821                                     u32 num_entries, u32 valid_flag)
4822 {
4823         u32 i, j;
4824
4825         for (i = 0, j = 0; j < num_entries; j++) {
4826                 if (valid_flag & (1 << j)) {
4827                         data->value[i] = cpu_to_be32(entry->mc_data[j]);
4828                         i++;
4829                 }
4830         }
4831 }
4832
4833 static void ci_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev,
4834                                                  const u32 memory_clock,
4835                                                  SMU7_Discrete_MCRegisterSet *mc_reg_table_data)
4836 {
4837         struct ci_power_info *pi = ci_get_pi(adev);
4838         u32 i = 0;
4839
4840         for(i = 0; i < pi->mc_reg_table.num_entries; i++) {
4841                 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
4842                         break;
4843         }
4844
4845         if ((i == pi->mc_reg_table.num_entries) && (i > 0))
4846                 --i;
4847
4848         ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i],
4849                                 mc_reg_table_data, pi->mc_reg_table.last,
4850                                 pi->mc_reg_table.valid_flag);
4851 }
4852
4853 static void ci_convert_mc_reg_table_to_smc(struct amdgpu_device *adev,
4854                                            SMU7_Discrete_MCRegisters *mc_reg_table)
4855 {
4856         struct ci_power_info *pi = ci_get_pi(adev);
4857         u32 i;
4858
4859         for (i = 0; i < pi->dpm_table.mclk_table.count; i++)
4860                 ci_convert_mc_reg_table_entry_to_smc(adev,
4861                                                      pi->dpm_table.mclk_table.dpm_levels[i].value,
4862                                                      &mc_reg_table->data[i]);
4863 }
4864
4865 static int ci_populate_initial_mc_reg_table(struct amdgpu_device *adev)
4866 {
4867         struct ci_power_info *pi = ci_get_pi(adev);
4868         int ret;
4869
4870         memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4871
4872         ret = ci_populate_mc_reg_addresses(adev, &pi->smc_mc_reg_table);
4873         if (ret)
4874                 return ret;
4875         ci_convert_mc_reg_table_to_smc(adev, &pi->smc_mc_reg_table);
4876
4877         return amdgpu_ci_copy_bytes_to_smc(adev,
4878                                     pi->mc_reg_table_start,
4879                                     (u8 *)&pi->smc_mc_reg_table,
4880                                     sizeof(SMU7_Discrete_MCRegisters),
4881                                     pi->sram_end);
4882 }
4883
4884 static int ci_update_and_upload_mc_reg_table(struct amdgpu_device *adev)
4885 {
4886         struct ci_power_info *pi = ci_get_pi(adev);
4887
4888         if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
4889                 return 0;
4890
4891         memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4892
4893         ci_convert_mc_reg_table_to_smc(adev, &pi->smc_mc_reg_table);
4894
4895         return amdgpu_ci_copy_bytes_to_smc(adev,
4896                                     pi->mc_reg_table_start +
4897                                     offsetof(SMU7_Discrete_MCRegisters, data[0]),
4898                                     (u8 *)&pi->smc_mc_reg_table.data[0],
4899                                     sizeof(SMU7_Discrete_MCRegisterSet) *
4900                                     pi->dpm_table.mclk_table.count,
4901                                     pi->sram_end);
4902 }
4903
4904 static void ci_enable_voltage_control(struct amdgpu_device *adev)
4905 {
4906         u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
4907
4908         tmp |= GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK;
4909         WREG32_SMC(ixGENERAL_PWRMGT, tmp);
4910 }
4911
4912 static enum amdgpu_pcie_gen ci_get_maximum_link_speed(struct amdgpu_device *adev,
4913                                                       struct amdgpu_ps *amdgpu_state)
4914 {
4915         struct ci_ps *state = ci_get_ps(amdgpu_state);
4916         int i;
4917         u16 pcie_speed, max_speed = 0;
4918
4919         for (i = 0; i < state->performance_level_count; i++) {
4920                 pcie_speed = state->performance_levels[i].pcie_gen;
4921                 if (max_speed < pcie_speed)
4922                         max_speed = pcie_speed;
4923         }
4924
4925         return max_speed;
4926 }
4927
4928 static u16 ci_get_current_pcie_speed(struct amdgpu_device *adev)
4929 {
4930         u32 speed_cntl = 0;
4931
4932         speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL) &
4933                 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK;
4934         speed_cntl >>= PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
4935
4936         return (u16)speed_cntl;
4937 }
4938
4939 static int ci_get_current_pcie_lane_number(struct amdgpu_device *adev)
4940 {
4941         u32 link_width = 0;
4942
4943         link_width = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL) &
4944                 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK;
4945         link_width >>= PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
4946
4947         switch (link_width) {
4948         case 1:
4949                 return 1;
4950         case 2:
4951                 return 2;
4952         case 3:
4953                 return 4;
4954         case 4:
4955                 return 8;
4956         case 0:
4957         case 6:
4958         default:
4959                 return 16;
4960         }
4961 }
4962
4963 static void ci_request_link_speed_change_before_state_change(struct amdgpu_device *adev,
4964                                                              struct amdgpu_ps *amdgpu_new_state,
4965                                                              struct amdgpu_ps *amdgpu_current_state)
4966 {
4967         struct ci_power_info *pi = ci_get_pi(adev);
4968         enum amdgpu_pcie_gen target_link_speed =
4969                 ci_get_maximum_link_speed(adev, amdgpu_new_state);
4970         enum amdgpu_pcie_gen current_link_speed;
4971
4972         if (pi->force_pcie_gen == AMDGPU_PCIE_GEN_INVALID)
4973                 current_link_speed = ci_get_maximum_link_speed(adev, amdgpu_current_state);
4974         else
4975                 current_link_speed = pi->force_pcie_gen;
4976
4977         pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
4978         pi->pspp_notify_required = false;
4979         if (target_link_speed > current_link_speed) {
4980                 switch (target_link_speed) {
4981 #ifdef CONFIG_ACPI
4982                 case AMDGPU_PCIE_GEN3:
4983                         if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
4984                                 break;
4985                         pi->force_pcie_gen = AMDGPU_PCIE_GEN2;
4986                         if (current_link_speed == AMDGPU_PCIE_GEN2)
4987                                 break;
4988                 case AMDGPU_PCIE_GEN2:
4989                         if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
4990                                 break;
4991 #endif
4992                 default:
4993                         pi->force_pcie_gen = ci_get_current_pcie_speed(adev);
4994                         break;
4995                 }
4996         } else {
4997                 if (target_link_speed < current_link_speed)
4998                         pi->pspp_notify_required = true;
4999         }
5000 }
5001
5002 static void ci_notify_link_speed_change_after_state_change(struct amdgpu_device *adev,
5003                                                            struct amdgpu_ps *amdgpu_new_state,
5004                                                            struct amdgpu_ps *amdgpu_current_state)
5005 {
5006         struct ci_power_info *pi = ci_get_pi(adev);
5007         enum amdgpu_pcie_gen target_link_speed =
5008                 ci_get_maximum_link_speed(adev, amdgpu_new_state);
5009         u8 request;
5010
5011         if (pi->pspp_notify_required) {
5012                 if (target_link_speed == AMDGPU_PCIE_GEN3)
5013                         request = PCIE_PERF_REQ_PECI_GEN3;
5014                 else if (target_link_speed == AMDGPU_PCIE_GEN2)
5015                         request = PCIE_PERF_REQ_PECI_GEN2;
5016                 else
5017                         request = PCIE_PERF_REQ_PECI_GEN1;
5018
5019                 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
5020                     (ci_get_current_pcie_speed(adev) > 0))
5021                         return;
5022
5023 #ifdef CONFIG_ACPI
5024                 amdgpu_acpi_pcie_performance_request(adev, request, false);
5025 #endif
5026         }
5027 }
5028
5029 static int ci_set_private_data_variables_based_on_pptable(struct amdgpu_device *adev)
5030 {
5031         struct ci_power_info *pi = ci_get_pi(adev);
5032         struct amdgpu_clock_voltage_dependency_table *allowed_sclk_vddc_table =
5033                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
5034         struct amdgpu_clock_voltage_dependency_table *allowed_mclk_vddc_table =
5035                 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
5036         struct amdgpu_clock_voltage_dependency_table *allowed_mclk_vddci_table =
5037                 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
5038
5039         if (allowed_sclk_vddc_table == NULL)
5040                 return -EINVAL;
5041         if (allowed_sclk_vddc_table->count < 1)
5042                 return -EINVAL;
5043         if (allowed_mclk_vddc_table == NULL)
5044                 return -EINVAL;
5045         if (allowed_mclk_vddc_table->count < 1)
5046                 return -EINVAL;
5047         if (allowed_mclk_vddci_table == NULL)
5048                 return -EINVAL;
5049         if (allowed_mclk_vddci_table->count < 1)
5050                 return -EINVAL;
5051
5052         pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v;
5053         pi->max_vddc_in_pp_table =
5054                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
5055
5056         pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v;
5057         pi->max_vddci_in_pp_table =
5058                 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
5059
5060         adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk =
5061                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
5062         adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk =
5063                 allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
5064         adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc =
5065                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
5066         adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci =
5067                 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
5068
5069         return 0;
5070 }
5071
5072 static void ci_patch_with_vddc_leakage(struct amdgpu_device *adev, u16 *vddc)
5073 {
5074         struct ci_power_info *pi = ci_get_pi(adev);
5075         struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage;
5076         u32 leakage_index;
5077
5078         for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
5079                 if (leakage_table->leakage_id[leakage_index] == *vddc) {
5080                         *vddc = leakage_table->actual_voltage[leakage_index];
5081                         break;
5082                 }
5083         }
5084 }
5085
5086 static void ci_patch_with_vddci_leakage(struct amdgpu_device *adev, u16 *vddci)
5087 {
5088         struct ci_power_info *pi = ci_get_pi(adev);
5089         struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage;
5090         u32 leakage_index;
5091
5092         for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
5093                 if (leakage_table->leakage_id[leakage_index] == *vddci) {
5094                         *vddci = leakage_table->actual_voltage[leakage_index];
5095                         break;
5096                 }
5097         }
5098 }
5099
5100 static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device *adev,
5101                                                                       struct amdgpu_clock_voltage_dependency_table *table)
5102 {
5103         u32 i;
5104
5105         if (table) {
5106                 for (i = 0; i < table->count; i++)
5107                         ci_patch_with_vddc_leakage(adev, &table->entries[i].v);
5108         }
5109 }
5110
5111 static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct amdgpu_device *adev,
5112                                                                        struct amdgpu_clock_voltage_dependency_table *table)
5113 {
5114         u32 i;
5115
5116         if (table) {
5117                 for (i = 0; i < table->count; i++)
5118                         ci_patch_with_vddci_leakage(adev, &table->entries[i].v);
5119         }
5120 }
5121
5122 static void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device *adev,
5123                                                                           struct amdgpu_vce_clock_voltage_dependency_table *table)
5124 {
5125         u32 i;
5126
5127         if (table) {
5128                 for (i = 0; i < table->count; i++)
5129                         ci_patch_with_vddc_leakage(adev, &table->entries[i].v);
5130         }
5131 }
5132
5133 static void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device *adev,
5134                                                                           struct amdgpu_uvd_clock_voltage_dependency_table *table)
5135 {
5136         u32 i;
5137
5138         if (table) {
5139                 for (i = 0; i < table->count; i++)
5140                         ci_patch_with_vddc_leakage(adev, &table->entries[i].v);
5141         }
5142 }
5143
5144 static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct amdgpu_device *adev,
5145                                                                    struct amdgpu_phase_shedding_limits_table *table)
5146 {
5147         u32 i;
5148
5149         if (table) {
5150                 for (i = 0; i < table->count; i++)
5151                         ci_patch_with_vddc_leakage(adev, &table->entries[i].voltage);
5152         }
5153 }
5154
5155 static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct amdgpu_device *adev,
5156                                                             struct amdgpu_clock_and_voltage_limits *table)
5157 {
5158         if (table) {
5159                 ci_patch_with_vddc_leakage(adev, (u16 *)&table->vddc);
5160                 ci_patch_with_vddci_leakage(adev, (u16 *)&table->vddci);
5161         }
5162 }
5163
5164 static void ci_patch_cac_leakage_table_with_vddc_leakage(struct amdgpu_device *adev,
5165                                                          struct amdgpu_cac_leakage_table *table)
5166 {
5167         u32 i;
5168
5169         if (table) {
5170                 for (i = 0; i < table->count; i++)
5171                         ci_patch_with_vddc_leakage(adev, &table->entries[i].vddc);
5172         }
5173 }
5174
5175 static void ci_patch_dependency_tables_with_leakage(struct amdgpu_device *adev)
5176 {
5177
5178         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5179                                                                   &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5180         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5181                                                                   &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5182         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5183                                                                   &adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk);
5184         ci_patch_clock_voltage_dependency_table_with_vddci_leakage(adev,
5185                                                                    &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5186         ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(adev,
5187                                                                       &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table);
5188         ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(adev,
5189                                                                       &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table);
5190         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5191                                                                   &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table);
5192         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
5193                                                                   &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table);
5194         ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(adev,
5195                                                                &adev->pm.dpm.dyn_state.phase_shedding_limits_table);
5196         ci_patch_clock_voltage_limits_with_vddc_leakage(adev,
5197                                                         &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
5198         ci_patch_clock_voltage_limits_with_vddc_leakage(adev,
5199                                                         &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc);
5200         ci_patch_cac_leakage_table_with_vddc_leakage(adev,
5201                                                      &adev->pm.dpm.dyn_state.cac_leakage_table);
5202
5203 }
5204
5205 static void ci_update_current_ps(struct amdgpu_device *adev,
5206                                  struct amdgpu_ps *rps)
5207 {
5208         struct ci_ps *new_ps = ci_get_ps(rps);
5209         struct ci_power_info *pi = ci_get_pi(adev);
5210
5211         pi->current_rps = *rps;
5212         pi->current_ps = *new_ps;
5213         pi->current_rps.ps_priv = &pi->current_ps;
5214 }
5215
5216 static void ci_update_requested_ps(struct amdgpu_device *adev,
5217                                    struct amdgpu_ps *rps)
5218 {
5219         struct ci_ps *new_ps = ci_get_ps(rps);
5220         struct ci_power_info *pi = ci_get_pi(adev);
5221
5222         pi->requested_rps = *rps;
5223         pi->requested_ps = *new_ps;
5224         pi->requested_rps.ps_priv = &pi->requested_ps;
5225 }
5226
5227 static int ci_dpm_pre_set_power_state(struct amdgpu_device *adev)
5228 {
5229         struct ci_power_info *pi = ci_get_pi(adev);
5230         struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
5231         struct amdgpu_ps *new_ps = &requested_ps;
5232
5233         ci_update_requested_ps(adev, new_ps);
5234
5235         ci_apply_state_adjust_rules(adev, &pi->requested_rps);
5236
5237         return 0;
5238 }
5239
5240 static void ci_dpm_post_set_power_state(struct amdgpu_device *adev)
5241 {
5242         struct ci_power_info *pi = ci_get_pi(adev);
5243         struct amdgpu_ps *new_ps = &pi->requested_rps;
5244
5245         ci_update_current_ps(adev, new_ps);
5246 }
5247
5248
5249 static void ci_dpm_setup_asic(struct amdgpu_device *adev)
5250 {
5251         ci_read_clock_registers(adev);
5252         ci_enable_acpi_power_management(adev);
5253         ci_init_sclk_t(adev);
5254 }
5255
5256 static int ci_dpm_enable(struct amdgpu_device *adev)
5257 {
5258         struct ci_power_info *pi = ci_get_pi(adev);
5259         struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
5260         int ret;
5261
5262         if (amdgpu_ci_is_smc_running(adev))
5263                 return -EINVAL;
5264         if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
5265                 ci_enable_voltage_control(adev);
5266                 ret = ci_construct_voltage_tables(adev);
5267                 if (ret) {
5268                         DRM_ERROR("ci_construct_voltage_tables failed\n");
5269                         return ret;
5270                 }
5271         }
5272         if (pi->caps_dynamic_ac_timing) {
5273                 ret = ci_initialize_mc_reg_table(adev);
5274                 if (ret)
5275                         pi->caps_dynamic_ac_timing = false;
5276         }
5277         if (pi->dynamic_ss)
5278                 ci_enable_spread_spectrum(adev, true);
5279         if (pi->thermal_protection)
5280                 ci_enable_thermal_protection(adev, true);
5281         ci_program_sstp(adev);
5282         ci_enable_display_gap(adev);
5283         ci_program_vc(adev);
5284         ret = ci_upload_firmware(adev);
5285         if (ret) {
5286                 DRM_ERROR("ci_upload_firmware failed\n");
5287                 return ret;
5288         }
5289         ret = ci_process_firmware_header(adev);
5290         if (ret) {
5291                 DRM_ERROR("ci_process_firmware_header failed\n");
5292                 return ret;
5293         }
5294         ret = ci_initial_switch_from_arb_f0_to_f1(adev);
5295         if (ret) {
5296                 DRM_ERROR("ci_initial_switch_from_arb_f0_to_f1 failed\n");
5297                 return ret;
5298         }
5299         ret = ci_init_smc_table(adev);
5300         if (ret) {
5301                 DRM_ERROR("ci_init_smc_table failed\n");
5302                 return ret;
5303         }
5304         ret = ci_init_arb_table_index(adev);
5305         if (ret) {
5306                 DRM_ERROR("ci_init_arb_table_index failed\n");
5307                 return ret;
5308         }
5309         if (pi->caps_dynamic_ac_timing) {
5310                 ret = ci_populate_initial_mc_reg_table(adev);
5311                 if (ret) {
5312                         DRM_ERROR("ci_populate_initial_mc_reg_table failed\n");
5313                         return ret;
5314                 }
5315         }
5316         ret = ci_populate_pm_base(adev);
5317         if (ret) {
5318                 DRM_ERROR("ci_populate_pm_base failed\n");
5319                 return ret;
5320         }
5321         ci_dpm_start_smc(adev);
5322         ci_enable_vr_hot_gpio_interrupt(adev);
5323         ret = ci_notify_smc_display_change(adev, false);
5324         if (ret) {
5325                 DRM_ERROR("ci_notify_smc_display_change failed\n");
5326                 return ret;
5327         }
5328         ci_enable_sclk_control(adev, true);
5329         ret = ci_enable_ulv(adev, true);
5330         if (ret) {
5331                 DRM_ERROR("ci_enable_ulv failed\n");
5332                 return ret;
5333         }
5334         ret = ci_enable_ds_master_switch(adev, true);
5335         if (ret) {
5336                 DRM_ERROR("ci_enable_ds_master_switch failed\n");
5337                 return ret;
5338         }
5339         ret = ci_start_dpm(adev);
5340         if (ret) {
5341                 DRM_ERROR("ci_start_dpm failed\n");
5342                 return ret;
5343         }
5344         ret = ci_enable_didt(adev, true);
5345         if (ret) {
5346                 DRM_ERROR("ci_enable_didt failed\n");
5347                 return ret;
5348         }
5349         ret = ci_enable_smc_cac(adev, true);
5350         if (ret) {
5351                 DRM_ERROR("ci_enable_smc_cac failed\n");
5352                 return ret;
5353         }
5354         ret = ci_enable_power_containment(adev, true);
5355         if (ret) {
5356                 DRM_ERROR("ci_enable_power_containment failed\n");
5357                 return ret;
5358         }
5359
5360         ret = ci_power_control_set_level(adev);
5361         if (ret) {
5362                 DRM_ERROR("ci_power_control_set_level failed\n");
5363                 return ret;
5364         }
5365
5366         ci_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
5367
5368         ret = ci_enable_thermal_based_sclk_dpm(adev, true);
5369         if (ret) {
5370                 DRM_ERROR("ci_enable_thermal_based_sclk_dpm failed\n");
5371                 return ret;
5372         }
5373
5374         ci_thermal_start_thermal_controller(adev);
5375
5376         ci_update_current_ps(adev, boot_ps);
5377
5378         return 0;
5379 }
5380
5381 static void ci_dpm_disable(struct amdgpu_device *adev)
5382 {
5383         struct ci_power_info *pi = ci_get_pi(adev);
5384         struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
5385
5386         amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
5387                        AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
5388         amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
5389                        AMDGPU_THERMAL_IRQ_HIGH_TO_LOW);
5390
5391         ci_dpm_powergate_uvd(adev, false);
5392
5393         if (!amdgpu_ci_is_smc_running(adev))
5394                 return;
5395
5396         ci_thermal_stop_thermal_controller(adev);
5397
5398         if (pi->thermal_protection)
5399                 ci_enable_thermal_protection(adev, false);
5400         ci_enable_power_containment(adev, false);
5401         ci_enable_smc_cac(adev, false);
5402         ci_enable_didt(adev, false);
5403         ci_enable_spread_spectrum(adev, false);
5404         ci_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
5405         ci_stop_dpm(adev);
5406         ci_enable_ds_master_switch(adev, false);
5407         ci_enable_ulv(adev, false);
5408         ci_clear_vc(adev);
5409         ci_reset_to_default(adev);
5410         ci_dpm_stop_smc(adev);
5411         ci_force_switch_to_arb_f0(adev);
5412         ci_enable_thermal_based_sclk_dpm(adev, false);
5413
5414         ci_update_current_ps(adev, boot_ps);
5415 }
5416
5417 static int ci_dpm_set_power_state(struct amdgpu_device *adev)
5418 {
5419         struct ci_power_info *pi = ci_get_pi(adev);
5420         struct amdgpu_ps *new_ps = &pi->requested_rps;
5421         struct amdgpu_ps *old_ps = &pi->current_rps;
5422         int ret;
5423
5424         ci_find_dpm_states_clocks_in_dpm_table(adev, new_ps);
5425         if (pi->pcie_performance_request)
5426                 ci_request_link_speed_change_before_state_change(adev, new_ps, old_ps);
5427         ret = ci_freeze_sclk_mclk_dpm(adev);
5428         if (ret) {
5429                 DRM_ERROR("ci_freeze_sclk_mclk_dpm failed\n");
5430                 return ret;
5431         }
5432         ret = ci_populate_and_upload_sclk_mclk_dpm_levels(adev, new_ps);
5433         if (ret) {
5434                 DRM_ERROR("ci_populate_and_upload_sclk_mclk_dpm_levels failed\n");
5435                 return ret;
5436         }
5437         ret = ci_generate_dpm_level_enable_mask(adev, new_ps);
5438         if (ret) {
5439                 DRM_ERROR("ci_generate_dpm_level_enable_mask failed\n");
5440                 return ret;
5441         }
5442
5443         ret = ci_update_vce_dpm(adev, new_ps, old_ps);
5444         if (ret) {
5445                 DRM_ERROR("ci_update_vce_dpm failed\n");
5446                 return ret;
5447         }
5448
5449         ret = ci_update_sclk_t(adev);
5450         if (ret) {
5451                 DRM_ERROR("ci_update_sclk_t failed\n");
5452                 return ret;
5453         }
5454         if (pi->caps_dynamic_ac_timing) {
5455                 ret = ci_update_and_upload_mc_reg_table(adev);
5456                 if (ret) {
5457                         DRM_ERROR("ci_update_and_upload_mc_reg_table failed\n");
5458                         return ret;
5459                 }
5460         }
5461         ret = ci_program_memory_timing_parameters(adev);
5462         if (ret) {
5463                 DRM_ERROR("ci_program_memory_timing_parameters failed\n");
5464                 return ret;
5465         }
5466         ret = ci_unfreeze_sclk_mclk_dpm(adev);
5467         if (ret) {
5468                 DRM_ERROR("ci_unfreeze_sclk_mclk_dpm failed\n");
5469                 return ret;
5470         }
5471         ret = ci_upload_dpm_level_enable_mask(adev);
5472         if (ret) {
5473                 DRM_ERROR("ci_upload_dpm_level_enable_mask failed\n");
5474                 return ret;
5475         }
5476         if (pi->pcie_performance_request)
5477                 ci_notify_link_speed_change_after_state_change(adev, new_ps, old_ps);
5478
5479         return 0;
5480 }
5481
5482 #if 0
5483 static void ci_dpm_reset_asic(struct amdgpu_device *adev)
5484 {
5485         ci_set_boot_state(adev);
5486 }
5487 #endif
5488
5489 static void ci_dpm_display_configuration_changed(struct amdgpu_device *adev)
5490 {
5491         ci_program_display_gap(adev);
5492 }
5493
5494 union power_info {
5495         struct _ATOM_POWERPLAY_INFO info;
5496         struct _ATOM_POWERPLAY_INFO_V2 info_2;
5497         struct _ATOM_POWERPLAY_INFO_V3 info_3;
5498         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
5499         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
5500         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
5501 };
5502
5503 union pplib_clock_info {
5504         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
5505         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
5506         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
5507         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
5508         struct _ATOM_PPLIB_SI_CLOCK_INFO si;
5509         struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
5510 };
5511
5512 union pplib_power_state {
5513         struct _ATOM_PPLIB_STATE v1;
5514         struct _ATOM_PPLIB_STATE_V2 v2;
5515 };
5516
5517 static void ci_parse_pplib_non_clock_info(struct amdgpu_device *adev,
5518                                           struct amdgpu_ps *rps,
5519                                           struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
5520                                           u8 table_rev)
5521 {
5522         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
5523         rps->class = le16_to_cpu(non_clock_info->usClassification);
5524         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
5525
5526         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
5527                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
5528                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
5529         } else {
5530                 rps->vclk = 0;
5531                 rps->dclk = 0;
5532         }
5533
5534         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
5535                 adev->pm.dpm.boot_ps = rps;
5536         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
5537                 adev->pm.dpm.uvd_ps = rps;
5538 }
5539
5540 static void ci_parse_pplib_clock_info(struct amdgpu_device *adev,
5541                                       struct amdgpu_ps *rps, int index,
5542                                       union pplib_clock_info *clock_info)
5543 {
5544         struct ci_power_info *pi = ci_get_pi(adev);
5545         struct ci_ps *ps = ci_get_ps(rps);
5546         struct ci_pl *pl = &ps->performance_levels[index];
5547
5548         ps->performance_level_count = index + 1;
5549
5550         pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5551         pl->sclk |= clock_info->ci.ucEngineClockHigh << 16;
5552         pl->mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
5553         pl->mclk |= clock_info->ci.ucMemoryClockHigh << 16;
5554
5555         pl->pcie_gen = amdgpu_get_pcie_gen_support(adev,
5556                                                    pi->sys_pcie_mask,
5557                                                    pi->vbios_boot_state.pcie_gen_bootup_value,
5558                                                    clock_info->ci.ucPCIEGen);
5559         pl->pcie_lane = amdgpu_get_pcie_lane_support(adev,
5560                                                      pi->vbios_boot_state.pcie_lane_bootup_value,
5561                                                      le16_to_cpu(clock_info->ci.usPCIELane));
5562
5563         if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
5564                 pi->acpi_pcie_gen = pl->pcie_gen;
5565         }
5566
5567         if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) {
5568                 pi->ulv.supported = true;
5569                 pi->ulv.pl = *pl;
5570                 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT;
5571         }
5572
5573         /* patch up boot state */
5574         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
5575                 pl->mclk = pi->vbios_boot_state.mclk_bootup_value;
5576                 pl->sclk = pi->vbios_boot_state.sclk_bootup_value;
5577                 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value;
5578                 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value;
5579         }
5580
5581         switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
5582         case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
5583                 pi->use_pcie_powersaving_levels = true;
5584                 if (pi->pcie_gen_powersaving.max < pl->pcie_gen)
5585                         pi->pcie_gen_powersaving.max = pl->pcie_gen;
5586                 if (pi->pcie_gen_powersaving.min > pl->pcie_gen)
5587                         pi->pcie_gen_powersaving.min = pl->pcie_gen;
5588                 if (pi->pcie_lane_powersaving.max < pl->pcie_lane)
5589                         pi->pcie_lane_powersaving.max = pl->pcie_lane;
5590                 if (pi->pcie_lane_powersaving.min > pl->pcie_lane)
5591                         pi->pcie_lane_powersaving.min = pl->pcie_lane;
5592                 break;
5593         case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
5594                 pi->use_pcie_performance_levels = true;
5595                 if (pi->pcie_gen_performance.max < pl->pcie_gen)
5596                         pi->pcie_gen_performance.max = pl->pcie_gen;
5597                 if (pi->pcie_gen_performance.min > pl->pcie_gen)
5598                         pi->pcie_gen_performance.min = pl->pcie_gen;
5599                 if (pi->pcie_lane_performance.max < pl->pcie_lane)
5600                         pi->pcie_lane_performance.max = pl->pcie_lane;
5601                 if (pi->pcie_lane_performance.min > pl->pcie_lane)
5602                         pi->pcie_lane_performance.min = pl->pcie_lane;
5603                 break;
5604         default:
5605                 break;
5606         }
5607 }
5608
5609 static int ci_parse_power_table(struct amdgpu_device *adev)
5610 {
5611         struct amdgpu_mode_info *mode_info = &adev->mode_info;
5612         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
5613         union pplib_power_state *power_state;
5614         int i, j, k, non_clock_array_index, clock_array_index;
5615         union pplib_clock_info *clock_info;
5616         struct _StateArray *state_array;
5617         struct _ClockInfoArray *clock_info_array;
5618         struct _NonClockInfoArray *non_clock_info_array;
5619         union power_info *power_info;
5620         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
5621         u16 data_offset;
5622         u8 frev, crev;
5623         u8 *power_state_offset;
5624         struct ci_ps *ps;
5625
5626         if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
5627                                    &frev, &crev, &data_offset))
5628                 return -EINVAL;
5629         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
5630
5631         amdgpu_add_thermal_controller(adev);
5632
5633         state_array = (struct _StateArray *)
5634                 (mode_info->atom_context->bios + data_offset +
5635                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
5636         clock_info_array = (struct _ClockInfoArray *)
5637                 (mode_info->atom_context->bios + data_offset +
5638                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
5639         non_clock_info_array = (struct _NonClockInfoArray *)
5640                 (mode_info->atom_context->bios + data_offset +
5641                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
5642
5643         adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) *
5644                                   state_array->ucNumEntries, GFP_KERNEL);
5645         if (!adev->pm.dpm.ps)
5646                 return -ENOMEM;
5647         power_state_offset = (u8 *)state_array->states;
5648         for (i = 0; i < state_array->ucNumEntries; i++) {
5649                 u8 *idx;
5650                 power_state = (union pplib_power_state *)power_state_offset;
5651                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
5652                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
5653                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
5654                 ps = kzalloc(sizeof(struct ci_ps), GFP_KERNEL);
5655                 if (ps == NULL) {
5656                         kfree(adev->pm.dpm.ps);
5657                         return -ENOMEM;
5658                 }
5659                 adev->pm.dpm.ps[i].ps_priv = ps;
5660                 ci_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
5661                                               non_clock_info,
5662                                               non_clock_info_array->ucEntrySize);
5663                 k = 0;
5664                 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
5665                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
5666                         clock_array_index = idx[j];
5667                         if (clock_array_index >= clock_info_array->ucNumEntries)
5668                                 continue;
5669                         if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS)
5670                                 break;
5671                         clock_info = (union pplib_clock_info *)
5672                                 ((u8 *)&clock_info_array->clockInfo[0] +
5673                                  (clock_array_index * clock_info_array->ucEntrySize));
5674                         ci_parse_pplib_clock_info(adev,
5675                                                   &adev->pm.dpm.ps[i], k,
5676                                                   clock_info);
5677                         k++;
5678                 }
5679                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
5680         }
5681         adev->pm.dpm.num_ps = state_array->ucNumEntries;
5682
5683         /* fill in the vce power states */
5684         for (i = 0; i < AMDGPU_MAX_VCE_LEVELS; i++) {
5685                 u32 sclk, mclk;
5686                 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
5687                 clock_info = (union pplib_clock_info *)
5688                         &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
5689                 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5690                 sclk |= clock_info->ci.ucEngineClockHigh << 16;
5691                 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
5692                 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
5693                 adev->pm.dpm.vce_states[i].sclk = sclk;
5694                 adev->pm.dpm.vce_states[i].mclk = mclk;
5695         }
5696
5697         return 0;
5698 }
5699
5700 static int ci_get_vbios_boot_values(struct amdgpu_device *adev,
5701                                     struct ci_vbios_boot_state *boot_state)
5702 {
5703         struct amdgpu_mode_info *mode_info = &adev->mode_info;
5704         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
5705         ATOM_FIRMWARE_INFO_V2_2 *firmware_info;
5706         u8 frev, crev;
5707         u16 data_offset;
5708
5709         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
5710                                    &frev, &crev, &data_offset)) {
5711                 firmware_info =
5712                         (ATOM_FIRMWARE_INFO_V2_2 *)(mode_info->atom_context->bios +
5713                                                     data_offset);
5714                 boot_state->mvdd_bootup_value = le16_to_cpu(firmware_info->usBootUpMVDDCVoltage);
5715                 boot_state->vddc_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCVoltage);
5716                 boot_state->vddci_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCIVoltage);
5717                 boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(adev);
5718                 boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(adev);
5719                 boot_state->sclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultEngineClock);
5720                 boot_state->mclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultMemoryClock);
5721
5722                 return 0;
5723         }
5724         return -EINVAL;
5725 }
5726
5727 static void ci_dpm_fini(struct amdgpu_device *adev)
5728 {
5729         int i;
5730
5731         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
5732                 kfree(adev->pm.dpm.ps[i].ps_priv);
5733         }
5734         kfree(adev->pm.dpm.ps);
5735         kfree(adev->pm.dpm.priv);
5736         kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
5737         amdgpu_free_extended_power_table(adev);
5738 }
5739
5740 /**
5741  * ci_dpm_init_microcode - load ucode images from disk
5742  *
5743  * @adev: amdgpu_device pointer
5744  *
5745  * Use the firmware interface to load the ucode images into
5746  * the driver (not loaded into hw).
5747  * Returns 0 on success, error on failure.
5748  */
5749 static int ci_dpm_init_microcode(struct amdgpu_device *adev)
5750 {
5751         const char *chip_name;
5752         char fw_name[30];
5753         int err;
5754
5755         DRM_DEBUG("\n");
5756
5757         switch (adev->asic_type) {
5758         case CHIP_BONAIRE:
5759                 if ((adev->pdev->revision == 0x80) ||
5760                     (adev->pdev->revision == 0x81) ||
5761                     (adev->pdev->device == 0x665f))
5762                         chip_name = "bonaire_k";
5763                 else
5764                         chip_name = "bonaire";
5765                 break;
5766         case CHIP_HAWAII:
5767                 if (adev->pdev->revision == 0x80)
5768                         chip_name = "hawaii_k";
5769                 else
5770                         chip_name = "hawaii";
5771                 break;
5772         case CHIP_KAVERI:
5773         case CHIP_KABINI:
5774         default: BUG();
5775         }
5776
5777         snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
5778         err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
5779         if (err)
5780                 goto out;
5781         err = amdgpu_ucode_validate(adev->pm.fw);
5782
5783 out:
5784         if (err) {
5785                 printk(KERN_ERR
5786                        "cik_smc: Failed to load firmware \"%s\"\n",
5787                        fw_name);
5788                 release_firmware(adev->pm.fw);
5789                 adev->pm.fw = NULL;
5790         }
5791         return err;
5792 }
5793
5794 static int ci_dpm_init(struct amdgpu_device *adev)
5795 {
5796         int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
5797         SMU7_Discrete_DpmTable *dpm_table;
5798         struct amdgpu_gpio_rec gpio;
5799         u16 data_offset, size;
5800         u8 frev, crev;
5801         struct ci_power_info *pi;
5802         int ret;
5803
5804         pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL);
5805         if (pi == NULL)
5806                 return -ENOMEM;
5807         adev->pm.dpm.priv = pi;
5808
5809         pi->sys_pcie_mask =
5810                 (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) >>
5811                 CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT;
5812
5813         pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
5814
5815         pi->pcie_gen_performance.max = AMDGPU_PCIE_GEN1;
5816         pi->pcie_gen_performance.min = AMDGPU_PCIE_GEN3;
5817         pi->pcie_gen_powersaving.max = AMDGPU_PCIE_GEN1;
5818         pi->pcie_gen_powersaving.min = AMDGPU_PCIE_GEN3;
5819
5820         pi->pcie_lane_performance.max = 0;
5821         pi->pcie_lane_performance.min = 16;
5822         pi->pcie_lane_powersaving.max = 0;
5823         pi->pcie_lane_powersaving.min = 16;
5824
5825         ret = ci_get_vbios_boot_values(adev, &pi->vbios_boot_state);
5826         if (ret) {
5827                 ci_dpm_fini(adev);
5828                 return ret;
5829         }
5830
5831         ret = amdgpu_get_platform_caps(adev);
5832         if (ret) {
5833                 ci_dpm_fini(adev);
5834                 return ret;
5835         }
5836
5837         ret = amdgpu_parse_extended_power_table(adev);
5838         if (ret) {
5839                 ci_dpm_fini(adev);
5840                 return ret;
5841         }
5842
5843         ret = ci_parse_power_table(adev);
5844         if (ret) {
5845                 ci_dpm_fini(adev);
5846                 return ret;
5847         }
5848
5849         pi->dll_default_on = false;
5850         pi->sram_end = SMC_RAM_END;
5851
5852         pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT;
5853         pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT;
5854         pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT;
5855         pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT;
5856         pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT;
5857         pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT;
5858         pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT;
5859         pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT;
5860
5861         pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT;
5862
5863         pi->sclk_dpm_key_disabled = 0;
5864         pi->mclk_dpm_key_disabled = 0;
5865         pi->pcie_dpm_key_disabled = 0;
5866         pi->thermal_sclk_dpm_enabled = 0;
5867
5868         pi->caps_sclk_ds = true;
5869
5870         pi->mclk_strobe_mode_threshold = 40000;
5871         pi->mclk_stutter_mode_threshold = 40000;
5872         pi->mclk_edc_enable_threshold = 40000;
5873         pi->mclk_edc_wr_enable_threshold = 40000;
5874
5875         ci_initialize_powertune_defaults(adev);
5876
5877         pi->caps_fps = false;
5878
5879         pi->caps_sclk_throttle_low_notification = false;
5880
5881         pi->caps_uvd_dpm = true;
5882         pi->caps_vce_dpm = true;
5883
5884         ci_get_leakage_voltages(adev);
5885         ci_patch_dependency_tables_with_leakage(adev);
5886         ci_set_private_data_variables_based_on_pptable(adev);
5887
5888         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
5889                 kzalloc(4 * sizeof(struct amdgpu_clock_voltage_dependency_entry), GFP_KERNEL);
5890         if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
5891                 ci_dpm_fini(adev);
5892                 return -ENOMEM;
5893         }
5894         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
5895         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
5896         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
5897         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
5898         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
5899         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
5900         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
5901         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
5902         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
5903
5904         adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
5905         adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
5906         adev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
5907
5908         adev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
5909         adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
5910         adev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
5911         adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
5912
5913         if (adev->asic_type == CHIP_HAWAII) {
5914                 pi->thermal_temp_setting.temperature_low = 94500;
5915                 pi->thermal_temp_setting.temperature_high = 95000;
5916                 pi->thermal_temp_setting.temperature_shutdown = 104000;
5917         } else {
5918                 pi->thermal_temp_setting.temperature_low = 99500;
5919                 pi->thermal_temp_setting.temperature_high = 100000;
5920                 pi->thermal_temp_setting.temperature_shutdown = 104000;
5921         }
5922
5923         pi->uvd_enabled = false;
5924
5925         dpm_table = &pi->smc_state_table;
5926
5927         gpio = amdgpu_atombios_lookup_gpio(adev, VDDC_VRHOT_GPIO_PINID);
5928         if (gpio.valid) {
5929                 dpm_table->VRHotGpio = gpio.shift;
5930                 adev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
5931         } else {
5932                 dpm_table->VRHotGpio = CISLANDS_UNUSED_GPIO_PIN;
5933                 adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
5934         }
5935
5936         gpio = amdgpu_atombios_lookup_gpio(adev, PP_AC_DC_SWITCH_GPIO_PINID);
5937         if (gpio.valid) {
5938                 dpm_table->AcDcGpio = gpio.shift;
5939                 adev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_HARDWAREDC;
5940         } else {
5941                 dpm_table->AcDcGpio = CISLANDS_UNUSED_GPIO_PIN;
5942                 adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_HARDWAREDC;
5943         }
5944
5945         gpio = amdgpu_atombios_lookup_gpio(adev, VDDC_PCC_GPIO_PINID);
5946         if (gpio.valid) {
5947                 u32 tmp = RREG32_SMC(ixCNB_PWRMGT_CNTL);
5948
5949                 switch (gpio.shift) {
5950                 case 0:
5951                         tmp &= ~CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK;
5952                         tmp |= 1 << CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT;
5953                         break;
5954                 case 1:
5955                         tmp &= ~CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK;
5956                         tmp |= 2 << CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT;
5957                         break;
5958                 case 2:
5959                         tmp |= CNB_PWRMGT_CNTL__GNB_SLOW_MASK;
5960                         break;
5961                 case 3:
5962                         tmp |= CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK;
5963                         break;
5964                 case 4:
5965                         tmp |= CNB_PWRMGT_CNTL__DPM_ENABLED_MASK;
5966                         break;
5967                 default:
5968                         DRM_ERROR("Invalid PCC GPIO: %u!\n", gpio.shift);
5969                         break;
5970                 }
5971                 WREG32_SMC(ixCNB_PWRMGT_CNTL, tmp);
5972         }
5973
5974         pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5975         pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5976         pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5977         if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
5978                 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5979         else if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
5980                 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5981
5982         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) {
5983                 if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
5984                         pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5985                 else if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
5986                         pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5987                 else
5988                         adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL;
5989         }
5990
5991         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) {
5992                 if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
5993                         pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5994                 else if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
5995                         pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5996                 else
5997                         adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL;
5998         }
5999
6000         pi->vddc_phase_shed_control = true;
6001
6002 #if defined(CONFIG_ACPI)
6003         pi->pcie_performance_request =
6004                 amdgpu_acpi_is_pcie_performance_request_supported(adev);
6005 #else
6006         pi->pcie_performance_request = false;
6007 #endif
6008
6009         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
6010                                    &frev, &crev, &data_offset)) {
6011                 pi->caps_sclk_ss_support = true;
6012                 pi->caps_mclk_ss_support = true;
6013                 pi->dynamic_ss = true;
6014         } else {
6015                 pi->caps_sclk_ss_support = false;
6016                 pi->caps_mclk_ss_support = false;
6017                 pi->dynamic_ss = true;
6018         }
6019
6020         if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE)
6021                 pi->thermal_protection = true;
6022         else
6023                 pi->thermal_protection = false;
6024
6025         pi->caps_dynamic_ac_timing = true;
6026
6027         pi->uvd_power_gated = false;
6028
6029         /* make sure dc limits are valid */
6030         if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
6031             (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
6032                 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
6033                         adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
6034
6035         pi->fan_ctrl_is_in_default_mode = true;
6036
6037         return 0;
6038 }
6039
6040 static void
6041 ci_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
6042                                                struct seq_file *m)
6043 {
6044         struct ci_power_info *pi = ci_get_pi(adev);
6045         struct amdgpu_ps *rps = &pi->current_rps;
6046         u32 sclk = ci_get_average_sclk_freq(adev);
6047         u32 mclk = ci_get_average_mclk_freq(adev);
6048         u32 activity_percent = 50;
6049         int ret;
6050
6051         ret = ci_read_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, AverageGraphicsA),
6052                                         &activity_percent);
6053
6054         if (ret == 0) {
6055                 activity_percent += 0x80;
6056                 activity_percent >>= 8;
6057                 activity_percent = activity_percent > 100 ? 100 : activity_percent;
6058         }
6059
6060         seq_printf(m, "uvd %sabled\n", pi->uvd_enabled ? "en" : "dis");
6061         seq_printf(m, "vce %sabled\n", rps->vce_active ? "en" : "dis");
6062         seq_printf(m, "power level avg    sclk: %u mclk: %u\n",
6063                    sclk, mclk);
6064         seq_printf(m, "GPU load: %u %%\n", activity_percent);
6065 }
6066
6067 static void ci_dpm_print_power_state(struct amdgpu_device *adev,
6068                                      struct amdgpu_ps *rps)
6069 {
6070         struct ci_ps *ps = ci_get_ps(rps);
6071         struct ci_pl *pl;
6072         int i;
6073
6074         amdgpu_dpm_print_class_info(rps->class, rps->class2);
6075         amdgpu_dpm_print_cap_info(rps->caps);
6076         printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
6077         for (i = 0; i < ps->performance_level_count; i++) {
6078                 pl = &ps->performance_levels[i];
6079                 printk("\t\tpower level %d    sclk: %u mclk: %u pcie gen: %u pcie lanes: %u\n",
6080                        i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane);
6081         }
6082         amdgpu_dpm_print_ps_status(adev, rps);
6083 }
6084
6085 static u32 ci_dpm_get_sclk(struct amdgpu_device *adev, bool low)
6086 {
6087         struct ci_power_info *pi = ci_get_pi(adev);
6088         struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
6089
6090         if (low)
6091                 return requested_state->performance_levels[0].sclk;
6092         else
6093                 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
6094 }
6095
6096 static u32 ci_dpm_get_mclk(struct amdgpu_device *adev, bool low)
6097 {
6098         struct ci_power_info *pi = ci_get_pi(adev);
6099         struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
6100
6101         if (low)
6102                 return requested_state->performance_levels[0].mclk;
6103         else
6104                 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
6105 }
6106
6107 /* get temperature in millidegrees */
6108 static int ci_dpm_get_temp(struct amdgpu_device *adev)
6109 {
6110         u32 temp;
6111         int actual_temp = 0;
6112
6113         temp = (RREG32_SMC(ixCG_MULT_THERMAL_STATUS) & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
6114                 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
6115
6116         if (temp & 0x200)
6117                 actual_temp = 255;
6118         else
6119                 actual_temp = temp & 0x1ff;
6120
6121         actual_temp = actual_temp * 1000;
6122
6123         return actual_temp;
6124 }
6125
6126 static int ci_set_temperature_range(struct amdgpu_device *adev)
6127 {
6128         int ret;
6129
6130         ret = ci_thermal_enable_alert(adev, false);
6131         if (ret)
6132                 return ret;
6133         ret = ci_thermal_set_temperature_range(adev, CISLANDS_TEMP_RANGE_MIN,
6134                                                CISLANDS_TEMP_RANGE_MAX);
6135         if (ret)
6136                 return ret;
6137         ret = ci_thermal_enable_alert(adev, true);
6138         if (ret)
6139                 return ret;
6140         return ret;
6141 }
6142
6143 static int ci_dpm_early_init(void *handle)
6144 {
6145         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6146
6147         ci_dpm_set_dpm_funcs(adev);
6148         ci_dpm_set_irq_funcs(adev);
6149
6150         return 0;
6151 }
6152
6153 static int ci_dpm_late_init(void *handle)
6154 {
6155         int ret;
6156         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6157
6158         if (!amdgpu_dpm)
6159                 return 0;
6160
6161         /* init the sysfs and debugfs files late */
6162         ret = amdgpu_pm_sysfs_init(adev);
6163         if (ret)
6164                 return ret;
6165
6166         ret = ci_set_temperature_range(adev);
6167         if (ret)
6168                 return ret;
6169
6170         ci_dpm_powergate_uvd(adev, true);
6171
6172         return 0;
6173 }
6174
6175 static int ci_dpm_sw_init(void *handle)
6176 {
6177         int ret;
6178         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6179
6180         ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq);
6181         if (ret)
6182                 return ret;
6183
6184         ret = amdgpu_irq_add_id(adev, 231, &adev->pm.dpm.thermal.irq);
6185         if (ret)
6186                 return ret;
6187
6188         /* default to balanced state */
6189         adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
6190         adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
6191         adev->pm.dpm.forced_level = AMDGPU_DPM_FORCED_LEVEL_AUTO;
6192         adev->pm.default_sclk = adev->clock.default_sclk;
6193         adev->pm.default_mclk = adev->clock.default_mclk;
6194         adev->pm.current_sclk = adev->clock.default_sclk;
6195         adev->pm.current_mclk = adev->clock.default_mclk;
6196         adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
6197
6198         if (amdgpu_dpm == 0)
6199                 return 0;
6200
6201         ret = ci_dpm_init_microcode(adev);
6202         if (ret)
6203                 return ret;
6204
6205         INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
6206         mutex_lock(&adev->pm.mutex);
6207         ret = ci_dpm_init(adev);
6208         if (ret)
6209                 goto dpm_failed;
6210         adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
6211         if (amdgpu_dpm == 1)
6212                 amdgpu_pm_print_power_states(adev);
6213         mutex_unlock(&adev->pm.mutex);
6214         DRM_INFO("amdgpu: dpm initialized\n");
6215
6216         return 0;
6217
6218 dpm_failed:
6219         ci_dpm_fini(adev);
6220         mutex_unlock(&adev->pm.mutex);
6221         DRM_ERROR("amdgpu: dpm initialization failed\n");
6222         return ret;
6223 }
6224
6225 static int ci_dpm_sw_fini(void *handle)
6226 {
6227         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6228
6229         mutex_lock(&adev->pm.mutex);
6230         amdgpu_pm_sysfs_fini(adev);
6231         ci_dpm_fini(adev);
6232         mutex_unlock(&adev->pm.mutex);
6233
6234         release_firmware(adev->pm.fw);
6235         adev->pm.fw = NULL;
6236
6237         return 0;
6238 }
6239
6240 static int ci_dpm_hw_init(void *handle)
6241 {
6242         int ret;
6243
6244         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6245
6246         if (!amdgpu_dpm)
6247                 return 0;
6248
6249         mutex_lock(&adev->pm.mutex);
6250         ci_dpm_setup_asic(adev);
6251         ret = ci_dpm_enable(adev);
6252         if (ret)
6253                 adev->pm.dpm_enabled = false;
6254         else
6255                 adev->pm.dpm_enabled = true;
6256         mutex_unlock(&adev->pm.mutex);
6257
6258         return ret;
6259 }
6260
6261 static int ci_dpm_hw_fini(void *handle)
6262 {
6263         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6264
6265         if (adev->pm.dpm_enabled) {
6266                 mutex_lock(&adev->pm.mutex);
6267                 ci_dpm_disable(adev);
6268                 mutex_unlock(&adev->pm.mutex);
6269         }
6270
6271         return 0;
6272 }
6273
6274 static int ci_dpm_suspend(void *handle)
6275 {
6276         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6277
6278         if (adev->pm.dpm_enabled) {
6279                 mutex_lock(&adev->pm.mutex);
6280                 /* disable dpm */
6281                 ci_dpm_disable(adev);
6282                 /* reset the power state */
6283                 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
6284                 mutex_unlock(&adev->pm.mutex);
6285         }
6286         return 0;
6287 }
6288
6289 static int ci_dpm_resume(void *handle)
6290 {
6291         int ret;
6292         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6293
6294         if (adev->pm.dpm_enabled) {
6295                 /* asic init will reset to the boot state */
6296                 mutex_lock(&adev->pm.mutex);
6297                 ci_dpm_setup_asic(adev);
6298                 ret = ci_dpm_enable(adev);
6299                 if (ret)
6300                         adev->pm.dpm_enabled = false;
6301                 else
6302                         adev->pm.dpm_enabled = true;
6303                 mutex_unlock(&adev->pm.mutex);
6304                 if (adev->pm.dpm_enabled)
6305                         amdgpu_pm_compute_clocks(adev);
6306         }
6307         return 0;
6308 }
6309
6310 static bool ci_dpm_is_idle(void *handle)
6311 {
6312         /* XXX */
6313         return true;
6314 }
6315
6316 static int ci_dpm_wait_for_idle(void *handle)
6317 {
6318         /* XXX */
6319         return 0;
6320 }
6321
6322 static int ci_dpm_soft_reset(void *handle)
6323 {
6324         return 0;
6325 }
6326
6327 static int ci_dpm_set_interrupt_state(struct amdgpu_device *adev,
6328                                       struct amdgpu_irq_src *source,
6329                                       unsigned type,
6330                                       enum amdgpu_interrupt_state state)
6331 {
6332         u32 cg_thermal_int;
6333
6334         switch (type) {
6335         case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
6336                 switch (state) {
6337                 case AMDGPU_IRQ_STATE_DISABLE:
6338                         cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
6339                         cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
6340                         WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
6341                         break;
6342                 case AMDGPU_IRQ_STATE_ENABLE:
6343                         cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
6344                         cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
6345                         WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
6346                         break;
6347                 default:
6348                         break;
6349                 }
6350                 break;
6351
6352         case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
6353                 switch (state) {
6354                 case AMDGPU_IRQ_STATE_DISABLE:
6355                         cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
6356                         cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
6357                         WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
6358                         break;
6359                 case AMDGPU_IRQ_STATE_ENABLE:
6360                         cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
6361                         cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
6362                         WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
6363                         break;
6364                 default:
6365                         break;
6366                 }
6367                 break;
6368
6369         default:
6370                 break;
6371         }
6372         return 0;
6373 }
6374
6375 static int ci_dpm_process_interrupt(struct amdgpu_device *adev,
6376                                     struct amdgpu_irq_src *source,
6377                                     struct amdgpu_iv_entry *entry)
6378 {
6379         bool queue_thermal = false;
6380
6381         if (entry == NULL)
6382                 return -EINVAL;
6383
6384         switch (entry->src_id) {
6385         case 230: /* thermal low to high */
6386                 DRM_DEBUG("IH: thermal low to high\n");
6387                 adev->pm.dpm.thermal.high_to_low = false;
6388                 queue_thermal = true;
6389                 break;
6390         case 231: /* thermal high to low */
6391                 DRM_DEBUG("IH: thermal high to low\n");
6392                 adev->pm.dpm.thermal.high_to_low = true;
6393                 queue_thermal = true;
6394                 break;
6395         default:
6396                 break;
6397         }
6398
6399         if (queue_thermal)
6400                 schedule_work(&adev->pm.dpm.thermal.work);
6401
6402         return 0;
6403 }
6404
6405 static int ci_dpm_set_clockgating_state(void *handle,
6406                                           enum amd_clockgating_state state)
6407 {
6408         return 0;
6409 }
6410
6411 static int ci_dpm_set_powergating_state(void *handle,
6412                                           enum amd_powergating_state state)
6413 {
6414         return 0;
6415 }
6416
6417 const struct amd_ip_funcs ci_dpm_ip_funcs = {
6418         .name = "ci_dpm",
6419         .early_init = ci_dpm_early_init,
6420         .late_init = ci_dpm_late_init,
6421         .sw_init = ci_dpm_sw_init,
6422         .sw_fini = ci_dpm_sw_fini,
6423         .hw_init = ci_dpm_hw_init,
6424         .hw_fini = ci_dpm_hw_fini,
6425         .suspend = ci_dpm_suspend,
6426         .resume = ci_dpm_resume,
6427         .is_idle = ci_dpm_is_idle,
6428         .wait_for_idle = ci_dpm_wait_for_idle,
6429         .soft_reset = ci_dpm_soft_reset,
6430         .set_clockgating_state = ci_dpm_set_clockgating_state,
6431         .set_powergating_state = ci_dpm_set_powergating_state,
6432 };
6433
6434 static const struct amdgpu_dpm_funcs ci_dpm_funcs = {
6435         .get_temperature = &ci_dpm_get_temp,
6436         .pre_set_power_state = &ci_dpm_pre_set_power_state,
6437         .set_power_state = &ci_dpm_set_power_state,
6438         .post_set_power_state = &ci_dpm_post_set_power_state,
6439         .display_configuration_changed = &ci_dpm_display_configuration_changed,
6440         .get_sclk = &ci_dpm_get_sclk,
6441         .get_mclk = &ci_dpm_get_mclk,
6442         .print_power_state = &ci_dpm_print_power_state,
6443         .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
6444         .force_performance_level = &ci_dpm_force_performance_level,
6445         .vblank_too_short = &ci_dpm_vblank_too_short,
6446         .powergate_uvd = &ci_dpm_powergate_uvd,
6447         .set_fan_control_mode = &ci_dpm_set_fan_control_mode,
6448         .get_fan_control_mode = &ci_dpm_get_fan_control_mode,
6449         .set_fan_speed_percent = &ci_dpm_set_fan_speed_percent,
6450         .get_fan_speed_percent = &ci_dpm_get_fan_speed_percent,
6451 };
6452
6453 static void ci_dpm_set_dpm_funcs(struct amdgpu_device *adev)
6454 {
6455         if (adev->pm.funcs == NULL)
6456                 adev->pm.funcs = &ci_dpm_funcs;
6457 }
6458
6459 static const struct amdgpu_irq_src_funcs ci_dpm_irq_funcs = {
6460         .set = ci_dpm_set_interrupt_state,
6461         .process = ci_dpm_process_interrupt,
6462 };
6463
6464 static void ci_dpm_set_irq_funcs(struct amdgpu_device *adev)
6465 {
6466         adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
6467         adev->pm.dpm.thermal.irq.funcs = &ci_dpm_irq_funcs;
6468 }