drivers/gpu/drm/amd/amdgpu/dce_v11_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "drmP.h"
  24 #include "amdgpu.h"
  25 #include "amdgpu_pm.h"
  26 #include "amdgpu_i2c.h"
  27 #include "vid.h"
  28 #include "atom.h"
  29 #include "amdgpu_atombios.h"
  30 #include "atombios_crtc.h"
  31 #include "atombios_encoders.h"
  32 #include "amdgpu_pll.h"
  33 #include "amdgpu_connectors.h"
  34
  35 #include "dce/dce_11_0_d.h"
  36 #include "dce/dce_11_0_sh_mask.h"
  37 #include "dce/dce_11_0_enum.h"
  38 #include "oss/oss_3_0_d.h"
  39 #include "oss/oss_3_0_sh_mask.h"
  40 #include "gmc/gmc_8_1_d.h"
  41 #include "gmc/gmc_8_1_sh_mask.h"
  42
  43 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev);
  44 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev);
  45
  46 static const u32 crtc_offsets[] =
  47 {
  48         CRTC0_REGISTER_OFFSET,
  49         CRTC1_REGISTER_OFFSET,
  50         CRTC2_REGISTER_OFFSET,
  51         CRTC3_REGISTER_OFFSET,
  52         CRTC4_REGISTER_OFFSET,
  53         CRTC5_REGISTER_OFFSET,
  54         CRTC6_REGISTER_OFFSET
  55 };
  56
  57 static const u32 hpd_offsets[] =
  58 {
  59         HPD0_REGISTER_OFFSET,
  60         HPD1_REGISTER_OFFSET,
  61         HPD2_REGISTER_OFFSET,
  62         HPD3_REGISTER_OFFSET,
  63         HPD4_REGISTER_OFFSET,
  64         HPD5_REGISTER_OFFSET
  65 };
  66
  67 static const uint32_t dig_offsets[] = {
  68         DIG0_REGISTER_OFFSET,
  69         DIG1_REGISTER_OFFSET,
  70         DIG2_REGISTER_OFFSET,
  71         DIG3_REGISTER_OFFSET,
  72         DIG4_REGISTER_OFFSET,
  73         DIG5_REGISTER_OFFSET,
  74         DIG6_REGISTER_OFFSET,
  75         DIG7_REGISTER_OFFSET,
  76         DIG8_REGISTER_OFFSET
  77 };
  78
  79 static const struct {
  80         uint32_t        reg;
  81         uint32_t        vblank;
  82         uint32_t        vline;
  83         uint32_t        hpd;
  84
  85 } interrupt_status_offsets[] = { {
  86         .reg = mmDISP_INTERRUPT_STATUS,
  87         .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
  88         .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
  89         .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
  90 }, {
  91         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
  92         .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
  93         .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
  94         .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
  95 }, {
  96         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
  97         .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
  98         .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
  99         .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
 100 }, {
 101         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
 102         .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
 103         .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
 104         .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
 105 }, {
 106         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
 107         .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
 108         .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
 109         .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
 110 }, {
 111         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
 112         .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
 113         .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
 114         .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
 115 } };
 116
 117 static const u32 cz_golden_settings_a11[] =
 118 {
 119         mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
 120         mmFBC_MISC, 0x1f311fff, 0x14300000,
 121 };
 122
 123 static const u32 cz_mgcg_cgcg_init[] =
 124 {
 125         mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
 126         mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
 127 };
 128
 129 static const u32 stoney_golden_settings_a11[] =
 130 {
 131         mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
 132         mmFBC_MISC, 0x1f311fff, 0x14302000,
 133 };
 134
 135 static const u32 polaris11_golden_settings_a11[] =
 136 {
 137         mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
 138         mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
 139         mmFBC_DEBUG1, 0xffffffff, 0x00000008,
 140         mmFBC_MISC, 0x9f313fff, 0x14300008,
 141         mmHDMI_CONTROL, 0x313f031f, 0x00000011,
 142 };
 143
 144 static const u32 polaris10_golden_settings_a11[] =
 145 {
 146         mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
 147         mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
 148         mmFBC_MISC, 0x9f313fff, 0x14300008,
 149         mmHDMI_CONTROL, 0x313f031f, 0x00000011,
 150 };
 151
 152 static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
 153 {
 154         switch (adev->asic_type) {
 155         case CHIP_CARRIZO:
 156                 amdgpu_program_register_sequence(adev,
 157                                                  cz_mgcg_cgcg_init,
 158                                                  (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
 159                 amdgpu_program_register_sequence(adev,
 160                                                  cz_golden_settings_a11,
 161                                                  (const u32)ARRAY_SIZE(cz_golden_settings_a11));
 162                 break;
 163         case CHIP_STONEY:
 164                 amdgpu_program_register_sequence(adev,
 165                                                  stoney_golden_settings_a11,
 166                                                  (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
 167                 break;
 168         case CHIP_POLARIS11:
 169                 amdgpu_program_register_sequence(adev,
 170                                                  polaris11_golden_settings_a11,
 171                                                  (const u32)ARRAY_SIZE(polaris11_golden_settings_a11));
 172                 break;
 173         case CHIP_POLARIS10:
 174                 amdgpu_program_register_sequence(adev,
 175                                                  polaris10_golden_settings_a11,
 176                                                  (const u32)ARRAY_SIZE(polaris10_golden_settings_a11));
 177                 break;
 178         default:
 179                 break;
 180         }
 181 }
 182
 183 static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev,
 184                                      u32 block_offset, u32 reg)
 185 {
 186         unsigned long flags;
 187         u32 r;
 188
 189         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 190         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 191         r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
 192         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 193
 194         return r;
 195 }
 196
 197 static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev,
 198                                       u32 block_offset, u32 reg, u32 v)
 199 {
 200         unsigned long flags;
 201
 202         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 203         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 204         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
 205         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 206 }
 207
 208 static bool dce_v11_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
 209 {
 210         if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
 211                         CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
 212                 return true;
 213         else
 214                 return false;
 215 }
 216
 217 static bool dce_v11_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
 218 {
 219         u32 pos1, pos2;
 220
 221         pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 222         pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 223
 224         if (pos1 != pos2)
 225                 return true;
 226         else
 227                 return false;
 228 }
 229
 230 /**
 231  * dce_v11_0_vblank_wait - vblank wait asic callback.
 232  *
 233  * @adev: amdgpu_device pointer
 234  * @crtc: crtc to wait for vblank on
 235  *
 236  * Wait for vblank on the requested crtc (evergreen+).
 237  */
 238 static void dce_v11_0_vblank_wait(struct amdgpu_device *adev, int crtc)
 239 {
 240         unsigned i = 100;
 241
 242         if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
 243                 return;
 244
 245         if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
 246                 return;
 247
 248         /* depending on when we hit vblank, we may be close to active; if so,
 249          * wait for another frame.
 250          */
 251         while (dce_v11_0_is_in_vblank(adev, crtc)) {
 252                 if (i++ == 100) {
 253                         i = 0;
 254                         if (!dce_v11_0_is_counter_moving(adev, crtc))
 255                                 break;
 256                 }
 257         }
 258
 259         while (!dce_v11_0_is_in_vblank(adev, crtc)) {
 260                 if (i++ == 100) {
 261                         i = 0;
 262                         if (!dce_v11_0_is_counter_moving(adev, crtc))
 263                                 break;
 264                 }
 265         }
 266 }
 267
 268 static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 269 {
 270         if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
 271                 return 0;
 272         else
 273                 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
 274 }
 275
 276 static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev)
 277 {
 278         unsigned i;
 279
 280         /* Enable pflip interrupts */
 281         for (i = 0; i < adev->mode_info.num_crtc; i++)
 282                 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
 283 }
 284
 285 static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
 286 {
 287         unsigned i;
 288
 289         /* Disable pflip interrupts */
 290         for (i = 0; i < adev->mode_info.num_crtc; i++)
 291                 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
 292 }
 293
 294 /**
 295  * dce_v11_0_page_flip - pageflip callback.
 296  *
 297  * @adev: amdgpu_device pointer
 298  * @crtc_id: crtc to cleanup pageflip on
 299  * @crtc_base: new address of the crtc (GPU MC address)
 300  *
 301  * Triggers the actual pageflip by updating the primary
 302  * surface base address.
 303  */
 304 static void dce_v11_0_page_flip(struct amdgpu_device *adev,
 305                                 int crtc_id, u64 crtc_base, bool async)
 306 {
 307         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
 308         u32 tmp;
 309
 310         /* flip at hsync for async, default is vsync */
 311         /* use UPDATE_IMMEDIATE_EN instead for async? */
 312         tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
 313         tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
 314                             GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0);
 315         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
 316         /* update the scanout addresses */
 317         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
 318                upper_32_bits(crtc_base));
 319         /* writing to the low address triggers the update */
 320         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
 321                lower_32_bits(crtc_base));
 322         /* post the write */
 323         RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
 324 }
 325
 326 static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 327                                         u32 *vbl, u32 *position)
 328 {
 329         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 330                 return -EINVAL;
 331
 332         *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
 333         *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 334
 335         return 0;
 336 }
 337
 338 /**
 339  * dce_v11_0_hpd_sense - hpd sense callback.
 340  *
 341  * @adev: amdgpu_device pointer
 342  * @hpd: hpd (hotplug detect) pin
 343  *
 344  * Checks if a digital monitor is connected (evergreen+).
 345  * Returns true if connected, false if not connected.
 346  */
 347 static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev,
 348                                enum amdgpu_hpd_id hpd)
 349 {
 350         int idx;
 351         bool connected = false;
 352
 353         switch (hpd) {
 354         case AMDGPU_HPD_1:
 355                 idx = 0;
 356                 break;
 357         case AMDGPU_HPD_2:
 358                 idx = 1;
 359                 break;
 360         case AMDGPU_HPD_3:
 361                 idx = 2;
 362                 break;
 363         case AMDGPU_HPD_4:
 364                 idx = 3;
 365                 break;
 366         case AMDGPU_HPD_5:
 367                 idx = 4;
 368                 break;
 369         case AMDGPU_HPD_6:
 370                 idx = 5;
 371                 break;
 372         default:
 373                 return connected;
 374         }
 375
 376         if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) &
 377             DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
 378                 connected = true;
 379
 380         return connected;
 381 }
 382
 383 /**
 384  * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
 385  *
 386  * @adev: amdgpu_device pointer
 387  * @hpd: hpd (hotplug detect) pin
 388  *
 389  * Set the polarity of the hpd pin (evergreen+).
 390  */
 391 static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev,
 392                                       enum amdgpu_hpd_id hpd)
 393 {
 394         u32 tmp;
 395         bool connected = dce_v11_0_hpd_sense(adev, hpd);
 396         int idx;
 397
 398         switch (hpd) {
 399         case AMDGPU_HPD_1:
 400                 idx = 0;
 401                 break;
 402         case AMDGPU_HPD_2:
 403                 idx = 1;
 404                 break;
 405         case AMDGPU_HPD_3:
 406                 idx = 2;
 407                 break;
 408         case AMDGPU_HPD_4:
 409                 idx = 3;
 410                 break;
 411         case AMDGPU_HPD_5:
 412                 idx = 4;
 413                 break;
 414         case AMDGPU_HPD_6:
 415                 idx = 5;
 416                 break;
 417         default:
 418                 return;
 419         }
 420
 421         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]);
 422         if (connected)
 423                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
 424         else
 425                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
 426         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp);
 427 }
 428
 429 /**
 430  * dce_v11_0_hpd_init - hpd setup callback.
 431  *
 432  * @adev: amdgpu_device pointer
 433  *
 434  * Setup the hpd pins used by the card (evergreen+).
 435  * Enable the pin, set the polarity, and enable the hpd interrupts.
 436  */
 437 static void dce_v11_0_hpd_init(struct amdgpu_device *adev)
 438 {
 439         struct drm_device *dev = adev->ddev;
 440         struct drm_connector *connector;
 441         u32 tmp;
 442         int idx;
 443
 444         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 445                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 446
 447                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
 448                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 449                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
 450                          * aux dp channel on imac and help (but not completely fix)
 451                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
 452                          * also avoid interrupt storms during dpms.
 453                          */
 454                         continue;
 455                 }
 456
 457                 switch (amdgpu_connector->hpd.hpd) {
 458                 case AMDGPU_HPD_1:
 459                         idx = 0;
 460                         break;
 461                 case AMDGPU_HPD_2:
 462                         idx = 1;
 463                         break;
 464                 case AMDGPU_HPD_3:
 465                         idx = 2;
 466                         break;
 467                 case AMDGPU_HPD_4:
 468                         idx = 3;
 469                         break;
 470                 case AMDGPU_HPD_5:
 471                         idx = 4;
 472                         break;
 473                 case AMDGPU_HPD_6:
 474                         idx = 5;
 475                         break;
 476                 default:
 477                         continue;
 478                 }
 479
 480                 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
 481                 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
 482                 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
 483
 484                 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]);
 485                 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
 486                                     DC_HPD_CONNECT_INT_DELAY,
 487                                     AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
 488                 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
 489                                     DC_HPD_DISCONNECT_INT_DELAY,
 490                                     AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
 491                 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp);
 492
 493                 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
 494                 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
 495         }
 496 }
 497
 498 /**
 499  * dce_v11_0_hpd_fini - hpd tear down callback.
 500  *
 501  * @adev: amdgpu_device pointer
 502  *
 503  * Tear down the hpd pins used by the card (evergreen+).
 504  * Disable the hpd interrupts.
 505  */
 506 static void dce_v11_0_hpd_fini(struct amdgpu_device *adev)
 507 {
 508         struct drm_device *dev = adev->ddev;
 509         struct drm_connector *connector;
 510         u32 tmp;
 511         int idx;
 512
 513         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 514                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 515
 516                 switch (amdgpu_connector->hpd.hpd) {
 517                 case AMDGPU_HPD_1:
 518                         idx = 0;
 519                         break;
 520                 case AMDGPU_HPD_2:
 521                         idx = 1;
 522                         break;
 523                 case AMDGPU_HPD_3:
 524                         idx = 2;
 525                         break;
 526                 case AMDGPU_HPD_4:
 527                         idx = 3;
 528                         break;
 529                 case AMDGPU_HPD_5:
 530                         idx = 4;
 531                         break;
 532                 case AMDGPU_HPD_6:
 533                         idx = 5;
 534                         break;
 535                 default:
 536                         continue;
 537                 }
 538
 539                 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
 540                 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
 541                 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
 542
 543                 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
 544         }
 545 }
 546
 547 static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
 548 {
 549         return mmDC_GPIO_HPD_A;
 550 }
 551
 552 static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev)
 553 {
 554         u32 crtc_hung = 0;
 555         u32 crtc_status[6];
 556         u32 i, j, tmp;
 557
 558         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 559                 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 560                 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
 561                         crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 562                         crtc_hung |= (1 << i);
 563                 }
 564         }
 565
 566         for (j = 0; j < 10; j++) {
 567                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
 568                         if (crtc_hung & (1 << i)) {
 569                                 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 570                                 if (tmp != crtc_status[i])
 571                                         crtc_hung &= ~(1 << i);
 572                         }
 573                 }
 574                 if (crtc_hung == 0)
 575                         return false;
 576                 udelay(100);
 577         }
 578
 579         return true;
 580 }
 581
 582 static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev,
 583                                      struct amdgpu_mode_mc_save *save)
 584 {
 585         u32 crtc_enabled, tmp;
 586         int i;
 587
 588         save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
 589         save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
 590
 591         /* disable VGA render */
 592         tmp = RREG32(mmVGA_RENDER_CONTROL);
 593         tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 594         WREG32(mmVGA_RENDER_CONTROL, tmp);
 595
 596         /* blank the display controllers */
 597         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 598                 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
 599                                              CRTC_CONTROL, CRTC_MASTER_EN);
 600                 if (crtc_enabled) {
 601 #if 1
 602                         save->crtc_enabled[i] = true;
 603                         tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
 604                         if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
 605                                 /*it is correct only for RGB ; black is 0*/
 606                                 WREG32(mmCRTC_BLANK_DATA_COLOR + crtc_offsets[i], 0);
 607                                 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
 608                                 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
 609                         }
 610 #else
 611                         /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
 612                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 613                         tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 614                         tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
 615                         WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
 616                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 617                         save->crtc_enabled[i] = false;
 618                         /* ***** */
 619 #endif
 620                 } else {
 621                         save->crtc_enabled[i] = false;
 622                 }
 623         }
 624 }
 625
 626 static void dce_v11_0_resume_mc_access(struct amdgpu_device *adev,
 627                                        struct amdgpu_mode_mc_save *save)
 628 {
 629         u32 tmp;
 630         int i;
 631
 632         /* update crtc base addresses */
 633         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 634                 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
 635                        upper_32_bits(adev->mc.vram_start));
 636                 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
 637                        (u32)adev->mc.vram_start);
 638
 639                 if (save->crtc_enabled[i]) {
 640                         tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
 641                         tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
 642                         WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
 643                 }
 644         }
 645
 646         WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
 647         WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
 648
 649         /* Unlock vga access */
 650         WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
 651         mdelay(1);
 652         WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
 653 }
 654
 655 static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,
 656                                            bool render)
 657 {
 658         u32 tmp;
 659
 660         /* Lockout access through VGA aperture*/
 661         tmp = RREG32(mmVGA_HDP_CONTROL);
 662         if (render)
 663                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
 664         else
 665                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 666         WREG32(mmVGA_HDP_CONTROL, tmp);
 667
 668         /* disable VGA render */
 669         tmp = RREG32(mmVGA_RENDER_CONTROL);
 670         if (render)
 671                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
 672         else
 673                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 674         WREG32(mmVGA_RENDER_CONTROL, tmp);
 675 }
 676
 677 static void dce_v11_0_program_fmt(struct drm_encoder *encoder)
 678 {
 679         struct drm_device *dev = encoder->dev;
 680         struct amdgpu_device *adev = dev->dev_private;
 681         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 682         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
 683         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
 684         int bpc = 0;
 685         u32 tmp = 0;
 686         enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
 687
 688         if (connector) {
 689                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 690                 bpc = amdgpu_connector_get_monitor_bpc(connector);
 691                 dither = amdgpu_connector->dither;
 692         }
 693
 694         /* LVDS/eDP FMT is set up by atom */
 695         if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
 696                 return;
 697
 698         /* not needed for analog */
 699         if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
 700             (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
 701                 return;
 702
 703         if (bpc == 0)
 704                 return;
 705
 706         switch (bpc) {
 707         case 6:
 708                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 709                         /* XXX sort out optimal dither settings */
 710                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 711                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 712                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 713                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
 714                 } else {
 715                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 716                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
 717                 }
 718                 break;
 719         case 8:
 720                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 721                         /* XXX sort out optimal dither settings */
 722                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 723                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 724                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
 725                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 726                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
 727                 } else {
 728                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 729                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
 730                 }
 731                 break;
 732         case 10:
 733                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 734                         /* XXX sort out optimal dither settings */
 735                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 736                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 737                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
 738                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 739                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
 740                 } else {
 741                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 742                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
 743                 }
 744                 break;
 745         default:
 746                 /* not needed */
 747                 break;
 748         }
 749
 750         WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
 751 }
 752
 753
 754 /* display watermark setup */
 755 /**
 756  * dce_v11_0_line_buffer_adjust - Set up the line buffer
 757  *
 758  * @adev: amdgpu_device pointer
 759  * @amdgpu_crtc: the selected display controller
 760  * @mode: the current display mode on the selected display
 761  * controller
 762  *
 763  * Setup up the line buffer allocation for
 764  * the selected display controller (CIK).
 765  * Returns the line buffer size in pixels.
 766  */
 767 static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev,
 768                                        struct amdgpu_crtc *amdgpu_crtc,
 769                                        struct drm_display_mode *mode)
 770 {
 771         u32 tmp, buffer_alloc, i, mem_cfg;
 772         u32 pipe_offset = amdgpu_crtc->crtc_id;
 773         /*
 774          * Line Buffer Setup
 775          * There are 6 line buffers, one for each display controllers.
 776          * There are 3 partitions per LB. Select the number of partitions
 777          * to enable based on the display width.  For display widths larger
 778          * than 4096, you need use to use 2 display controllers and combine
 779          * them using the stereo blender.
 780          */
 781         if (amdgpu_crtc->base.enabled && mode) {
 782                 if (mode->crtc_hdisplay < 1920) {
 783                         mem_cfg = 1;
 784                         buffer_alloc = 2;
 785                 } else if (mode->crtc_hdisplay < 2560) {
 786                         mem_cfg = 2;
 787                         buffer_alloc = 2;
 788                 } else if (mode->crtc_hdisplay < 4096) {
 789                         mem_cfg = 0;
 790                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 791                 } else {
 792                         DRM_DEBUG_KMS("Mode too big for LB!\n");
 793                         mem_cfg = 0;
 794                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 795                 }
 796         } else {
 797                 mem_cfg = 1;
 798                 buffer_alloc = 0;
 799         }
 800
 801         tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
 802         tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
 803         WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
 804
 805         tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
 806         tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
 807         WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
 808
 809         for (i = 0; i < adev->usec_timeout; i++) {
 810                 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
 811                 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
 812                         break;
 813                 udelay(1);
 814         }
 815
 816         if (amdgpu_crtc->base.enabled && mode) {
 817                 switch (mem_cfg) {
 818                 case 0:
 819                 default:
 820                         return 4096 * 2;
 821                 case 1:
 822                         return 1920 * 2;
 823                 case 2:
 824                         return 2560 * 2;
 825                 }
 826         }
 827
 828         /* controller not enabled, so no lb used */
 829         return 0;
 830 }
 831
 832 /**
 833  * cik_get_number_of_dram_channels - get the number of dram channels
 834  *
 835  * @adev: amdgpu_device pointer
 836  *
 837  * Look up the number of video ram channels (CIK).
 838  * Used for display watermark bandwidth calculations
 839  * Returns the number of dram channels
 840  */
 841 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
 842 {
 843         u32 tmp = RREG32(mmMC_SHARED_CHMAP);
 844
 845         switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 846         case 0:
 847         default:
 848                 return 1;
 849         case 1:
 850                 return 2;
 851         case 2:
 852                 return 4;
 853         case 3:
 854                 return 8;
 855         case 4:
 856                 return 3;
 857         case 5:
 858                 return 6;
 859         case 6:
 860                 return 10;
 861         case 7:
 862                 return 12;
 863         case 8:
 864                 return 16;
 865         }
 866 }
 867
 868 struct dce10_wm_params {
 869         u32 dram_channels; /* number of dram channels */
 870         u32 yclk;          /* bandwidth per dram data pin in kHz */
 871         u32 sclk;          /* engine clock in kHz */
 872         u32 disp_clk;      /* display clock in kHz */
 873         u32 src_width;     /* viewport width */
 874         u32 active_time;   /* active display time in ns */
 875         u32 blank_time;    /* blank time in ns */
 876         bool interlaced;    /* mode is interlaced */
 877         fixed20_12 vsc;    /* vertical scale ratio */
 878         u32 num_heads;     /* number of active crtcs */
 879         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 880         u32 lb_size;       /* line buffer allocated to pipe */
 881         u32 vtaps;         /* vertical scaler taps */
 882 };
 883
 884 /**
 885  * dce_v11_0_dram_bandwidth - get the dram bandwidth
 886  *
 887  * @wm: watermark calculation data
 888  *
 889  * Calculate the raw dram bandwidth (CIK).
 890  * Used for display watermark bandwidth calculations
 891  * Returns the dram bandwidth in MBytes/s
 892  */
 893 static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm)
 894 {
 895         /* Calculate raw DRAM Bandwidth */
 896         fixed20_12 dram_efficiency; /* 0.7 */
 897         fixed20_12 yclk, dram_channels, bandwidth;
 898         fixed20_12 a;
 899
 900         a.full = dfixed_const(1000);
 901         yclk.full = dfixed_const(wm->yclk);
 902         yclk.full = dfixed_div(yclk, a);
 903         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 904         a.full = dfixed_const(10);
 905         dram_efficiency.full = dfixed_const(7);
 906         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 907         bandwidth.full = dfixed_mul(dram_channels, yclk);
 908         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 909
 910         return dfixed_trunc(bandwidth);
 911 }
 912
 913 /**
 914  * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display
 915  *
 916  * @wm: watermark calculation data
 917  *
 918  * Calculate the dram bandwidth used for display (CIK).
 919  * Used for display watermark bandwidth calculations
 920  * Returns the dram bandwidth for display in MBytes/s
 921  */
 922 static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
 923 {
 924         /* Calculate DRAM Bandwidth and the part allocated to display. */
 925         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 926         fixed20_12 yclk, dram_channels, bandwidth;
 927         fixed20_12 a;
 928
 929         a.full = dfixed_const(1000);
 930         yclk.full = dfixed_const(wm->yclk);
 931         yclk.full = dfixed_div(yclk, a);
 932         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 933         a.full = dfixed_const(10);
 934         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 935         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 936         bandwidth.full = dfixed_mul(dram_channels, yclk);
 937         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 938
 939         return dfixed_trunc(bandwidth);
 940 }
 941
 942 /**
 943  * dce_v11_0_data_return_bandwidth - get the data return bandwidth
 944  *
 945  * @wm: watermark calculation data
 946  *
 947  * Calculate the data return bandwidth used for display (CIK).
 948  * Used for display watermark bandwidth calculations
 949  * Returns the data return bandwidth in MBytes/s
 950  */
 951 static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm)
 952 {
 953         /* Calculate the display Data return Bandwidth */
 954         fixed20_12 return_efficiency; /* 0.8 */
 955         fixed20_12 sclk, bandwidth;
 956         fixed20_12 a;
 957
 958         a.full = dfixed_const(1000);
 959         sclk.full = dfixed_const(wm->sclk);
 960         sclk.full = dfixed_div(sclk, a);
 961         a.full = dfixed_const(10);
 962         return_efficiency.full = dfixed_const(8);
 963         return_efficiency.full = dfixed_div(return_efficiency, a);
 964         a.full = dfixed_const(32);
 965         bandwidth.full = dfixed_mul(a, sclk);
 966         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
 967
 968         return dfixed_trunc(bandwidth);
 969 }
 970
 971 /**
 972  * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth
 973  *
 974  * @wm: watermark calculation data
 975  *
 976  * Calculate the dmif bandwidth used for display (CIK).
 977  * Used for display watermark bandwidth calculations
 978  * Returns the dmif bandwidth in MBytes/s
 979  */
 980 static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
 981 {
 982         /* Calculate the DMIF Request Bandwidth */
 983         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
 984         fixed20_12 disp_clk, bandwidth;
 985         fixed20_12 a, b;
 986
 987         a.full = dfixed_const(1000);
 988         disp_clk.full = dfixed_const(wm->disp_clk);
 989         disp_clk.full = dfixed_div(disp_clk, a);
 990         a.full = dfixed_const(32);
 991         b.full = dfixed_mul(a, disp_clk);
 992
 993         a.full = dfixed_const(10);
 994         disp_clk_request_efficiency.full = dfixed_const(8);
 995         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
 996
 997         bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
 998
 999         return dfixed_trunc(bandwidth);
1000 }
1001
1002 /**
1003  * dce_v11_0_available_bandwidth - get the min available bandwidth
1004  *
1005  * @wm: watermark calculation data
1006  *
1007  * Calculate the min available bandwidth used for display (CIK).
1008  * Used for display watermark bandwidth calculations
1009  * Returns the min available bandwidth in MBytes/s
1010  */
1011 static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm)
1012 {
1013         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
1014         u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm);
1015         u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm);
1016         u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm);
1017
1018         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
1019 }
1020
1021 /**
1022  * dce_v11_0_average_bandwidth - get the average available bandwidth
1023  *
1024  * @wm: watermark calculation data
1025  *
1026  * Calculate the average available bandwidth used for display (CIK).
1027  * Used for display watermark bandwidth calculations
1028  * Returns the average available bandwidth in MBytes/s
1029  */
1030 static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm)
1031 {
1032         /* Calculate the display mode Average Bandwidth
1033          * DisplayMode should contain the source and destination dimensions,
1034          * timing, etc.
1035          */
1036         fixed20_12 bpp;
1037         fixed20_12 line_time;
1038         fixed20_12 src_width;
1039         fixed20_12 bandwidth;
1040         fixed20_12 a;
1041
1042         a.full = dfixed_const(1000);
1043         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
1044         line_time.full = dfixed_div(line_time, a);
1045         bpp.full = dfixed_const(wm->bytes_per_pixel);
1046         src_width.full = dfixed_const(wm->src_width);
1047         bandwidth.full = dfixed_mul(src_width, bpp);
1048         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
1049         bandwidth.full = dfixed_div(bandwidth, line_time);
1050
1051         return dfixed_trunc(bandwidth);
1052 }
1053
1054 /**
1055  * dce_v11_0_latency_watermark - get the latency watermark
1056  *
1057  * @wm: watermark calculation data
1058  *
1059  * Calculate the latency watermark (CIK).
1060  * Used for display watermark bandwidth calculations
1061  * Returns the latency watermark in ns
1062  */
1063 static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm)
1064 {
1065         /* First calculate the latency in ns */
1066         u32 mc_latency = 2000; /* 2000 ns. */
1067         u32 available_bandwidth = dce_v11_0_available_bandwidth(wm);
1068         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
1069         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
1070         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
1071         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
1072                 (wm->num_heads * cursor_line_pair_return_time);
1073         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
1074         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
1075         u32 tmp, dmif_size = 12288;
1076         fixed20_12 a, b, c;
1077
1078         if (wm->num_heads == 0)
1079                 return 0;
1080
1081         a.full = dfixed_const(2);
1082         b.full = dfixed_const(1);
1083         if ((wm->vsc.full > a.full) ||
1084             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
1085             (wm->vtaps >= 5) ||
1086             ((wm->vsc.full >= a.full) && wm->interlaced))
1087                 max_src_lines_per_dst_line = 4;
1088         else
1089                 max_src_lines_per_dst_line = 2;
1090
1091         a.full = dfixed_const(available_bandwidth);
1092         b.full = dfixed_const(wm->num_heads);
1093         a.full = dfixed_div(a, b);
1094
1095         b.full = dfixed_const(mc_latency + 512);
1096         c.full = dfixed_const(wm->disp_clk);
1097         b.full = dfixed_div(b, c);
1098
1099         c.full = dfixed_const(dmif_size);
1100         b.full = dfixed_div(c, b);
1101
1102         tmp = min(dfixed_trunc(a), dfixed_trunc(b));
1103
1104         b.full = dfixed_const(1000);
1105         c.full = dfixed_const(wm->disp_clk);
1106         b.full = dfixed_div(c, b);
1107         c.full = dfixed_const(wm->bytes_per_pixel);
1108         b.full = dfixed_mul(b, c);
1109
1110         lb_fill_bw = min(tmp, dfixed_trunc(b));
1111
1112         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1113         b.full = dfixed_const(1000);
1114         c.full = dfixed_const(lb_fill_bw);
1115         b.full = dfixed_div(c, b);
1116         a.full = dfixed_div(a, b);
1117         line_fill_time = dfixed_trunc(a);
1118
1119         if (line_fill_time < wm->active_time)
1120                 return latency;
1121         else
1122                 return latency + (line_fill_time - wm->active_time);
1123
1124 }
1125
1126 /**
1127  * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1128  * average and available dram bandwidth
1129  *
1130  * @wm: watermark calculation data
1131  *
1132  * Check if the display average bandwidth fits in the display
1133  * dram bandwidth (CIK).
1134  * Used for display watermark bandwidth calculations
1135  * Returns true if the display fits, false if not.
1136  */
1137 static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
1138 {
1139         if (dce_v11_0_average_bandwidth(wm) <=
1140             (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1141                 return true;
1142         else
1143                 return false;
1144 }
1145
1146 /**
1147  * dce_v11_0_average_bandwidth_vs_available_bandwidth - check
1148  * average and available bandwidth
1149  *
1150  * @wm: watermark calculation data
1151  *
1152  * Check if the display average bandwidth fits in the display
1153  * available bandwidth (CIK).
1154  * Used for display watermark bandwidth calculations
1155  * Returns true if the display fits, false if not.
1156  */
1157 static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
1158 {
1159         if (dce_v11_0_average_bandwidth(wm) <=
1160             (dce_v11_0_available_bandwidth(wm) / wm->num_heads))
1161                 return true;
1162         else
1163                 return false;
1164 }
1165
1166 /**
1167  * dce_v11_0_check_latency_hiding - check latency hiding
1168  *
1169  * @wm: watermark calculation data
1170  *
1171  * Check latency hiding (CIK).
1172  * Used for display watermark bandwidth calculations
1173  * Returns true if the display fits, false if not.
1174  */
1175 static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm)
1176 {
1177         u32 lb_partitions = wm->lb_size / wm->src_width;
1178         u32 line_time = wm->active_time + wm->blank_time;
1179         u32 latency_tolerant_lines;
1180         u32 latency_hiding;
1181         fixed20_12 a;
1182
1183         a.full = dfixed_const(1);
1184         if (wm->vsc.full > a.full)
1185                 latency_tolerant_lines = 1;
1186         else {
1187                 if (lb_partitions <= (wm->vtaps + 1))
1188                         latency_tolerant_lines = 1;
1189                 else
1190                         latency_tolerant_lines = 2;
1191         }
1192
1193         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1194
1195         if (dce_v11_0_latency_watermark(wm) <= latency_hiding)
1196                 return true;
1197         else
1198                 return false;
1199 }
1200
1201 /**
1202  * dce_v11_0_program_watermarks - program display watermarks
1203  *
1204  * @adev: amdgpu_device pointer
1205  * @amdgpu_crtc: the selected display controller
1206  * @lb_size: line buffer size
1207  * @num_heads: number of display controllers in use
1208  *
1209  * Calculate and program the display watermarks for the
1210  * selected display controller (CIK).
1211  */
1212 static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
1213                                         struct amdgpu_crtc *amdgpu_crtc,
1214                                         u32 lb_size, u32 num_heads)
1215 {
1216         struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1217         struct dce10_wm_params wm_low, wm_high;
1218         u32 pixel_period;
1219         u32 line_time = 0;
1220         u32 latency_watermark_a = 0, latency_watermark_b = 0;
1221         u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1222
1223         if (amdgpu_crtc->base.enabled && num_heads && mode) {
1224                 pixel_period = 1000000 / (u32)mode->clock;
1225                 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1226
1227                 /* watermark for high clocks */
1228                 if (adev->pm.dpm_enabled) {
1229                         wm_high.yclk =
1230                                 amdgpu_dpm_get_mclk(adev, false) * 10;
1231                         wm_high.sclk =
1232                                 amdgpu_dpm_get_sclk(adev, false) * 10;
1233                 } else {
1234                         wm_high.yclk = adev->pm.current_mclk * 10;
1235                         wm_high.sclk = adev->pm.current_sclk * 10;
1236                 }
1237
1238                 wm_high.disp_clk = mode->clock;
1239                 wm_high.src_width = mode->crtc_hdisplay;
1240                 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
1241                 wm_high.blank_time = line_time - wm_high.active_time;
1242                 wm_high.interlaced = false;
1243                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1244                         wm_high.interlaced = true;
1245                 wm_high.vsc = amdgpu_crtc->vsc;
1246                 wm_high.vtaps = 1;
1247                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1248                         wm_high.vtaps = 2;
1249                 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1250                 wm_high.lb_size = lb_size;
1251                 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1252                 wm_high.num_heads = num_heads;
1253
1254                 /* set for high clocks */
1255                 latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535);
1256
1257                 /* possibly force display priority to high */
1258                 /* should really do this at mode validation time... */
1259                 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1260                     !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1261                     !dce_v11_0_check_latency_hiding(&wm_high) ||
1262                     (adev->mode_info.disp_priority == 2)) {
1263                         DRM_DEBUG_KMS("force priority to high\n");
1264                 }
1265
1266                 /* watermark for low clocks */
1267                 if (adev->pm.dpm_enabled) {
1268                         wm_low.yclk =
1269                                 amdgpu_dpm_get_mclk(adev, true) * 10;
1270                         wm_low.sclk =
1271                                 amdgpu_dpm_get_sclk(adev, true) * 10;
1272                 } else {
1273                         wm_low.yclk = adev->pm.current_mclk * 10;
1274                         wm_low.sclk = adev->pm.current_sclk * 10;
1275                 }
1276
1277                 wm_low.disp_clk = mode->clock;
1278                 wm_low.src_width = mode->crtc_hdisplay;
1279                 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
1280                 wm_low.blank_time = line_time - wm_low.active_time;
1281                 wm_low.interlaced = false;
1282                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1283                         wm_low.interlaced = true;
1284                 wm_low.vsc = amdgpu_crtc->vsc;
1285                 wm_low.vtaps = 1;
1286                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1287                         wm_low.vtaps = 2;
1288                 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1289                 wm_low.lb_size = lb_size;
1290                 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1291                 wm_low.num_heads = num_heads;
1292
1293                 /* set for low clocks */
1294                 latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535);
1295
1296                 /* possibly force display priority to high */
1297                 /* should really do this at mode validation time... */
1298                 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1299                     !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1300                     !dce_v11_0_check_latency_hiding(&wm_low) ||
1301                     (adev->mode_info.disp_priority == 2)) {
1302                         DRM_DEBUG_KMS("force priority to high\n");
1303                 }
1304                 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1305         }
1306
1307         /* select wm A */
1308         wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1309         tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1310         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1311         tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1312         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1313         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1314         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1315         /* select wm B */
1316         tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1317         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1318         tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1319         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1320         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1321         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1322         /* restore original selection */
1323         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1324
1325         /* save values for DPM */
1326         amdgpu_crtc->line_time = line_time;
1327         amdgpu_crtc->wm_high = latency_watermark_a;
1328         amdgpu_crtc->wm_low = latency_watermark_b;
1329         /* Save number of lines the linebuffer leads before the scanout */
1330         amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1331 }
1332
1333 /**
1334  * dce_v11_0_bandwidth_update - program display watermarks
1335  *
1336  * @adev: amdgpu_device pointer
1337  *
1338  * Calculate and program the display watermarks and line
1339  * buffer allocation (CIK).
1340  */
1341 static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev)
1342 {
1343         struct drm_display_mode *mode = NULL;
1344         u32 num_heads = 0, lb_size;
1345         int i;
1346
1347         amdgpu_update_display_priority(adev);
1348
1349         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1350                 if (adev->mode_info.crtcs[i]->base.enabled)
1351                         num_heads++;
1352         }
1353         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1354                 mode = &adev->mode_info.crtcs[i]->base.mode;
1355                 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1356                 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1357                                             lb_size, num_heads);
1358         }
1359 }
1360
1361 static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev)
1362 {
1363         int i;
1364         u32 offset, tmp;
1365
1366         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1367                 offset = adev->mode_info.audio.pin[i].offset;
1368                 tmp = RREG32_AUDIO_ENDPT(offset,
1369                                          ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1370                 if (((tmp &
1371                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1372                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1373                         adev->mode_info.audio.pin[i].connected = false;
1374                 else
1375                         adev->mode_info.audio.pin[i].connected = true;
1376         }
1377 }
1378
1379 static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev)
1380 {
1381         int i;
1382
1383         dce_v11_0_audio_get_connected_pins(adev);
1384
1385         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1386                 if (adev->mode_info.audio.pin[i].connected)
1387                         return &adev->mode_info.audio.pin[i];
1388         }
1389         DRM_ERROR("No connected audio pins found!\n");
1390         return NULL;
1391 }
1392
1393 static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1394 {
1395         struct amdgpu_device *adev = encoder->dev->dev_private;
1396         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1397         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1398         u32 tmp;
1399
1400         if (!dig || !dig->afmt || !dig->afmt->pin)
1401                 return;
1402
1403         tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1404         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1405         WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1406 }
1407
1408 static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder,
1409                                                 struct drm_display_mode *mode)
1410 {
1411         struct amdgpu_device *adev = encoder->dev->dev_private;
1412         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1413         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1414         struct drm_connector *connector;
1415         struct amdgpu_connector *amdgpu_connector = NULL;
1416         u32 tmp;
1417         int interlace = 0;
1418
1419         if (!dig || !dig->afmt || !dig->afmt->pin)
1420                 return;
1421
1422         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1423                 if (connector->encoder == encoder) {
1424                         amdgpu_connector = to_amdgpu_connector(connector);
1425                         break;
1426                 }
1427         }
1428
1429         if (!amdgpu_connector) {
1430                 DRM_ERROR("Couldn't find encoder's connector\n");
1431                 return;
1432         }
1433
1434         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1435                 interlace = 1;
1436         if (connector->latency_present[interlace]) {
1437                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1438                                     VIDEO_LIPSYNC, connector->video_latency[interlace]);
1439                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1440                                     AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1441         } else {
1442                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1443                                     VIDEO_LIPSYNC, 0);
1444                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1445                                     AUDIO_LIPSYNC, 0);
1446         }
1447         WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1448                            ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1449 }
1450
1451 static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1452 {
1453         struct amdgpu_device *adev = encoder->dev->dev_private;
1454         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1455         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1456         struct drm_connector *connector;
1457         struct amdgpu_connector *amdgpu_connector = NULL;
1458         u32 tmp;
1459         u8 *sadb = NULL;
1460         int sad_count;
1461
1462         if (!dig || !dig->afmt || !dig->afmt->pin)
1463                 return;
1464
1465         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1466                 if (connector->encoder == encoder) {
1467                         amdgpu_connector = to_amdgpu_connector(connector);
1468                         break;
1469                 }
1470         }
1471
1472         if (!amdgpu_connector) {
1473                 DRM_ERROR("Couldn't find encoder's connector\n");
1474                 return;
1475         }
1476
1477         sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1478         if (sad_count < 0) {
1479                 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1480                 sad_count = 0;
1481         }
1482
1483         /* program the speaker allocation */
1484         tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1485                                  ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1486         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1487                             DP_CONNECTION, 0);
1488         /* set HDMI mode */
1489         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1490                             HDMI_CONNECTION, 1);
1491         if (sad_count)
1492                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1493                                     SPEAKER_ALLOCATION, sadb[0]);
1494         else
1495                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1496                                     SPEAKER_ALLOCATION, 5); /* stereo */
1497         WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1498                            ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1499
1500         kfree(sadb);
1501 }
1502
1503 static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder)
1504 {
1505         struct amdgpu_device *adev = encoder->dev->dev_private;
1506         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1507         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1508         struct drm_connector *connector;
1509         struct amdgpu_connector *amdgpu_connector = NULL;
1510         struct cea_sad *sads;
1511         int i, sad_count;
1512
1513         static const u16 eld_reg_to_type[][2] = {
1514                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1515                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1516                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1517                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1518                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1519                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1520                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1521                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1522                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1523                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1524                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1525                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1526         };
1527
1528         if (!dig || !dig->afmt || !dig->afmt->pin)
1529                 return;
1530
1531         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1532                 if (connector->encoder == encoder) {
1533                         amdgpu_connector = to_amdgpu_connector(connector);
1534                         break;
1535                 }
1536         }
1537
1538         if (!amdgpu_connector) {
1539                 DRM_ERROR("Couldn't find encoder's connector\n");
1540                 return;
1541         }
1542
1543         sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1544         if (sad_count <= 0) {
1545                 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1546                 return;
1547         }
1548         BUG_ON(!sads);
1549
1550         for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1551                 u32 tmp = 0;
1552                 u8 stereo_freqs = 0;
1553                 int max_channels = -1;
1554                 int j;
1555
1556                 for (j = 0; j < sad_count; j++) {
1557                         struct cea_sad *sad = &sads[j];
1558
1559                         if (sad->format == eld_reg_to_type[i][1]) {
1560                                 if (sad->channels > max_channels) {
1561                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1562                                                             MAX_CHANNELS, sad->channels);
1563                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1564                                                             DESCRIPTOR_BYTE_2, sad->byte2);
1565                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1566                                                             SUPPORTED_FREQUENCIES, sad->freq);
1567                                         max_channels = sad->channels;
1568                                 }
1569
1570                                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1571                                         stereo_freqs |= sad->freq;
1572                                 else
1573                                         break;
1574                         }
1575                 }
1576
1577                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1578                                     SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1579                 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1580         }
1581
1582         kfree(sads);
1583 }
1584
1585 static void dce_v11_0_audio_enable(struct amdgpu_device *adev,
1586                                   struct amdgpu_audio_pin *pin,
1587                                   bool enable)
1588 {
1589         if (!pin)
1590                 return;
1591
1592         WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1593                            enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1594 }
1595
1596 static const u32 pin_offsets[] =
1597 {
1598         AUD0_REGISTER_OFFSET,
1599         AUD1_REGISTER_OFFSET,
1600         AUD2_REGISTER_OFFSET,
1601         AUD3_REGISTER_OFFSET,
1602         AUD4_REGISTER_OFFSET,
1603         AUD5_REGISTER_OFFSET,
1604         AUD6_REGISTER_OFFSET,
1605 };
1606
1607 static int dce_v11_0_audio_init(struct amdgpu_device *adev)
1608 {
1609         int i;
1610
1611         if (!amdgpu_audio)
1612                 return 0;
1613
1614         adev->mode_info.audio.enabled = true;
1615
1616         switch (adev->asic_type) {
1617         case CHIP_CARRIZO:
1618         case CHIP_STONEY:
1619                 adev->mode_info.audio.num_pins = 7;
1620                 break;
1621         case CHIP_POLARIS10:
1622                 adev->mode_info.audio.num_pins = 8;
1623                 break;
1624         case CHIP_POLARIS11:
1625                 adev->mode_info.audio.num_pins = 6;
1626                 break;
1627         default:
1628                 return -EINVAL;
1629         }
1630
1631         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1632                 adev->mode_info.audio.pin[i].channels = -1;
1633                 adev->mode_info.audio.pin[i].rate = -1;
1634                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1635                 adev->mode_info.audio.pin[i].status_bits = 0;
1636                 adev->mode_info.audio.pin[i].category_code = 0;
1637                 adev->mode_info.audio.pin[i].connected = false;
1638                 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1639                 adev->mode_info.audio.pin[i].id = i;
1640                 /* disable audio.  it will be set up later */
1641                 /* XXX remove once we switch to ip funcs */
1642                 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1643         }
1644
1645         return 0;
1646 }
1647
1648 static void dce_v11_0_audio_fini(struct amdgpu_device *adev)
1649 {
1650         int i;
1651
1652         if (!amdgpu_audio)
1653                 return;
1654
1655         if (!adev->mode_info.audio.enabled)
1656                 return;
1657
1658         for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1659                 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1660
1661         adev->mode_info.audio.enabled = false;
1662 }
1663
1664 /*
1665  * update the N and CTS parameters for a given pixel clock rate
1666  */
1667 static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1668 {
1669         struct drm_device *dev = encoder->dev;
1670         struct amdgpu_device *adev = dev->dev_private;
1671         struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1672         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1673         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1674         u32 tmp;
1675
1676         tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1677         tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1678         WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1679         tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1680         tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1681         WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1682
1683         tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1684         tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1685         WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1686         tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1687         tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1688         WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1689
1690         tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1691         tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1692         WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1693         tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1694         tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1695         WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1696
1697 }
1698
1699 /*
1700  * build a HDMI Video Info Frame
1701  */
1702 static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1703                                                void *buffer, size_t size)
1704 {
1705         struct drm_device *dev = encoder->dev;
1706         struct amdgpu_device *adev = dev->dev_private;
1707         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1708         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1709         uint8_t *frame = buffer + 3;
1710         uint8_t *header = buffer;
1711
1712         WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1713                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1714         WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1715                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1716         WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1717                 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1718         WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1719                 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1720 }
1721
1722 static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1723 {
1724         struct drm_device *dev = encoder->dev;
1725         struct amdgpu_device *adev = dev->dev_private;
1726         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1727         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1728         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1729         u32 dto_phase = 24 * 1000;
1730         u32 dto_modulo = clock;
1731         u32 tmp;
1732
1733         if (!dig || !dig->afmt)
1734                 return;
1735
1736         /* XXX two dtos; generally use dto0 for hdmi */
1737         /* Express [24MHz / target pixel clock] as an exact rational
1738          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
1739          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1740          */
1741         tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1742         tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1743                             amdgpu_crtc->crtc_id);
1744         WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1745         WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1746         WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1747 }
1748
1749 /*
1750  * update the info frames with the data from the current display mode
1751  */
1752 static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder,
1753                                   struct drm_display_mode *mode)
1754 {
1755         struct drm_device *dev = encoder->dev;
1756         struct amdgpu_device *adev = dev->dev_private;
1757         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1758         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1759         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1760         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1761         struct hdmi_avi_infoframe frame;
1762         ssize_t err;
1763         u32 tmp;
1764         int bpc = 8;
1765
1766         if (!dig || !dig->afmt)
1767                 return;
1768
1769         /* Silent, r600_hdmi_enable will raise WARN for us */
1770         if (!dig->afmt->enabled)
1771                 return;
1772
1773         /* hdmi deep color mode general control packets setup, if bpc > 8 */
1774         if (encoder->crtc) {
1775                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1776                 bpc = amdgpu_crtc->bpc;
1777         }
1778
1779         /* disable audio prior to setting up hw */
1780         dig->afmt->pin = dce_v11_0_audio_get_pin(adev);
1781         dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1782
1783         dce_v11_0_audio_set_dto(encoder, mode->clock);
1784
1785         tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1786         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1787         WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1788
1789         WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1790
1791         tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1792         switch (bpc) {
1793         case 0:
1794         case 6:
1795         case 8:
1796         case 16:
1797         default:
1798                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1799                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1800                 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1801                           connector->name, bpc);
1802                 break;
1803         case 10:
1804                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1805                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1806                 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1807                           connector->name);
1808                 break;
1809         case 12:
1810                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1811                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1812                 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1813                           connector->name);
1814                 break;
1815         }
1816         WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1817
1818         tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1819         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1820         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1821         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1822         WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1823
1824         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1825         /* enable audio info frames (frames won't be set until audio is enabled) */
1826         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1827         /* required for audio info values to be updated */
1828         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1829         WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1830
1831         tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1832         /* required for audio info values to be updated */
1833         tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1834         WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1835
1836         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1837         /* anything other than 0 */
1838         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1839         WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1840
1841         WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1842
1843         tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1844         /* set the default audio delay */
1845         tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1846         /* should be suffient for all audio modes and small enough for all hblanks */
1847         tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1848         WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1849
1850         tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1851         /* allow 60958 channel status fields to be updated */
1852         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1853         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1854
1855         tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1856         if (bpc > 8)
1857                 /* clear SW CTS value */
1858                 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1859         else
1860                 /* select SW CTS value */
1861                 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1862         /* allow hw to sent ACR packets when required */
1863         tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1864         WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1865
1866         dce_v11_0_afmt_update_ACR(encoder, mode->clock);
1867
1868         tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1869         tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1870         WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1871
1872         tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1873         tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1874         WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1875
1876         tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1877         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1878         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1879         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1880         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1881         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1882         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1883         WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1884
1885         dce_v11_0_audio_write_speaker_allocation(encoder);
1886
1887         WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1888                (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1889
1890         dce_v11_0_afmt_audio_select_pin(encoder);
1891         dce_v11_0_audio_write_sad_regs(encoder);
1892         dce_v11_0_audio_write_latency_fields(encoder, mode);
1893
1894         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1895         if (err < 0) {
1896                 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1897                 return;
1898         }
1899
1900         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1901         if (err < 0) {
1902                 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1903                 return;
1904         }
1905
1906         dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1907
1908         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1909         /* enable AVI info frames */
1910         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1911         /* required for audio info values to be updated */
1912         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1913         WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1914
1915         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1916         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1917         WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1918
1919         tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1920         /* send audio packets */
1921         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1922         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1923
1924         WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1925         WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1926         WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1927         WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1928
1929         /* enable audio after to setting up hw */
1930         dce_v11_0_audio_enable(adev, dig->afmt->pin, true);
1931 }
1932
1933 static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1934 {
1935         struct drm_device *dev = encoder->dev;
1936         struct amdgpu_device *adev = dev->dev_private;
1937         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1938         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1939
1940         if (!dig || !dig->afmt)
1941                 return;
1942
1943         /* Silent, r600_hdmi_enable will raise WARN for us */
1944         if (enable && dig->afmt->enabled)
1945                 return;
1946         if (!enable && !dig->afmt->enabled)
1947                 return;
1948
1949         if (!enable && dig->afmt->pin) {
1950                 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1951                 dig->afmt->pin = NULL;
1952         }
1953
1954         dig->afmt->enabled = enable;
1955
1956         DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1957                   enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1958 }
1959
1960 static int dce_v11_0_afmt_init(struct amdgpu_device *adev)
1961 {
1962         int i;
1963
1964         for (i = 0; i < adev->mode_info.num_dig; i++)
1965                 adev->mode_info.afmt[i] = NULL;
1966
1967         /* DCE11 has audio blocks tied to DIG encoders */
1968         for (i = 0; i < adev->mode_info.num_dig; i++) {
1969                 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1970                 if (adev->mode_info.afmt[i]) {
1971                         adev->mode_info.afmt[i]->offset = dig_offsets[i];
1972                         adev->mode_info.afmt[i]->id = i;
1973                 } else {
1974                         int j;
1975                         for (j = 0; j < i; j++) {
1976                                 kfree(adev->mode_info.afmt[j]);
1977                                 adev->mode_info.afmt[j] = NULL;
1978                         }
1979                         return -ENOMEM;
1980                 }
1981         }
1982         return 0;
1983 }
1984
1985 static void dce_v11_0_afmt_fini(struct amdgpu_device *adev)
1986 {
1987         int i;
1988
1989         for (i = 0; i < adev->mode_info.num_dig; i++) {
1990                 kfree(adev->mode_info.afmt[i]);
1991                 adev->mode_info.afmt[i] = NULL;
1992         }
1993 }
1994
1995 static const u32 vga_control_regs[6] =
1996 {
1997         mmD1VGA_CONTROL,
1998         mmD2VGA_CONTROL,
1999         mmD3VGA_CONTROL,
2000         mmD4VGA_CONTROL,
2001         mmD5VGA_CONTROL,
2002         mmD6VGA_CONTROL,
2003 };
2004
2005 static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable)
2006 {
2007         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2008         struct drm_device *dev = crtc->dev;
2009         struct amdgpu_device *adev = dev->dev_private;
2010         u32 vga_control;
2011
2012         vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
2013         if (enable)
2014                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
2015         else
2016                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
2017 }
2018
2019 static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable)
2020 {
2021         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2022         struct drm_device *dev = crtc->dev;
2023         struct amdgpu_device *adev = dev->dev_private;
2024
2025         if (enable)
2026                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
2027         else
2028                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
2029 }
2030
2031 static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
2032                                      struct drm_framebuffer *fb,
2033                                      int x, int y, int atomic)
2034 {
2035         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2036         struct drm_device *dev = crtc->dev;
2037         struct amdgpu_device *adev = dev->dev_private;
2038         struct amdgpu_framebuffer *amdgpu_fb;
2039         struct drm_framebuffer *target_fb;
2040         struct drm_gem_object *obj;
2041         struct amdgpu_bo *rbo;
2042         uint64_t fb_location, tiling_flags;
2043         uint32_t fb_format, fb_pitch_pixels;
2044         u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
2045         u32 pipe_config;
2046         u32 tmp, viewport_w, viewport_h;
2047         int r;
2048         bool bypass_lut = false;
2049
2050         /* no fb bound */
2051         if (!atomic && !crtc->primary->fb) {
2052                 DRM_DEBUG_KMS("No FB bound\n");
2053                 return 0;
2054         }
2055
2056         if (atomic) {
2057                 amdgpu_fb = to_amdgpu_framebuffer(fb);
2058                 target_fb = fb;
2059         } else {
2060                 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2061                 target_fb = crtc->primary->fb;
2062         }
2063
2064         /* If atomic, assume fb object is pinned & idle & fenced and
2065          * just update base pointers
2066          */
2067         obj = amdgpu_fb->obj;
2068         rbo = gem_to_amdgpu_bo(obj);
2069         r = amdgpu_bo_reserve(rbo, false);
2070         if (unlikely(r != 0))
2071                 return r;
2072
2073         if (atomic) {
2074                 fb_location = amdgpu_bo_gpu_offset(rbo);
2075         } else {
2076                 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
2077                 if (unlikely(r != 0)) {
2078                         amdgpu_bo_unreserve(rbo);
2079                         return -EINVAL;
2080                 }
2081         }
2082
2083         amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
2084         amdgpu_bo_unreserve(rbo);
2085
2086         pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2087
2088         switch (target_fb->pixel_format) {
2089         case DRM_FORMAT_C8:
2090                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
2091                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2092                 break;
2093         case DRM_FORMAT_XRGB4444:
2094         case DRM_FORMAT_ARGB4444:
2095                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2096                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
2097 #ifdef __BIG_ENDIAN
2098                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2099                                         ENDIAN_8IN16);
2100 #endif
2101                 break;
2102         case DRM_FORMAT_XRGB1555:
2103         case DRM_FORMAT_ARGB1555:
2104                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2105                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2106 #ifdef __BIG_ENDIAN
2107                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2108                                         ENDIAN_8IN16);
2109 #endif
2110                 break;
2111         case DRM_FORMAT_BGRX5551:
2112         case DRM_FORMAT_BGRA5551:
2113                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2114                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
2115 #ifdef __BIG_ENDIAN
2116                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2117                                         ENDIAN_8IN16);
2118 #endif
2119                 break;
2120         case DRM_FORMAT_RGB565:
2121                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2122                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2123 #ifdef __BIG_ENDIAN
2124                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2125                                         ENDIAN_8IN16);
2126 #endif
2127                 break;
2128         case DRM_FORMAT_XRGB8888:
2129         case DRM_FORMAT_ARGB8888:
2130                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2131                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2132 #ifdef __BIG_ENDIAN
2133                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2134                                         ENDIAN_8IN32);
2135 #endif
2136                 break;
2137         case DRM_FORMAT_XRGB2101010:
2138         case DRM_FORMAT_ARGB2101010:
2139                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2140                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2141 #ifdef __BIG_ENDIAN
2142                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2143                                         ENDIAN_8IN32);
2144 #endif
2145                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2146                 bypass_lut = true;
2147                 break;
2148         case DRM_FORMAT_BGRX1010102:
2149         case DRM_FORMAT_BGRA1010102:
2150                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2151                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
2152 #ifdef __BIG_ENDIAN
2153                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2154                                         ENDIAN_8IN32);
2155 #endif
2156                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2157                 bypass_lut = true;
2158                 break;
2159         default:
2160                 DRM_ERROR("Unsupported screen format %s\n",
2161                         drm_get_format_name(target_fb->pixel_format));
2162                 return -EINVAL;
2163         }
2164
2165         if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2166                 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2167
2168                 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2169                 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2170                 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2171                 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2172                 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2173
2174                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2175                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2176                                           ARRAY_2D_TILED_THIN1);
2177                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2178                                           tile_split);
2179                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2180                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2181                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2182                                           mtaspect);
2183                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2184                                           ADDR_SURF_MICRO_TILING_DISPLAY);
2185         } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2186                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2187                                           ARRAY_1D_TILED_THIN1);
2188         }
2189
2190         fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2191                                   pipe_config);
2192
2193         dce_v11_0_vga_enable(crtc, false);
2194
2195         /* Make sure surface address is updated at vertical blank rather than
2196          * horizontal blank
2197          */
2198         tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2199         tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2200                             GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2201         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2202
2203         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2204                upper_32_bits(fb_location));
2205         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2206                upper_32_bits(fb_location));
2207         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2208                (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2209         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2210                (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2211         WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2212         WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2213
2214         /*
2215          * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2216          * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2217          * retain the full precision throughout the pipeline.
2218          */
2219         tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2220         if (bypass_lut)
2221                 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2222         else
2223                 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2224         WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2225
2226         if (bypass_lut)
2227                 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2228
2229         WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2230         WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2231         WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2232         WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2233         WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2234         WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2235
2236         fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
2237         WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2238
2239         dce_v11_0_grph_enable(crtc, true);
2240
2241         WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2242                target_fb->height);
2243
2244         x &= ~3;
2245         y &= ~1;
2246         WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2247                (x << 16) | y);
2248         viewport_w = crtc->mode.hdisplay;
2249         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2250         WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2251                (viewport_w << 16) | viewport_h);
2252
2253         /* set pageflip to happen only at start of vblank interval (front porch) */
2254         WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3);
2255
2256         if (!atomic && fb && fb != crtc->primary->fb) {
2257                 amdgpu_fb = to_amdgpu_framebuffer(fb);
2258                 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2259                 r = amdgpu_bo_reserve(rbo, false);
2260                 if (unlikely(r != 0))
2261                         return r;
2262                 amdgpu_bo_unpin(rbo);
2263                 amdgpu_bo_unreserve(rbo);
2264         }
2265
2266         /* Bytes per pixel may have changed */
2267         dce_v11_0_bandwidth_update(adev);
2268
2269         return 0;
2270 }
2271
2272 static void dce_v11_0_set_interleave(struct drm_crtc *crtc,
2273                                      struct drm_display_mode *mode)
2274 {
2275         struct drm_device *dev = crtc->dev;
2276         struct amdgpu_device *adev = dev->dev_private;
2277         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2278         u32 tmp;
2279
2280         tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2281         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2282                 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2283         else
2284                 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2285         WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2286 }
2287
2288 static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc)
2289 {
2290         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2291         struct drm_device *dev = crtc->dev;
2292         struct amdgpu_device *adev = dev->dev_private;
2293         int i;
2294         u32 tmp;
2295
2296         DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2297
2298         tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2299         tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2300         WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2301
2302         tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2303         tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2304         WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2305
2306         tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2307         tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2308         WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2309
2310         WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2311
2312         WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2313         WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2314         WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2315
2316         WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2317         WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2318         WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2319
2320         WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2321         WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2322
2323         WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2324         for (i = 0; i < 256; i++) {
2325                 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2326                        (amdgpu_crtc->lut_r[i] << 20) |
2327                        (amdgpu_crtc->lut_g[i] << 10) |
2328                        (amdgpu_crtc->lut_b[i] << 0));
2329         }
2330
2331         tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2332         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2333         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2334         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0);
2335         WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2336
2337         tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2338         tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2339         WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2340
2341         tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2342         tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2343         WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2344
2345         tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2346         tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2347         WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2348
2349         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2350         WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2351         /* XXX this only needs to be programmed once per crtc at startup,
2352          * not sure where the best place for it is
2353          */
2354         tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2355         tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2356         WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2357 }
2358
2359 static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder)
2360 {
2361         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2362         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2363
2364         switch (amdgpu_encoder->encoder_id) {
2365         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2366                 if (dig->linkb)
2367                         return 1;
2368                 else
2369                         return 0;
2370                 break;
2371         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2372                 if (dig->linkb)
2373                         return 3;
2374                 else
2375                         return 2;
2376                 break;
2377         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2378                 if (dig->linkb)
2379                         return 5;
2380                 else
2381                         return 4;
2382                 break;
2383         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2384                 return 6;
2385                 break;
2386         default:
2387                 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2388                 return 0;
2389         }
2390 }
2391
2392 /**
2393  * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2394  *
2395  * @crtc: drm crtc
2396  *
2397  * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
2398  * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
2399  * monitors a dedicated PPLL must be used.  If a particular board has
2400  * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2401  * as there is no need to program the PLL itself.  If we are not able to
2402  * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2403  * avoid messing up an existing monitor.
2404  *
2405  * Asic specific PLL information
2406  *
2407  * DCE 10.x
2408  * Tonga
2409  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2410  * CI
2411  * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2412  *
2413  */
2414 static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
2415 {
2416         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2417         struct drm_device *dev = crtc->dev;
2418         struct amdgpu_device *adev = dev->dev_private;
2419         u32 pll_in_use;
2420         int pll;
2421
2422         if ((adev->asic_type == CHIP_POLARIS10) ||
2423             (adev->asic_type == CHIP_POLARIS11)) {
2424                 struct amdgpu_encoder *amdgpu_encoder =
2425                         to_amdgpu_encoder(amdgpu_crtc->encoder);
2426                 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2427
2428                 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2429                         return ATOM_DP_DTO;
2430
2431                 switch (amdgpu_encoder->encoder_id) {
2432                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2433                         if (dig->linkb)
2434                                 return ATOM_COMBOPHY_PLL1;
2435                         else
2436                                 return ATOM_COMBOPHY_PLL0;
2437                         break;
2438                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2439                         if (dig->linkb)
2440                                 return ATOM_COMBOPHY_PLL3;
2441                         else
2442                                 return ATOM_COMBOPHY_PLL2;
2443                         break;
2444                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2445                         if (dig->linkb)
2446                                 return ATOM_COMBOPHY_PLL5;
2447                         else
2448                                 return ATOM_COMBOPHY_PLL4;
2449                         break;
2450                 default:
2451                         DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2452                         return ATOM_PPLL_INVALID;
2453                 }
2454         }
2455
2456         if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2457                 if (adev->clock.dp_extclk)
2458                         /* skip PPLL programming if using ext clock */
2459                         return ATOM_PPLL_INVALID;
2460                 else {
2461                         /* use the same PPLL for all DP monitors */
2462                         pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2463                         if (pll != ATOM_PPLL_INVALID)
2464                                 return pll;
2465                 }
2466         } else {
2467                 /* use the same PPLL for all monitors with the same clock */
2468                 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2469                 if (pll != ATOM_PPLL_INVALID)
2470                         return pll;
2471         }
2472
2473         /* XXX need to determine what plls are available on each DCE11 part */
2474         pll_in_use = amdgpu_pll_get_use_mask(crtc);
2475         if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) {
2476                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2477                         return ATOM_PPLL1;
2478                 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2479                         return ATOM_PPLL0;
2480                 DRM_ERROR("unable to allocate a PPLL\n");
2481                 return ATOM_PPLL_INVALID;
2482         } else {
2483                 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2484                         return ATOM_PPLL2;
2485                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2486                         return ATOM_PPLL1;
2487                 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2488                         return ATOM_PPLL0;
2489                 DRM_ERROR("unable to allocate a PPLL\n");
2490                 return ATOM_PPLL_INVALID;
2491         }
2492         return ATOM_PPLL_INVALID;
2493 }
2494
2495 static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2496 {
2497         struct amdgpu_device *adev = crtc->dev->dev_private;
2498         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2499         uint32_t cur_lock;
2500
2501         cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2502         if (lock)
2503                 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2504         else
2505                 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2506         WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2507 }
2508
2509 static void dce_v11_0_hide_cursor(struct drm_crtc *crtc)
2510 {
2511         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2512         struct amdgpu_device *adev = crtc->dev->dev_private;
2513         u32 tmp;
2514
2515         tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2516         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2517         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2518 }
2519
2520 static void dce_v11_0_show_cursor(struct drm_crtc *crtc)
2521 {
2522         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2523         struct amdgpu_device *adev = crtc->dev->dev_private;
2524         u32 tmp;
2525
2526         WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2527                upper_32_bits(amdgpu_crtc->cursor_addr));
2528         WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2529                lower_32_bits(amdgpu_crtc->cursor_addr));
2530
2531         tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2532         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2533         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2534         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2535 }
2536
2537 static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc,
2538                                         int x, int y)
2539 {
2540         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2541         struct amdgpu_device *adev = crtc->dev->dev_private;
2542         int xorigin = 0, yorigin = 0;
2543
2544         /* avivo cursor are offset into the total surface */
2545         x += crtc->x;
2546         y += crtc->y;
2547         DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2548
2549         if (x < 0) {
2550                 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2551                 x = 0;
2552         }
2553         if (y < 0) {
2554                 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2555                 y = 0;
2556         }
2557
2558         WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2559         WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2560         WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2561                ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2562
2563         amdgpu_crtc->cursor_x = x;
2564         amdgpu_crtc->cursor_y = y;
2565
2566         return 0;
2567 }
2568
2569 static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc,
2570                                       int x, int y)
2571 {
2572         int ret;
2573
2574         dce_v11_0_lock_cursor(crtc, true);
2575         ret = dce_v11_0_cursor_move_locked(crtc, x, y);
2576         dce_v11_0_lock_cursor(crtc, false);
2577
2578         return ret;
2579 }
2580
2581 static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
2582                                       struct drm_file *file_priv,
2583                                       uint32_t handle,
2584                                       uint32_t width,
2585                                       uint32_t height,
2586                                       int32_t hot_x,
2587                                       int32_t hot_y)
2588 {
2589         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2590         struct drm_gem_object *obj;
2591         struct amdgpu_bo *aobj;
2592         int ret;
2593
2594         if (!handle) {
2595                 /* turn off cursor */
2596                 dce_v11_0_hide_cursor(crtc);
2597                 obj = NULL;
2598                 goto unpin;
2599         }
2600
2601         if ((width > amdgpu_crtc->max_cursor_width) ||
2602             (height > amdgpu_crtc->max_cursor_height)) {
2603                 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2604                 return -EINVAL;
2605         }
2606
2607         obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
2608         if (!obj) {
2609                 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2610                 return -ENOENT;
2611         }
2612
2613         aobj = gem_to_amdgpu_bo(obj);
2614         ret = amdgpu_bo_reserve(aobj, false);
2615         if (ret != 0) {
2616                 drm_gem_object_unreference_unlocked(obj);
2617                 return ret;
2618         }
2619
2620         ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2621         amdgpu_bo_unreserve(aobj);
2622         if (ret) {
2623                 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2624                 drm_gem_object_unreference_unlocked(obj);
2625                 return ret;
2626         }
2627
2628         amdgpu_crtc->cursor_width = width;
2629         amdgpu_crtc->cursor_height = height;
2630
2631         dce_v11_0_lock_cursor(crtc, true);
2632
2633         if (hot_x != amdgpu_crtc->cursor_hot_x ||
2634             hot_y != amdgpu_crtc->cursor_hot_y) {
2635                 int x, y;
2636
2637                 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2638                 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2639
2640                 dce_v11_0_cursor_move_locked(crtc, x, y);
2641
2642                 amdgpu_crtc->cursor_hot_x = hot_x;
2643                 amdgpu_crtc->cursor_hot_y = hot_y;
2644         }
2645
2646         dce_v11_0_show_cursor(crtc);
2647         dce_v11_0_lock_cursor(crtc, false);
2648
2649 unpin:
2650         if (amdgpu_crtc->cursor_bo) {
2651                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2652                 ret = amdgpu_bo_reserve(aobj, false);
2653                 if (likely(ret == 0)) {
2654                         amdgpu_bo_unpin(aobj);
2655                         amdgpu_bo_unreserve(aobj);
2656                 }
2657                 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2658         }
2659
2660         amdgpu_crtc->cursor_bo = obj;
2661         return 0;
2662 }
2663
2664 static void dce_v11_0_cursor_reset(struct drm_crtc *crtc)
2665 {
2666         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2667
2668         if (amdgpu_crtc->cursor_bo) {
2669                 dce_v11_0_lock_cursor(crtc, true);
2670
2671                 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2672                                              amdgpu_crtc->cursor_y);
2673
2674                 dce_v11_0_show_cursor(crtc);
2675
2676                 dce_v11_0_lock_cursor(crtc, false);
2677         }
2678 }
2679
2680 static void dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2681                                     u16 *blue, uint32_t start, uint32_t size)
2682 {
2683         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2684         int end = (start + size > 256) ? 256 : start + size, i;
2685
2686         /* userspace palettes are always correct as is */
2687         for (i = start; i < end; i++) {
2688                 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2689                 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2690                 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2691         }
2692         dce_v11_0_crtc_load_lut(crtc);
2693 }
2694
2695 static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc)
2696 {
2697         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2698
2699         drm_crtc_cleanup(crtc);
2700         kfree(amdgpu_crtc);
2701 }
2702
2703 static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = {
2704         .cursor_set2 = dce_v11_0_crtc_cursor_set2,
2705         .cursor_move = dce_v11_0_crtc_cursor_move,
2706         .gamma_set = dce_v11_0_crtc_gamma_set,
2707         .set_config = amdgpu_crtc_set_config,
2708         .destroy = dce_v11_0_crtc_destroy,
2709         .page_flip = amdgpu_crtc_page_flip,
2710 };
2711
2712 static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2713 {
2714         struct drm_device *dev = crtc->dev;
2715         struct amdgpu_device *adev = dev->dev_private;
2716         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2717         unsigned type;
2718
2719         switch (mode) {
2720         case DRM_MODE_DPMS_ON:
2721                 amdgpu_crtc->enabled = true;
2722                 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2723                 dce_v11_0_vga_enable(crtc, true);
2724                 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2725                 dce_v11_0_vga_enable(crtc, false);
2726                 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2727                 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2728                 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2729                 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2730                 drm_vblank_on(dev, amdgpu_crtc->crtc_id);
2731                 dce_v11_0_crtc_load_lut(crtc);
2732                 break;
2733         case DRM_MODE_DPMS_STANDBY:
2734         case DRM_MODE_DPMS_SUSPEND:
2735         case DRM_MODE_DPMS_OFF:
2736                 drm_vblank_off(dev, amdgpu_crtc->crtc_id);
2737                 if (amdgpu_crtc->enabled) {
2738                         dce_v11_0_vga_enable(crtc, true);
2739                         amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2740                         dce_v11_0_vga_enable(crtc, false);
2741                 }
2742                 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2743                 amdgpu_crtc->enabled = false;
2744                 break;
2745         }
2746         /* adjust pm to dpms */
2747         amdgpu_pm_compute_clocks(adev);
2748 }
2749
2750 static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc)
2751 {
2752         /* disable crtc pair power gating before programming */
2753         amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2754         amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2755         dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2756 }
2757
2758 static void dce_v11_0_crtc_commit(struct drm_crtc *crtc)
2759 {
2760         dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2761         amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2762 }
2763
2764 static void dce_v11_0_crtc_disable(struct drm_crtc *crtc)
2765 {
2766         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2767         struct drm_device *dev = crtc->dev;
2768         struct amdgpu_device *adev = dev->dev_private;
2769         struct amdgpu_atom_ss ss;
2770         int i;
2771
2772         dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2773         if (crtc->primary->fb) {
2774                 int r;
2775                 struct amdgpu_framebuffer *amdgpu_fb;
2776                 struct amdgpu_bo *rbo;
2777
2778                 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2779                 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2780                 r = amdgpu_bo_reserve(rbo, false);
2781                 if (unlikely(r))
2782                         DRM_ERROR("failed to reserve rbo before unpin\n");
2783                 else {
2784                         amdgpu_bo_unpin(rbo);
2785                         amdgpu_bo_unreserve(rbo);
2786                 }
2787         }
2788         /* disable the GRPH */
2789         dce_v11_0_grph_enable(crtc, false);
2790
2791         amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2792
2793         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2794                 if (adev->mode_info.crtcs[i] &&
2795                     adev->mode_info.crtcs[i]->enabled &&
2796                     i != amdgpu_crtc->crtc_id &&
2797                     amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2798                         /* one other crtc is using this pll don't turn
2799                          * off the pll
2800                          */
2801                         goto done;
2802                 }
2803         }
2804
2805         switch (amdgpu_crtc->pll_id) {
2806         case ATOM_PPLL0:
2807         case ATOM_PPLL1:
2808         case ATOM_PPLL2:
2809                 /* disable the ppll */
2810                 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2811                                                  0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2812                 break;
2813         case ATOM_COMBOPHY_PLL0:
2814         case ATOM_COMBOPHY_PLL1:
2815         case ATOM_COMBOPHY_PLL2:
2816         case ATOM_COMBOPHY_PLL3:
2817         case ATOM_COMBOPHY_PLL4:
2818         case ATOM_COMBOPHY_PLL5:
2819                 /* disable the ppll */
2820                 amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, amdgpu_crtc->pll_id,
2821                                                  0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2822                 break;
2823         default:
2824                 break;
2825         }
2826 done:
2827         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2828         amdgpu_crtc->adjusted_clock = 0;
2829         amdgpu_crtc->encoder = NULL;
2830         amdgpu_crtc->connector = NULL;
2831 }
2832
2833 static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,
2834                                   struct drm_display_mode *mode,
2835                                   struct drm_display_mode *adjusted_mode,
2836                                   int x, int y, struct drm_framebuffer *old_fb)
2837 {
2838         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2839         struct drm_device *dev = crtc->dev;
2840         struct amdgpu_device *adev = dev->dev_private;
2841
2842         if (!amdgpu_crtc->adjusted_clock)
2843                 return -EINVAL;
2844
2845         if ((adev->asic_type == CHIP_POLARIS10) ||
2846             (adev->asic_type == CHIP_POLARIS11)) {
2847                 struct amdgpu_encoder *amdgpu_encoder =
2848                         to_amdgpu_encoder(amdgpu_crtc->encoder);
2849                 int encoder_mode =
2850                         amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder);
2851
2852                 /* SetPixelClock calculates the plls and ss values now */
2853                 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id,
2854                                                  amdgpu_crtc->pll_id,
2855                                                  encoder_mode, amdgpu_encoder->encoder_id,
2856                                                  adjusted_mode->clock, 0, 0, 0, 0,
2857                                                  amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss);
2858         } else {
2859                 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2860         }
2861         amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2862         dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2863         amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2864         amdgpu_atombios_crtc_scaler_setup(crtc);
2865         dce_v11_0_cursor_reset(crtc);
2866         /* update the hw version fpr dpm */
2867         amdgpu_crtc->hw_mode = *adjusted_mode;
2868
2869         return 0;
2870 }
2871
2872 static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc,
2873                                      const struct drm_display_mode *mode,
2874                                      struct drm_display_mode *adjusted_mode)
2875 {
2876         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2877         struct drm_device *dev = crtc->dev;
2878         struct drm_encoder *encoder;
2879
2880         /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2881         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2882                 if (encoder->crtc == crtc) {
2883                         amdgpu_crtc->encoder = encoder;
2884                         amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2885                         break;
2886                 }
2887         }
2888         if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2889                 amdgpu_crtc->encoder = NULL;
2890                 amdgpu_crtc->connector = NULL;
2891                 return false;
2892         }
2893         if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2894                 return false;
2895         if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2896                 return false;
2897         /* pick pll */
2898         amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc);
2899         /* if we can't get a PPLL for a non-DP encoder, fail */
2900         if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2901             !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2902                 return false;
2903
2904         return true;
2905 }
2906
2907 static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2908                                   struct drm_framebuffer *old_fb)
2909 {
2910         return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2911 }
2912
2913 static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2914                                          struct drm_framebuffer *fb,
2915                                          int x, int y, enum mode_set_atomic state)
2916 {
2917        return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1);
2918 }
2919
2920 static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = {
2921         .dpms = dce_v11_0_crtc_dpms,
2922         .mode_fixup = dce_v11_0_crtc_mode_fixup,
2923         .mode_set = dce_v11_0_crtc_mode_set,
2924         .mode_set_base = dce_v11_0_crtc_set_base,
2925         .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic,
2926         .prepare = dce_v11_0_crtc_prepare,
2927         .commit = dce_v11_0_crtc_commit,
2928         .load_lut = dce_v11_0_crtc_load_lut,
2929         .disable = dce_v11_0_crtc_disable,
2930 };
2931
2932 static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index)
2933 {
2934         struct amdgpu_crtc *amdgpu_crtc;
2935         int i;
2936
2937         amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2938                               (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2939         if (amdgpu_crtc == NULL)
2940                 return -ENOMEM;
2941
2942         drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs);
2943
2944         drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2945         amdgpu_crtc->crtc_id = index;
2946         adev->mode_info.crtcs[index] = amdgpu_crtc;
2947
2948         amdgpu_crtc->max_cursor_width = 128;
2949         amdgpu_crtc->max_cursor_height = 128;
2950         adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2951         adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2952
2953         for (i = 0; i < 256; i++) {
2954                 amdgpu_crtc->lut_r[i] = i << 2;
2955                 amdgpu_crtc->lut_g[i] = i << 2;
2956                 amdgpu_crtc->lut_b[i] = i << 2;
2957         }
2958
2959         switch (amdgpu_crtc->crtc_id) {
2960         case 0:
2961         default:
2962                 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2963                 break;
2964         case 1:
2965                 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2966                 break;
2967         case 2:
2968                 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2969                 break;
2970         case 3:
2971                 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2972                 break;
2973         case 4:
2974                 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2975                 break;
2976         case 5:
2977                 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2978                 break;
2979         }
2980
2981         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2982         amdgpu_crtc->adjusted_clock = 0;
2983         amdgpu_crtc->encoder = NULL;
2984         amdgpu_crtc->connector = NULL;
2985         drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs);
2986
2987         return 0;
2988 }
2989
2990 static int dce_v11_0_early_init(void *handle)
2991 {
2992         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2993
2994         adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg;
2995         adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg;
2996
2997         dce_v11_0_set_display_funcs(adev);
2998         dce_v11_0_set_irq_funcs(adev);
2999
3000         switch (adev->asic_type) {
3001         case CHIP_CARRIZO:
3002                 adev->mode_info.num_crtc = 3;
3003                 adev->mode_info.num_hpd = 6;
3004                 adev->mode_info.num_dig = 9;
3005                 break;
3006         case CHIP_STONEY:
3007                 adev->mode_info.num_crtc = 2;
3008                 adev->mode_info.num_hpd = 6;
3009                 adev->mode_info.num_dig = 9;
3010                 break;
3011         case CHIP_POLARIS10:
3012                 adev->mode_info.num_crtc = 6;
3013                 adev->mode_info.num_hpd = 6;
3014                 adev->mode_info.num_dig = 6;
3015                 break;
3016         case CHIP_POLARIS11:
3017                 adev->mode_info.num_crtc = 5;
3018                 adev->mode_info.num_hpd = 5;
3019                 adev->mode_info.num_dig = 5;
3020                 break;
3021         default:
3022                 /* FIXME: not supported yet */
3023                 return -EINVAL;
3024         }
3025
3026         return 0;
3027 }
3028
3029 static int dce_v11_0_sw_init(void *handle)
3030 {
3031         int r, i;
3032         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3033
3034         for (i = 0; i < adev->mode_info.num_crtc; i++) {
3035                 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
3036                 if (r)
3037                         return r;
3038         }
3039
3040         for (i = 8; i < 20; i += 2) {
3041                 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
3042                 if (r)
3043                         return r;
3044         }
3045
3046         /* HPD hotplug */
3047         r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
3048         if (r)
3049                 return r;
3050
3051         adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
3052
3053         adev->ddev->mode_config.async_page_flip = true;
3054
3055         adev->ddev->mode_config.max_width = 16384;
3056         adev->ddev->mode_config.max_height = 16384;
3057
3058         adev->ddev->mode_config.preferred_depth = 24;
3059         adev->ddev->mode_config.prefer_shadow = 1;
3060
3061         adev->ddev->mode_config.fb_base = adev->mc.aper_base;
3062
3063         r = amdgpu_modeset_create_props(adev);
3064         if (r)
3065                 return r;
3066
3067         adev->ddev->mode_config.max_width = 16384;
3068         adev->ddev->mode_config.max_height = 16384;
3069
3070
3071         /* allocate crtcs */
3072         for (i = 0; i < adev->mode_info.num_crtc; i++) {
3073                 r = dce_v11_0_crtc_init(adev, i);
3074                 if (r)
3075                         return r;
3076         }
3077
3078         if (amdgpu_atombios_get_connector_info_from_object_table(adev))
3079                 amdgpu_print_display_setup(adev->ddev);
3080         else
3081                 return -EINVAL;
3082
3083         /* setup afmt */
3084         r = dce_v11_0_afmt_init(adev);
3085         if (r)
3086                 return r;
3087
3088         r = dce_v11_0_audio_init(adev);
3089         if (r)
3090                 return r;
3091
3092         drm_kms_helper_poll_init(adev->ddev);
3093
3094         adev->mode_info.mode_config_initialized = true;
3095         return 0;
3096 }
3097
3098 static int dce_v11_0_sw_fini(void *handle)
3099 {
3100         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3101
3102         kfree(adev->mode_info.bios_hardcoded_edid);
3103
3104         drm_kms_helper_poll_fini(adev->ddev);
3105
3106         dce_v11_0_audio_fini(adev);
3107
3108         dce_v11_0_afmt_fini(adev);
3109
3110         adev->mode_info.mode_config_initialized = false;
3111
3112         return 0;
3113 }
3114
3115 static int dce_v11_0_hw_init(void *handle)
3116 {
3117         int i;
3118         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3119
3120         dce_v11_0_init_golden_registers(adev);
3121
3122         /* init dig PHYs, disp eng pll */
3123         amdgpu_atombios_crtc_powergate_init(adev);
3124         amdgpu_atombios_encoder_init_dig(adev);
3125         if ((adev->asic_type == CHIP_POLARIS10) ||
3126             (adev->asic_type == CHIP_POLARIS11)) {
3127                 amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk,
3128                                                    DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS);
3129                 amdgpu_atombios_crtc_set_dce_clock(adev, 0,
3130                                                    DCE_CLOCK_TYPE_DPREFCLK, ATOM_GCK_DFS);
3131         } else {
3132                 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3133         }
3134
3135         /* initialize hpd */
3136         dce_v11_0_hpd_init(adev);
3137
3138         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3139                 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3140         }
3141
3142         dce_v11_0_pageflip_interrupt_init(adev);
3143
3144         return 0;
3145 }
3146
3147 static int dce_v11_0_hw_fini(void *handle)
3148 {
3149         int i;
3150         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3151
3152         dce_v11_0_hpd_fini(adev);
3153
3154         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3155                 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3156         }
3157
3158         dce_v11_0_pageflip_interrupt_fini(adev);
3159
3160         return 0;
3161 }
3162
3163 static int dce_v11_0_suspend(void *handle)
3164 {
3165         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3166
3167         amdgpu_atombios_scratch_regs_save(adev);
3168
3169         return dce_v11_0_hw_fini(handle);
3170 }
3171
3172 static int dce_v11_0_resume(void *handle)
3173 {
3174         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3175         int ret;
3176
3177         ret = dce_v11_0_hw_init(handle);
3178
3179         amdgpu_atombios_scratch_regs_restore(adev);
3180
3181         /* turn on the BL */
3182         if (adev->mode_info.bl_encoder) {
3183                 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3184                                                                   adev->mode_info.bl_encoder);
3185                 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3186                                                     bl_level);
3187         }
3188
3189         return ret;
3190 }
3191
3192 static bool dce_v11_0_is_idle(void *handle)
3193 {
3194         return true;
3195 }
3196
3197 static int dce_v11_0_wait_for_idle(void *handle)
3198 {
3199         return 0;
3200 }
3201
3202 static int dce_v11_0_soft_reset(void *handle)
3203 {
3204         u32 srbm_soft_reset = 0, tmp;
3205         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3206
3207         if (dce_v11_0_is_display_hung(adev))
3208                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3209
3210         if (srbm_soft_reset) {
3211                 tmp = RREG32(mmSRBM_SOFT_RESET);
3212                 tmp |= srbm_soft_reset;
3213                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3214                 WREG32(mmSRBM_SOFT_RESET, tmp);
3215                 tmp = RREG32(mmSRBM_SOFT_RESET);
3216
3217                 udelay(50);
3218
3219                 tmp &= ~srbm_soft_reset;
3220                 WREG32(mmSRBM_SOFT_RESET, tmp);
3221                 tmp = RREG32(mmSRBM_SOFT_RESET);
3222
3223                 /* Wait a little for things to settle down */
3224                 udelay(50);
3225         }
3226         return 0;
3227 }
3228
3229 static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3230                                                      int crtc,
3231                                                      enum amdgpu_interrupt_state state)
3232 {
3233         u32 lb_interrupt_mask;
3234
3235         if (crtc >= adev->mode_info.num_crtc) {
3236                 DRM_DEBUG("invalid crtc %d\n", crtc);
3237                 return;
3238         }
3239
3240         switch (state) {
3241         case AMDGPU_IRQ_STATE_DISABLE:
3242                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3243                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3244                                                   VBLANK_INTERRUPT_MASK, 0);
3245                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3246                 break;
3247         case AMDGPU_IRQ_STATE_ENABLE:
3248                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3249                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3250                                                   VBLANK_INTERRUPT_MASK, 1);
3251                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3252                 break;
3253         default:
3254                 break;
3255         }
3256 }
3257
3258 static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3259                                                     int crtc,
3260                                                     enum amdgpu_interrupt_state state)
3261 {
3262         u32 lb_interrupt_mask;
3263
3264         if (crtc >= adev->mode_info.num_crtc) {
3265                 DRM_DEBUG("invalid crtc %d\n", crtc);
3266                 return;
3267         }
3268
3269         switch (state) {
3270         case AMDGPU_IRQ_STATE_DISABLE:
3271                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3272                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3273                                                   VLINE_INTERRUPT_MASK, 0);
3274                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3275                 break;
3276         case AMDGPU_IRQ_STATE_ENABLE:
3277                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3278                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3279                                                   VLINE_INTERRUPT_MASK, 1);
3280                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3281                 break;
3282         default:
3283                 break;
3284         }
3285 }
3286
3287 static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev,
3288                                         struct amdgpu_irq_src *source,
3289                                         unsigned hpd,
3290                                         enum amdgpu_interrupt_state state)
3291 {
3292         u32 tmp;
3293
3294         if (hpd >= adev->mode_info.num_hpd) {
3295                 DRM_DEBUG("invalid hdp %d\n", hpd);
3296                 return 0;
3297         }
3298
3299         switch (state) {
3300         case AMDGPU_IRQ_STATE_DISABLE:
3301                 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3302                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3303                 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3304                 break;
3305         case AMDGPU_IRQ_STATE_ENABLE:
3306                 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3307                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3308                 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3309                 break;
3310         default:
3311                 break;
3312         }
3313
3314         return 0;
3315 }
3316
3317 static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev,
3318                                         struct amdgpu_irq_src *source,
3319                                         unsigned type,
3320                                         enum amdgpu_interrupt_state state)
3321 {
3322         switch (type) {
3323         case AMDGPU_CRTC_IRQ_VBLANK1:
3324                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3325                 break;
3326         case AMDGPU_CRTC_IRQ_VBLANK2:
3327                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3328                 break;
3329         case AMDGPU_CRTC_IRQ_VBLANK3:
3330                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3331                 break;
3332         case AMDGPU_CRTC_IRQ_VBLANK4:
3333                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3334                 break;
3335         case AMDGPU_CRTC_IRQ_VBLANK5:
3336                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3337                 break;
3338         case AMDGPU_CRTC_IRQ_VBLANK6:
3339                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3340                 break;
3341         case AMDGPU_CRTC_IRQ_VLINE1:
3342                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state);
3343                 break;
3344         case AMDGPU_CRTC_IRQ_VLINE2:
3345                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state);
3346                 break;
3347         case AMDGPU_CRTC_IRQ_VLINE3:
3348                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state);
3349                 break;
3350         case AMDGPU_CRTC_IRQ_VLINE4:
3351                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state);
3352                 break;
3353         case AMDGPU_CRTC_IRQ_VLINE5:
3354                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state);
3355                 break;
3356          case AMDGPU_CRTC_IRQ_VLINE6:
3357                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state);
3358                 break;
3359         default:
3360                 break;
3361         }
3362         return 0;
3363 }
3364
3365 static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3366                                             struct amdgpu_irq_src *src,
3367                                             unsigned type,
3368                                             enum amdgpu_interrupt_state state)
3369 {
3370         u32 reg;
3371
3372         if (type >= adev->mode_info.num_crtc) {
3373                 DRM_ERROR("invalid pageflip crtc %d\n", type);
3374                 return -EINVAL;
3375         }
3376
3377         reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3378         if (state == AMDGPU_IRQ_STATE_DISABLE)
3379                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3380                        reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3381         else
3382                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3383                        reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3384
3385         return 0;
3386 }
3387
3388 static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
3389                                   struct amdgpu_irq_src *source,
3390                                   struct amdgpu_iv_entry *entry)
3391 {
3392         unsigned long flags;
3393         unsigned crtc_id;
3394         struct amdgpu_crtc *amdgpu_crtc;
3395         struct amdgpu_flip_work *works;
3396
3397         crtc_id = (entry->src_id - 8) >> 1;
3398         amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3399
3400         if (crtc_id >= adev->mode_info.num_crtc) {
3401                 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3402                 return -EINVAL;
3403         }
3404
3405         if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3406             GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3407                 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3408                        GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3409
3410         /* IRQ could occur when in initial stage */
3411         if(amdgpu_crtc == NULL)
3412                 return 0;
3413
3414         spin_lock_irqsave(&adev->ddev->event_lock, flags);
3415         works = amdgpu_crtc->pflip_works;
3416         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3417                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3418                                                  "AMDGPU_FLIP_SUBMITTED(%d)\n",
3419                                                  amdgpu_crtc->pflip_status,
3420                                                  AMDGPU_FLIP_SUBMITTED);
3421                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3422                 return 0;
3423         }
3424
3425         /* page flip completed. clean up */
3426         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3427         amdgpu_crtc->pflip_works = NULL;
3428
3429         /* wakeup usersapce */
3430         if(works->event)
3431                 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3432
3433         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3434
3435         drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id);
3436         schedule_work(&works->unpin_work);
3437
3438         return 0;
3439 }
3440
3441 static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev,
3442                                   int hpd)
3443 {
3444         u32 tmp;
3445
3446         if (hpd >= adev->mode_info.num_hpd) {
3447                 DRM_DEBUG("invalid hdp %d\n", hpd);
3448                 return;
3449         }
3450
3451         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3452         tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3453         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3454 }
3455
3456 static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3457                                           int crtc)
3458 {
3459         u32 tmp;
3460
3461         if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3462                 DRM_DEBUG("invalid crtc %d\n", crtc);
3463                 return;
3464         }
3465
3466         tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3467         tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3468         WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3469 }
3470
3471 static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3472                                          int crtc)
3473 {
3474         u32 tmp;
3475
3476         if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3477                 DRM_DEBUG("invalid crtc %d\n", crtc);
3478                 return;
3479         }
3480
3481         tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3482         tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3483         WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3484 }
3485
3486 static int dce_v11_0_crtc_irq(struct amdgpu_device *adev,
3487                                 struct amdgpu_irq_src *source,
3488                                 struct amdgpu_iv_entry *entry)
3489 {
3490         unsigned crtc = entry->src_id - 1;
3491         uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3492         unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3493
3494         switch (entry->src_data) {
3495         case 0: /* vblank */
3496                 if (disp_int & interrupt_status_offsets[crtc].vblank)
3497                         dce_v11_0_crtc_vblank_int_ack(adev, crtc);
3498                 else
3499                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3500
3501                 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3502                         drm_handle_vblank(adev->ddev, crtc);
3503                 }
3504                 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3505
3506                 break;
3507         case 1: /* vline */
3508                 if (disp_int & interrupt_status_offsets[crtc].vline)
3509                         dce_v11_0_crtc_vline_int_ack(adev, crtc);
3510                 else
3511                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3512
3513                 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3514
3515                 break;
3516         default:
3517                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3518                 break;
3519         }
3520
3521         return 0;
3522 }
3523
3524 static int dce_v11_0_hpd_irq(struct amdgpu_device *adev,
3525                              struct amdgpu_irq_src *source,
3526                              struct amdgpu_iv_entry *entry)
3527 {
3528         uint32_t disp_int, mask;
3529         unsigned hpd;
3530
3531         if (entry->src_data >= adev->mode_info.num_hpd) {
3532                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3533                 return 0;
3534         }
3535
3536         hpd = entry->src_data;
3537         disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3538         mask = interrupt_status_offsets[hpd].hpd;
3539
3540         if (disp_int & mask) {
3541                 dce_v11_0_hpd_int_ack(adev, hpd);
3542                 schedule_work(&adev->hotplug_work);
3543                 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3544         }
3545
3546         return 0;
3547 }
3548
3549 static int dce_v11_0_set_clockgating_state(void *handle,
3550                                           enum amd_clockgating_state state)
3551 {
3552         return 0;
3553 }
3554
3555 static int dce_v11_0_set_powergating_state(void *handle,
3556                                           enum amd_powergating_state state)
3557 {
3558         return 0;
3559 }
3560
3561 const struct amd_ip_funcs dce_v11_0_ip_funcs = {
3562         .name = "dce_v11_0",
3563         .early_init = dce_v11_0_early_init,
3564         .late_init = NULL,
3565         .sw_init = dce_v11_0_sw_init,
3566         .sw_fini = dce_v11_0_sw_fini,
3567         .hw_init = dce_v11_0_hw_init,
3568         .hw_fini = dce_v11_0_hw_fini,
3569         .suspend = dce_v11_0_suspend,
3570         .resume = dce_v11_0_resume,
3571         .is_idle = dce_v11_0_is_idle,
3572         .wait_for_idle = dce_v11_0_wait_for_idle,
3573         .soft_reset = dce_v11_0_soft_reset,
3574         .set_clockgating_state = dce_v11_0_set_clockgating_state,
3575         .set_powergating_state = dce_v11_0_set_powergating_state,
3576 };
3577
3578 static void
3579 dce_v11_0_encoder_mode_set(struct drm_encoder *encoder,
3580                           struct drm_display_mode *mode,
3581                           struct drm_display_mode *adjusted_mode)
3582 {
3583         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3584
3585         amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3586
3587         /* need to call this here rather than in prepare() since we need some crtc info */
3588         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3589
3590         /* set scaler clears this on some chips */
3591         dce_v11_0_set_interleave(encoder->crtc, mode);
3592
3593         if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3594                 dce_v11_0_afmt_enable(encoder, true);
3595                 dce_v11_0_afmt_setmode(encoder, adjusted_mode);
3596         }
3597 }
3598
3599 static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder)
3600 {
3601         struct amdgpu_device *adev = encoder->dev->dev_private;
3602         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3603         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3604
3605         if ((amdgpu_encoder->active_device &
3606              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3607             (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3608              ENCODER_OBJECT_ID_NONE)) {
3609                 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3610                 if (dig) {
3611                         dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder);
3612                         if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3613                                 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3614                 }
3615         }
3616
3617         amdgpu_atombios_scratch_regs_lock(adev, true);
3618
3619         if (connector) {
3620                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3621
3622                 /* select the clock/data port if it uses a router */
3623                 if (amdgpu_connector->router.cd_valid)
3624                         amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3625
3626                 /* turn eDP panel on for mode set */
3627                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3628                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
3629                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
3630         }
3631
3632         /* this is needed for the pll/ss setup to work correctly in some cases */
3633         amdgpu_atombios_encoder_set_crtc_source(encoder);
3634         /* set up the FMT blocks */
3635         dce_v11_0_program_fmt(encoder);
3636 }
3637
3638 static void dce_v11_0_encoder_commit(struct drm_encoder *encoder)
3639 {
3640         struct drm_device *dev = encoder->dev;
3641         struct amdgpu_device *adev = dev->dev_private;
3642
3643         /* need to call this here as we need the crtc set up */
3644         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3645         amdgpu_atombios_scratch_regs_lock(adev, false);
3646 }
3647
3648 static void dce_v11_0_encoder_disable(struct drm_encoder *encoder)
3649 {
3650         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3651         struct amdgpu_encoder_atom_dig *dig;
3652
3653         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3654
3655         if (amdgpu_atombios_encoder_is_digital(encoder)) {
3656                 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3657                         dce_v11_0_afmt_enable(encoder, false);
3658                 dig = amdgpu_encoder->enc_priv;
3659                 dig->dig_encoder = -1;
3660         }
3661         amdgpu_encoder->active_device = 0;
3662 }
3663
3664 /* these are handled by the primary encoders */
3665 static void dce_v11_0_ext_prepare(struct drm_encoder *encoder)
3666 {
3667
3668 }
3669
3670 static void dce_v11_0_ext_commit(struct drm_encoder *encoder)
3671 {
3672
3673 }
3674
3675 static void
3676 dce_v11_0_ext_mode_set(struct drm_encoder *encoder,
3677                       struct drm_display_mode *mode,
3678                       struct drm_display_mode *adjusted_mode)
3679 {
3680
3681 }
3682
3683 static void dce_v11_0_ext_disable(struct drm_encoder *encoder)
3684 {
3685
3686 }
3687
3688 static void
3689 dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode)
3690 {
3691
3692 }
3693
3694 static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = {
3695         .dpms = dce_v11_0_ext_dpms,
3696         .prepare = dce_v11_0_ext_prepare,
3697         .mode_set = dce_v11_0_ext_mode_set,
3698         .commit = dce_v11_0_ext_commit,
3699         .disable = dce_v11_0_ext_disable,
3700         /* no detect for TMDS/LVDS yet */
3701 };
3702
3703 static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = {
3704         .dpms = amdgpu_atombios_encoder_dpms,
3705         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3706         .prepare = dce_v11_0_encoder_prepare,
3707         .mode_set = dce_v11_0_encoder_mode_set,
3708         .commit = dce_v11_0_encoder_commit,
3709         .disable = dce_v11_0_encoder_disable,
3710         .detect = amdgpu_atombios_encoder_dig_detect,
3711 };
3712
3713 static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = {
3714         .dpms = amdgpu_atombios_encoder_dpms,
3715         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3716         .prepare = dce_v11_0_encoder_prepare,
3717         .mode_set = dce_v11_0_encoder_mode_set,
3718         .commit = dce_v11_0_encoder_commit,
3719         .detect = amdgpu_atombios_encoder_dac_detect,
3720 };
3721
3722 static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder)
3723 {
3724         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3725         if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3726                 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3727         kfree(amdgpu_encoder->enc_priv);
3728         drm_encoder_cleanup(encoder);
3729         kfree(amdgpu_encoder);
3730 }
3731
3732 static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = {
3733         .destroy = dce_v11_0_encoder_destroy,
3734 };
3735
3736 static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
3737                                  uint32_t encoder_enum,
3738                                  uint32_t supported_device,
3739                                  u16 caps)
3740 {
3741         struct drm_device *dev = adev->ddev;
3742         struct drm_encoder *encoder;
3743         struct amdgpu_encoder *amdgpu_encoder;
3744
3745         /* see if we already added it */
3746         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3747                 amdgpu_encoder = to_amdgpu_encoder(encoder);
3748                 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3749                         amdgpu_encoder->devices |= supported_device;
3750                         return;
3751                 }
3752
3753         }
3754
3755         /* add a new one */
3756         amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3757         if (!amdgpu_encoder)
3758                 return;
3759
3760         encoder = &amdgpu_encoder->base;
3761         switch (adev->mode_info.num_crtc) {
3762         case 1:
3763                 encoder->possible_crtcs = 0x1;
3764                 break;
3765         case 2:
3766         default:
3767                 encoder->possible_crtcs = 0x3;
3768                 break;
3769         case 4:
3770                 encoder->possible_crtcs = 0xf;
3771                 break;
3772         case 6:
3773                 encoder->possible_crtcs = 0x3f;
3774                 break;
3775         }
3776
3777         amdgpu_encoder->enc_priv = NULL;
3778
3779         amdgpu_encoder->encoder_enum = encoder_enum;
3780         amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3781         amdgpu_encoder->devices = supported_device;
3782         amdgpu_encoder->rmx_type = RMX_OFF;
3783         amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3784         amdgpu_encoder->is_ext_encoder = false;
3785         amdgpu_encoder->caps = caps;
3786
3787         switch (amdgpu_encoder->encoder_id) {
3788         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3789         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3790                 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3791                                  DRM_MODE_ENCODER_DAC, NULL);
3792                 drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs);
3793                 break;
3794         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3795         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3796         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3797         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3798         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3799                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3800                         amdgpu_encoder->rmx_type = RMX_FULL;
3801                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3802                                          DRM_MODE_ENCODER_LVDS, NULL);
3803                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3804                 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3805                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3806                                          DRM_MODE_ENCODER_DAC, NULL);
3807                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3808                 } else {
3809                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3810                                          DRM_MODE_ENCODER_TMDS, NULL);
3811                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3812                 }
3813                 drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs);
3814                 break;
3815         case ENCODER_OBJECT_ID_SI170B:
3816         case ENCODER_OBJECT_ID_CH7303:
3817         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3818         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3819         case ENCODER_OBJECT_ID_TITFP513:
3820         case ENCODER_OBJECT_ID_VT1623:
3821         case ENCODER_OBJECT_ID_HDMI_SI1930:
3822         case ENCODER_OBJECT_ID_TRAVIS:
3823         case ENCODER_OBJECT_ID_NUTMEG:
3824                 /* these are handled by the primary encoders */
3825                 amdgpu_encoder->is_ext_encoder = true;
3826                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3827                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3828                                          DRM_MODE_ENCODER_LVDS, NULL);
3829                 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3830                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3831                                          DRM_MODE_ENCODER_DAC, NULL);
3832                 else
3833                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3834                                          DRM_MODE_ENCODER_TMDS, NULL);
3835                 drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs);
3836                 break;
3837         }
3838 }
3839
3840 static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
3841         .set_vga_render_state = &dce_v11_0_set_vga_render_state,
3842         .bandwidth_update = &dce_v11_0_bandwidth_update,
3843         .vblank_get_counter = &dce_v11_0_vblank_get_counter,
3844         .vblank_wait = &dce_v11_0_vblank_wait,
3845         .is_display_hung = &dce_v11_0_is_display_hung,
3846         .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3847         .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3848         .hpd_sense = &dce_v11_0_hpd_sense,
3849         .hpd_set_polarity = &dce_v11_0_hpd_set_polarity,
3850         .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg,
3851         .page_flip = &dce_v11_0_page_flip,
3852         .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos,
3853         .add_encoder = &dce_v11_0_encoder_add,
3854         .add_connector = &amdgpu_connector_add,
3855         .stop_mc_access = &dce_v11_0_stop_mc_access,
3856         .resume_mc_access = &dce_v11_0_resume_mc_access,
3857 };
3858
3859 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev)
3860 {
3861         if (adev->mode_info.funcs == NULL)
3862                 adev->mode_info.funcs = &dce_v11_0_display_funcs;
3863 }
3864
3865 static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = {
3866         .set = dce_v11_0_set_crtc_irq_state,
3867         .process = dce_v11_0_crtc_irq,
3868 };
3869
3870 static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = {
3871         .set = dce_v11_0_set_pageflip_irq_state,
3872         .process = dce_v11_0_pageflip_irq,
3873 };
3874
3875 static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = {
3876         .set = dce_v11_0_set_hpd_irq_state,
3877         .process = dce_v11_0_hpd_irq,
3878 };
3879
3880 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev)
3881 {
3882         adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3883         adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs;
3884
3885         adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3886         adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs;
3887
3888         adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3889         adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs;
3890 }