drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include "drmP.h"
  25 #include "amdgpu.h"
  26 #include "amdgpu_ih.h"
  27 #include "amdgpu_gfx.h"
  28 #include "cikd.h"
  29 #include "cik.h"
  30 #include "atom.h"
  31 #include "amdgpu_ucode.h"
  32 #include "clearstate_ci.h"
  33
  34 #include "dce/dce_8_0_d.h"
  35 #include "dce/dce_8_0_sh_mask.h"
  36
  37 #include "bif/bif_4_1_d.h"
  38 #include "bif/bif_4_1_sh_mask.h"
  39
  40 #include "gca/gfx_7_0_d.h"
  41 #include "gca/gfx_7_2_enum.h"
  42 #include "gca/gfx_7_2_sh_mask.h"
  43
  44 #include "gmc/gmc_7_0_d.h"
  45 #include "gmc/gmc_7_0_sh_mask.h"
  46
  47 #include "oss/oss_2_0_d.h"
  48 #include "oss/oss_2_0_sh_mask.h"
  49
  50 #define GFX7_NUM_GFX_RINGS     1
  51 #define GFX7_NUM_COMPUTE_RINGS 8
  52
  53 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev);
  54 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev);
  55 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev);
  56
  57 MODULE_FIRMWARE("radeon/bonaire_pfp.bin");
  58 MODULE_FIRMWARE("radeon/bonaire_me.bin");
  59 MODULE_FIRMWARE("radeon/bonaire_ce.bin");
  60 MODULE_FIRMWARE("radeon/bonaire_rlc.bin");
  61 MODULE_FIRMWARE("radeon/bonaire_mec.bin");
  62
  63 MODULE_FIRMWARE("radeon/hawaii_pfp.bin");
  64 MODULE_FIRMWARE("radeon/hawaii_me.bin");
  65 MODULE_FIRMWARE("radeon/hawaii_ce.bin");
  66 MODULE_FIRMWARE("radeon/hawaii_rlc.bin");
  67 MODULE_FIRMWARE("radeon/hawaii_mec.bin");
  68
  69 MODULE_FIRMWARE("radeon/kaveri_pfp.bin");
  70 MODULE_FIRMWARE("radeon/kaveri_me.bin");
  71 MODULE_FIRMWARE("radeon/kaveri_ce.bin");
  72 MODULE_FIRMWARE("radeon/kaveri_rlc.bin");
  73 MODULE_FIRMWARE("radeon/kaveri_mec.bin");
  74 MODULE_FIRMWARE("radeon/kaveri_mec2.bin");
  75
  76 MODULE_FIRMWARE("radeon/kabini_pfp.bin");
  77 MODULE_FIRMWARE("radeon/kabini_me.bin");
  78 MODULE_FIRMWARE("radeon/kabini_ce.bin");
  79 MODULE_FIRMWARE("radeon/kabini_rlc.bin");
  80 MODULE_FIRMWARE("radeon/kabini_mec.bin");
  81
  82 MODULE_FIRMWARE("radeon/mullins_pfp.bin");
  83 MODULE_FIRMWARE("radeon/mullins_me.bin");
  84 MODULE_FIRMWARE("radeon/mullins_ce.bin");
  85 MODULE_FIRMWARE("radeon/mullins_rlc.bin");
  86 MODULE_FIRMWARE("radeon/mullins_mec.bin");
  87
  88 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
  89 {
  90         {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
  91         {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
  92         {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
  93         {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
  94         {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
  95         {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
  96         {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
  97         {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
  98         {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
  99         {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
 100         {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
 101         {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
 102         {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
 103         {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
 104         {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
 105         {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
 106 };
 107
 108 static const u32 spectre_rlc_save_restore_register_list[] =
 109 {
 110         (0x0e00 << 16) | (0xc12c >> 2),
 111         0x00000000,
 112         (0x0e00 << 16) | (0xc140 >> 2),
 113         0x00000000,
 114         (0x0e00 << 16) | (0xc150 >> 2),
 115         0x00000000,
 116         (0x0e00 << 16) | (0xc15c >> 2),
 117         0x00000000,
 118         (0x0e00 << 16) | (0xc168 >> 2),
 119         0x00000000,
 120         (0x0e00 << 16) | (0xc170 >> 2),
 121         0x00000000,
 122         (0x0e00 << 16) | (0xc178 >> 2),
 123         0x00000000,
 124         (0x0e00 << 16) | (0xc204 >> 2),
 125         0x00000000,
 126         (0x0e00 << 16) | (0xc2b4 >> 2),
 127         0x00000000,
 128         (0x0e00 << 16) | (0xc2b8 >> 2),
 129         0x00000000,
 130         (0x0e00 << 16) | (0xc2bc >> 2),
 131         0x00000000,
 132         (0x0e00 << 16) | (0xc2c0 >> 2),
 133         0x00000000,
 134         (0x0e00 << 16) | (0x8228 >> 2),
 135         0x00000000,
 136         (0x0e00 << 16) | (0x829c >> 2),
 137         0x00000000,
 138         (0x0e00 << 16) | (0x869c >> 2),
 139         0x00000000,
 140         (0x0600 << 16) | (0x98f4 >> 2),
 141         0x00000000,
 142         (0x0e00 << 16) | (0x98f8 >> 2),
 143         0x00000000,
 144         (0x0e00 << 16) | (0x9900 >> 2),
 145         0x00000000,
 146         (0x0e00 << 16) | (0xc260 >> 2),
 147         0x00000000,
 148         (0x0e00 << 16) | (0x90e8 >> 2),
 149         0x00000000,
 150         (0x0e00 << 16) | (0x3c000 >> 2),
 151         0x00000000,
 152         (0x0e00 << 16) | (0x3c00c >> 2),
 153         0x00000000,
 154         (0x0e00 << 16) | (0x8c1c >> 2),
 155         0x00000000,
 156         (0x0e00 << 16) | (0x9700 >> 2),
 157         0x00000000,
 158         (0x0e00 << 16) | (0xcd20 >> 2),
 159         0x00000000,
 160         (0x4e00 << 16) | (0xcd20 >> 2),
 161         0x00000000,
 162         (0x5e00 << 16) | (0xcd20 >> 2),
 163         0x00000000,
 164         (0x6e00 << 16) | (0xcd20 >> 2),
 165         0x00000000,
 166         (0x7e00 << 16) | (0xcd20 >> 2),
 167         0x00000000,
 168         (0x8e00 << 16) | (0xcd20 >> 2),
 169         0x00000000,
 170         (0x9e00 << 16) | (0xcd20 >> 2),
 171         0x00000000,
 172         (0xae00 << 16) | (0xcd20 >> 2),
 173         0x00000000,
 174         (0xbe00 << 16) | (0xcd20 >> 2),
 175         0x00000000,
 176         (0x0e00 << 16) | (0x89bc >> 2),
 177         0x00000000,
 178         (0x0e00 << 16) | (0x8900 >> 2),
 179         0x00000000,
 180         0x3,
 181         (0x0e00 << 16) | (0xc130 >> 2),
 182         0x00000000,
 183         (0x0e00 << 16) | (0xc134 >> 2),
 184         0x00000000,
 185         (0x0e00 << 16) | (0xc1fc >> 2),
 186         0x00000000,
 187         (0x0e00 << 16) | (0xc208 >> 2),
 188         0x00000000,
 189         (0x0e00 << 16) | (0xc264 >> 2),
 190         0x00000000,
 191         (0x0e00 << 16) | (0xc268 >> 2),
 192         0x00000000,
 193         (0x0e00 << 16) | (0xc26c >> 2),
 194         0x00000000,
 195         (0x0e00 << 16) | (0xc270 >> 2),
 196         0x00000000,
 197         (0x0e00 << 16) | (0xc274 >> 2),
 198         0x00000000,
 199         (0x0e00 << 16) | (0xc278 >> 2),
 200         0x00000000,
 201         (0x0e00 << 16) | (0xc27c >> 2),
 202         0x00000000,
 203         (0x0e00 << 16) | (0xc280 >> 2),
 204         0x00000000,
 205         (0x0e00 << 16) | (0xc284 >> 2),
 206         0x00000000,
 207         (0x0e00 << 16) | (0xc288 >> 2),
 208         0x00000000,
 209         (0x0e00 << 16) | (0xc28c >> 2),
 210         0x00000000,
 211         (0x0e00 << 16) | (0xc290 >> 2),
 212         0x00000000,
 213         (0x0e00 << 16) | (0xc294 >> 2),
 214         0x00000000,
 215         (0x0e00 << 16) | (0xc298 >> 2),
 216         0x00000000,
 217         (0x0e00 << 16) | (0xc29c >> 2),
 218         0x00000000,
 219         (0x0e00 << 16) | (0xc2a0 >> 2),
 220         0x00000000,
 221         (0x0e00 << 16) | (0xc2a4 >> 2),
 222         0x00000000,
 223         (0x0e00 << 16) | (0xc2a8 >> 2),
 224         0x00000000,
 225         (0x0e00 << 16) | (0xc2ac  >> 2),
 226         0x00000000,
 227         (0x0e00 << 16) | (0xc2b0 >> 2),
 228         0x00000000,
 229         (0x0e00 << 16) | (0x301d0 >> 2),
 230         0x00000000,
 231         (0x0e00 << 16) | (0x30238 >> 2),
 232         0x00000000,
 233         (0x0e00 << 16) | (0x30250 >> 2),
 234         0x00000000,
 235         (0x0e00 << 16) | (0x30254 >> 2),
 236         0x00000000,
 237         (0x0e00 << 16) | (0x30258 >> 2),
 238         0x00000000,
 239         (0x0e00 << 16) | (0x3025c >> 2),
 240         0x00000000,
 241         (0x4e00 << 16) | (0xc900 >> 2),
 242         0x00000000,
 243         (0x5e00 << 16) | (0xc900 >> 2),
 244         0x00000000,
 245         (0x6e00 << 16) | (0xc900 >> 2),
 246         0x00000000,
 247         (0x7e00 << 16) | (0xc900 >> 2),
 248         0x00000000,
 249         (0x8e00 << 16) | (0xc900 >> 2),
 250         0x00000000,
 251         (0x9e00 << 16) | (0xc900 >> 2),
 252         0x00000000,
 253         (0xae00 << 16) | (0xc900 >> 2),
 254         0x00000000,
 255         (0xbe00 << 16) | (0xc900 >> 2),
 256         0x00000000,
 257         (0x4e00 << 16) | (0xc904 >> 2),
 258         0x00000000,
 259         (0x5e00 << 16) | (0xc904 >> 2),
 260         0x00000000,
 261         (0x6e00 << 16) | (0xc904 >> 2),
 262         0x00000000,
 263         (0x7e00 << 16) | (0xc904 >> 2),
 264         0x00000000,
 265         (0x8e00 << 16) | (0xc904 >> 2),
 266         0x00000000,
 267         (0x9e00 << 16) | (0xc904 >> 2),
 268         0x00000000,
 269         (0xae00 << 16) | (0xc904 >> 2),
 270         0x00000000,
 271         (0xbe00 << 16) | (0xc904 >> 2),
 272         0x00000000,
 273         (0x4e00 << 16) | (0xc908 >> 2),
 274         0x00000000,
 275         (0x5e00 << 16) | (0xc908 >> 2),
 276         0x00000000,
 277         (0x6e00 << 16) | (0xc908 >> 2),
 278         0x00000000,
 279         (0x7e00 << 16) | (0xc908 >> 2),
 280         0x00000000,
 281         (0x8e00 << 16) | (0xc908 >> 2),
 282         0x00000000,
 283         (0x9e00 << 16) | (0xc908 >> 2),
 284         0x00000000,
 285         (0xae00 << 16) | (0xc908 >> 2),
 286         0x00000000,
 287         (0xbe00 << 16) | (0xc908 >> 2),
 288         0x00000000,
 289         (0x4e00 << 16) | (0xc90c >> 2),
 290         0x00000000,
 291         (0x5e00 << 16) | (0xc90c >> 2),
 292         0x00000000,
 293         (0x6e00 << 16) | (0xc90c >> 2),
 294         0x00000000,
 295         (0x7e00 << 16) | (0xc90c >> 2),
 296         0x00000000,
 297         (0x8e00 << 16) | (0xc90c >> 2),
 298         0x00000000,
 299         (0x9e00 << 16) | (0xc90c >> 2),
 300         0x00000000,
 301         (0xae00 << 16) | (0xc90c >> 2),
 302         0x00000000,
 303         (0xbe00 << 16) | (0xc90c >> 2),
 304         0x00000000,
 305         (0x4e00 << 16) | (0xc910 >> 2),
 306         0x00000000,
 307         (0x5e00 << 16) | (0xc910 >> 2),
 308         0x00000000,
 309         (0x6e00 << 16) | (0xc910 >> 2),
 310         0x00000000,
 311         (0x7e00 << 16) | (0xc910 >> 2),
 312         0x00000000,
 313         (0x8e00 << 16) | (0xc910 >> 2),
 314         0x00000000,
 315         (0x9e00 << 16) | (0xc910 >> 2),
 316         0x00000000,
 317         (0xae00 << 16) | (0xc910 >> 2),
 318         0x00000000,
 319         (0xbe00 << 16) | (0xc910 >> 2),
 320         0x00000000,
 321         (0x0e00 << 16) | (0xc99c >> 2),
 322         0x00000000,
 323         (0x0e00 << 16) | (0x9834 >> 2),
 324         0x00000000,
 325         (0x0000 << 16) | (0x30f00 >> 2),
 326         0x00000000,
 327         (0x0001 << 16) | (0x30f00 >> 2),
 328         0x00000000,
 329         (0x0000 << 16) | (0x30f04 >> 2),
 330         0x00000000,
 331         (0x0001 << 16) | (0x30f04 >> 2),
 332         0x00000000,
 333         (0x0000 << 16) | (0x30f08 >> 2),
 334         0x00000000,
 335         (0x0001 << 16) | (0x30f08 >> 2),
 336         0x00000000,
 337         (0x0000 << 16) | (0x30f0c >> 2),
 338         0x00000000,
 339         (0x0001 << 16) | (0x30f0c >> 2),
 340         0x00000000,
 341         (0x0600 << 16) | (0x9b7c >> 2),
 342         0x00000000,
 343         (0x0e00 << 16) | (0x8a14 >> 2),
 344         0x00000000,
 345         (0x0e00 << 16) | (0x8a18 >> 2),
 346         0x00000000,
 347         (0x0600 << 16) | (0x30a00 >> 2),
 348         0x00000000,
 349         (0x0e00 << 16) | (0x8bf0 >> 2),
 350         0x00000000,
 351         (0x0e00 << 16) | (0x8bcc >> 2),
 352         0x00000000,
 353         (0x0e00 << 16) | (0x8b24 >> 2),
 354         0x00000000,
 355         (0x0e00 << 16) | (0x30a04 >> 2),
 356         0x00000000,
 357         (0x0600 << 16) | (0x30a10 >> 2),
 358         0x00000000,
 359         (0x0600 << 16) | (0x30a14 >> 2),
 360         0x00000000,
 361         (0x0600 << 16) | (0x30a18 >> 2),
 362         0x00000000,
 363         (0x0600 << 16) | (0x30a2c >> 2),
 364         0x00000000,
 365         (0x0e00 << 16) | (0xc700 >> 2),
 366         0x00000000,
 367         (0x0e00 << 16) | (0xc704 >> 2),
 368         0x00000000,
 369         (0x0e00 << 16) | (0xc708 >> 2),
 370         0x00000000,
 371         (0x0e00 << 16) | (0xc768 >> 2),
 372         0x00000000,
 373         (0x0400 << 16) | (0xc770 >> 2),
 374         0x00000000,
 375         (0x0400 << 16) | (0xc774 >> 2),
 376         0x00000000,
 377         (0x0400 << 16) | (0xc778 >> 2),
 378         0x00000000,
 379         (0x0400 << 16) | (0xc77c >> 2),
 380         0x00000000,
 381         (0x0400 << 16) | (0xc780 >> 2),
 382         0x00000000,
 383         (0x0400 << 16) | (0xc784 >> 2),
 384         0x00000000,
 385         (0x0400 << 16) | (0xc788 >> 2),
 386         0x00000000,
 387         (0x0400 << 16) | (0xc78c >> 2),
 388         0x00000000,
 389         (0x0400 << 16) | (0xc798 >> 2),
 390         0x00000000,
 391         (0x0400 << 16) | (0xc79c >> 2),
 392         0x00000000,
 393         (0x0400 << 16) | (0xc7a0 >> 2),
 394         0x00000000,
 395         (0x0400 << 16) | (0xc7a4 >> 2),
 396         0x00000000,
 397         (0x0400 << 16) | (0xc7a8 >> 2),
 398         0x00000000,
 399         (0x0400 << 16) | (0xc7ac >> 2),
 400         0x00000000,
 401         (0x0400 << 16) | (0xc7b0 >> 2),
 402         0x00000000,
 403         (0x0400 << 16) | (0xc7b4 >> 2),
 404         0x00000000,
 405         (0x0e00 << 16) | (0x9100 >> 2),
 406         0x00000000,
 407         (0x0e00 << 16) | (0x3c010 >> 2),
 408         0x00000000,
 409         (0x0e00 << 16) | (0x92a8 >> 2),
 410         0x00000000,
 411         (0x0e00 << 16) | (0x92ac >> 2),
 412         0x00000000,
 413         (0x0e00 << 16) | (0x92b4 >> 2),
 414         0x00000000,
 415         (0x0e00 << 16) | (0x92b8 >> 2),
 416         0x00000000,
 417         (0x0e00 << 16) | (0x92bc >> 2),
 418         0x00000000,
 419         (0x0e00 << 16) | (0x92c0 >> 2),
 420         0x00000000,
 421         (0x0e00 << 16) | (0x92c4 >> 2),
 422         0x00000000,
 423         (0x0e00 << 16) | (0x92c8 >> 2),
 424         0x00000000,
 425         (0x0e00 << 16) | (0x92cc >> 2),
 426         0x00000000,
 427         (0x0e00 << 16) | (0x92d0 >> 2),
 428         0x00000000,
 429         (0x0e00 << 16) | (0x8c00 >> 2),
 430         0x00000000,
 431         (0x0e00 << 16) | (0x8c04 >> 2),
 432         0x00000000,
 433         (0x0e00 << 16) | (0x8c20 >> 2),
 434         0x00000000,
 435         (0x0e00 << 16) | (0x8c38 >> 2),
 436         0x00000000,
 437         (0x0e00 << 16) | (0x8c3c >> 2),
 438         0x00000000,
 439         (0x0e00 << 16) | (0xae00 >> 2),
 440         0x00000000,
 441         (0x0e00 << 16) | (0x9604 >> 2),
 442         0x00000000,
 443         (0x0e00 << 16) | (0xac08 >> 2),
 444         0x00000000,
 445         (0x0e00 << 16) | (0xac0c >> 2),
 446         0x00000000,
 447         (0x0e00 << 16) | (0xac10 >> 2),
 448         0x00000000,
 449         (0x0e00 << 16) | (0xac14 >> 2),
 450         0x00000000,
 451         (0x0e00 << 16) | (0xac58 >> 2),
 452         0x00000000,
 453         (0x0e00 << 16) | (0xac68 >> 2),
 454         0x00000000,
 455         (0x0e00 << 16) | (0xac6c >> 2),
 456         0x00000000,
 457         (0x0e00 << 16) | (0xac70 >> 2),
 458         0x00000000,
 459         (0x0e00 << 16) | (0xac74 >> 2),
 460         0x00000000,
 461         (0x0e00 << 16) | (0xac78 >> 2),
 462         0x00000000,
 463         (0x0e00 << 16) | (0xac7c >> 2),
 464         0x00000000,
 465         (0x0e00 << 16) | (0xac80 >> 2),
 466         0x00000000,
 467         (0x0e00 << 16) | (0xac84 >> 2),
 468         0x00000000,
 469         (0x0e00 << 16) | (0xac88 >> 2),
 470         0x00000000,
 471         (0x0e00 << 16) | (0xac8c >> 2),
 472         0x00000000,
 473         (0x0e00 << 16) | (0x970c >> 2),
 474         0x00000000,
 475         (0x0e00 << 16) | (0x9714 >> 2),
 476         0x00000000,
 477         (0x0e00 << 16) | (0x9718 >> 2),
 478         0x00000000,
 479         (0x0e00 << 16) | (0x971c >> 2),
 480         0x00000000,
 481         (0x0e00 << 16) | (0x31068 >> 2),
 482         0x00000000,
 483         (0x4e00 << 16) | (0x31068 >> 2),
 484         0x00000000,
 485         (0x5e00 << 16) | (0x31068 >> 2),
 486         0x00000000,
 487         (0x6e00 << 16) | (0x31068 >> 2),
 488         0x00000000,
 489         (0x7e00 << 16) | (0x31068 >> 2),
 490         0x00000000,
 491         (0x8e00 << 16) | (0x31068 >> 2),
 492         0x00000000,
 493         (0x9e00 << 16) | (0x31068 >> 2),
 494         0x00000000,
 495         (0xae00 << 16) | (0x31068 >> 2),
 496         0x00000000,
 497         (0xbe00 << 16) | (0x31068 >> 2),
 498         0x00000000,
 499         (0x0e00 << 16) | (0xcd10 >> 2),
 500         0x00000000,
 501         (0x0e00 << 16) | (0xcd14 >> 2),
 502         0x00000000,
 503         (0x0e00 << 16) | (0x88b0 >> 2),
 504         0x00000000,
 505         (0x0e00 << 16) | (0x88b4 >> 2),
 506         0x00000000,
 507         (0x0e00 << 16) | (0x88b8 >> 2),
 508         0x00000000,
 509         (0x0e00 << 16) | (0x88bc >> 2),
 510         0x00000000,
 511         (0x0400 << 16) | (0x89c0 >> 2),
 512         0x00000000,
 513         (0x0e00 << 16) | (0x88c4 >> 2),
 514         0x00000000,
 515         (0x0e00 << 16) | (0x88c8 >> 2),
 516         0x00000000,
 517         (0x0e00 << 16) | (0x88d0 >> 2),
 518         0x00000000,
 519         (0x0e00 << 16) | (0x88d4 >> 2),
 520         0x00000000,
 521         (0x0e00 << 16) | (0x88d8 >> 2),
 522         0x00000000,
 523         (0x0e00 << 16) | (0x8980 >> 2),
 524         0x00000000,
 525         (0x0e00 << 16) | (0x30938 >> 2),
 526         0x00000000,
 527         (0x0e00 << 16) | (0x3093c >> 2),
 528         0x00000000,
 529         (0x0e00 << 16) | (0x30940 >> 2),
 530         0x00000000,
 531         (0x0e00 << 16) | (0x89a0 >> 2),
 532         0x00000000,
 533         (0x0e00 << 16) | (0x30900 >> 2),
 534         0x00000000,
 535         (0x0e00 << 16) | (0x30904 >> 2),
 536         0x00000000,
 537         (0x0e00 << 16) | (0x89b4 >> 2),
 538         0x00000000,
 539         (0x0e00 << 16) | (0x3c210 >> 2),
 540         0x00000000,
 541         (0x0e00 << 16) | (0x3c214 >> 2),
 542         0x00000000,
 543         (0x0e00 << 16) | (0x3c218 >> 2),
 544         0x00000000,
 545         (0x0e00 << 16) | (0x8904 >> 2),
 546         0x00000000,
 547         0x5,
 548         (0x0e00 << 16) | (0x8c28 >> 2),
 549         (0x0e00 << 16) | (0x8c2c >> 2),
 550         (0x0e00 << 16) | (0x8c30 >> 2),
 551         (0x0e00 << 16) | (0x8c34 >> 2),
 552         (0x0e00 << 16) | (0x9600 >> 2),
 553 };
 554
 555 static const u32 kalindi_rlc_save_restore_register_list[] =
 556 {
 557         (0x0e00 << 16) | (0xc12c >> 2),
 558         0x00000000,
 559         (0x0e00 << 16) | (0xc140 >> 2),
 560         0x00000000,
 561         (0x0e00 << 16) | (0xc150 >> 2),
 562         0x00000000,
 563         (0x0e00 << 16) | (0xc15c >> 2),
 564         0x00000000,
 565         (0x0e00 << 16) | (0xc168 >> 2),
 566         0x00000000,
 567         (0x0e00 << 16) | (0xc170 >> 2),
 568         0x00000000,
 569         (0x0e00 << 16) | (0xc204 >> 2),
 570         0x00000000,
 571         (0x0e00 << 16) | (0xc2b4 >> 2),
 572         0x00000000,
 573         (0x0e00 << 16) | (0xc2b8 >> 2),
 574         0x00000000,
 575         (0x0e00 << 16) | (0xc2bc >> 2),
 576         0x00000000,
 577         (0x0e00 << 16) | (0xc2c0 >> 2),
 578         0x00000000,
 579         (0x0e00 << 16) | (0x8228 >> 2),
 580         0x00000000,
 581         (0x0e00 << 16) | (0x829c >> 2),
 582         0x00000000,
 583         (0x0e00 << 16) | (0x869c >> 2),
 584         0x00000000,
 585         (0x0600 << 16) | (0x98f4 >> 2),
 586         0x00000000,
 587         (0x0e00 << 16) | (0x98f8 >> 2),
 588         0x00000000,
 589         (0x0e00 << 16) | (0x9900 >> 2),
 590         0x00000000,
 591         (0x0e00 << 16) | (0xc260 >> 2),
 592         0x00000000,
 593         (0x0e00 << 16) | (0x90e8 >> 2),
 594         0x00000000,
 595         (0x0e00 << 16) | (0x3c000 >> 2),
 596         0x00000000,
 597         (0x0e00 << 16) | (0x3c00c >> 2),
 598         0x00000000,
 599         (0x0e00 << 16) | (0x8c1c >> 2),
 600         0x00000000,
 601         (0x0e00 << 16) | (0x9700 >> 2),
 602         0x00000000,
 603         (0x0e00 << 16) | (0xcd20 >> 2),
 604         0x00000000,
 605         (0x4e00 << 16) | (0xcd20 >> 2),
 606         0x00000000,
 607         (0x5e00 << 16) | (0xcd20 >> 2),
 608         0x00000000,
 609         (0x6e00 << 16) | (0xcd20 >> 2),
 610         0x00000000,
 611         (0x7e00 << 16) | (0xcd20 >> 2),
 612         0x00000000,
 613         (0x0e00 << 16) | (0x89bc >> 2),
 614         0x00000000,
 615         (0x0e00 << 16) | (0x8900 >> 2),
 616         0x00000000,
 617         0x3,
 618         (0x0e00 << 16) | (0xc130 >> 2),
 619         0x00000000,
 620         (0x0e00 << 16) | (0xc134 >> 2),
 621         0x00000000,
 622         (0x0e00 << 16) | (0xc1fc >> 2),
 623         0x00000000,
 624         (0x0e00 << 16) | (0xc208 >> 2),
 625         0x00000000,
 626         (0x0e00 << 16) | (0xc264 >> 2),
 627         0x00000000,
 628         (0x0e00 << 16) | (0xc268 >> 2),
 629         0x00000000,
 630         (0x0e00 << 16) | (0xc26c >> 2),
 631         0x00000000,
 632         (0x0e00 << 16) | (0xc270 >> 2),
 633         0x00000000,
 634         (0x0e00 << 16) | (0xc274 >> 2),
 635         0x00000000,
 636         (0x0e00 << 16) | (0xc28c >> 2),
 637         0x00000000,
 638         (0x0e00 << 16) | (0xc290 >> 2),
 639         0x00000000,
 640         (0x0e00 << 16) | (0xc294 >> 2),
 641         0x00000000,
 642         (0x0e00 << 16) | (0xc298 >> 2),
 643         0x00000000,
 644         (0x0e00 << 16) | (0xc2a0 >> 2),
 645         0x00000000,
 646         (0x0e00 << 16) | (0xc2a4 >> 2),
 647         0x00000000,
 648         (0x0e00 << 16) | (0xc2a8 >> 2),
 649         0x00000000,
 650         (0x0e00 << 16) | (0xc2ac >> 2),
 651         0x00000000,
 652         (0x0e00 << 16) | (0x301d0 >> 2),
 653         0x00000000,
 654         (0x0e00 << 16) | (0x30238 >> 2),
 655         0x00000000,
 656         (0x0e00 << 16) | (0x30250 >> 2),
 657         0x00000000,
 658         (0x0e00 << 16) | (0x30254 >> 2),
 659         0x00000000,
 660         (0x0e00 << 16) | (0x30258 >> 2),
 661         0x00000000,
 662         (0x0e00 << 16) | (0x3025c >> 2),
 663         0x00000000,
 664         (0x4e00 << 16) | (0xc900 >> 2),
 665         0x00000000,
 666         (0x5e00 << 16) | (0xc900 >> 2),
 667         0x00000000,
 668         (0x6e00 << 16) | (0xc900 >> 2),
 669         0x00000000,
 670         (0x7e00 << 16) | (0xc900 >> 2),
 671         0x00000000,
 672         (0x4e00 << 16) | (0xc904 >> 2),
 673         0x00000000,
 674         (0x5e00 << 16) | (0xc904 >> 2),
 675         0x00000000,
 676         (0x6e00 << 16) | (0xc904 >> 2),
 677         0x00000000,
 678         (0x7e00 << 16) | (0xc904 >> 2),
 679         0x00000000,
 680         (0x4e00 << 16) | (0xc908 >> 2),
 681         0x00000000,
 682         (0x5e00 << 16) | (0xc908 >> 2),
 683         0x00000000,
 684         (0x6e00 << 16) | (0xc908 >> 2),
 685         0x00000000,
 686         (0x7e00 << 16) | (0xc908 >> 2),
 687         0x00000000,
 688         (0x4e00 << 16) | (0xc90c >> 2),
 689         0x00000000,
 690         (0x5e00 << 16) | (0xc90c >> 2),
 691         0x00000000,
 692         (0x6e00 << 16) | (0xc90c >> 2),
 693         0x00000000,
 694         (0x7e00 << 16) | (0xc90c >> 2),
 695         0x00000000,
 696         (0x4e00 << 16) | (0xc910 >> 2),
 697         0x00000000,
 698         (0x5e00 << 16) | (0xc910 >> 2),
 699         0x00000000,
 700         (0x6e00 << 16) | (0xc910 >> 2),
 701         0x00000000,
 702         (0x7e00 << 16) | (0xc910 >> 2),
 703         0x00000000,
 704         (0x0e00 << 16) | (0xc99c >> 2),
 705         0x00000000,
 706         (0x0e00 << 16) | (0x9834 >> 2),
 707         0x00000000,
 708         (0x0000 << 16) | (0x30f00 >> 2),
 709         0x00000000,
 710         (0x0000 << 16) | (0x30f04 >> 2),
 711         0x00000000,
 712         (0x0000 << 16) | (0x30f08 >> 2),
 713         0x00000000,
 714         (0x0000 << 16) | (0x30f0c >> 2),
 715         0x00000000,
 716         (0x0600 << 16) | (0x9b7c >> 2),
 717         0x00000000,
 718         (0x0e00 << 16) | (0x8a14 >> 2),
 719         0x00000000,
 720         (0x0e00 << 16) | (0x8a18 >> 2),
 721         0x00000000,
 722         (0x0600 << 16) | (0x30a00 >> 2),
 723         0x00000000,
 724         (0x0e00 << 16) | (0x8bf0 >> 2),
 725         0x00000000,
 726         (0x0e00 << 16) | (0x8bcc >> 2),
 727         0x00000000,
 728         (0x0e00 << 16) | (0x8b24 >> 2),
 729         0x00000000,
 730         (0x0e00 << 16) | (0x30a04 >> 2),
 731         0x00000000,
 732         (0x0600 << 16) | (0x30a10 >> 2),
 733         0x00000000,
 734         (0x0600 << 16) | (0x30a14 >> 2),
 735         0x00000000,
 736         (0x0600 << 16) | (0x30a18 >> 2),
 737         0x00000000,
 738         (0x0600 << 16) | (0x30a2c >> 2),
 739         0x00000000,
 740         (0x0e00 << 16) | (0xc700 >> 2),
 741         0x00000000,
 742         (0x0e00 << 16) | (0xc704 >> 2),
 743         0x00000000,
 744         (0x0e00 << 16) | (0xc708 >> 2),
 745         0x00000000,
 746         (0x0e00 << 16) | (0xc768 >> 2),
 747         0x00000000,
 748         (0x0400 << 16) | (0xc770 >> 2),
 749         0x00000000,
 750         (0x0400 << 16) | (0xc774 >> 2),
 751         0x00000000,
 752         (0x0400 << 16) | (0xc798 >> 2),
 753         0x00000000,
 754         (0x0400 << 16) | (0xc79c >> 2),
 755         0x00000000,
 756         (0x0e00 << 16) | (0x9100 >> 2),
 757         0x00000000,
 758         (0x0e00 << 16) | (0x3c010 >> 2),
 759         0x00000000,
 760         (0x0e00 << 16) | (0x8c00 >> 2),
 761         0x00000000,
 762         (0x0e00 << 16) | (0x8c04 >> 2),
 763         0x00000000,
 764         (0x0e00 << 16) | (0x8c20 >> 2),
 765         0x00000000,
 766         (0x0e00 << 16) | (0x8c38 >> 2),
 767         0x00000000,
 768         (0x0e00 << 16) | (0x8c3c >> 2),
 769         0x00000000,
 770         (0x0e00 << 16) | (0xae00 >> 2),
 771         0x00000000,
 772         (0x0e00 << 16) | (0x9604 >> 2),
 773         0x00000000,
 774         (0x0e00 << 16) | (0xac08 >> 2),
 775         0x00000000,
 776         (0x0e00 << 16) | (0xac0c >> 2),
 777         0x00000000,
 778         (0x0e00 << 16) | (0xac10 >> 2),
 779         0x00000000,
 780         (0x0e00 << 16) | (0xac14 >> 2),
 781         0x00000000,
 782         (0x0e00 << 16) | (0xac58 >> 2),
 783         0x00000000,
 784         (0x0e00 << 16) | (0xac68 >> 2),
 785         0x00000000,
 786         (0x0e00 << 16) | (0xac6c >> 2),
 787         0x00000000,
 788         (0x0e00 << 16) | (0xac70 >> 2),
 789         0x00000000,
 790         (0x0e00 << 16) | (0xac74 >> 2),
 791         0x00000000,
 792         (0x0e00 << 16) | (0xac78 >> 2),
 793         0x00000000,
 794         (0x0e00 << 16) | (0xac7c >> 2),
 795         0x00000000,
 796         (0x0e00 << 16) | (0xac80 >> 2),
 797         0x00000000,
 798         (0x0e00 << 16) | (0xac84 >> 2),
 799         0x00000000,
 800         (0x0e00 << 16) | (0xac88 >> 2),
 801         0x00000000,
 802         (0x0e00 << 16) | (0xac8c >> 2),
 803         0x00000000,
 804         (0x0e00 << 16) | (0x970c >> 2),
 805         0x00000000,
 806         (0x0e00 << 16) | (0x9714 >> 2),
 807         0x00000000,
 808         (0x0e00 << 16) | (0x9718 >> 2),
 809         0x00000000,
 810         (0x0e00 << 16) | (0x971c >> 2),
 811         0x00000000,
 812         (0x0e00 << 16) | (0x31068 >> 2),
 813         0x00000000,
 814         (0x4e00 << 16) | (0x31068 >> 2),
 815         0x00000000,
 816         (0x5e00 << 16) | (0x31068 >> 2),
 817         0x00000000,
 818         (0x6e00 << 16) | (0x31068 >> 2),
 819         0x00000000,
 820         (0x7e00 << 16) | (0x31068 >> 2),
 821         0x00000000,
 822         (0x0e00 << 16) | (0xcd10 >> 2),
 823         0x00000000,
 824         (0x0e00 << 16) | (0xcd14 >> 2),
 825         0x00000000,
 826         (0x0e00 << 16) | (0x88b0 >> 2),
 827         0x00000000,
 828         (0x0e00 << 16) | (0x88b4 >> 2),
 829         0x00000000,
 830         (0x0e00 << 16) | (0x88b8 >> 2),
 831         0x00000000,
 832         (0x0e00 << 16) | (0x88bc >> 2),
 833         0x00000000,
 834         (0x0400 << 16) | (0x89c0 >> 2),
 835         0x00000000,
 836         (0x0e00 << 16) | (0x88c4 >> 2),
 837         0x00000000,
 838         (0x0e00 << 16) | (0x88c8 >> 2),
 839         0x00000000,
 840         (0x0e00 << 16) | (0x88d0 >> 2),
 841         0x00000000,
 842         (0x0e00 << 16) | (0x88d4 >> 2),
 843         0x00000000,
 844         (0x0e00 << 16) | (0x88d8 >> 2),
 845         0x00000000,
 846         (0x0e00 << 16) | (0x8980 >> 2),
 847         0x00000000,
 848         (0x0e00 << 16) | (0x30938 >> 2),
 849         0x00000000,
 850         (0x0e00 << 16) | (0x3093c >> 2),
 851         0x00000000,
 852         (0x0e00 << 16) | (0x30940 >> 2),
 853         0x00000000,
 854         (0x0e00 << 16) | (0x89a0 >> 2),
 855         0x00000000,
 856         (0x0e00 << 16) | (0x30900 >> 2),
 857         0x00000000,
 858         (0x0e00 << 16) | (0x30904 >> 2),
 859         0x00000000,
 860         (0x0e00 << 16) | (0x89b4 >> 2),
 861         0x00000000,
 862         (0x0e00 << 16) | (0x3e1fc >> 2),
 863         0x00000000,
 864         (0x0e00 << 16) | (0x3c210 >> 2),
 865         0x00000000,
 866         (0x0e00 << 16) | (0x3c214 >> 2),
 867         0x00000000,
 868         (0x0e00 << 16) | (0x3c218 >> 2),
 869         0x00000000,
 870         (0x0e00 << 16) | (0x8904 >> 2),
 871         0x00000000,
 872         0x5,
 873         (0x0e00 << 16) | (0x8c28 >> 2),
 874         (0x0e00 << 16) | (0x8c2c >> 2),
 875         (0x0e00 << 16) | (0x8c30 >> 2),
 876         (0x0e00 << 16) | (0x8c34 >> 2),
 877         (0x0e00 << 16) | (0x9600 >> 2),
 878 };
 879
 880 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev);
 881 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
 882 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev);
 883 static void gfx_v7_0_init_pg(struct amdgpu_device *adev);
 884 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev);
 885
 886 /*
 887  * Core functions
 888  */
 889 /**
 890  * gfx_v7_0_init_microcode - load ucode images from disk
 891  *
 892  * @adev: amdgpu_device pointer
 893  *
 894  * Use the firmware interface to load the ucode images into
 895  * the driver (not loaded into hw).
 896  * Returns 0 on success, error on failure.
 897  */
 898 static int gfx_v7_0_init_microcode(struct amdgpu_device *adev)
 899 {
 900         const char *chip_name;
 901         char fw_name[30];
 902         int err;
 903
 904         DRM_DEBUG("\n");
 905
 906         switch (adev->asic_type) {
 907         case CHIP_BONAIRE:
 908                 chip_name = "bonaire";
 909                 break;
 910         case CHIP_HAWAII:
 911                 chip_name = "hawaii";
 912                 break;
 913         case CHIP_KAVERI:
 914                 chip_name = "kaveri";
 915                 break;
 916         case CHIP_KABINI:
 917                 chip_name = "kabini";
 918                 break;
 919         case CHIP_MULLINS:
 920                 chip_name = "mullins";
 921                 break;
 922         default: BUG();
 923         }
 924
 925         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
 926         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
 927         if (err)
 928                 goto out;
 929         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
 930         if (err)
 931                 goto out;
 932
 933         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
 934         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
 935         if (err)
 936                 goto out;
 937         err = amdgpu_ucode_validate(adev->gfx.me_fw);
 938         if (err)
 939                 goto out;
 940
 941         snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
 942         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
 943         if (err)
 944                 goto out;
 945         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
 946         if (err)
 947                 goto out;
 948
 949         snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", chip_name);
 950         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
 951         if (err)
 952                 goto out;
 953         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
 954         if (err)
 955                 goto out;
 956
 957         if (adev->asic_type == CHIP_KAVERI) {
 958                 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec2.bin", chip_name);
 959                 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
 960                 if (err)
 961                         goto out;
 962                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
 963                 if (err)
 964                         goto out;
 965         }
 966
 967         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
 968         err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 969         if (err)
 970                 goto out;
 971         err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
 972
 973 out:
 974         if (err) {
 975                 printk(KERN_ERR
 976                        "gfx7: Failed to load firmware \"%s\"\n",
 977                        fw_name);
 978                 release_firmware(adev->gfx.pfp_fw);
 979                 adev->gfx.pfp_fw = NULL;
 980                 release_firmware(adev->gfx.me_fw);
 981                 adev->gfx.me_fw = NULL;
 982                 release_firmware(adev->gfx.ce_fw);
 983                 adev->gfx.ce_fw = NULL;
 984                 release_firmware(adev->gfx.mec_fw);
 985                 adev->gfx.mec_fw = NULL;
 986                 release_firmware(adev->gfx.mec2_fw);
 987                 adev->gfx.mec2_fw = NULL;
 988                 release_firmware(adev->gfx.rlc_fw);
 989                 adev->gfx.rlc_fw = NULL;
 990         }
 991         return err;
 992 }
 993
 994 /**
 995  * gfx_v7_0_tiling_mode_table_init - init the hw tiling table
 996  *
 997  * @adev: amdgpu_device pointer
 998  *
 999  * Starting with SI, the tiling setup is done globally in a
1000  * set of 32 tiling modes.  Rather than selecting each set of
1001  * parameters per surface as on older asics, we just select
1002  * which index in the tiling table we want to use, and the
1003  * surface uses those parameters (CIK).
1004  */
1005 static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev)
1006 {
1007         const u32 num_tile_mode_states =
1008                         ARRAY_SIZE(adev->gfx.config.tile_mode_array);
1009         const u32 num_secondary_tile_mode_states =
1010                         ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
1011         u32 reg_offset, split_equal_to_row_size;
1012         uint32_t *tile, *macrotile;
1013
1014         tile = adev->gfx.config.tile_mode_array;
1015         macrotile = adev->gfx.config.macrotile_mode_array;
1016
1017         switch (adev->gfx.config.mem_row_size_in_kb) {
1018         case 1:
1019                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
1020                 break;
1021         case 2:
1022         default:
1023                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
1024                 break;
1025         case 4:
1026                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
1027                 break;
1028         }
1029
1030         for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1031                 tile[reg_offset] = 0;
1032         for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1033                 macrotile[reg_offset] = 0;
1034
1035         switch (adev->asic_type) {
1036         case CHIP_BONAIRE:
1037                 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1038                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1039                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1040                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1041                 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1042                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1043                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1044                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1045                 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1046                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1047                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1048                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1049                 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1050                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1051                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1052                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1053                 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1054                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1055                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1056                            TILE_SPLIT(split_equal_to_row_size));
1057                 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1058                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1059                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1060                 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1061                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1062                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1063                            TILE_SPLIT(split_equal_to_row_size));
1064                 tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1065                 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1066                            PIPE_CONFIG(ADDR_SURF_P4_16x16));
1067                 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1068                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1069                            MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1070                 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1071                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1072                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1073                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1074                 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1075                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1076                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1077                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1078                 tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1079                 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1080                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1081                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1082                 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1083                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1084                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1085                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1086                 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1087                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1088                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1089                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1090                 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1091                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1092                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1093                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1094                 tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1095                 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1096                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1097                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1098                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1099                 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1100                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1101                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1102                 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1103                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1104                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1105                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1106                 tile[21] =  (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1107                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1108                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1109                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1110                 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1111                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1112                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1113                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1114                 tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1115                 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1116                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1117                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1118                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1119                 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1120                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1121                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1122                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1123                 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1124                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1125                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1126                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1127                 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1128                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1129                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1130                 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1131                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1132                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1133                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1134                 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1135                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1136                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1137                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1138                 tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1139
1140                 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1141                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1142                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1143                                 NUM_BANKS(ADDR_SURF_16_BANK));
1144                 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1145                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1146                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1147                                 NUM_BANKS(ADDR_SURF_16_BANK));
1148                 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1149                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1150                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1151                                 NUM_BANKS(ADDR_SURF_16_BANK));
1152                 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1153                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1154                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1155                                 NUM_BANKS(ADDR_SURF_16_BANK));
1156                 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1157                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1158                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1159                                 NUM_BANKS(ADDR_SURF_16_BANK));
1160                 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1161                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1162                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1163                                 NUM_BANKS(ADDR_SURF_8_BANK));
1164                 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1165                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1166                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1167                                 NUM_BANKS(ADDR_SURF_4_BANK));
1168                 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1169                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1170                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1171                                 NUM_BANKS(ADDR_SURF_16_BANK));
1172                 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1173                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1174                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1175                                 NUM_BANKS(ADDR_SURF_16_BANK));
1176                 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1177                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1178                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1179                                 NUM_BANKS(ADDR_SURF_16_BANK));
1180                 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1181                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1182                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1183                                 NUM_BANKS(ADDR_SURF_16_BANK));
1184                 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1185                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1186                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1187                                 NUM_BANKS(ADDR_SURF_16_BANK));
1188                 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1189                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1190                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1191                                 NUM_BANKS(ADDR_SURF_8_BANK));
1192                 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1193                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1194                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1195                                 NUM_BANKS(ADDR_SURF_4_BANK));
1196
1197                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1198                         WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1199                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1200                         if (reg_offset != 7)
1201                                 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1202                 break;
1203         case CHIP_HAWAII:
1204                 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1205                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1206                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1207                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1208                 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1209                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1210                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1211                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1212                 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1213                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1214                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1215                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1216                 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1217                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1218                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1219                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1220                 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1221                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1222                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1223                            TILE_SPLIT(split_equal_to_row_size));
1224                 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1225                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1226                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1227                            TILE_SPLIT(split_equal_to_row_size));
1228                 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1229                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1230                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1231                            TILE_SPLIT(split_equal_to_row_size));
1232                 tile[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1233                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1234                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1235                            TILE_SPLIT(split_equal_to_row_size));
1236                 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1237                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
1238                 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1239                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1240                            MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1241                 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1242                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1243                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1244                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1245                 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1246                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1247                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1248                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1249                 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
1250                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1251                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1252                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1253                 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1254                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1255                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1256                 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1257                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1258                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1259                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1260                 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1261                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1262                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1263                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1264                 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1265                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1266                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1267                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1268                 tile[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1269                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1270                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1271                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1272                 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1273                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1274                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1275                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1276                 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1277                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1278                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1279                 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1280                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1281                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1282                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1283                 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1284                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1285                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1286                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1287                 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1288                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1289                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1290                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1291                 tile[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1292                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1293                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1294                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1295                 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1296                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1297                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1298                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1299                 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1300                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1301                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1302                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1303                 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1304                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1305                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1306                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1307                 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1308                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1309                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1310                 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1311                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1312                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1313                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1314                 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1315                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1316                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1317                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1318                 tile[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1319                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1320                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1321                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1322
1323                 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1324                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1325                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1326                                 NUM_BANKS(ADDR_SURF_16_BANK));
1327                 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1328                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1329                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1330                                 NUM_BANKS(ADDR_SURF_16_BANK));
1331                 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1332                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1333                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1334                                 NUM_BANKS(ADDR_SURF_16_BANK));
1335                 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1336                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1337                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1338                                 NUM_BANKS(ADDR_SURF_16_BANK));
1339                 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1340                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1341                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1342                                 NUM_BANKS(ADDR_SURF_8_BANK));
1343                 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1344                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1345                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1346                                 NUM_BANKS(ADDR_SURF_4_BANK));
1347                 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1348                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1349                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1350                                 NUM_BANKS(ADDR_SURF_4_BANK));
1351                 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1352                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1353                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1354                                 NUM_BANKS(ADDR_SURF_16_BANK));
1355                 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1356                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1357                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1358                                 NUM_BANKS(ADDR_SURF_16_BANK));
1359                 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1360                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1361                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1362                                 NUM_BANKS(ADDR_SURF_16_BANK));
1363                 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1364                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1365                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1366                                 NUM_BANKS(ADDR_SURF_8_BANK));
1367                 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1368                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1369                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1370                                 NUM_BANKS(ADDR_SURF_16_BANK));
1371                 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1372                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1373                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1374                                 NUM_BANKS(ADDR_SURF_8_BANK));
1375                 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1376                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1377                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1378                                 NUM_BANKS(ADDR_SURF_4_BANK));
1379
1380                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1381                         WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1382                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1383                         if (reg_offset != 7)
1384                                 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1385                 break;
1386         case CHIP_KABINI:
1387         case CHIP_KAVERI:
1388         case CHIP_MULLINS:
1389         default:
1390                 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1391                            PIPE_CONFIG(ADDR_SURF_P2) |
1392                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1393                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1394                 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1395                            PIPE_CONFIG(ADDR_SURF_P2) |
1396                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1397                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1398                 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1399                            PIPE_CONFIG(ADDR_SURF_P2) |
1400                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1401                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1402                 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1403                            PIPE_CONFIG(ADDR_SURF_P2) |
1404                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1405                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1406                 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1407                            PIPE_CONFIG(ADDR_SURF_P2) |
1408                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1409                            TILE_SPLIT(split_equal_to_row_size));
1410                 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1411                            PIPE_CONFIG(ADDR_SURF_P2) |
1412                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1413                 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1414                            PIPE_CONFIG(ADDR_SURF_P2) |
1415                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1416                            TILE_SPLIT(split_equal_to_row_size));
1417                 tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1418                 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1419                            PIPE_CONFIG(ADDR_SURF_P2));
1420                 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1421                            PIPE_CONFIG(ADDR_SURF_P2) |
1422                            MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1423                 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1424                             PIPE_CONFIG(ADDR_SURF_P2) |
1425                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1426                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1427                 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1428                             PIPE_CONFIG(ADDR_SURF_P2) |
1429                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1430                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1431                 tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1432                 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1433                             PIPE_CONFIG(ADDR_SURF_P2) |
1434                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1435                 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1436                             PIPE_CONFIG(ADDR_SURF_P2) |
1437                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1438                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1439                 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1440                             PIPE_CONFIG(ADDR_SURF_P2) |
1441                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1442                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1443                 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1444                             PIPE_CONFIG(ADDR_SURF_P2) |
1445                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1446                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1447                 tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1448                 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1449                             PIPE_CONFIG(ADDR_SURF_P2) |
1450                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1451                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1452                 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1453                             PIPE_CONFIG(ADDR_SURF_P2) |
1454                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1455                 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1456                             PIPE_CONFIG(ADDR_SURF_P2) |
1457                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1458                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1459                 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1460                             PIPE_CONFIG(ADDR_SURF_P2) |
1461                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1462                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1463                 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1464                             PIPE_CONFIG(ADDR_SURF_P2) |
1465                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1466                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1467                 tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1468                 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1469                             PIPE_CONFIG(ADDR_SURF_P2) |
1470                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1471                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1472                 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1473                             PIPE_CONFIG(ADDR_SURF_P2) |
1474                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1475                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1476                 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1477                             PIPE_CONFIG(ADDR_SURF_P2) |
1478                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1479                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1480                 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1481                             PIPE_CONFIG(ADDR_SURF_P2) |
1482                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1483                 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1484                             PIPE_CONFIG(ADDR_SURF_P2) |
1485                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1486                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1487                 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1488                             PIPE_CONFIG(ADDR_SURF_P2) |
1489                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1490                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1491                 tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1492
1493                 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1494                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1495                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1496                                 NUM_BANKS(ADDR_SURF_8_BANK));
1497                 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1498                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1499                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1500                                 NUM_BANKS(ADDR_SURF_8_BANK));
1501                 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1502                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1503                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1504                                 NUM_BANKS(ADDR_SURF_8_BANK));
1505                 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1506                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1507                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1508                                 NUM_BANKS(ADDR_SURF_8_BANK));
1509                 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1510                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1511                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1512                                 NUM_BANKS(ADDR_SURF_8_BANK));
1513                 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1514                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1515                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1516                                 NUM_BANKS(ADDR_SURF_8_BANK));
1517                 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1518                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1519                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1520                                 NUM_BANKS(ADDR_SURF_8_BANK));
1521                 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1522                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1523                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1524                                 NUM_BANKS(ADDR_SURF_16_BANK));
1525                 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1526                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1527                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1528                                 NUM_BANKS(ADDR_SURF_16_BANK));
1529                 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1530                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1531                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1532                                 NUM_BANKS(ADDR_SURF_16_BANK));
1533                 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1534                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1535                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1536                                 NUM_BANKS(ADDR_SURF_16_BANK));
1537                 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1538                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1539                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1540                                 NUM_BANKS(ADDR_SURF_16_BANK));
1541                 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1542                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1543                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1544                                 NUM_BANKS(ADDR_SURF_16_BANK));
1545                 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1546                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1547                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1548                                 NUM_BANKS(ADDR_SURF_8_BANK));
1549
1550                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1551                         WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1552                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1553                         if (reg_offset != 7)
1554                                 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1555                 break;
1556         }
1557 }
1558
1559 /**
1560  * gfx_v7_0_select_se_sh - select which SE, SH to address
1561  *
1562  * @adev: amdgpu_device pointer
1563  * @se_num: shader engine to address
1564  * @sh_num: sh block to address
1565  *
1566  * Select which SE, SH combinations to address. Certain
1567  * registers are instanced per SE or SH.  0xffffffff means
1568  * broadcast to all SEs or SHs (CIK).
1569  */
1570 void gfx_v7_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num)
1571 {
1572         u32 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK;
1573
1574         if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1575                 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1576                         GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
1577         else if (se_num == 0xffffffff)
1578                 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1579                         (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
1580         else if (sh_num == 0xffffffff)
1581                 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1582                         (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1583         else
1584                 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1585                         (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1586         WREG32(mmGRBM_GFX_INDEX, data);
1587 }
1588
1589 /**
1590  * gfx_v7_0_create_bitmask - create a bitmask
1591  *
1592  * @bit_width: length of the mask
1593  *
1594  * create a variable length bit mask (CIK).
1595  * Returns the bitmask.
1596  */
1597 static u32 gfx_v7_0_create_bitmask(u32 bit_width)
1598 {
1599         return (u32)((1ULL << bit_width) - 1);
1600 }
1601
1602 /**
1603  * gfx_v7_0_get_rb_active_bitmap - computes the mask of enabled RBs
1604  *
1605  * @adev: amdgpu_device pointer
1606  *
1607  * Calculates the bitmask of enabled RBs (CIK).
1608  * Returns the enabled RB bitmask.
1609  */
1610 static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1611 {
1612         u32 data, mask;
1613
1614         data = RREG32(mmCC_RB_BACKEND_DISABLE);
1615         data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1616
1617         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1618         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1619
1620         mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_backends_per_se /
1621                                        adev->gfx.config.max_sh_per_se);
1622
1623         return (~data) & mask;
1624 }
1625
1626 /**
1627  * gfx_v7_0_setup_rb - setup the RBs on the asic
1628  *
1629  * @adev: amdgpu_device pointer
1630  * @se_num: number of SEs (shader engines) for the asic
1631  * @sh_per_se: number of SH blocks per SE for the asic
1632  *
1633  * Configures per-SE/SH RB registers (CIK).
1634  */
1635 static void gfx_v7_0_setup_rb(struct amdgpu_device *adev)
1636 {
1637         int i, j;
1638         u32 data;
1639         u32 active_rbs = 0;
1640         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1641                                         adev->gfx.config.max_sh_per_se;
1642
1643         mutex_lock(&adev->grbm_idx_mutex);
1644         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1645                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1646                         gfx_v7_0_select_se_sh(adev, i, j);
1647                         data = gfx_v7_0_get_rb_active_bitmap(adev);
1648                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1649                                                rb_bitmap_width_per_sh);
1650                 }
1651         }
1652         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
1653         mutex_unlock(&adev->grbm_idx_mutex);
1654
1655         adev->gfx.config.backend_enable_mask = active_rbs;
1656         adev->gfx.config.num_rbs = hweight32(active_rbs);
1657 }
1658
1659 /**
1660  * gmc_v7_0_init_compute_vmid - gart enable
1661  *
1662  * @rdev: amdgpu_device pointer
1663  *
1664  * Initialize compute vmid sh_mem registers
1665  *
1666  */
1667 #define DEFAULT_SH_MEM_BASES    (0x6000)
1668 #define FIRST_COMPUTE_VMID      (8)
1669 #define LAST_COMPUTE_VMID       (16)
1670 static void gmc_v7_0_init_compute_vmid(struct amdgpu_device *adev)
1671 {
1672         int i;
1673         uint32_t sh_mem_config;
1674         uint32_t sh_mem_bases;
1675
1676         /*
1677          * Configure apertures:
1678          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
1679          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
1680          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
1681         */
1682         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1683         sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1684                         SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1685         sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT;
1686         mutex_lock(&adev->srbm_mutex);
1687         for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1688                 cik_srbm_select(adev, 0, 0, 0, i);
1689                 /* CP and shaders */
1690                 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
1691                 WREG32(mmSH_MEM_APE1_BASE, 1);
1692                 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1693                 WREG32(mmSH_MEM_BASES, sh_mem_bases);
1694         }
1695         cik_srbm_select(adev, 0, 0, 0, 0);
1696         mutex_unlock(&adev->srbm_mutex);
1697 }
1698
1699 /**
1700  * gfx_v7_0_gpu_init - setup the 3D engine
1701  *
1702  * @adev: amdgpu_device pointer
1703  *
1704  * Configures the 3D engine and tiling configuration
1705  * registers so that the 3D engine is usable.
1706  */
1707 static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
1708 {
1709         u32 tmp, sh_mem_cfg;
1710         int i;
1711
1712         WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
1713
1714         WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1715         WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1716         WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
1717
1718         gfx_v7_0_tiling_mode_table_init(adev);
1719
1720         gfx_v7_0_setup_rb(adev);
1721         gfx_v7_0_get_cu_info(adev);
1722
1723         /* set HW defaults for 3D engine */
1724         WREG32(mmCP_MEQ_THRESHOLDS,
1725                (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
1726                (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
1727
1728         mutex_lock(&adev->grbm_idx_mutex);
1729         /*
1730          * making sure that the following register writes will be broadcasted
1731          * to all the shaders
1732          */
1733         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
1734
1735         /* XXX SH_MEM regs */
1736         /* where to put LDS, scratch, GPUVM in FSA64 space */
1737         sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1738                                    SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1739
1740         mutex_lock(&adev->srbm_mutex);
1741         for (i = 0; i < 16; i++) {
1742                 cik_srbm_select(adev, 0, 0, 0, i);
1743                 /* CP and shaders */
1744                 WREG32(mmSH_MEM_CONFIG, sh_mem_cfg);
1745                 WREG32(mmSH_MEM_APE1_BASE, 1);
1746                 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1747                 WREG32(mmSH_MEM_BASES, 0);
1748         }
1749         cik_srbm_select(adev, 0, 0, 0, 0);
1750         mutex_unlock(&adev->srbm_mutex);
1751
1752         gmc_v7_0_init_compute_vmid(adev);
1753
1754         WREG32(mmSX_DEBUG_1, 0x20);
1755
1756         WREG32(mmTA_CNTL_AUX, 0x00010000);
1757
1758         tmp = RREG32(mmSPI_CONFIG_CNTL);
1759         tmp |= 0x03000000;
1760         WREG32(mmSPI_CONFIG_CNTL, tmp);
1761
1762         WREG32(mmSQ_CONFIG, 1);
1763
1764         WREG32(mmDB_DEBUG, 0);
1765
1766         tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff;
1767         tmp |= 0x00000400;
1768         WREG32(mmDB_DEBUG2, tmp);
1769
1770         tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c;
1771         tmp |= 0x00020200;
1772         WREG32(mmDB_DEBUG3, tmp);
1773
1774         tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000;
1775         tmp |= 0x00018208;
1776         WREG32(mmCB_HW_CONTROL, tmp);
1777
1778         WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
1779
1780         WREG32(mmPA_SC_FIFO_SIZE,
1781                 ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1782                 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1783                 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1784                 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
1785
1786         WREG32(mmVGT_NUM_INSTANCES, 1);
1787
1788         WREG32(mmCP_PERFMON_CNTL, 0);
1789
1790         WREG32(mmSQ_CONFIG, 0);
1791
1792         WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS,
1793                 ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
1794                 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
1795
1796         WREG32(mmVGT_CACHE_INVALIDATION,
1797                 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
1798                 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
1799
1800         WREG32(mmVGT_GS_VERTEX_REUSE, 16);
1801         WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
1802
1803         WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
1804                         (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
1805         WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK);
1806         mutex_unlock(&adev->grbm_idx_mutex);
1807
1808         udelay(50);
1809 }
1810
1811 /*
1812  * GPU scratch registers helpers function.
1813  */
1814 /**
1815  * gfx_v7_0_scratch_init - setup driver info for CP scratch regs
1816  *
1817  * @adev: amdgpu_device pointer
1818  *
1819  * Set up the number and offset of the CP scratch registers.
1820  * NOTE: use of CP scratch registers is a legacy inferface and
1821  * is not used by default on newer asics (r6xx+).  On newer asics,
1822  * memory buffers are used for fences rather than scratch regs.
1823  */
1824 static void gfx_v7_0_scratch_init(struct amdgpu_device *adev)
1825 {
1826         int i;
1827
1828         adev->gfx.scratch.num_reg = 7;
1829         adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
1830         for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
1831                 adev->gfx.scratch.free[i] = true;
1832                 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
1833         }
1834 }
1835
1836 /**
1837  * gfx_v7_0_ring_test_ring - basic gfx ring test
1838  *
1839  * @adev: amdgpu_device pointer
1840  * @ring: amdgpu_ring structure holding ring information
1841  *
1842  * Allocate a scratch register and write to it using the gfx ring (CIK).
1843  * Provides a basic gfx ring test to verify that the ring is working.
1844  * Used by gfx_v7_0_cp_gfx_resume();
1845  * Returns 0 on success, error on failure.
1846  */
1847 static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring)
1848 {
1849         struct amdgpu_device *adev = ring->adev;
1850         uint32_t scratch;
1851         uint32_t tmp = 0;
1852         unsigned i;
1853         int r;
1854
1855         r = amdgpu_gfx_scratch_get(adev, &scratch);
1856         if (r) {
1857                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
1858                 return r;
1859         }
1860         WREG32(scratch, 0xCAFEDEAD);
1861         r = amdgpu_ring_alloc(ring, 3);
1862         if (r) {
1863                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r);
1864                 amdgpu_gfx_scratch_free(adev, scratch);
1865                 return r;
1866         }
1867         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
1868         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
1869         amdgpu_ring_write(ring, 0xDEADBEEF);
1870         amdgpu_ring_commit(ring);
1871
1872         for (i = 0; i < adev->usec_timeout; i++) {
1873                 tmp = RREG32(scratch);
1874                 if (tmp == 0xDEADBEEF)
1875                         break;
1876                 DRM_UDELAY(1);
1877         }
1878         if (i < adev->usec_timeout) {
1879                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
1880         } else {
1881                 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
1882                           ring->idx, scratch, tmp);
1883                 r = -EINVAL;
1884         }
1885         amdgpu_gfx_scratch_free(adev, scratch);
1886         return r;
1887 }
1888
1889 /**
1890  * gfx_v7_0_ring_emit_hdp - emit an hdp flush on the cp
1891  *
1892  * @adev: amdgpu_device pointer
1893  * @ridx: amdgpu ring index
1894  *
1895  * Emits an hdp flush on the cp.
1896  */
1897 static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
1898 {
1899         u32 ref_and_mask;
1900         int usepfp = ring->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1;
1901
1902         if (ring->type == AMDGPU_RING_TYPE_COMPUTE) {
1903                 switch (ring->me) {
1904                 case 1:
1905                         ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
1906                         break;
1907                 case 2:
1908                         ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
1909                         break;
1910                 default:
1911                         return;
1912                 }
1913         } else {
1914                 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
1915         }
1916
1917         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
1918         amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
1919                                  WAIT_REG_MEM_FUNCTION(3) |  /* == */
1920                                  WAIT_REG_MEM_ENGINE(usepfp)));   /* pfp or me */
1921         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
1922         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
1923         amdgpu_ring_write(ring, ref_and_mask);
1924         amdgpu_ring_write(ring, ref_and_mask);
1925         amdgpu_ring_write(ring, 0x20); /* poll interval */
1926 }
1927
1928 /**
1929  * gfx_v7_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp
1930  *
1931  * @adev: amdgpu_device pointer
1932  * @ridx: amdgpu ring index
1933  *
1934  * Emits an hdp invalidate on the cp.
1935  */
1936 static void gfx_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
1937 {
1938         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1939         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
1940                                  WRITE_DATA_DST_SEL(0) |
1941                                  WR_CONFIRM));
1942         amdgpu_ring_write(ring, mmHDP_DEBUG0);
1943         amdgpu_ring_write(ring, 0);
1944         amdgpu_ring_write(ring, 1);
1945 }
1946
1947 /**
1948  * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring
1949  *
1950  * @adev: amdgpu_device pointer
1951  * @fence: amdgpu fence object
1952  *
1953  * Emits a fence sequnce number on the gfx ring and flushes
1954  * GPU caches.
1955  */
1956 static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
1957                                          u64 seq, unsigned flags)
1958 {
1959         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
1960         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
1961         /* Workaround for cache flush problems. First send a dummy EOP
1962          * event down the pipe with seq one below.
1963          */
1964         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1965         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
1966                                  EOP_TC_ACTION_EN |
1967                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
1968                                  EVENT_INDEX(5)));
1969         amdgpu_ring_write(ring, addr & 0xfffffffc);
1970         amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
1971                                 DATA_SEL(1) | INT_SEL(0));
1972         amdgpu_ring_write(ring, lower_32_bits(seq - 1));
1973         amdgpu_ring_write(ring, upper_32_bits(seq - 1));
1974
1975         /* Then send the real EOP event down the pipe. */
1976         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1977         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
1978                                  EOP_TC_ACTION_EN |
1979                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
1980                                  EVENT_INDEX(5)));
1981         amdgpu_ring_write(ring, addr & 0xfffffffc);
1982         amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
1983                                 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
1984         amdgpu_ring_write(ring, lower_32_bits(seq));
1985         amdgpu_ring_write(ring, upper_32_bits(seq));
1986 }
1987
1988 /**
1989  * gfx_v7_0_ring_emit_fence_compute - emit a fence on the compute ring
1990  *
1991  * @adev: amdgpu_device pointer
1992  * @fence: amdgpu fence object
1993  *
1994  * Emits a fence sequnce number on the compute ring and flushes
1995  * GPU caches.
1996  */
1997 static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
1998                                              u64 addr, u64 seq,
1999                                              unsigned flags)
2000 {
2001         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2002         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2003
2004         /* RELEASE_MEM - flush caches, send int */
2005         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
2006         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2007                                  EOP_TC_ACTION_EN |
2008                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2009                                  EVENT_INDEX(5)));
2010         amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2011         amdgpu_ring_write(ring, addr & 0xfffffffc);
2012         amdgpu_ring_write(ring, upper_32_bits(addr));
2013         amdgpu_ring_write(ring, lower_32_bits(seq));
2014         amdgpu_ring_write(ring, upper_32_bits(seq));
2015 }
2016
2017 /*
2018  * IB stuff
2019  */
2020 /**
2021  * gfx_v7_0_ring_emit_ib - emit an IB (Indirect Buffer) on the ring
2022  *
2023  * @ring: amdgpu_ring structure holding ring information
2024  * @ib: amdgpu indirect buffer object
2025  *
2026  * Emits an DE (drawing engine) or CE (constant engine) IB
2027  * on the gfx ring.  IBs are usually generated by userspace
2028  * acceleration drivers and submitted to the kernel for
2029  * sheduling on the ring.  This function schedules the IB
2030  * on the gfx ring for execution by the GPU.
2031  */
2032 static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
2033                                       struct amdgpu_ib *ib,
2034                                       unsigned vm_id, bool ctx_switch)
2035 {
2036         u32 header, control = 0;
2037         u32 next_rptr = ring->wptr + 5;
2038
2039         if (ctx_switch)
2040                 next_rptr += 2;
2041
2042         next_rptr += 4;
2043         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2044         amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
2045         amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
2046         amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
2047         amdgpu_ring_write(ring, next_rptr);
2048
2049         /* insert SWITCH_BUFFER packet before first IB in the ring frame */
2050         if (ctx_switch) {
2051                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2052                 amdgpu_ring_write(ring, 0);
2053         }
2054
2055         if (ib->flags & AMDGPU_IB_FLAG_CE)
2056                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
2057         else
2058                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2059
2060         control |= ib->length_dw | (vm_id << 24);
2061
2062         amdgpu_ring_write(ring, header);
2063         amdgpu_ring_write(ring,
2064 #ifdef __BIG_ENDIAN
2065                           (2 << 0) |
2066 #endif
2067                           (ib->gpu_addr & 0xFFFFFFFC));
2068         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2069         amdgpu_ring_write(ring, control);
2070 }
2071
2072 static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
2073                                           struct amdgpu_ib *ib,
2074                                           unsigned vm_id, bool ctx_switch)
2075 {
2076         u32 header, control = 0;
2077         u32 next_rptr = ring->wptr + 5;
2078
2079         control |= INDIRECT_BUFFER_VALID;
2080         next_rptr += 4;
2081         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2082         amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
2083         amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
2084         amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
2085         amdgpu_ring_write(ring, next_rptr);
2086
2087         header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2088
2089         control |= ib->length_dw | (vm_id << 24);
2090
2091         amdgpu_ring_write(ring, header);
2092         amdgpu_ring_write(ring,
2093 #ifdef __BIG_ENDIAN
2094                                           (2 << 0) |
2095 #endif
2096                                           (ib->gpu_addr & 0xFFFFFFFC));
2097         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2098         amdgpu_ring_write(ring, control);
2099 }
2100
2101 /**
2102  * gfx_v7_0_ring_test_ib - basic ring IB test
2103  *
2104  * @ring: amdgpu_ring structure holding ring information
2105  *
2106  * Allocate an IB and execute it on the gfx ring (CIK).
2107  * Provides a basic gfx ring test to verify that IBs are working.
2108  * Returns 0 on success, error on failure.
2109  */
2110 static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring)
2111 {
2112         struct amdgpu_device *adev = ring->adev;
2113         struct amdgpu_ib ib;
2114         struct fence *f = NULL;
2115         uint32_t scratch;
2116         uint32_t tmp = 0;
2117         unsigned i;
2118         int r;
2119
2120         r = amdgpu_gfx_scratch_get(adev, &scratch);
2121         if (r) {
2122                 DRM_ERROR("amdgpu: failed to get scratch reg (%d).\n", r);
2123                 return r;
2124         }
2125         WREG32(scratch, 0xCAFEDEAD);
2126         memset(&ib, 0, sizeof(ib));
2127         r = amdgpu_ib_get(adev, NULL, 256, &ib);
2128         if (r) {
2129                 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
2130                 goto err1;
2131         }
2132         ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
2133         ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
2134         ib.ptr[2] = 0xDEADBEEF;
2135         ib.length_dw = 3;
2136
2137         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
2138         if (r)
2139                 goto err2;
2140
2141         r = fence_wait(f, false);
2142         if (r) {
2143                 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
2144                 goto err2;
2145         }
2146         for (i = 0; i < adev->usec_timeout; i++) {
2147                 tmp = RREG32(scratch);
2148                 if (tmp == 0xDEADBEEF)
2149                         break;
2150                 DRM_UDELAY(1);
2151         }
2152         if (i < adev->usec_timeout) {
2153                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
2154                          ring->idx, i);
2155                 goto err2;
2156         } else {
2157                 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
2158                           scratch, tmp);
2159                 r = -EINVAL;
2160         }
2161
2162 err2:
2163         fence_put(f);
2164         amdgpu_ib_free(adev, &ib, NULL);
2165         fence_put(f);
2166 err1:
2167         amdgpu_gfx_scratch_free(adev, scratch);
2168         return r;
2169 }
2170
2171 /*
2172  * CP.
2173  * On CIK, gfx and compute now have independant command processors.
2174  *
2175  * GFX
2176  * Gfx consists of a single ring and can process both gfx jobs and
2177  * compute jobs.  The gfx CP consists of three microengines (ME):
2178  * PFP - Pre-Fetch Parser
2179  * ME - Micro Engine
2180  * CE - Constant Engine
2181  * The PFP and ME make up what is considered the Drawing Engine (DE).
2182  * The CE is an asynchronous engine used for updating buffer desciptors
2183  * used by the DE so that they can be loaded into cache in parallel
2184  * while the DE is processing state update packets.
2185  *
2186  * Compute
2187  * The compute CP consists of two microengines (ME):
2188  * MEC1 - Compute MicroEngine 1
2189  * MEC2 - Compute MicroEngine 2
2190  * Each MEC supports 4 compute pipes and each pipe supports 8 queues.
2191  * The queues are exposed to userspace and are programmed directly
2192  * by the compute runtime.
2193  */
2194 /**
2195  * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs
2196  *
2197  * @adev: amdgpu_device pointer
2198  * @enable: enable or disable the MEs
2199  *
2200  * Halts or unhalts the gfx MEs.
2201  */
2202 static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2203 {
2204         int i;
2205
2206         if (enable) {
2207                 WREG32(mmCP_ME_CNTL, 0);
2208         } else {
2209                 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK));
2210                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2211                         adev->gfx.gfx_ring[i].ready = false;
2212         }
2213         udelay(50);
2214 }
2215
2216 /**
2217  * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode
2218  *
2219  * @adev: amdgpu_device pointer
2220  *
2221  * Loads the gfx PFP, ME, and CE ucode.
2222  * Returns 0 for success, -EINVAL if the ucode is not available.
2223  */
2224 static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2225 {
2226         const struct gfx_firmware_header_v1_0 *pfp_hdr;
2227         const struct gfx_firmware_header_v1_0 *ce_hdr;
2228         const struct gfx_firmware_header_v1_0 *me_hdr;
2229         const __le32 *fw_data;
2230         unsigned i, fw_size;
2231
2232         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2233                 return -EINVAL;
2234
2235         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2236         ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2237         me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2238
2239         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2240         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2241         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2242         adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version);
2243         adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version);
2244         adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version);
2245         adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version);
2246         adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version);
2247         adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version);
2248
2249         gfx_v7_0_cp_gfx_enable(adev, false);
2250
2251         /* PFP */
2252         fw_data = (const __le32 *)
2253                 (adev->gfx.pfp_fw->data +
2254                  le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2255         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2256         WREG32(mmCP_PFP_UCODE_ADDR, 0);
2257         for (i = 0; i < fw_size; i++)
2258                 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2259         WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2260
2261         /* CE */
2262         fw_data = (const __le32 *)
2263                 (adev->gfx.ce_fw->data +
2264                  le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2265         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2266         WREG32(mmCP_CE_UCODE_ADDR, 0);
2267         for (i = 0; i < fw_size; i++)
2268                 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2269         WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2270
2271         /* ME */
2272         fw_data = (const __le32 *)
2273                 (adev->gfx.me_fw->data +
2274                  le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2275         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2276         WREG32(mmCP_ME_RAM_WADDR, 0);
2277         for (i = 0; i < fw_size; i++)
2278                 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2279         WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2280
2281         return 0;
2282 }
2283
2284 /**
2285  * gfx_v7_0_cp_gfx_start - start the gfx ring
2286  *
2287  * @adev: amdgpu_device pointer
2288  *
2289  * Enables the ring and loads the clear state context and other
2290  * packets required to init the ring.
2291  * Returns 0 for success, error for failure.
2292  */
2293 static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev)
2294 {
2295         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2296         const struct cs_section_def *sect = NULL;
2297         const struct cs_extent_def *ext = NULL;
2298         int r, i;
2299
2300         /* init the CP */
2301         WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2302         WREG32(mmCP_ENDIAN_SWAP, 0);
2303         WREG32(mmCP_DEVICE_ID, 1);
2304
2305         gfx_v7_0_cp_gfx_enable(adev, true);
2306
2307         r = amdgpu_ring_alloc(ring, gfx_v7_0_get_csb_size(adev) + 8);
2308         if (r) {
2309                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2310                 return r;
2311         }
2312
2313         /* init the CE partitions.  CE only used for gfx on CIK */
2314         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2315         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2316         amdgpu_ring_write(ring, 0x8000);
2317         amdgpu_ring_write(ring, 0x8000);
2318
2319         /* clear state buffer */
2320         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2321         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2322
2323         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2324         amdgpu_ring_write(ring, 0x80000000);
2325         amdgpu_ring_write(ring, 0x80000000);
2326
2327         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2328                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2329                         if (sect->id == SECT_CONTEXT) {
2330                                 amdgpu_ring_write(ring,
2331                                                   PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2332                                 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2333                                 for (i = 0; i < ext->reg_count; i++)
2334                                         amdgpu_ring_write(ring, ext->extent[i]);
2335                         }
2336                 }
2337         }
2338
2339         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2340         amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2341         switch (adev->asic_type) {
2342         case CHIP_BONAIRE:
2343                 amdgpu_ring_write(ring, 0x16000012);
2344                 amdgpu_ring_write(ring, 0x00000000);
2345                 break;
2346         case CHIP_KAVERI:
2347                 amdgpu_ring_write(ring, 0x00000000); /* XXX */
2348                 amdgpu_ring_write(ring, 0x00000000);
2349                 break;
2350         case CHIP_KABINI:
2351         case CHIP_MULLINS:
2352                 amdgpu_ring_write(ring, 0x00000000); /* XXX */
2353                 amdgpu_ring_write(ring, 0x00000000);
2354                 break;
2355         case CHIP_HAWAII:
2356                 amdgpu_ring_write(ring, 0x3a00161a);
2357                 amdgpu_ring_write(ring, 0x0000002e);
2358                 break;
2359         default:
2360                 amdgpu_ring_write(ring, 0x00000000);
2361                 amdgpu_ring_write(ring, 0x00000000);
2362                 break;
2363         }
2364
2365         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2366         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2367
2368         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2369         amdgpu_ring_write(ring, 0);
2370
2371         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2372         amdgpu_ring_write(ring, 0x00000316);
2373         amdgpu_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
2374         amdgpu_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
2375
2376         amdgpu_ring_commit(ring);
2377
2378         return 0;
2379 }
2380
2381 /**
2382  * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers
2383  *
2384  * @adev: amdgpu_device pointer
2385  *
2386  * Program the location and size of the gfx ring buffer
2387  * and test it to make sure it's working.
2388  * Returns 0 for success, error for failure.
2389  */
2390 static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev)
2391 {
2392         struct amdgpu_ring *ring;
2393         u32 tmp;
2394         u32 rb_bufsz;
2395         u64 rb_addr, rptr_addr;
2396         int r;
2397
2398         WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
2399         if (adev->asic_type != CHIP_HAWAII)
2400                 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2401
2402         /* Set the write pointer delay */
2403         WREG32(mmCP_RB_WPTR_DELAY, 0);
2404
2405         /* set the RB to use vmid 0 */
2406         WREG32(mmCP_RB_VMID, 0);
2407
2408         WREG32(mmSCRATCH_ADDR, 0);
2409
2410         /* ring 0 - compute and gfx */
2411         /* Set ring buffer size */
2412         ring = &adev->gfx.gfx_ring[0];
2413         rb_bufsz = order_base_2(ring->ring_size / 8);
2414         tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2415 #ifdef __BIG_ENDIAN
2416         tmp |= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT;
2417 #endif
2418         WREG32(mmCP_RB0_CNTL, tmp);
2419
2420         /* Initialize the ring buffer's read and write pointers */
2421         WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2422         ring->wptr = 0;
2423         WREG32(mmCP_RB0_WPTR, ring->wptr);
2424
2425         /* set the wb address wether it's enabled or not */
2426         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2427         WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2428         WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2429
2430         /* scratch register shadowing is no longer supported */
2431         WREG32(mmSCRATCH_UMSK, 0);
2432
2433         mdelay(1);
2434         WREG32(mmCP_RB0_CNTL, tmp);
2435
2436         rb_addr = ring->gpu_addr >> 8;
2437         WREG32(mmCP_RB0_BASE, rb_addr);
2438         WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2439
2440         /* start the ring */
2441         gfx_v7_0_cp_gfx_start(adev);
2442         ring->ready = true;
2443         r = amdgpu_ring_test_ring(ring);
2444         if (r) {
2445                 ring->ready = false;
2446                 return r;
2447         }
2448
2449         return 0;
2450 }
2451
2452 static u32 gfx_v7_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
2453 {
2454         return ring->adev->wb.wb[ring->rptr_offs];
2455 }
2456
2457 static u32 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
2458 {
2459         struct amdgpu_device *adev = ring->adev;
2460
2461         return RREG32(mmCP_RB0_WPTR);
2462 }
2463
2464 static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2465 {
2466         struct amdgpu_device *adev = ring->adev;
2467
2468         WREG32(mmCP_RB0_WPTR, ring->wptr);
2469         (void)RREG32(mmCP_RB0_WPTR);
2470 }
2471
2472 static u32 gfx_v7_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
2473 {
2474         return ring->adev->wb.wb[ring->rptr_offs];
2475 }
2476
2477 static u32 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
2478 {
2479         /* XXX check if swapping is necessary on BE */
2480         return ring->adev->wb.wb[ring->wptr_offs];
2481 }
2482
2483 static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2484 {
2485         struct amdgpu_device *adev = ring->adev;
2486
2487         /* XXX check if swapping is necessary on BE */
2488         adev->wb.wb[ring->wptr_offs] = ring->wptr;
2489         WDOORBELL32(ring->doorbell_index, ring->wptr);
2490 }
2491
2492 /**
2493  * gfx_v7_0_cp_compute_enable - enable/disable the compute CP MEs
2494  *
2495  * @adev: amdgpu_device pointer
2496  * @enable: enable or disable the MEs
2497  *
2498  * Halts or unhalts the compute MEs.
2499  */
2500 static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2501 {
2502         int i;
2503
2504         if (enable) {
2505                 WREG32(mmCP_MEC_CNTL, 0);
2506         } else {
2507                 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2508                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2509                         adev->gfx.compute_ring[i].ready = false;
2510         }
2511         udelay(50);
2512 }
2513
2514 /**
2515  * gfx_v7_0_cp_compute_load_microcode - load the compute CP ME ucode
2516  *
2517  * @adev: amdgpu_device pointer
2518  *
2519  * Loads the compute MEC1&2 ucode.
2520  * Returns 0 for success, -EINVAL if the ucode is not available.
2521  */
2522 static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2523 {
2524         const struct gfx_firmware_header_v1_0 *mec_hdr;
2525         const __le32 *fw_data;
2526         unsigned i, fw_size;
2527
2528         if (!adev->gfx.mec_fw)
2529                 return -EINVAL;
2530
2531         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2532         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2533         adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version);
2534         adev->gfx.mec_feature_version = le32_to_cpu(
2535                                         mec_hdr->ucode_feature_version);
2536
2537         gfx_v7_0_cp_compute_enable(adev, false);
2538
2539         /* MEC1 */
2540         fw_data = (const __le32 *)
2541                 (adev->gfx.mec_fw->data +
2542                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2543         fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
2544         WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2545         for (i = 0; i < fw_size; i++)
2546                 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++));
2547         WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2548
2549         if (adev->asic_type == CHIP_KAVERI) {
2550                 const struct gfx_firmware_header_v1_0 *mec2_hdr;
2551
2552                 if (!adev->gfx.mec2_fw)
2553                         return -EINVAL;
2554
2555                 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2556                 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
2557                 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version);
2558                 adev->gfx.mec2_feature_version = le32_to_cpu(
2559                                 mec2_hdr->ucode_feature_version);
2560
2561                 /* MEC2 */
2562                 fw_data = (const __le32 *)
2563                         (adev->gfx.mec2_fw->data +
2564                          le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
2565                 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
2566                 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2567                 for (i = 0; i < fw_size; i++)
2568                         WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++));
2569                 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2570         }
2571
2572         return 0;
2573 }
2574
2575 /**
2576  * gfx_v7_0_cp_compute_fini - stop the compute queues
2577  *
2578  * @adev: amdgpu_device pointer
2579  *
2580  * Stop the compute queues and tear down the driver queue
2581  * info.
2582  */
2583 static void gfx_v7_0_cp_compute_fini(struct amdgpu_device *adev)
2584 {
2585         int i, r;
2586
2587         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2588                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2589
2590                 if (ring->mqd_obj) {
2591                         r = amdgpu_bo_reserve(ring->mqd_obj, false);
2592                         if (unlikely(r != 0))
2593                                 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
2594
2595                         amdgpu_bo_unpin(ring->mqd_obj);
2596                         amdgpu_bo_unreserve(ring->mqd_obj);
2597
2598                         amdgpu_bo_unref(&ring->mqd_obj);
2599                         ring->mqd_obj = NULL;
2600                 }
2601         }
2602 }
2603
2604 static void gfx_v7_0_mec_fini(struct amdgpu_device *adev)
2605 {
2606         int r;
2607
2608         if (adev->gfx.mec.hpd_eop_obj) {
2609                 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
2610                 if (unlikely(r != 0))
2611                         dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
2612                 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
2613                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
2614
2615                 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
2616                 adev->gfx.mec.hpd_eop_obj = NULL;
2617         }
2618 }
2619
2620 #define MEC_HPD_SIZE 2048
2621
2622 static int gfx_v7_0_mec_init(struct amdgpu_device *adev)
2623 {
2624         int r;
2625         u32 *hpd;
2626
2627         /*
2628          * KV:    2 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 64 Queues total
2629          * CI/KB: 1 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 32 Queues total
2630          * Nonetheless, we assign only 1 pipe because all other pipes will
2631          * be handled by KFD
2632          */
2633         adev->gfx.mec.num_mec = 1;
2634         adev->gfx.mec.num_pipe = 1;
2635         adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
2636
2637         if (adev->gfx.mec.hpd_eop_obj == NULL) {
2638                 r = amdgpu_bo_create(adev,
2639                                      adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
2640                                      PAGE_SIZE, true,
2641                                      AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
2642                                      &adev->gfx.mec.hpd_eop_obj);
2643                 if (r) {
2644                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
2645                         return r;
2646                 }
2647         }
2648
2649         r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
2650         if (unlikely(r != 0)) {
2651                 gfx_v7_0_mec_fini(adev);
2652                 return r;
2653         }
2654         r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
2655                           &adev->gfx.mec.hpd_eop_gpu_addr);
2656         if (r) {
2657                 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
2658                 gfx_v7_0_mec_fini(adev);
2659                 return r;
2660         }
2661         r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
2662         if (r) {
2663                 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
2664                 gfx_v7_0_mec_fini(adev);
2665                 return r;
2666         }
2667
2668         /* clear memory.  Not sure if this is required or not */
2669         memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2);
2670
2671         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
2672         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
2673
2674         return 0;
2675 }
2676
2677 struct hqd_registers
2678 {
2679         u32 cp_mqd_base_addr;
2680         u32 cp_mqd_base_addr_hi;
2681         u32 cp_hqd_active;
2682         u32 cp_hqd_vmid;
2683         u32 cp_hqd_persistent_state;
2684         u32 cp_hqd_pipe_priority;
2685         u32 cp_hqd_queue_priority;
2686         u32 cp_hqd_quantum;
2687         u32 cp_hqd_pq_base;
2688         u32 cp_hqd_pq_base_hi;
2689         u32 cp_hqd_pq_rptr;
2690         u32 cp_hqd_pq_rptr_report_addr;
2691         u32 cp_hqd_pq_rptr_report_addr_hi;
2692         u32 cp_hqd_pq_wptr_poll_addr;
2693         u32 cp_hqd_pq_wptr_poll_addr_hi;
2694         u32 cp_hqd_pq_doorbell_control;
2695         u32 cp_hqd_pq_wptr;
2696         u32 cp_hqd_pq_control;
2697         u32 cp_hqd_ib_base_addr;
2698         u32 cp_hqd_ib_base_addr_hi;
2699         u32 cp_hqd_ib_rptr;
2700         u32 cp_hqd_ib_control;
2701         u32 cp_hqd_iq_timer;
2702         u32 cp_hqd_iq_rptr;
2703         u32 cp_hqd_dequeue_request;
2704         u32 cp_hqd_dma_offload;
2705         u32 cp_hqd_sema_cmd;
2706         u32 cp_hqd_msg_type;
2707         u32 cp_hqd_atomic0_preop_lo;
2708         u32 cp_hqd_atomic0_preop_hi;
2709         u32 cp_hqd_atomic1_preop_lo;
2710         u32 cp_hqd_atomic1_preop_hi;
2711         u32 cp_hqd_hq_scheduler0;
2712         u32 cp_hqd_hq_scheduler1;
2713         u32 cp_mqd_control;
2714 };
2715
2716 struct bonaire_mqd
2717 {
2718         u32 header;
2719         u32 dispatch_initiator;
2720         u32 dimensions[3];
2721         u32 start_idx[3];
2722         u32 num_threads[3];
2723         u32 pipeline_stat_enable;
2724         u32 perf_counter_enable;
2725         u32 pgm[2];
2726         u32 tba[2];
2727         u32 tma[2];
2728         u32 pgm_rsrc[2];
2729         u32 vmid;
2730         u32 resource_limits;
2731         u32 static_thread_mgmt01[2];
2732         u32 tmp_ring_size;
2733         u32 static_thread_mgmt23[2];
2734         u32 restart[3];
2735         u32 thread_trace_enable;
2736         u32 reserved1;
2737         u32 user_data[16];
2738         u32 vgtcs_invoke_count[2];
2739         struct hqd_registers queue_state;
2740         u32 dequeue_cntr;
2741         u32 interrupt_queue[64];
2742 };
2743
2744 /**
2745  * gfx_v7_0_cp_compute_resume - setup the compute queue registers
2746  *
2747  * @adev: amdgpu_device pointer
2748  *
2749  * Program the compute queues and test them to make sure they
2750  * are working.
2751  * Returns 0 for success, error for failure.
2752  */
2753 static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev)
2754 {
2755         int r, i, j;
2756         u32 tmp;
2757         bool use_doorbell = true;
2758         u64 hqd_gpu_addr;
2759         u64 mqd_gpu_addr;
2760         u64 eop_gpu_addr;
2761         u64 wb_gpu_addr;
2762         u32 *buf;
2763         struct bonaire_mqd *mqd;
2764
2765         gfx_v7_0_cp_compute_enable(adev, true);
2766
2767         /* fix up chicken bits */
2768         tmp = RREG32(mmCP_CPF_DEBUG);
2769         tmp |= (1 << 23);
2770         WREG32(mmCP_CPF_DEBUG, tmp);
2771
2772         /* init the pipes */
2773         mutex_lock(&adev->srbm_mutex);
2774         for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
2775                 int me = (i < 4) ? 1 : 2;
2776                 int pipe = (i < 4) ? i : (i - 4);
2777
2778                 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE * 2);
2779
2780                 cik_srbm_select(adev, me, pipe, 0, 0);
2781
2782                 /* write the EOP addr */
2783                 WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8);
2784                 WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);
2785
2786                 /* set the VMID assigned */
2787                 WREG32(mmCP_HPD_EOP_VMID, 0);
2788
2789                 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2790                 tmp = RREG32(mmCP_HPD_EOP_CONTROL);
2791                 tmp &= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK;
2792                 tmp |= order_base_2(MEC_HPD_SIZE / 8);
2793                 WREG32(mmCP_HPD_EOP_CONTROL, tmp);
2794         }
2795         cik_srbm_select(adev, 0, 0, 0, 0);
2796         mutex_unlock(&adev->srbm_mutex);
2797
2798         /* init the queues.  Just two for now. */
2799         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2800                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2801
2802                 if (ring->mqd_obj == NULL) {
2803                         r = amdgpu_bo_create(adev,
2804                                              sizeof(struct bonaire_mqd),
2805                                              PAGE_SIZE, true,
2806                                              AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
2807                                              &ring->mqd_obj);
2808                         if (r) {
2809                                 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
2810                                 return r;
2811                         }
2812                 }
2813
2814                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2815                 if (unlikely(r != 0)) {
2816                         gfx_v7_0_cp_compute_fini(adev);
2817                         return r;
2818                 }
2819                 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
2820                                   &mqd_gpu_addr);
2821                 if (r) {
2822                         dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
2823                         gfx_v7_0_cp_compute_fini(adev);
2824                         return r;
2825                 }
2826                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
2827                 if (r) {
2828                         dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
2829                         gfx_v7_0_cp_compute_fini(adev);
2830                         return r;
2831                 }
2832
2833                 /* init the mqd struct */
2834                 memset(buf, 0, sizeof(struct bonaire_mqd));
2835
2836                 mqd = (struct bonaire_mqd *)buf;
2837                 mqd->header = 0xC0310800;
2838                 mqd->static_thread_mgmt01[0] = 0xffffffff;
2839                 mqd->static_thread_mgmt01[1] = 0xffffffff;
2840                 mqd->static_thread_mgmt23[0] = 0xffffffff;
2841                 mqd->static_thread_mgmt23[1] = 0xffffffff;
2842
2843                 mutex_lock(&adev->srbm_mutex);
2844                 cik_srbm_select(adev, ring->me,
2845                                 ring->pipe,
2846                                 ring->queue, 0);
2847
2848                 /* disable wptr polling */
2849                 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
2850                 tmp &= ~CP_PQ_WPTR_POLL_CNTL__EN_MASK;
2851                 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
2852
2853                 /* enable doorbell? */
2854                 mqd->queue_state.cp_hqd_pq_doorbell_control =
2855                         RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
2856                 if (use_doorbell)
2857                         mqd->queue_state.cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2858                 else
2859                         mqd->queue_state.cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2860                 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
2861                        mqd->queue_state.cp_hqd_pq_doorbell_control);
2862
2863                 /* disable the queue if it's active */
2864                 mqd->queue_state.cp_hqd_dequeue_request = 0;
2865                 mqd->queue_state.cp_hqd_pq_rptr = 0;
2866                 mqd->queue_state.cp_hqd_pq_wptr= 0;
2867                 if (RREG32(mmCP_HQD_ACTIVE) & 1) {
2868                         WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
2869                         for (j = 0; j < adev->usec_timeout; j++) {
2870                                 if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
2871                                         break;
2872                                 udelay(1);
2873                         }
2874                         WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request);
2875                         WREG32(mmCP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr);
2876                         WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
2877                 }
2878
2879                 /* set the pointer to the MQD */
2880                 mqd->queue_state.cp_mqd_base_addr = mqd_gpu_addr & 0xfffffffc;
2881                 mqd->queue_state.cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
2882                 WREG32(mmCP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr);
2883                 WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi);
2884                 /* set MQD vmid to 0 */
2885                 mqd->queue_state.cp_mqd_control = RREG32(mmCP_MQD_CONTROL);
2886                 mqd->queue_state.cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK;
2887                 WREG32(mmCP_MQD_CONTROL, mqd->queue_state.cp_mqd_control);
2888
2889                 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2890                 hqd_gpu_addr = ring->gpu_addr >> 8;
2891                 mqd->queue_state.cp_hqd_pq_base = hqd_gpu_addr;
2892                 mqd->queue_state.cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
2893                 WREG32(mmCP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base);
2894                 WREG32(mmCP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi);
2895
2896                 /* set up the HQD, this is similar to CP_RB0_CNTL */
2897                 mqd->queue_state.cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL);
2898                 mqd->queue_state.cp_hqd_pq_control &=
2899                         ~(CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK |
2900                                         CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK);
2901
2902                 mqd->queue_state.cp_hqd_pq_control |=
2903                         order_base_2(ring->ring_size / 8);
2904                 mqd->queue_state.cp_hqd_pq_control |=
2905                         (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8);
2906 #ifdef __BIG_ENDIAN
2907                 mqd->queue_state.cp_hqd_pq_control |=
2908                         2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT;
2909 #endif
2910                 mqd->queue_state.cp_hqd_pq_control &=
2911                         ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK |
2912                                 CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK |
2913                                 CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK);
2914                 mqd->queue_state.cp_hqd_pq_control |=
2915                         CP_HQD_PQ_CONTROL__PRIV_STATE_MASK |
2916                         CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK; /* assuming kernel queue control */
2917                 WREG32(mmCP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control);
2918
2919                 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2920                 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2921                 mqd->queue_state.cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
2922                 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2923                 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr);
2924                 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
2925                        mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi);
2926
2927                 /* set the wb address wether it's enabled or not */
2928                 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2929                 mqd->queue_state.cp_hqd_pq_rptr_report_addr = wb_gpu_addr & 0xfffffffc;
2930                 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi =
2931                         upper_32_bits(wb_gpu_addr) & 0xffff;
2932                 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR,
2933                        mqd->queue_state.cp_hqd_pq_rptr_report_addr);
2934                 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
2935                        mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi);
2936
2937                 /* enable the doorbell if requested */
2938                 if (use_doorbell) {
2939                         mqd->queue_state.cp_hqd_pq_doorbell_control =
2940                                 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
2941                         mqd->queue_state.cp_hqd_pq_doorbell_control &=
2942                                 ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK;
2943                         mqd->queue_state.cp_hqd_pq_doorbell_control |=
2944                                 (ring->doorbell_index <<
2945                                  CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT);
2946                         mqd->queue_state.cp_hqd_pq_doorbell_control |=
2947                                 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2948                         mqd->queue_state.cp_hqd_pq_doorbell_control &=
2949                                 ~(CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK |
2950                                 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK);
2951
2952                 } else {
2953                         mqd->queue_state.cp_hqd_pq_doorbell_control = 0;
2954                 }
2955                 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
2956                        mqd->queue_state.cp_hqd_pq_doorbell_control);
2957
2958                 /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2959                 ring->wptr = 0;
2960                 mqd->queue_state.cp_hqd_pq_wptr = ring->wptr;
2961                 WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
2962                 mqd->queue_state.cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
2963
2964                 /* set the vmid for the queue */
2965                 mqd->queue_state.cp_hqd_vmid = 0;
2966                 WREG32(mmCP_HQD_VMID, mqd->queue_state.cp_hqd_vmid);
2967
2968                 /* activate the queue */
2969                 mqd->queue_state.cp_hqd_active = 1;
2970                 WREG32(mmCP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active);
2971
2972                 cik_srbm_select(adev, 0, 0, 0, 0);
2973                 mutex_unlock(&adev->srbm_mutex);
2974
2975                 amdgpu_bo_kunmap(ring->mqd_obj);
2976                 amdgpu_bo_unreserve(ring->mqd_obj);
2977
2978                 ring->ready = true;
2979                 r = amdgpu_ring_test_ring(ring);
2980                 if (r)
2981                         ring->ready = false;
2982         }
2983
2984         return 0;
2985 }
2986
2987 static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable)
2988 {
2989         gfx_v7_0_cp_gfx_enable(adev, enable);
2990         gfx_v7_0_cp_compute_enable(adev, enable);
2991 }
2992
2993 static int gfx_v7_0_cp_load_microcode(struct amdgpu_device *adev)
2994 {
2995         int r;
2996
2997         r = gfx_v7_0_cp_gfx_load_microcode(adev);
2998         if (r)
2999                 return r;
3000         r = gfx_v7_0_cp_compute_load_microcode(adev);
3001         if (r)
3002                 return r;
3003
3004         return 0;
3005 }
3006
3007 static void gfx_v7_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
3008                                                bool enable)
3009 {
3010         u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
3011
3012         if (enable)
3013                 tmp |= (CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3014                                 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3015         else
3016                 tmp &= ~(CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3017                                 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3018         WREG32(mmCP_INT_CNTL_RING0, tmp);
3019 }
3020
3021 static int gfx_v7_0_cp_resume(struct amdgpu_device *adev)
3022 {
3023         int r;
3024
3025         gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3026
3027         r = gfx_v7_0_cp_load_microcode(adev);
3028         if (r)
3029                 return r;
3030
3031         r = gfx_v7_0_cp_gfx_resume(adev);
3032         if (r)
3033                 return r;
3034         r = gfx_v7_0_cp_compute_resume(adev);
3035         if (r)
3036                 return r;
3037
3038         gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3039
3040         return 0;
3041 }
3042
3043 /**
3044  * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3045  *
3046  * @ring: the ring to emmit the commands to
3047  *
3048  * Sync the command pipeline with the PFP. E.g. wait for everything
3049  * to be completed.
3050  */
3051 static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
3052 {
3053         int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
3054         uint32_t seq = ring->fence_drv.sync_seq;
3055         uint64_t addr = ring->fence_drv.gpu_addr;
3056
3057         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3058         amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
3059                                  WAIT_REG_MEM_FUNCTION(3) | /* equal */
3060                                  WAIT_REG_MEM_ENGINE(usepfp)));   /* pfp or me */
3061         amdgpu_ring_write(ring, addr & 0xfffffffc);
3062         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
3063         amdgpu_ring_write(ring, seq);
3064         amdgpu_ring_write(ring, 0xffffffff);
3065         amdgpu_ring_write(ring, 4); /* poll interval */
3066
3067         if (usepfp) {
3068                 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3069                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3070                 amdgpu_ring_write(ring, 0);
3071                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3072                 amdgpu_ring_write(ring, 0);
3073         }
3074 }
3075
3076 /*
3077  * vm
3078  * VMID 0 is the physical GPU addresses as used by the kernel.
3079  * VMIDs 1-15 are used for userspace clients and are handled
3080  * by the amdgpu vm/hsa code.
3081  */
3082 /**
3083  * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3084  *
3085  * @adev: amdgpu_device pointer
3086  *
3087  * Update the page table base and flush the VM TLB
3088  * using the CP (CIK).
3089  */
3090 static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3091                                         unsigned vm_id, uint64_t pd_addr)
3092 {
3093         int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
3094
3095         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3096         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
3097                                  WRITE_DATA_DST_SEL(0)));
3098         if (vm_id < 8) {
3099                 amdgpu_ring_write(ring,
3100                                   (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
3101         } else {
3102                 amdgpu_ring_write(ring,
3103                                   (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
3104         }
3105         amdgpu_ring_write(ring, 0);
3106         amdgpu_ring_write(ring, pd_addr >> 12);
3107
3108         /* bits 0-15 are the VM contexts0-15 */
3109         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3110         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3111                                  WRITE_DATA_DST_SEL(0)));
3112         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3113         amdgpu_ring_write(ring, 0);
3114         amdgpu_ring_write(ring, 1 << vm_id);
3115
3116         /* wait for the invalidate to complete */
3117         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3118         amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
3119                                  WAIT_REG_MEM_FUNCTION(0) |  /* always */
3120                                  WAIT_REG_MEM_ENGINE(0))); /* me */
3121         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3122         amdgpu_ring_write(ring, 0);
3123         amdgpu_ring_write(ring, 0); /* ref */
3124         amdgpu_ring_write(ring, 0); /* mask */
3125         amdgpu_ring_write(ring, 0x20); /* poll interval */
3126
3127         /* compute doesn't have PFP */
3128         if (usepfp) {
3129                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3130                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3131                 amdgpu_ring_write(ring, 0x0);
3132
3133                 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3134                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3135                 amdgpu_ring_write(ring, 0);
3136                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3137                 amdgpu_ring_write(ring, 0);
3138         }
3139 }
3140
3141 /*
3142  * RLC
3143  * The RLC is a multi-purpose microengine that handles a
3144  * variety of functions.
3145  */
3146 static void gfx_v7_0_rlc_fini(struct amdgpu_device *adev)
3147 {
3148         int r;
3149
3150         /* save restore block */
3151         if (adev->gfx.rlc.save_restore_obj) {
3152                 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
3153                 if (unlikely(r != 0))
3154                         dev_warn(adev->dev, "(%d) reserve RLC sr bo failed\n", r);
3155                 amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj);
3156                 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3157
3158                 amdgpu_bo_unref(&adev->gfx.rlc.save_restore_obj);
3159                 adev->gfx.rlc.save_restore_obj = NULL;
3160         }
3161
3162         /* clear state block */
3163         if (adev->gfx.rlc.clear_state_obj) {
3164                 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
3165                 if (unlikely(r != 0))
3166                         dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r);
3167                 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
3168                 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3169
3170                 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
3171                 adev->gfx.rlc.clear_state_obj = NULL;
3172         }
3173
3174         /* clear state block */
3175         if (adev->gfx.rlc.cp_table_obj) {
3176                 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
3177                 if (unlikely(r != 0))
3178                         dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
3179                 amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj);
3180                 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3181
3182                 amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj);
3183                 adev->gfx.rlc.cp_table_obj = NULL;
3184         }
3185 }
3186
3187 static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
3188 {
3189         const u32 *src_ptr;
3190         volatile u32 *dst_ptr;
3191         u32 dws, i;
3192         const struct cs_section_def *cs_data;
3193         int r;
3194
3195         /* allocate rlc buffers */
3196         if (adev->flags & AMD_IS_APU) {
3197                 if (adev->asic_type == CHIP_KAVERI) {
3198                         adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list;
3199                         adev->gfx.rlc.reg_list_size =
3200                                 (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list);
3201                 } else {
3202                         adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list;
3203                         adev->gfx.rlc.reg_list_size =
3204                                 (u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list);
3205                 }
3206         }
3207         adev->gfx.rlc.cs_data = ci_cs_data;
3208         adev->gfx.rlc.cp_table_size = CP_ME_TABLE_SIZE * 5 * 4;
3209
3210         src_ptr = adev->gfx.rlc.reg_list;
3211         dws = adev->gfx.rlc.reg_list_size;
3212         dws += (5 * 16) + 48 + 48 + 64;
3213
3214         cs_data = adev->gfx.rlc.cs_data;
3215
3216         if (src_ptr) {
3217                 /* save restore block */
3218                 if (adev->gfx.rlc.save_restore_obj == NULL) {
3219                         r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
3220                                              AMDGPU_GEM_DOMAIN_VRAM,
3221                                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
3222                                              NULL, NULL,
3223                                              &adev->gfx.rlc.save_restore_obj);
3224                         if (r) {
3225                                 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r);
3226                                 return r;
3227                         }
3228                 }
3229
3230                 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
3231                 if (unlikely(r != 0)) {
3232                         gfx_v7_0_rlc_fini(adev);
3233                         return r;
3234                 }
3235                 r = amdgpu_bo_pin(adev->gfx.rlc.save_restore_obj, AMDGPU_GEM_DOMAIN_VRAM,
3236                                   &adev->gfx.rlc.save_restore_gpu_addr);
3237                 if (r) {
3238                         amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3239                         dev_warn(adev->dev, "(%d) pin RLC sr bo failed\n", r);
3240                         gfx_v7_0_rlc_fini(adev);
3241                         return r;
3242                 }
3243
3244                 r = amdgpu_bo_kmap(adev->gfx.rlc.save_restore_obj, (void **)&adev->gfx.rlc.sr_ptr);
3245                 if (r) {
3246                         dev_warn(adev->dev, "(%d) map RLC sr bo failed\n", r);
3247                         gfx_v7_0_rlc_fini(adev);
3248                         return r;
3249                 }
3250                 /* write the sr buffer */
3251                 dst_ptr = adev->gfx.rlc.sr_ptr;
3252                 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
3253                         dst_ptr[i] = cpu_to_le32(src_ptr[i]);
3254                 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
3255                 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3256         }
3257
3258         if (cs_data) {
3259                 /* clear state block */
3260                 adev->gfx.rlc.clear_state_size = dws = gfx_v7_0_get_csb_size(adev);
3261
3262                 if (adev->gfx.rlc.clear_state_obj == NULL) {
3263                         r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
3264                                              AMDGPU_GEM_DOMAIN_VRAM,
3265                                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
3266                                              NULL, NULL,
3267                                              &adev->gfx.rlc.clear_state_obj);
3268                         if (r) {
3269                                 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
3270                                 gfx_v7_0_rlc_fini(adev);
3271                                 return r;
3272                         }
3273                 }
3274                 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
3275                 if (unlikely(r != 0)) {
3276                         gfx_v7_0_rlc_fini(adev);
3277                         return r;
3278                 }
3279                 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM,
3280                                   &adev->gfx.rlc.clear_state_gpu_addr);
3281                 if (r) {
3282                         amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3283                         dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r);
3284                         gfx_v7_0_rlc_fini(adev);
3285                         return r;
3286                 }
3287
3288                 r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr);
3289                 if (r) {
3290                         dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r);
3291                         gfx_v7_0_rlc_fini(adev);
3292                         return r;
3293                 }
3294                 /* set up the cs buffer */
3295                 dst_ptr = adev->gfx.rlc.cs_ptr;
3296                 gfx_v7_0_get_csb_buffer(adev, dst_ptr);
3297                 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
3298                 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3299         }
3300
3301         if (adev->gfx.rlc.cp_table_size) {
3302                 if (adev->gfx.rlc.cp_table_obj == NULL) {
3303                         r = amdgpu_bo_create(adev, adev->gfx.rlc.cp_table_size, PAGE_SIZE, true,
3304                                              AMDGPU_GEM_DOMAIN_VRAM,
3305                                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
3306                                              NULL, NULL,
3307                                              &adev->gfx.rlc.cp_table_obj);
3308                         if (r) {
3309                                 dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r);
3310                                 gfx_v7_0_rlc_fini(adev);
3311                                 return r;
3312                         }
3313                 }
3314
3315                 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
3316                 if (unlikely(r != 0)) {
3317                         dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
3318                         gfx_v7_0_rlc_fini(adev);
3319                         return r;
3320                 }
3321                 r = amdgpu_bo_pin(adev->gfx.rlc.cp_table_obj, AMDGPU_GEM_DOMAIN_VRAM,
3322                                   &adev->gfx.rlc.cp_table_gpu_addr);
3323                 if (r) {
3324                         amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3325                         dev_warn(adev->dev, "(%d) pin RLC cp_table bo failed\n", r);
3326                         gfx_v7_0_rlc_fini(adev);
3327                         return r;
3328                 }
3329                 r = amdgpu_bo_kmap(adev->gfx.rlc.cp_table_obj, (void **)&adev->gfx.rlc.cp_table_ptr);
3330                 if (r) {
3331                         dev_warn(adev->dev, "(%d) map RLC cp table bo failed\n", r);
3332                         gfx_v7_0_rlc_fini(adev);
3333                         return r;
3334                 }
3335
3336                 gfx_v7_0_init_cp_pg_table(adev);
3337
3338                 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
3339                 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3340
3341         }
3342
3343         return 0;
3344 }
3345
3346 static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
3347 {
3348         u32 tmp;
3349
3350         tmp = RREG32(mmRLC_LB_CNTL);
3351         if (enable)
3352                 tmp |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3353         else
3354                 tmp &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3355         WREG32(mmRLC_LB_CNTL, tmp);
3356 }
3357
3358 static void gfx_v7_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
3359 {
3360         u32 i, j, k;
3361         u32 mask;
3362
3363         mutex_lock(&adev->grbm_idx_mutex);
3364         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3365                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3366                         gfx_v7_0_select_se_sh(adev, i, j);
3367                         for (k = 0; k < adev->usec_timeout; k++) {
3368                                 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
3369                                         break;
3370                                 udelay(1);
3371                         }
3372                 }
3373         }
3374         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3375         mutex_unlock(&adev->grbm_idx_mutex);
3376
3377         mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
3378                 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
3379                 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
3380                 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
3381         for (k = 0; k < adev->usec_timeout; k++) {
3382                 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
3383                         break;
3384                 udelay(1);
3385         }
3386 }
3387
3388 static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
3389 {
3390         u32 tmp;
3391
3392         tmp = RREG32(mmRLC_CNTL);
3393         if (tmp != rlc)
3394                 WREG32(mmRLC_CNTL, rlc);
3395 }
3396
3397 static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev)
3398 {
3399         u32 data, orig;
3400
3401         orig = data = RREG32(mmRLC_CNTL);
3402
3403         if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
3404                 u32 i;
3405
3406                 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
3407                 WREG32(mmRLC_CNTL, data);
3408
3409                 for (i = 0; i < adev->usec_timeout; i++) {
3410                         if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0)
3411                                 break;
3412                         udelay(1);
3413                 }
3414
3415                 gfx_v7_0_wait_for_rlc_serdes(adev);
3416         }
3417
3418         return orig;
3419 }
3420
3421 void gfx_v7_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
3422 {
3423         u32 tmp, i, mask;
3424
3425         tmp = 0x1 | (1 << 1);
3426         WREG32(mmRLC_GPR_REG2, tmp);
3427
3428         mask = RLC_GPM_STAT__GFX_POWER_STATUS_MASK |
3429                 RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK;
3430         for (i = 0; i < adev->usec_timeout; i++) {
3431                 if ((RREG32(mmRLC_GPM_STAT) & mask) == mask)
3432                         break;
3433                 udelay(1);
3434         }
3435
3436         for (i = 0; i < adev->usec_timeout; i++) {
3437                 if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0)
3438                         break;
3439                 udelay(1);
3440         }
3441 }
3442
3443 void gfx_v7_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
3444 {
3445         u32 tmp;
3446
3447         tmp = 0x1 | (0 << 1);
3448         WREG32(mmRLC_GPR_REG2, tmp);
3449 }
3450
3451 /**
3452  * gfx_v7_0_rlc_stop - stop the RLC ME
3453  *
3454  * @adev: amdgpu_device pointer
3455  *
3456  * Halt the RLC ME (MicroEngine) (CIK).
3457  */
3458 void gfx_v7_0_rlc_stop(struct amdgpu_device *adev)
3459 {
3460         WREG32(mmRLC_CNTL, 0);
3461
3462         gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3463
3464         gfx_v7_0_wait_for_rlc_serdes(adev);
3465 }
3466
3467 /**
3468  * gfx_v7_0_rlc_start - start the RLC ME
3469  *
3470  * @adev: amdgpu_device pointer
3471  *
3472  * Unhalt the RLC ME (MicroEngine) (CIK).
3473  */
3474 static void gfx_v7_0_rlc_start(struct amdgpu_device *adev)
3475 {
3476         WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
3477
3478         gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3479
3480         udelay(50);
3481 }
3482
3483 static void gfx_v7_0_rlc_reset(struct amdgpu_device *adev)
3484 {
3485         u32 tmp = RREG32(mmGRBM_SOFT_RESET);
3486
3487         tmp |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3488         WREG32(mmGRBM_SOFT_RESET, tmp);
3489         udelay(50);
3490         tmp &= ~GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3491         WREG32(mmGRBM_SOFT_RESET, tmp);
3492         udelay(50);
3493 }
3494
3495 /**
3496  * gfx_v7_0_rlc_resume - setup the RLC hw
3497  *
3498  * @adev: amdgpu_device pointer
3499  *
3500  * Initialize the RLC registers, load the ucode,
3501  * and start the RLC (CIK).
3502  * Returns 0 for success, -EINVAL if the ucode is not available.
3503  */
3504 static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev)
3505 {
3506         const struct rlc_firmware_header_v1_0 *hdr;
3507         const __le32 *fw_data;
3508         unsigned i, fw_size;
3509         u32 tmp;
3510
3511         if (!adev->gfx.rlc_fw)
3512                 return -EINVAL;
3513
3514         hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
3515         amdgpu_ucode_print_rlc_hdr(&hdr->header);
3516         adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version);
3517         adev->gfx.rlc_feature_version = le32_to_cpu(
3518                                         hdr->ucode_feature_version);
3519
3520         gfx_v7_0_rlc_stop(adev);
3521
3522         /* disable CG */
3523         tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc;
3524         WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);
3525
3526         gfx_v7_0_rlc_reset(adev);
3527
3528         gfx_v7_0_init_pg(adev);
3529
3530         WREG32(mmRLC_LB_CNTR_INIT, 0);
3531         WREG32(mmRLC_LB_CNTR_MAX, 0x00008000);
3532
3533         mutex_lock(&adev->grbm_idx_mutex);
3534         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3535         WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
3536         WREG32(mmRLC_LB_PARAMS, 0x00600408);
3537         WREG32(mmRLC_LB_CNTL, 0x80000004);
3538         mutex_unlock(&adev->grbm_idx_mutex);
3539
3540         WREG32(mmRLC_MC_CNTL, 0);
3541         WREG32(mmRLC_UCODE_CNTL, 0);
3542
3543         fw_data = (const __le32 *)
3544                 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3545         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
3546         WREG32(mmRLC_GPM_UCODE_ADDR, 0);
3547         for (i = 0; i < fw_size; i++)
3548                 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
3549         WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
3550
3551         /* XXX - find out what chips support lbpw */
3552         gfx_v7_0_enable_lbpw(adev, false);
3553
3554         if (adev->asic_type == CHIP_BONAIRE)
3555                 WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0);
3556
3557         gfx_v7_0_rlc_start(adev);
3558
3559         return 0;
3560 }
3561
3562 static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
3563 {
3564         u32 data, orig, tmp, tmp2;
3565
3566         orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
3567
3568         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
3569                 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3570
3571                 tmp = gfx_v7_0_halt_rlc(adev);
3572
3573                 mutex_lock(&adev->grbm_idx_mutex);
3574                 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3575                 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3576                 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3577                 tmp2 = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3578                         RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK |
3579                         RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK;
3580                 WREG32(mmRLC_SERDES_WR_CTRL, tmp2);
3581                 mutex_unlock(&adev->grbm_idx_mutex);
3582
3583                 gfx_v7_0_update_rlc(adev, tmp);
3584
3585                 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3586         } else {
3587                 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3588
3589                 RREG32(mmCB_CGTT_SCLK_CTRL);
3590                 RREG32(mmCB_CGTT_SCLK_CTRL);
3591                 RREG32(mmCB_CGTT_SCLK_CTRL);
3592                 RREG32(mmCB_CGTT_SCLK_CTRL);
3593
3594                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3595         }
3596
3597         if (orig != data)
3598                 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
3599
3600 }
3601
3602 static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
3603 {
3604         u32 data, orig, tmp = 0;
3605
3606         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3607                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3608                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
3609                                 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
3610                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3611                                 if (orig != data)
3612                                         WREG32(mmCP_MEM_SLP_CNTL, data);
3613                         }
3614                 }
3615
3616                 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3617                 data |= 0x00000001;
3618                 data &= 0xfffffffd;
3619                 if (orig != data)
3620                         WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3621
3622                 tmp = gfx_v7_0_halt_rlc(adev);
3623
3624                 mutex_lock(&adev->grbm_idx_mutex);
3625                 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3626                 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3627                 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3628                 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3629                         RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK;
3630                 WREG32(mmRLC_SERDES_WR_CTRL, data);
3631                 mutex_unlock(&adev->grbm_idx_mutex);
3632
3633                 gfx_v7_0_update_rlc(adev, tmp);
3634
3635                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) {
3636                         orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3637                         data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK;
3638                         data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
3639                         data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
3640                         data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
3641                         if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) &&
3642                             (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS))
3643                                 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3644                         data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK;
3645                         data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
3646                         data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
3647                         if (orig != data)
3648                                 WREG32(mmCGTS_SM_CTRL_REG, data);
3649                 }
3650         } else {
3651                 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3652                 data |= 0x00000003;
3653                 if (orig != data)
3654                         WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3655
3656                 data = RREG32(mmRLC_MEM_SLP_CNTL);
3657                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3658                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3659                         WREG32(mmRLC_MEM_SLP_CNTL, data);
3660                 }
3661
3662                 data = RREG32(mmCP_MEM_SLP_CNTL);
3663                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3664                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3665                         WREG32(mmCP_MEM_SLP_CNTL, data);
3666                 }
3667
3668                 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3669                 data |= CGTS_SM_CTRL_REG__OVERRIDE_MASK | CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3670                 if (orig != data)
3671                         WREG32(mmCGTS_SM_CTRL_REG, data);
3672
3673                 tmp = gfx_v7_0_halt_rlc(adev);
3674
3675                 mutex_lock(&adev->grbm_idx_mutex);
3676                 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3677                 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3678                 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3679                 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK;
3680                 WREG32(mmRLC_SERDES_WR_CTRL, data);
3681                 mutex_unlock(&adev->grbm_idx_mutex);
3682
3683                 gfx_v7_0_update_rlc(adev, tmp);
3684         }
3685 }
3686
3687 static void gfx_v7_0_update_cg(struct amdgpu_device *adev,
3688                                bool enable)
3689 {
3690         gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3691         /* order matters! */
3692         if (enable) {
3693                 gfx_v7_0_enable_mgcg(adev, true);
3694                 gfx_v7_0_enable_cgcg(adev, true);
3695         } else {
3696                 gfx_v7_0_enable_cgcg(adev, false);
3697                 gfx_v7_0_enable_mgcg(adev, false);
3698         }
3699         gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3700 }
3701
3702 static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
3703                                                 bool enable)
3704 {
3705         u32 data, orig;
3706
3707         orig = data = RREG32(mmRLC_PG_CNTL);
3708         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
3709                 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3710         else
3711                 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3712         if (orig != data)
3713                 WREG32(mmRLC_PG_CNTL, data);
3714 }
3715
3716 static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
3717                                                 bool enable)
3718 {
3719         u32 data, orig;
3720
3721         orig = data = RREG32(mmRLC_PG_CNTL);
3722         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
3723                 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3724         else
3725                 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3726         if (orig != data)
3727                 WREG32(mmRLC_PG_CNTL, data);
3728 }
3729
3730 static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
3731 {
3732         u32 data, orig;
3733
3734         orig = data = RREG32(mmRLC_PG_CNTL);
3735         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
3736                 data &= ~0x8000;
3737         else
3738                 data |= 0x8000;
3739         if (orig != data)
3740                 WREG32(mmRLC_PG_CNTL, data);
3741 }
3742
3743 static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
3744 {
3745         u32 data, orig;
3746
3747         orig = data = RREG32(mmRLC_PG_CNTL);
3748         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GDS))
3749                 data &= ~0x2000;
3750         else
3751                 data |= 0x2000;
3752         if (orig != data)
3753                 WREG32(mmRLC_PG_CNTL, data);
3754 }
3755
3756 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev)
3757 {
3758         const __le32 *fw_data;
3759         volatile u32 *dst_ptr;
3760         int me, i, max_me = 4;
3761         u32 bo_offset = 0;
3762         u32 table_offset, table_size;
3763
3764         if (adev->asic_type == CHIP_KAVERI)
3765                 max_me = 5;
3766
3767         if (adev->gfx.rlc.cp_table_ptr == NULL)
3768                 return;
3769
3770         /* write the cp table buffer */
3771         dst_ptr = adev->gfx.rlc.cp_table_ptr;
3772         for (me = 0; me < max_me; me++) {
3773                 if (me == 0) {
3774                         const struct gfx_firmware_header_v1_0 *hdr =
3775                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
3776                         fw_data = (const __le32 *)
3777                                 (adev->gfx.ce_fw->data +
3778                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3779                         table_offset = le32_to_cpu(hdr->jt_offset);
3780                         table_size = le32_to_cpu(hdr->jt_size);
3781                 } else if (me == 1) {
3782                         const struct gfx_firmware_header_v1_0 *hdr =
3783                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
3784                         fw_data = (const __le32 *)
3785                                 (adev->gfx.pfp_fw->data +
3786                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3787                         table_offset = le32_to_cpu(hdr->jt_offset);
3788                         table_size = le32_to_cpu(hdr->jt_size);
3789                 } else if (me == 2) {
3790                         const struct gfx_firmware_header_v1_0 *hdr =
3791                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3792                         fw_data = (const __le32 *)
3793                                 (adev->gfx.me_fw->data +
3794                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3795                         table_offset = le32_to_cpu(hdr->jt_offset);
3796                         table_size = le32_to_cpu(hdr->jt_size);
3797                 } else if (me == 3) {
3798                         const struct gfx_firmware_header_v1_0 *hdr =
3799                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3800                         fw_data = (const __le32 *)
3801                                 (adev->gfx.mec_fw->data +
3802                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3803                         table_offset = le32_to_cpu(hdr->jt_offset);
3804                         table_size = le32_to_cpu(hdr->jt_size);
3805                 } else {
3806                         const struct gfx_firmware_header_v1_0 *hdr =
3807                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
3808                         fw_data = (const __le32 *)
3809                                 (adev->gfx.mec2_fw->data +
3810                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3811                         table_offset = le32_to_cpu(hdr->jt_offset);
3812                         table_size = le32_to_cpu(hdr->jt_size);
3813                 }
3814
3815                 for (i = 0; i < table_size; i ++) {
3816                         dst_ptr[bo_offset + i] =
3817                                 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
3818                 }
3819
3820                 bo_offset += table_size;
3821         }
3822 }
3823
3824 static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev,
3825                                      bool enable)
3826 {
3827         u32 data, orig;
3828
3829         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
3830                 orig = data = RREG32(mmRLC_PG_CNTL);
3831                 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
3832                 if (orig != data)
3833                         WREG32(mmRLC_PG_CNTL, data);
3834
3835                 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
3836                 data |= RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
3837                 if (orig != data)
3838                         WREG32(mmRLC_AUTO_PG_CTRL, data);
3839         } else {
3840                 orig = data = RREG32(mmRLC_PG_CNTL);
3841                 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
3842                 if (orig != data)
3843                         WREG32(mmRLC_PG_CNTL, data);
3844
3845                 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
3846                 data &= ~RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
3847                 if (orig != data)
3848                         WREG32(mmRLC_AUTO_PG_CTRL, data);
3849
3850                 data = RREG32(mmDB_RENDER_CONTROL);
3851         }
3852 }
3853
3854 static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev)
3855 {
3856         u32 data, mask;
3857
3858         data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
3859         data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
3860
3861         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
3862         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
3863
3864         mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_cu_per_sh);
3865
3866         return (~data) & mask;
3867 }
3868
3869 static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev)
3870 {
3871         u32 tmp;
3872
3873         WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
3874
3875         tmp = RREG32(mmRLC_MAX_PG_CU);
3876         tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
3877         tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
3878         WREG32(mmRLC_MAX_PG_CU, tmp);
3879 }
3880
3881 static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
3882                                             bool enable)
3883 {
3884         u32 data, orig;
3885
3886         orig = data = RREG32(mmRLC_PG_CNTL);
3887         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
3888                 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
3889         else
3890                 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
3891         if (orig != data)
3892                 WREG32(mmRLC_PG_CNTL, data);
3893 }
3894
3895 static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
3896                                              bool enable)
3897 {
3898         u32 data, orig;
3899
3900         orig = data = RREG32(mmRLC_PG_CNTL);
3901         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
3902                 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
3903         else
3904                 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
3905         if (orig != data)
3906                 WREG32(mmRLC_PG_CNTL, data);
3907 }
3908
3909 #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
3910 #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET    0x3D
3911
3912 static void gfx_v7_0_init_gfx_cgpg(struct amdgpu_device *adev)
3913 {
3914         u32 data, orig;
3915         u32 i;
3916
3917         if (adev->gfx.rlc.cs_data) {
3918                 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
3919                 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
3920                 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
3921                 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size);
3922         } else {
3923                 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
3924                 for (i = 0; i < 3; i++)
3925                         WREG32(mmRLC_GPM_SCRATCH_DATA, 0);
3926         }
3927         if (adev->gfx.rlc.reg_list) {
3928                 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET);
3929                 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
3930                         WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]);
3931         }
3932
3933         orig = data = RREG32(mmRLC_PG_CNTL);
3934         data |= RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK;
3935         if (orig != data)
3936                 WREG32(mmRLC_PG_CNTL, data);
3937
3938         WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
3939         WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
3940
3941         data = RREG32(mmCP_RB_WPTR_POLL_CNTL);
3942         data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
3943         data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3944         WREG32(mmCP_RB_WPTR_POLL_CNTL, data);
3945
3946         data = 0x10101010;
3947         WREG32(mmRLC_PG_DELAY, data);
3948
3949         data = RREG32(mmRLC_PG_DELAY_2);
3950         data &= ~0xff;
3951         data |= 0x3;
3952         WREG32(mmRLC_PG_DELAY_2, data);
3953
3954         data = RREG32(mmRLC_AUTO_PG_CTRL);
3955         data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
3956         data |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
3957         WREG32(mmRLC_AUTO_PG_CTRL, data);
3958
3959 }
3960
3961 static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
3962 {
3963         gfx_v7_0_enable_gfx_cgpg(adev, enable);
3964         gfx_v7_0_enable_gfx_static_mgpg(adev, enable);
3965         gfx_v7_0_enable_gfx_dynamic_mgpg(adev, enable);
3966 }
3967
3968 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev)
3969 {
3970         u32 count = 0;
3971         const struct cs_section_def *sect = NULL;
3972         const struct cs_extent_def *ext = NULL;
3973
3974         if (adev->gfx.rlc.cs_data == NULL)
3975                 return 0;
3976
3977         /* begin clear state */
3978         count += 2;
3979         /* context control state */
3980         count += 3;
3981
3982         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
3983                 for (ext = sect->section; ext->extent != NULL; ++ext) {
3984                         if (sect->id == SECT_CONTEXT)
3985                                 count += 2 + ext->reg_count;
3986                         else
3987                                 return 0;
3988                 }
3989         }
3990         /* pa_sc_raster_config/pa_sc_raster_config1 */
3991         count += 4;
3992         /* end clear state */
3993         count += 2;
3994         /* clear state */
3995         count += 2;
3996
3997         return count;
3998 }
3999
4000 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev,
4001                                     volatile u32 *buffer)
4002 {
4003         u32 count = 0, i;
4004         const struct cs_section_def *sect = NULL;
4005         const struct cs_extent_def *ext = NULL;
4006
4007         if (adev->gfx.rlc.cs_data == NULL)
4008                 return;
4009         if (buffer == NULL)
4010                 return;
4011
4012         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4013         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4014
4015         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4016         buffer[count++] = cpu_to_le32(0x80000000);
4017         buffer[count++] = cpu_to_le32(0x80000000);
4018
4019         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4020                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4021                         if (sect->id == SECT_CONTEXT) {
4022                                 buffer[count++] =
4023                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4024                                 buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
4025                                 for (i = 0; i < ext->reg_count; i++)
4026                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
4027                         } else {
4028                                 return;
4029                         }
4030                 }
4031         }
4032
4033         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
4034         buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
4035         switch (adev->asic_type) {
4036         case CHIP_BONAIRE:
4037                 buffer[count++] = cpu_to_le32(0x16000012);
4038                 buffer[count++] = cpu_to_le32(0x00000000);
4039                 break;
4040         case CHIP_KAVERI:
4041                 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4042                 buffer[count++] = cpu_to_le32(0x00000000);
4043                 break;
4044         case CHIP_KABINI:
4045         case CHIP_MULLINS:
4046                 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4047                 buffer[count++] = cpu_to_le32(0x00000000);
4048                 break;
4049         case CHIP_HAWAII:
4050                 buffer[count++] = cpu_to_le32(0x3a00161a);
4051                 buffer[count++] = cpu_to_le32(0x0000002e);
4052                 break;
4053         default:
4054                 buffer[count++] = cpu_to_le32(0x00000000);
4055                 buffer[count++] = cpu_to_le32(0x00000000);
4056                 break;
4057         }
4058
4059         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4060         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4061
4062         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4063         buffer[count++] = cpu_to_le32(0);
4064 }
4065
4066 static void gfx_v7_0_init_pg(struct amdgpu_device *adev)
4067 {
4068         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4069                               AMD_PG_SUPPORT_GFX_SMG |
4070                               AMD_PG_SUPPORT_GFX_DMG |
4071                               AMD_PG_SUPPORT_CP |
4072                               AMD_PG_SUPPORT_GDS |
4073                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
4074                 gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true);
4075                 gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true);
4076                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
4077                         gfx_v7_0_init_gfx_cgpg(adev);
4078                         gfx_v7_0_enable_cp_pg(adev, true);
4079                         gfx_v7_0_enable_gds_pg(adev, true);
4080                 }
4081                 gfx_v7_0_init_ao_cu_mask(adev);
4082                 gfx_v7_0_update_gfx_pg(adev, true);
4083         }
4084 }
4085
4086 static void gfx_v7_0_fini_pg(struct amdgpu_device *adev)
4087 {
4088         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4089                               AMD_PG_SUPPORT_GFX_SMG |
4090                               AMD_PG_SUPPORT_GFX_DMG |
4091                               AMD_PG_SUPPORT_CP |
4092                               AMD_PG_SUPPORT_GDS |
4093                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
4094                 gfx_v7_0_update_gfx_pg(adev, false);
4095                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
4096                         gfx_v7_0_enable_cp_pg(adev, false);
4097                         gfx_v7_0_enable_gds_pg(adev, false);
4098                 }
4099         }
4100 }
4101
4102 /**
4103  * gfx_v7_0_get_gpu_clock_counter - return GPU clock counter snapshot
4104  *
4105  * @adev: amdgpu_device pointer
4106  *
4107  * Fetches a GPU clock counter snapshot (SI).
4108  * Returns the 64 bit clock counter snapshot.
4109  */
4110 uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev)
4111 {
4112         uint64_t clock;
4113
4114         mutex_lock(&adev->gfx.gpu_clock_mutex);
4115         WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4116         clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
4117                 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4118         mutex_unlock(&adev->gfx.gpu_clock_mutex);
4119         return clock;
4120 }
4121
4122 static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4123                                           uint32_t vmid,
4124                                           uint32_t gds_base, uint32_t gds_size,
4125                                           uint32_t gws_base, uint32_t gws_size,
4126                                           uint32_t oa_base, uint32_t oa_size)
4127 {
4128         gds_base = gds_base >> AMDGPU_GDS_SHIFT;
4129         gds_size = gds_size >> AMDGPU_GDS_SHIFT;
4130
4131         gws_base = gws_base >> AMDGPU_GWS_SHIFT;
4132         gws_size = gws_size >> AMDGPU_GWS_SHIFT;
4133
4134         oa_base = oa_base >> AMDGPU_OA_SHIFT;
4135         oa_size = oa_size >> AMDGPU_OA_SHIFT;
4136
4137         /* GDS Base */
4138         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4139         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4140                                 WRITE_DATA_DST_SEL(0)));
4141         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
4142         amdgpu_ring_write(ring, 0);
4143         amdgpu_ring_write(ring, gds_base);
4144
4145         /* GDS Size */
4146         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4147         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4148                                 WRITE_DATA_DST_SEL(0)));
4149         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
4150         amdgpu_ring_write(ring, 0);
4151         amdgpu_ring_write(ring, gds_size);
4152
4153         /* GWS */
4154         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4155         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4156                                 WRITE_DATA_DST_SEL(0)));
4157         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
4158         amdgpu_ring_write(ring, 0);
4159         amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
4160
4161         /* OA */
4162         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4163         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4164                                 WRITE_DATA_DST_SEL(0)));
4165         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
4166         amdgpu_ring_write(ring, 0);
4167         amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
4168 }
4169
4170 static int gfx_v7_0_early_init(void *handle)
4171 {
4172         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4173
4174         adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS;
4175         adev->gfx.num_compute_rings = GFX7_NUM_COMPUTE_RINGS;
4176         gfx_v7_0_set_ring_funcs(adev);
4177         gfx_v7_0_set_irq_funcs(adev);
4178         gfx_v7_0_set_gds_init(adev);
4179
4180         return 0;
4181 }
4182
4183 static int gfx_v7_0_late_init(void *handle)
4184 {
4185         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4186         int r;
4187
4188         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4189         if (r)
4190                 return r;
4191
4192         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4193         if (r)
4194                 return r;
4195
4196         return 0;
4197 }
4198
4199 static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev)
4200 {
4201         u32 gb_addr_config;
4202         u32 mc_shared_chmap, mc_arb_ramcfg;
4203         u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
4204         u32 tmp;
4205
4206         switch (adev->asic_type) {
4207         case CHIP_BONAIRE:
4208                 adev->gfx.config.max_shader_engines = 2;
4209                 adev->gfx.config.max_tile_pipes = 4;
4210                 adev->gfx.config.max_cu_per_sh = 7;
4211                 adev->gfx.config.max_sh_per_se = 1;
4212                 adev->gfx.config.max_backends_per_se = 2;
4213                 adev->gfx.config.max_texture_channel_caches = 4;
4214                 adev->gfx.config.max_gprs = 256;
4215                 adev->gfx.config.max_gs_threads = 32;
4216                 adev->gfx.config.max_hw_contexts = 8;
4217
4218                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4219                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4220                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4221                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4222                 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4223                 break;
4224         case CHIP_HAWAII:
4225                 adev->gfx.config.max_shader_engines = 4;
4226                 adev->gfx.config.max_tile_pipes = 16;
4227                 adev->gfx.config.max_cu_per_sh = 11;
4228                 adev->gfx.config.max_sh_per_se = 1;
4229                 adev->gfx.config.max_backends_per_se = 4;
4230                 adev->gfx.config.max_texture_channel_caches = 16;
4231                 adev->gfx.config.max_gprs = 256;
4232                 adev->gfx.config.max_gs_threads = 32;
4233                 adev->gfx.config.max_hw_contexts = 8;
4234
4235                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4236                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4237                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4238                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4239                 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN;
4240                 break;
4241         case CHIP_KAVERI:
4242                 adev->gfx.config.max_shader_engines = 1;
4243                 adev->gfx.config.max_tile_pipes = 4;
4244                 if ((adev->pdev->device == 0x1304) ||
4245                     (adev->pdev->device == 0x1305) ||
4246                     (adev->pdev->device == 0x130C) ||
4247                     (adev->pdev->device == 0x130F) ||
4248                     (adev->pdev->device == 0x1310) ||
4249                     (adev->pdev->device == 0x1311) ||
4250                     (adev->pdev->device == 0x131C)) {
4251                         adev->gfx.config.max_cu_per_sh = 8;
4252                         adev->gfx.config.max_backends_per_se = 2;
4253                 } else if ((adev->pdev->device == 0x1309) ||
4254                            (adev->pdev->device == 0x130A) ||
4255                            (adev->pdev->device == 0x130D) ||
4256                            (adev->pdev->device == 0x1313) ||
4257                            (adev->pdev->device == 0x131D)) {
4258                         adev->gfx.config.max_cu_per_sh = 6;
4259                         adev->gfx.config.max_backends_per_se = 2;
4260                 } else if ((adev->pdev->device == 0x1306) ||
4261                            (adev->pdev->device == 0x1307) ||
4262                            (adev->pdev->device == 0x130B) ||
4263                            (adev->pdev->device == 0x130E) ||
4264                            (adev->pdev->device == 0x1315) ||
4265                            (adev->pdev->device == 0x131B)) {
4266                         adev->gfx.config.max_cu_per_sh = 4;
4267                         adev->gfx.config.max_backends_per_se = 1;
4268                 } else {
4269                         adev->gfx.config.max_cu_per_sh = 3;
4270                         adev->gfx.config.max_backends_per_se = 1;
4271                 }
4272                 adev->gfx.config.max_sh_per_se = 1;
4273                 adev->gfx.config.max_texture_channel_caches = 4;
4274                 adev->gfx.config.max_gprs = 256;
4275                 adev->gfx.config.max_gs_threads = 16;
4276                 adev->gfx.config.max_hw_contexts = 8;
4277
4278                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4279                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4280                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4281                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4282                 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4283                 break;
4284         case CHIP_KABINI:
4285         case CHIP_MULLINS:
4286         default:
4287                 adev->gfx.config.max_shader_engines = 1;
4288                 adev->gfx.config.max_tile_pipes = 2;
4289                 adev->gfx.config.max_cu_per_sh = 2;
4290                 adev->gfx.config.max_sh_per_se = 1;
4291                 adev->gfx.config.max_backends_per_se = 1;
4292                 adev->gfx.config.max_texture_channel_caches = 2;
4293                 adev->gfx.config.max_gprs = 256;
4294                 adev->gfx.config.max_gs_threads = 16;
4295                 adev->gfx.config.max_hw_contexts = 8;
4296
4297                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4298                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4299                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4300                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4301                 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4302                 break;
4303         }
4304
4305         mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
4306         adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
4307         mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
4308
4309         adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
4310         adev->gfx.config.mem_max_burst_length_bytes = 256;
4311         if (adev->flags & AMD_IS_APU) {
4312                 /* Get memory bank mapping mode. */
4313                 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
4314                 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4315                 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4316
4317                 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
4318                 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4319                 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4320
4321                 /* Validate settings in case only one DIMM installed. */
4322                 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
4323                         dimm00_addr_map = 0;
4324                 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
4325                         dimm01_addr_map = 0;
4326                 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
4327                         dimm10_addr_map = 0;
4328                 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
4329                         dimm11_addr_map = 0;
4330
4331                 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
4332                 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
4333                 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
4334                         adev->gfx.config.mem_row_size_in_kb = 2;
4335                 else
4336                         adev->gfx.config.mem_row_size_in_kb = 1;
4337         } else {
4338                 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
4339                 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
4340                 if (adev->gfx.config.mem_row_size_in_kb > 4)
4341                         adev->gfx.config.mem_row_size_in_kb = 4;
4342         }
4343         /* XXX use MC settings? */
4344         adev->gfx.config.shader_engine_tile_size = 32;
4345         adev->gfx.config.num_gpus = 1;
4346         adev->gfx.config.multi_gpu_tile_size = 64;
4347
4348         /* fix up row size */
4349         gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
4350         switch (adev->gfx.config.mem_row_size_in_kb) {
4351         case 1:
4352         default:
4353                 gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4354                 break;
4355         case 2:
4356                 gb_addr_config |= (1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4357                 break;
4358         case 4:
4359                 gb_addr_config |= (2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4360                 break;
4361         }
4362         adev->gfx.config.gb_addr_config = gb_addr_config;
4363 }
4364
4365 static int gfx_v7_0_sw_init(void *handle)
4366 {
4367         struct amdgpu_ring *ring;
4368         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4369         int i, r;
4370
4371         /* EOP Event */
4372         r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
4373         if (r)
4374                 return r;
4375
4376         /* Privileged reg */
4377         r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
4378         if (r)
4379                 return r;
4380
4381         /* Privileged inst */
4382         r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
4383         if (r)
4384                 return r;
4385
4386         gfx_v7_0_scratch_init(adev);
4387
4388         r = gfx_v7_0_init_microcode(adev);
4389         if (r) {
4390                 DRM_ERROR("Failed to load gfx firmware!\n");
4391                 return r;
4392         }
4393
4394         r = gfx_v7_0_rlc_init(adev);
4395         if (r) {
4396                 DRM_ERROR("Failed to init rlc BOs!\n");
4397                 return r;
4398         }
4399
4400         /* allocate mec buffers */
4401         r = gfx_v7_0_mec_init(adev);
4402         if (r) {
4403                 DRM_ERROR("Failed to init MEC BOs!\n");
4404                 return r;
4405         }
4406
4407         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4408                 ring = &adev->gfx.gfx_ring[i];
4409                 ring->ring_obj = NULL;
4410                 sprintf(ring->name, "gfx");
4411                 r = amdgpu_ring_init(adev, ring, 1024,
4412                                      PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
4413                                      &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
4414                                      AMDGPU_RING_TYPE_GFX);
4415                 if (r)
4416                         return r;
4417         }
4418
4419         /* set up the compute queues */
4420         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4421                 unsigned irq_type;
4422
4423                 /* max 32 queues per MEC */
4424                 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
4425                         DRM_ERROR("Too many (%d) compute rings!\n", i);
4426                         break;
4427                 }
4428                 ring = &adev->gfx.compute_ring[i];
4429                 ring->ring_obj = NULL;
4430                 ring->use_doorbell = true;
4431                 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i;
4432                 ring->me = 1; /* first MEC */
4433                 ring->pipe = i / 8;
4434                 ring->queue = i % 8;
4435                 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4436                 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
4437                 /* type-2 packets are deprecated on MEC, use type-3 instead */
4438                 r = amdgpu_ring_init(adev, ring, 1024,
4439                                      PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
4440                                      &adev->gfx.eop_irq, irq_type,
4441                                      AMDGPU_RING_TYPE_COMPUTE);
4442                 if (r)
4443                         return r;
4444         }
4445
4446         /* reserve GDS, GWS and OA resource for gfx */
4447         r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size,
4448                         PAGE_SIZE, true,
4449                         AMDGPU_GEM_DOMAIN_GDS, 0,
4450                         NULL, NULL, &adev->gds.gds_gfx_bo);
4451         if (r)
4452                 return r;
4453
4454         r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size,
4455                 PAGE_SIZE, true,
4456                 AMDGPU_GEM_DOMAIN_GWS, 0,
4457                 NULL, NULL, &adev->gds.gws_gfx_bo);
4458         if (r)
4459                 return r;
4460
4461         r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size,
4462                         PAGE_SIZE, true,
4463                         AMDGPU_GEM_DOMAIN_OA, 0,
4464                         NULL, NULL, &adev->gds.oa_gfx_bo);
4465         if (r)
4466                 return r;
4467
4468         adev->gfx.ce_ram_size = 0x8000;
4469
4470         gfx_v7_0_gpu_early_init(adev);
4471
4472         return r;
4473 }
4474
4475 static int gfx_v7_0_sw_fini(void *handle)
4476 {
4477         int i;
4478         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4479
4480         amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
4481         amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
4482         amdgpu_bo_unref(&adev->gds.gds_gfx_bo);
4483
4484         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4485                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4486         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4487                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4488
4489         gfx_v7_0_cp_compute_fini(adev);
4490         gfx_v7_0_rlc_fini(adev);
4491         gfx_v7_0_mec_fini(adev);
4492
4493         return 0;
4494 }
4495
4496 static int gfx_v7_0_hw_init(void *handle)
4497 {
4498         int r;
4499         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4500
4501         gfx_v7_0_gpu_init(adev);
4502
4503         /* init rlc */
4504         r = gfx_v7_0_rlc_resume(adev);
4505         if (r)
4506                 return r;
4507
4508         r = gfx_v7_0_cp_resume(adev);
4509         if (r)
4510                 return r;
4511
4512         return r;
4513 }
4514
4515 static int gfx_v7_0_hw_fini(void *handle)
4516 {
4517         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4518
4519         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4520         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
4521         gfx_v7_0_cp_enable(adev, false);
4522         gfx_v7_0_rlc_stop(adev);
4523         gfx_v7_0_fini_pg(adev);
4524
4525         return 0;
4526 }
4527
4528 static int gfx_v7_0_suspend(void *handle)
4529 {
4530         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4531
4532         return gfx_v7_0_hw_fini(adev);
4533 }
4534
4535 static int gfx_v7_0_resume(void *handle)
4536 {
4537         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4538
4539         return gfx_v7_0_hw_init(adev);
4540 }
4541
4542 static bool gfx_v7_0_is_idle(void *handle)
4543 {
4544         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4545
4546         if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
4547                 return false;
4548         else
4549                 return true;
4550 }
4551
4552 static int gfx_v7_0_wait_for_idle(void *handle)
4553 {
4554         unsigned i;
4555         u32 tmp;
4556         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4557
4558         for (i = 0; i < adev->usec_timeout; i++) {
4559                 /* read MC_STATUS */
4560                 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
4561
4562                 if (!tmp)
4563                         return 0;
4564                 udelay(1);
4565         }
4566         return -ETIMEDOUT;
4567 }
4568
4569 static int gfx_v7_0_soft_reset(void *handle)
4570 {
4571         u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
4572         u32 tmp;
4573         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4574
4575         /* GRBM_STATUS */
4576         tmp = RREG32(mmGRBM_STATUS);
4577         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
4578                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
4579                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
4580                    GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
4581                    GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
4582                    GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK))
4583                 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK |
4584                         GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK;
4585
4586         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
4587                 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK;
4588                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4589         }
4590
4591         /* GRBM_STATUS2 */
4592         tmp = RREG32(mmGRBM_STATUS2);
4593         if (tmp & GRBM_STATUS2__RLC_BUSY_MASK)
4594                 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
4595
4596         /* SRBM_STATUS */
4597         tmp = RREG32(mmSRBM_STATUS);
4598         if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK)
4599                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4600
4601         if (grbm_soft_reset || srbm_soft_reset) {
4602                 /* disable CG/PG */
4603                 gfx_v7_0_fini_pg(adev);
4604                 gfx_v7_0_update_cg(adev, false);
4605
4606                 /* stop the rlc */
4607                 gfx_v7_0_rlc_stop(adev);
4608
4609                 /* Disable GFX parsing/prefetching */
4610                 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);
4611
4612                 /* Disable MEC parsing/prefetching */
4613                 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);
4614
4615                 if (grbm_soft_reset) {
4616                         tmp = RREG32(mmGRBM_SOFT_RESET);
4617                         tmp |= grbm_soft_reset;
4618                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
4619                         WREG32(mmGRBM_SOFT_RESET, tmp);
4620                         tmp = RREG32(mmGRBM_SOFT_RESET);
4621
4622                         udelay(50);
4623
4624                         tmp &= ~grbm_soft_reset;
4625                         WREG32(mmGRBM_SOFT_RESET, tmp);
4626                         tmp = RREG32(mmGRBM_SOFT_RESET);
4627                 }
4628
4629                 if (srbm_soft_reset) {
4630                         tmp = RREG32(mmSRBM_SOFT_RESET);
4631                         tmp |= srbm_soft_reset;
4632                         dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
4633                         WREG32(mmSRBM_SOFT_RESET, tmp);
4634                         tmp = RREG32(mmSRBM_SOFT_RESET);
4635
4636                         udelay(50);
4637
4638                         tmp &= ~srbm_soft_reset;
4639                         WREG32(mmSRBM_SOFT_RESET, tmp);
4640                         tmp = RREG32(mmSRBM_SOFT_RESET);
4641                 }
4642                 /* Wait a little for things to settle down */
4643                 udelay(50);
4644         }
4645         return 0;
4646 }
4647
4648 static void gfx_v7_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4649                                                  enum amdgpu_interrupt_state state)
4650 {
4651         u32 cp_int_cntl;
4652
4653         switch (state) {
4654         case AMDGPU_IRQ_STATE_DISABLE:
4655                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4656                 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4657                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4658                 break;
4659         case AMDGPU_IRQ_STATE_ENABLE:
4660                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4661                 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4662                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4663                 break;
4664         default:
4665                 break;
4666         }
4667 }
4668
4669 static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4670                                                      int me, int pipe,
4671                                                      enum amdgpu_interrupt_state state)
4672 {
4673         u32 mec_int_cntl, mec_int_cntl_reg;
4674
4675         /*
4676          * amdgpu controls only pipe 0 of MEC1. That's why this function only
4677          * handles the setting of interrupts for this specific pipe. All other
4678          * pipes' interrupts are set by amdkfd.
4679          */
4680
4681         if (me == 1) {
4682                 switch (pipe) {
4683                 case 0:
4684                         mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
4685                         break;
4686                 default:
4687                         DRM_DEBUG("invalid pipe %d\n", pipe);
4688                         return;
4689                 }
4690         } else {
4691                 DRM_DEBUG("invalid me %d\n", me);
4692                 return;
4693         }
4694
4695         switch (state) {
4696         case AMDGPU_IRQ_STATE_DISABLE:
4697                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4698                 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4699                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4700                 break;
4701         case AMDGPU_IRQ_STATE_ENABLE:
4702                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4703                 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4704                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4705                 break;
4706         default:
4707                 break;
4708         }
4709 }
4710
4711 static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4712                                              struct amdgpu_irq_src *src,
4713                                              unsigned type,
4714                                              enum amdgpu_interrupt_state state)
4715 {
4716         u32 cp_int_cntl;
4717
4718         switch (state) {
4719         case AMDGPU_IRQ_STATE_DISABLE:
4720                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4721                 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
4722                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4723                 break;
4724         case AMDGPU_IRQ_STATE_ENABLE:
4725                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4726                 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
4727                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4728                 break;
4729         default:
4730                 break;
4731         }
4732
4733         return 0;
4734 }
4735
4736 static int gfx_v7_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4737                                               struct amdgpu_irq_src *src,
4738                                               unsigned type,
4739                                               enum amdgpu_interrupt_state state)
4740 {
4741         u32 cp_int_cntl;
4742
4743         switch (state) {
4744         case AMDGPU_IRQ_STATE_DISABLE:
4745                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4746                 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
4747                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4748                 break;
4749         case AMDGPU_IRQ_STATE_ENABLE:
4750                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4751                 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
4752                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4753                 break;
4754         default:
4755                 break;
4756         }
4757
4758         return 0;
4759 }
4760
4761 static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4762                                             struct amdgpu_irq_src *src,
4763                                             unsigned type,
4764                                             enum amdgpu_interrupt_state state)
4765 {
4766         switch (type) {
4767         case AMDGPU_CP_IRQ_GFX_EOP:
4768                 gfx_v7_0_set_gfx_eop_interrupt_state(adev, state);
4769                 break;
4770         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4771                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4772                 break;
4773         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4774                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4775                 break;
4776         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4777                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4778                 break;
4779         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4780                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4781                 break;
4782         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4783                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4784                 break;
4785         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4786                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4787                 break;
4788         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4789                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4790                 break;
4791         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4792                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4793                 break;
4794         default:
4795                 break;
4796         }
4797         return 0;
4798 }
4799
4800 static int gfx_v7_0_eop_irq(struct amdgpu_device *adev,
4801                             struct amdgpu_irq_src *source,
4802                             struct amdgpu_iv_entry *entry)
4803 {
4804         u8 me_id, pipe_id;
4805         struct amdgpu_ring *ring;
4806         int i;
4807
4808         DRM_DEBUG("IH: CP EOP\n");
4809         me_id = (entry->ring_id & 0x0c) >> 2;
4810         pipe_id = (entry->ring_id & 0x03) >> 0;
4811         switch (me_id) {
4812         case 0:
4813                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4814                 break;
4815         case 1:
4816         case 2:
4817                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4818                         ring = &adev->gfx.compute_ring[i];
4819                         if ((ring->me == me_id) & (ring->pipe == pipe_id))
4820                                 amdgpu_fence_process(ring);
4821                 }
4822                 break;
4823         }
4824         return 0;
4825 }
4826
4827 static int gfx_v7_0_priv_reg_irq(struct amdgpu_device *adev,
4828                                  struct amdgpu_irq_src *source,
4829                                  struct amdgpu_iv_entry *entry)
4830 {
4831         DRM_ERROR("Illegal register access in command stream\n");
4832         schedule_work(&adev->reset_work);
4833         return 0;
4834 }
4835
4836 static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev,
4837                                   struct amdgpu_irq_src *source,
4838                                   struct amdgpu_iv_entry *entry)
4839 {
4840         DRM_ERROR("Illegal instruction in command stream\n");
4841         // XXX soft reset the gfx block only
4842         schedule_work(&adev->reset_work);
4843         return 0;
4844 }
4845
4846 static int gfx_v7_0_set_clockgating_state(void *handle,
4847                                           enum amd_clockgating_state state)
4848 {
4849         bool gate = false;
4850         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4851
4852         if (state == AMD_CG_STATE_GATE)
4853                 gate = true;
4854
4855         gfx_v7_0_enable_gui_idle_interrupt(adev, false);
4856         /* order matters! */
4857         if (gate) {
4858                 gfx_v7_0_enable_mgcg(adev, true);
4859                 gfx_v7_0_enable_cgcg(adev, true);
4860         } else {
4861                 gfx_v7_0_enable_cgcg(adev, false);
4862                 gfx_v7_0_enable_mgcg(adev, false);
4863         }
4864         gfx_v7_0_enable_gui_idle_interrupt(adev, true);
4865
4866         return 0;
4867 }
4868
4869 static int gfx_v7_0_set_powergating_state(void *handle,
4870                                           enum amd_powergating_state state)
4871 {
4872         bool gate = false;
4873         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4874
4875         if (state == AMD_PG_STATE_GATE)
4876                 gate = true;
4877
4878         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4879                               AMD_PG_SUPPORT_GFX_SMG |
4880                               AMD_PG_SUPPORT_GFX_DMG |
4881                               AMD_PG_SUPPORT_CP |
4882                               AMD_PG_SUPPORT_GDS |
4883                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
4884                 gfx_v7_0_update_gfx_pg(adev, gate);
4885                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
4886                         gfx_v7_0_enable_cp_pg(adev, gate);
4887                         gfx_v7_0_enable_gds_pg(adev, gate);
4888                 }
4889         }
4890
4891         return 0;
4892 }
4893
4894 const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
4895         .name = "gfx_v7_0",
4896         .early_init = gfx_v7_0_early_init,
4897         .late_init = gfx_v7_0_late_init,
4898         .sw_init = gfx_v7_0_sw_init,
4899         .sw_fini = gfx_v7_0_sw_fini,
4900         .hw_init = gfx_v7_0_hw_init,
4901         .hw_fini = gfx_v7_0_hw_fini,
4902         .suspend = gfx_v7_0_suspend,
4903         .resume = gfx_v7_0_resume,
4904         .is_idle = gfx_v7_0_is_idle,
4905         .wait_for_idle = gfx_v7_0_wait_for_idle,
4906         .soft_reset = gfx_v7_0_soft_reset,
4907         .set_clockgating_state = gfx_v7_0_set_clockgating_state,
4908         .set_powergating_state = gfx_v7_0_set_powergating_state,
4909 };
4910
4911 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
4912         .get_rptr = gfx_v7_0_ring_get_rptr_gfx,
4913         .get_wptr = gfx_v7_0_ring_get_wptr_gfx,
4914         .set_wptr = gfx_v7_0_ring_set_wptr_gfx,
4915         .parse_cs = NULL,
4916         .emit_ib = gfx_v7_0_ring_emit_ib_gfx,
4917         .emit_fence = gfx_v7_0_ring_emit_fence_gfx,
4918         .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
4919         .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
4920         .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
4921         .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
4922         .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate,
4923         .test_ring = gfx_v7_0_ring_test_ring,
4924         .test_ib = gfx_v7_0_ring_test_ib,
4925         .insert_nop = amdgpu_ring_insert_nop,
4926         .pad_ib = amdgpu_ring_generic_pad_ib,
4927 };
4928
4929 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
4930         .get_rptr = gfx_v7_0_ring_get_rptr_compute,
4931         .get_wptr = gfx_v7_0_ring_get_wptr_compute,
4932         .set_wptr = gfx_v7_0_ring_set_wptr_compute,
4933         .parse_cs = NULL,
4934         .emit_ib = gfx_v7_0_ring_emit_ib_compute,
4935         .emit_fence = gfx_v7_0_ring_emit_fence_compute,
4936         .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
4937         .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
4938         .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
4939         .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
4940         .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate,
4941         .test_ring = gfx_v7_0_ring_test_ring,
4942         .test_ib = gfx_v7_0_ring_test_ib,
4943         .insert_nop = amdgpu_ring_insert_nop,
4944         .pad_ib = amdgpu_ring_generic_pad_ib,
4945 };
4946
4947 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev)
4948 {
4949         int i;
4950
4951         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4952                 adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx;
4953         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4954                 adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute;
4955 }
4956
4957 static const struct amdgpu_irq_src_funcs gfx_v7_0_eop_irq_funcs = {
4958         .set = gfx_v7_0_set_eop_interrupt_state,
4959         .process = gfx_v7_0_eop_irq,
4960 };
4961
4962 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_reg_irq_funcs = {
4963         .set = gfx_v7_0_set_priv_reg_fault_state,
4964         .process = gfx_v7_0_priv_reg_irq,
4965 };
4966
4967 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_inst_irq_funcs = {
4968         .set = gfx_v7_0_set_priv_inst_fault_state,
4969         .process = gfx_v7_0_priv_inst_irq,
4970 };
4971
4972 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev)
4973 {
4974         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4975         adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs;
4976
4977         adev->gfx.priv_reg_irq.num_types = 1;
4978         adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs;
4979
4980         adev->gfx.priv_inst_irq.num_types = 1;
4981         adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs;
4982 }
4983
4984 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev)
4985 {
4986         /* init asci gds info */
4987         adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
4988         adev->gds.gws.total_size = 64;
4989         adev->gds.oa.total_size = 16;
4990
4991         if (adev->gds.mem.total_size == 64 * 1024) {
4992                 adev->gds.mem.gfx_partition_size = 4096;
4993                 adev->gds.mem.cs_partition_size = 4096;
4994
4995                 adev->gds.gws.gfx_partition_size = 4;
4996                 adev->gds.gws.cs_partition_size = 4;
4997
4998                 adev->gds.oa.gfx_partition_size = 4;
4999                 adev->gds.oa.cs_partition_size = 1;
5000         } else {
5001                 adev->gds.mem.gfx_partition_size = 1024;
5002                 adev->gds.mem.cs_partition_size = 1024;
5003
5004                 adev->gds.gws.gfx_partition_size = 16;
5005                 adev->gds.gws.cs_partition_size = 16;
5006
5007                 adev->gds.oa.gfx_partition_size = 4;
5008                 adev->gds.oa.cs_partition_size = 4;
5009         }
5010 }
5011
5012
5013 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev)
5014 {
5015         int i, j, k, counter, active_cu_number = 0;
5016         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
5017         struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
5018
5019         memset(cu_info, 0, sizeof(*cu_info));
5020
5021         mutex_lock(&adev->grbm_idx_mutex);
5022         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5023                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5024                         mask = 1;
5025                         ao_bitmap = 0;
5026                         counter = 0;
5027                         gfx_v7_0_select_se_sh(adev, i, j);
5028                         bitmap = gfx_v7_0_get_cu_active_bitmap(adev);
5029                         cu_info->bitmap[i][j] = bitmap;
5030
5031                         for (k = 0; k < 16; k ++) {
5032                                 if (bitmap & mask) {
5033                                         if (counter < 2)
5034                                                 ao_bitmap |= mask;
5035                                         counter ++;
5036                                 }
5037                                 mask <<= 1;
5038                         }
5039                         active_cu_number += counter;
5040                         ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
5041                 }
5042         }
5043         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
5044         mutex_unlock(&adev->grbm_idx_mutex);
5045
5046         cu_info->number = active_cu_number;
5047         cu_info->ao_cu_mask = ao_cu_mask;
5048 }