drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include "drmP.h"
  25 #include "amdgpu.h"
  26 #include "amdgpu_ih.h"
  27 #include "amdgpu_gfx.h"
  28 #include "cikd.h"
  29 #include "cik.h"
  30 #include "atom.h"
  31 #include "amdgpu_ucode.h"
  32 #include "clearstate_ci.h"
  33
  34 #include "dce/dce_8_0_d.h"
  35 #include "dce/dce_8_0_sh_mask.h"
  36
  37 #include "bif/bif_4_1_d.h"
  38 #include "bif/bif_4_1_sh_mask.h"
  39
  40 #include "gca/gfx_7_0_d.h"
  41 #include "gca/gfx_7_2_enum.h"
  42 #include "gca/gfx_7_2_sh_mask.h"
  43
  44 #include "gmc/gmc_7_0_d.h"
  45 #include "gmc/gmc_7_0_sh_mask.h"
  46
  47 #include "oss/oss_2_0_d.h"
  48 #include "oss/oss_2_0_sh_mask.h"
  49
  50 #define GFX7_NUM_GFX_RINGS     1
  51 #define GFX7_NUM_COMPUTE_RINGS 8
  52
  53 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev);
  54 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev);
  55 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev);
  56
  57 MODULE_FIRMWARE("radeon/bonaire_pfp.bin");
  58 MODULE_FIRMWARE("radeon/bonaire_me.bin");
  59 MODULE_FIRMWARE("radeon/bonaire_ce.bin");
  60 MODULE_FIRMWARE("radeon/bonaire_rlc.bin");
  61 MODULE_FIRMWARE("radeon/bonaire_mec.bin");
  62
  63 MODULE_FIRMWARE("radeon/hawaii_pfp.bin");
  64 MODULE_FIRMWARE("radeon/hawaii_me.bin");
  65 MODULE_FIRMWARE("radeon/hawaii_ce.bin");
  66 MODULE_FIRMWARE("radeon/hawaii_rlc.bin");
  67 MODULE_FIRMWARE("radeon/hawaii_mec.bin");
  68
  69 MODULE_FIRMWARE("radeon/kaveri_pfp.bin");
  70 MODULE_FIRMWARE("radeon/kaveri_me.bin");
  71 MODULE_FIRMWARE("radeon/kaveri_ce.bin");
  72 MODULE_FIRMWARE("radeon/kaveri_rlc.bin");
  73 MODULE_FIRMWARE("radeon/kaveri_mec.bin");
  74 MODULE_FIRMWARE("radeon/kaveri_mec2.bin");
  75
  76 MODULE_FIRMWARE("radeon/kabini_pfp.bin");
  77 MODULE_FIRMWARE("radeon/kabini_me.bin");
  78 MODULE_FIRMWARE("radeon/kabini_ce.bin");
  79 MODULE_FIRMWARE("radeon/kabini_rlc.bin");
  80 MODULE_FIRMWARE("radeon/kabini_mec.bin");
  81
  82 MODULE_FIRMWARE("radeon/mullins_pfp.bin");
  83 MODULE_FIRMWARE("radeon/mullins_me.bin");
  84 MODULE_FIRMWARE("radeon/mullins_ce.bin");
  85 MODULE_FIRMWARE("radeon/mullins_rlc.bin");
  86 MODULE_FIRMWARE("radeon/mullins_mec.bin");
  87
  88 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
  89 {
  90         {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
  91         {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
  92         {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
  93         {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
  94         {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
  95         {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
  96         {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
  97         {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
  98         {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
  99         {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
 100         {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
 101         {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
 102         {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
 103         {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
 104         {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
 105         {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
 106 };
 107
 108 static const u32 spectre_rlc_save_restore_register_list[] =
 109 {
 110         (0x0e00 << 16) | (0xc12c >> 2),
 111         0x00000000,
 112         (0x0e00 << 16) | (0xc140 >> 2),
 113         0x00000000,
 114         (0x0e00 << 16) | (0xc150 >> 2),
 115         0x00000000,
 116         (0x0e00 << 16) | (0xc15c >> 2),
 117         0x00000000,
 118         (0x0e00 << 16) | (0xc168 >> 2),
 119         0x00000000,
 120         (0x0e00 << 16) | (0xc170 >> 2),
 121         0x00000000,
 122         (0x0e00 << 16) | (0xc178 >> 2),
 123         0x00000000,
 124         (0x0e00 << 16) | (0xc204 >> 2),
 125         0x00000000,
 126         (0x0e00 << 16) | (0xc2b4 >> 2),
 127         0x00000000,
 128         (0x0e00 << 16) | (0xc2b8 >> 2),
 129         0x00000000,
 130         (0x0e00 << 16) | (0xc2bc >> 2),
 131         0x00000000,
 132         (0x0e00 << 16) | (0xc2c0 >> 2),
 133         0x00000000,
 134         (0x0e00 << 16) | (0x8228 >> 2),
 135         0x00000000,
 136         (0x0e00 << 16) | (0x829c >> 2),
 137         0x00000000,
 138         (0x0e00 << 16) | (0x869c >> 2),
 139         0x00000000,
 140         (0x0600 << 16) | (0x98f4 >> 2),
 141         0x00000000,
 142         (0x0e00 << 16) | (0x98f8 >> 2),
 143         0x00000000,
 144         (0x0e00 << 16) | (0x9900 >> 2),
 145         0x00000000,
 146         (0x0e00 << 16) | (0xc260 >> 2),
 147         0x00000000,
 148         (0x0e00 << 16) | (0x90e8 >> 2),
 149         0x00000000,
 150         (0x0e00 << 16) | (0x3c000 >> 2),
 151         0x00000000,
 152         (0x0e00 << 16) | (0x3c00c >> 2),
 153         0x00000000,
 154         (0x0e00 << 16) | (0x8c1c >> 2),
 155         0x00000000,
 156         (0x0e00 << 16) | (0x9700 >> 2),
 157         0x00000000,
 158         (0x0e00 << 16) | (0xcd20 >> 2),
 159         0x00000000,
 160         (0x4e00 << 16) | (0xcd20 >> 2),
 161         0x00000000,
 162         (0x5e00 << 16) | (0xcd20 >> 2),
 163         0x00000000,
 164         (0x6e00 << 16) | (0xcd20 >> 2),
 165         0x00000000,
 166         (0x7e00 << 16) | (0xcd20 >> 2),
 167         0x00000000,
 168         (0x8e00 << 16) | (0xcd20 >> 2),
 169         0x00000000,
 170         (0x9e00 << 16) | (0xcd20 >> 2),
 171         0x00000000,
 172         (0xae00 << 16) | (0xcd20 >> 2),
 173         0x00000000,
 174         (0xbe00 << 16) | (0xcd20 >> 2),
 175         0x00000000,
 176         (0x0e00 << 16) | (0x89bc >> 2),
 177         0x00000000,
 178         (0x0e00 << 16) | (0x8900 >> 2),
 179         0x00000000,
 180         0x3,
 181         (0x0e00 << 16) | (0xc130 >> 2),
 182         0x00000000,
 183         (0x0e00 << 16) | (0xc134 >> 2),
 184         0x00000000,
 185         (0x0e00 << 16) | (0xc1fc >> 2),
 186         0x00000000,
 187         (0x0e00 << 16) | (0xc208 >> 2),
 188         0x00000000,
 189         (0x0e00 << 16) | (0xc264 >> 2),
 190         0x00000000,
 191         (0x0e00 << 16) | (0xc268 >> 2),
 192         0x00000000,
 193         (0x0e00 << 16) | (0xc26c >> 2),
 194         0x00000000,
 195         (0x0e00 << 16) | (0xc270 >> 2),
 196         0x00000000,
 197         (0x0e00 << 16) | (0xc274 >> 2),
 198         0x00000000,
 199         (0x0e00 << 16) | (0xc278 >> 2),
 200         0x00000000,
 201         (0x0e00 << 16) | (0xc27c >> 2),
 202         0x00000000,
 203         (0x0e00 << 16) | (0xc280 >> 2),
 204         0x00000000,
 205         (0x0e00 << 16) | (0xc284 >> 2),
 206         0x00000000,
 207         (0x0e00 << 16) | (0xc288 >> 2),
 208         0x00000000,
 209         (0x0e00 << 16) | (0xc28c >> 2),
 210         0x00000000,
 211         (0x0e00 << 16) | (0xc290 >> 2),
 212         0x00000000,
 213         (0x0e00 << 16) | (0xc294 >> 2),
 214         0x00000000,
 215         (0x0e00 << 16) | (0xc298 >> 2),
 216         0x00000000,
 217         (0x0e00 << 16) | (0xc29c >> 2),
 218         0x00000000,
 219         (0x0e00 << 16) | (0xc2a0 >> 2),
 220         0x00000000,
 221         (0x0e00 << 16) | (0xc2a4 >> 2),
 222         0x00000000,
 223         (0x0e00 << 16) | (0xc2a8 >> 2),
 224         0x00000000,
 225         (0x0e00 << 16) | (0xc2ac  >> 2),
 226         0x00000000,
 227         (0x0e00 << 16) | (0xc2b0 >> 2),
 228         0x00000000,
 229         (0x0e00 << 16) | (0x301d0 >> 2),
 230         0x00000000,
 231         (0x0e00 << 16) | (0x30238 >> 2),
 232         0x00000000,
 233         (0x0e00 << 16) | (0x30250 >> 2),
 234         0x00000000,
 235         (0x0e00 << 16) | (0x30254 >> 2),
 236         0x00000000,
 237         (0x0e00 << 16) | (0x30258 >> 2),
 238         0x00000000,
 239         (0x0e00 << 16) | (0x3025c >> 2),
 240         0x00000000,
 241         (0x4e00 << 16) | (0xc900 >> 2),
 242         0x00000000,
 243         (0x5e00 << 16) | (0xc900 >> 2),
 244         0x00000000,
 245         (0x6e00 << 16) | (0xc900 >> 2),
 246         0x00000000,
 247         (0x7e00 << 16) | (0xc900 >> 2),
 248         0x00000000,
 249         (0x8e00 << 16) | (0xc900 >> 2),
 250         0x00000000,
 251         (0x9e00 << 16) | (0xc900 >> 2),
 252         0x00000000,
 253         (0xae00 << 16) | (0xc900 >> 2),
 254         0x00000000,
 255         (0xbe00 << 16) | (0xc900 >> 2),
 256         0x00000000,
 257         (0x4e00 << 16) | (0xc904 >> 2),
 258         0x00000000,
 259         (0x5e00 << 16) | (0xc904 >> 2),
 260         0x00000000,
 261         (0x6e00 << 16) | (0xc904 >> 2),
 262         0x00000000,
 263         (0x7e00 << 16) | (0xc904 >> 2),
 264         0x00000000,
 265         (0x8e00 << 16) | (0xc904 >> 2),
 266         0x00000000,
 267         (0x9e00 << 16) | (0xc904 >> 2),
 268         0x00000000,
 269         (0xae00 << 16) | (0xc904 >> 2),
 270         0x00000000,
 271         (0xbe00 << 16) | (0xc904 >> 2),
 272         0x00000000,
 273         (0x4e00 << 16) | (0xc908 >> 2),
 274         0x00000000,
 275         (0x5e00 << 16) | (0xc908 >> 2),
 276         0x00000000,
 277         (0x6e00 << 16) | (0xc908 >> 2),
 278         0x00000000,
 279         (0x7e00 << 16) | (0xc908 >> 2),
 280         0x00000000,
 281         (0x8e00 << 16) | (0xc908 >> 2),
 282         0x00000000,
 283         (0x9e00 << 16) | (0xc908 >> 2),
 284         0x00000000,
 285         (0xae00 << 16) | (0xc908 >> 2),
 286         0x00000000,
 287         (0xbe00 << 16) | (0xc908 >> 2),
 288         0x00000000,
 289         (0x4e00 << 16) | (0xc90c >> 2),
 290         0x00000000,
 291         (0x5e00 << 16) | (0xc90c >> 2),
 292         0x00000000,
 293         (0x6e00 << 16) | (0xc90c >> 2),
 294         0x00000000,
 295         (0x7e00 << 16) | (0xc90c >> 2),
 296         0x00000000,
 297         (0x8e00 << 16) | (0xc90c >> 2),
 298         0x00000000,
 299         (0x9e00 << 16) | (0xc90c >> 2),
 300         0x00000000,
 301         (0xae00 << 16) | (0xc90c >> 2),
 302         0x00000000,
 303         (0xbe00 << 16) | (0xc90c >> 2),
 304         0x00000000,
 305         (0x4e00 << 16) | (0xc910 >> 2),
 306         0x00000000,
 307         (0x5e00 << 16) | (0xc910 >> 2),
 308         0x00000000,
 309         (0x6e00 << 16) | (0xc910 >> 2),
 310         0x00000000,
 311         (0x7e00 << 16) | (0xc910 >> 2),
 312         0x00000000,
 313         (0x8e00 << 16) | (0xc910 >> 2),
 314         0x00000000,
 315         (0x9e00 << 16) | (0xc910 >> 2),
 316         0x00000000,
 317         (0xae00 << 16) | (0xc910 >> 2),
 318         0x00000000,
 319         (0xbe00 << 16) | (0xc910 >> 2),
 320         0x00000000,
 321         (0x0e00 << 16) | (0xc99c >> 2),
 322         0x00000000,
 323         (0x0e00 << 16) | (0x9834 >> 2),
 324         0x00000000,
 325         (0x0000 << 16) | (0x30f00 >> 2),
 326         0x00000000,
 327         (0x0001 << 16) | (0x30f00 >> 2),
 328         0x00000000,
 329         (0x0000 << 16) | (0x30f04 >> 2),
 330         0x00000000,
 331         (0x0001 << 16) | (0x30f04 >> 2),
 332         0x00000000,
 333         (0x0000 << 16) | (0x30f08 >> 2),
 334         0x00000000,
 335         (0x0001 << 16) | (0x30f08 >> 2),
 336         0x00000000,
 337         (0x0000 << 16) | (0x30f0c >> 2),
 338         0x00000000,
 339         (0x0001 << 16) | (0x30f0c >> 2),
 340         0x00000000,
 341         (0x0600 << 16) | (0x9b7c >> 2),
 342         0x00000000,
 343         (0x0e00 << 16) | (0x8a14 >> 2),
 344         0x00000000,
 345         (0x0e00 << 16) | (0x8a18 >> 2),
 346         0x00000000,
 347         (0x0600 << 16) | (0x30a00 >> 2),
 348         0x00000000,
 349         (0x0e00 << 16) | (0x8bf0 >> 2),
 350         0x00000000,
 351         (0x0e00 << 16) | (0x8bcc >> 2),
 352         0x00000000,
 353         (0x0e00 << 16) | (0x8b24 >> 2),
 354         0x00000000,
 355         (0x0e00 << 16) | (0x30a04 >> 2),
 356         0x00000000,
 357         (0x0600 << 16) | (0x30a10 >> 2),
 358         0x00000000,
 359         (0x0600 << 16) | (0x30a14 >> 2),
 360         0x00000000,
 361         (0x0600 << 16) | (0x30a18 >> 2),
 362         0x00000000,
 363         (0x0600 << 16) | (0x30a2c >> 2),
 364         0x00000000,
 365         (0x0e00 << 16) | (0xc700 >> 2),
 366         0x00000000,
 367         (0x0e00 << 16) | (0xc704 >> 2),
 368         0x00000000,
 369         (0x0e00 << 16) | (0xc708 >> 2),
 370         0x00000000,
 371         (0x0e00 << 16) | (0xc768 >> 2),
 372         0x00000000,
 373         (0x0400 << 16) | (0xc770 >> 2),
 374         0x00000000,
 375         (0x0400 << 16) | (0xc774 >> 2),
 376         0x00000000,
 377         (0x0400 << 16) | (0xc778 >> 2),
 378         0x00000000,
 379         (0x0400 << 16) | (0xc77c >> 2),
 380         0x00000000,
 381         (0x0400 << 16) | (0xc780 >> 2),
 382         0x00000000,
 383         (0x0400 << 16) | (0xc784 >> 2),
 384         0x00000000,
 385         (0x0400 << 16) | (0xc788 >> 2),
 386         0x00000000,
 387         (0x0400 << 16) | (0xc78c >> 2),
 388         0x00000000,
 389         (0x0400 << 16) | (0xc798 >> 2),
 390         0x00000000,
 391         (0x0400 << 16) | (0xc79c >> 2),
 392         0x00000000,
 393         (0x0400 << 16) | (0xc7a0 >> 2),
 394         0x00000000,
 395         (0x0400 << 16) | (0xc7a4 >> 2),
 396         0x00000000,
 397         (0x0400 << 16) | (0xc7a8 >> 2),
 398         0x00000000,
 399         (0x0400 << 16) | (0xc7ac >> 2),
 400         0x00000000,
 401         (0x0400 << 16) | (0xc7b0 >> 2),
 402         0x00000000,
 403         (0x0400 << 16) | (0xc7b4 >> 2),
 404         0x00000000,
 405         (0x0e00 << 16) | (0x9100 >> 2),
 406         0x00000000,
 407         (0x0e00 << 16) | (0x3c010 >> 2),
 408         0x00000000,
 409         (0x0e00 << 16) | (0x92a8 >> 2),
 410         0x00000000,
 411         (0x0e00 << 16) | (0x92ac >> 2),
 412         0x00000000,
 413         (0x0e00 << 16) | (0x92b4 >> 2),
 414         0x00000000,
 415         (0x0e00 << 16) | (0x92b8 >> 2),
 416         0x00000000,
 417         (0x0e00 << 16) | (0x92bc >> 2),
 418         0x00000000,
 419         (0x0e00 << 16) | (0x92c0 >> 2),
 420         0x00000000,
 421         (0x0e00 << 16) | (0x92c4 >> 2),
 422         0x00000000,
 423         (0x0e00 << 16) | (0x92c8 >> 2),
 424         0x00000000,
 425         (0x0e00 << 16) | (0x92cc >> 2),
 426         0x00000000,
 427         (0x0e00 << 16) | (0x92d0 >> 2),
 428         0x00000000,
 429         (0x0e00 << 16) | (0x8c00 >> 2),
 430         0x00000000,
 431         (0x0e00 << 16) | (0x8c04 >> 2),
 432         0x00000000,
 433         (0x0e00 << 16) | (0x8c20 >> 2),
 434         0x00000000,
 435         (0x0e00 << 16) | (0x8c38 >> 2),
 436         0x00000000,
 437         (0x0e00 << 16) | (0x8c3c >> 2),
 438         0x00000000,
 439         (0x0e00 << 16) | (0xae00 >> 2),
 440         0x00000000,
 441         (0x0e00 << 16) | (0x9604 >> 2),
 442         0x00000000,
 443         (0x0e00 << 16) | (0xac08 >> 2),
 444         0x00000000,
 445         (0x0e00 << 16) | (0xac0c >> 2),
 446         0x00000000,
 447         (0x0e00 << 16) | (0xac10 >> 2),
 448         0x00000000,
 449         (0x0e00 << 16) | (0xac14 >> 2),
 450         0x00000000,
 451         (0x0e00 << 16) | (0xac58 >> 2),
 452         0x00000000,
 453         (0x0e00 << 16) | (0xac68 >> 2),
 454         0x00000000,
 455         (0x0e00 << 16) | (0xac6c >> 2),
 456         0x00000000,
 457         (0x0e00 << 16) | (0xac70 >> 2),
 458         0x00000000,
 459         (0x0e00 << 16) | (0xac74 >> 2),
 460         0x00000000,
 461         (0x0e00 << 16) | (0xac78 >> 2),
 462         0x00000000,
 463         (0x0e00 << 16) | (0xac7c >> 2),
 464         0x00000000,
 465         (0x0e00 << 16) | (0xac80 >> 2),
 466         0x00000000,
 467         (0x0e00 << 16) | (0xac84 >> 2),
 468         0x00000000,
 469         (0x0e00 << 16) | (0xac88 >> 2),
 470         0x00000000,
 471         (0x0e00 << 16) | (0xac8c >> 2),
 472         0x00000000,
 473         (0x0e00 << 16) | (0x970c >> 2),
 474         0x00000000,
 475         (0x0e00 << 16) | (0x9714 >> 2),
 476         0x00000000,
 477         (0x0e00 << 16) | (0x9718 >> 2),
 478         0x00000000,
 479         (0x0e00 << 16) | (0x971c >> 2),
 480         0x00000000,
 481         (0x0e00 << 16) | (0x31068 >> 2),
 482         0x00000000,
 483         (0x4e00 << 16) | (0x31068 >> 2),
 484         0x00000000,
 485         (0x5e00 << 16) | (0x31068 >> 2),
 486         0x00000000,
 487         (0x6e00 << 16) | (0x31068 >> 2),
 488         0x00000000,
 489         (0x7e00 << 16) | (0x31068 >> 2),
 490         0x00000000,
 491         (0x8e00 << 16) | (0x31068 >> 2),
 492         0x00000000,
 493         (0x9e00 << 16) | (0x31068 >> 2),
 494         0x00000000,
 495         (0xae00 << 16) | (0x31068 >> 2),
 496         0x00000000,
 497         (0xbe00 << 16) | (0x31068 >> 2),
 498         0x00000000,
 499         (0x0e00 << 16) | (0xcd10 >> 2),
 500         0x00000000,
 501         (0x0e00 << 16) | (0xcd14 >> 2),
 502         0x00000000,
 503         (0x0e00 << 16) | (0x88b0 >> 2),
 504         0x00000000,
 505         (0x0e00 << 16) | (0x88b4 >> 2),
 506         0x00000000,
 507         (0x0e00 << 16) | (0x88b8 >> 2),
 508         0x00000000,
 509         (0x0e00 << 16) | (0x88bc >> 2),
 510         0x00000000,
 511         (0x0400 << 16) | (0x89c0 >> 2),
 512         0x00000000,
 513         (0x0e00 << 16) | (0x88c4 >> 2),
 514         0x00000000,
 515         (0x0e00 << 16) | (0x88c8 >> 2),
 516         0x00000000,
 517         (0x0e00 << 16) | (0x88d0 >> 2),
 518         0x00000000,
 519         (0x0e00 << 16) | (0x88d4 >> 2),
 520         0x00000000,
 521         (0x0e00 << 16) | (0x88d8 >> 2),
 522         0x00000000,
 523         (0x0e00 << 16) | (0x8980 >> 2),
 524         0x00000000,
 525         (0x0e00 << 16) | (0x30938 >> 2),
 526         0x00000000,
 527         (0x0e00 << 16) | (0x3093c >> 2),
 528         0x00000000,
 529         (0x0e00 << 16) | (0x30940 >> 2),
 530         0x00000000,
 531         (0x0e00 << 16) | (0x89a0 >> 2),
 532         0x00000000,
 533         (0x0e00 << 16) | (0x30900 >> 2),
 534         0x00000000,
 535         (0x0e00 << 16) | (0x30904 >> 2),
 536         0x00000000,
 537         (0x0e00 << 16) | (0x89b4 >> 2),
 538         0x00000000,
 539         (0x0e00 << 16) | (0x3c210 >> 2),
 540         0x00000000,
 541         (0x0e00 << 16) | (0x3c214 >> 2),
 542         0x00000000,
 543         (0x0e00 << 16) | (0x3c218 >> 2),
 544         0x00000000,
 545         (0x0e00 << 16) | (0x8904 >> 2),
 546         0x00000000,
 547         0x5,
 548         (0x0e00 << 16) | (0x8c28 >> 2),
 549         (0x0e00 << 16) | (0x8c2c >> 2),
 550         (0x0e00 << 16) | (0x8c30 >> 2),
 551         (0x0e00 << 16) | (0x8c34 >> 2),
 552         (0x0e00 << 16) | (0x9600 >> 2),
 553 };
 554
 555 static const u32 kalindi_rlc_save_restore_register_list[] =
 556 {
 557         (0x0e00 << 16) | (0xc12c >> 2),
 558         0x00000000,
 559         (0x0e00 << 16) | (0xc140 >> 2),
 560         0x00000000,
 561         (0x0e00 << 16) | (0xc150 >> 2),
 562         0x00000000,
 563         (0x0e00 << 16) | (0xc15c >> 2),
 564         0x00000000,
 565         (0x0e00 << 16) | (0xc168 >> 2),
 566         0x00000000,
 567         (0x0e00 << 16) | (0xc170 >> 2),
 568         0x00000000,
 569         (0x0e00 << 16) | (0xc204 >> 2),
 570         0x00000000,
 571         (0x0e00 << 16) | (0xc2b4 >> 2),
 572         0x00000000,
 573         (0x0e00 << 16) | (0xc2b8 >> 2),
 574         0x00000000,
 575         (0x0e00 << 16) | (0xc2bc >> 2),
 576         0x00000000,
 577         (0x0e00 << 16) | (0xc2c0 >> 2),
 578         0x00000000,
 579         (0x0e00 << 16) | (0x8228 >> 2),
 580         0x00000000,
 581         (0x0e00 << 16) | (0x829c >> 2),
 582         0x00000000,
 583         (0x0e00 << 16) | (0x869c >> 2),
 584         0x00000000,
 585         (0x0600 << 16) | (0x98f4 >> 2),
 586         0x00000000,
 587         (0x0e00 << 16) | (0x98f8 >> 2),
 588         0x00000000,
 589         (0x0e00 << 16) | (0x9900 >> 2),
 590         0x00000000,
 591         (0x0e00 << 16) | (0xc260 >> 2),
 592         0x00000000,
 593         (0x0e00 << 16) | (0x90e8 >> 2),
 594         0x00000000,
 595         (0x0e00 << 16) | (0x3c000 >> 2),
 596         0x00000000,
 597         (0x0e00 << 16) | (0x3c00c >> 2),
 598         0x00000000,
 599         (0x0e00 << 16) | (0x8c1c >> 2),
 600         0x00000000,
 601         (0x0e00 << 16) | (0x9700 >> 2),
 602         0x00000000,
 603         (0x0e00 << 16) | (0xcd20 >> 2),
 604         0x00000000,
 605         (0x4e00 << 16) | (0xcd20 >> 2),
 606         0x00000000,
 607         (0x5e00 << 16) | (0xcd20 >> 2),
 608         0x00000000,
 609         (0x6e00 << 16) | (0xcd20 >> 2),
 610         0x00000000,
 611         (0x7e00 << 16) | (0xcd20 >> 2),
 612         0x00000000,
 613         (0x0e00 << 16) | (0x89bc >> 2),
 614         0x00000000,
 615         (0x0e00 << 16) | (0x8900 >> 2),
 616         0x00000000,
 617         0x3,
 618         (0x0e00 << 16) | (0xc130 >> 2),
 619         0x00000000,
 620         (0x0e00 << 16) | (0xc134 >> 2),
 621         0x00000000,
 622         (0x0e00 << 16) | (0xc1fc >> 2),
 623         0x00000000,
 624         (0x0e00 << 16) | (0xc208 >> 2),
 625         0x00000000,
 626         (0x0e00 << 16) | (0xc264 >> 2),
 627         0x00000000,
 628         (0x0e00 << 16) | (0xc268 >> 2),
 629         0x00000000,
 630         (0x0e00 << 16) | (0xc26c >> 2),
 631         0x00000000,
 632         (0x0e00 << 16) | (0xc270 >> 2),
 633         0x00000000,
 634         (0x0e00 << 16) | (0xc274 >> 2),
 635         0x00000000,
 636         (0x0e00 << 16) | (0xc28c >> 2),
 637         0x00000000,
 638         (0x0e00 << 16) | (0xc290 >> 2),
 639         0x00000000,
 640         (0x0e00 << 16) | (0xc294 >> 2),
 641         0x00000000,
 642         (0x0e00 << 16) | (0xc298 >> 2),
 643         0x00000000,
 644         (0x0e00 << 16) | (0xc2a0 >> 2),
 645         0x00000000,
 646         (0x0e00 << 16) | (0xc2a4 >> 2),
 647         0x00000000,
 648         (0x0e00 << 16) | (0xc2a8 >> 2),
 649         0x00000000,
 650         (0x0e00 << 16) | (0xc2ac >> 2),
 651         0x00000000,
 652         (0x0e00 << 16) | (0x301d0 >> 2),
 653         0x00000000,
 654         (0x0e00 << 16) | (0x30238 >> 2),
 655         0x00000000,
 656         (0x0e00 << 16) | (0x30250 >> 2),
 657         0x00000000,
 658         (0x0e00 << 16) | (0x30254 >> 2),
 659         0x00000000,
 660         (0x0e00 << 16) | (0x30258 >> 2),
 661         0x00000000,
 662         (0x0e00 << 16) | (0x3025c >> 2),
 663         0x00000000,
 664         (0x4e00 << 16) | (0xc900 >> 2),
 665         0x00000000,
 666         (0x5e00 << 16) | (0xc900 >> 2),
 667         0x00000000,
 668         (0x6e00 << 16) | (0xc900 >> 2),
 669         0x00000000,
 670         (0x7e00 << 16) | (0xc900 >> 2),
 671         0x00000000,
 672         (0x4e00 << 16) | (0xc904 >> 2),
 673         0x00000000,
 674         (0x5e00 << 16) | (0xc904 >> 2),
 675         0x00000000,
 676         (0x6e00 << 16) | (0xc904 >> 2),
 677         0x00000000,
 678         (0x7e00 << 16) | (0xc904 >> 2),
 679         0x00000000,
 680         (0x4e00 << 16) | (0xc908 >> 2),
 681         0x00000000,
 682         (0x5e00 << 16) | (0xc908 >> 2),
 683         0x00000000,
 684         (0x6e00 << 16) | (0xc908 >> 2),
 685         0x00000000,
 686         (0x7e00 << 16) | (0xc908 >> 2),
 687         0x00000000,
 688         (0x4e00 << 16) | (0xc90c >> 2),
 689         0x00000000,
 690         (0x5e00 << 16) | (0xc90c >> 2),
 691         0x00000000,
 692         (0x6e00 << 16) | (0xc90c >> 2),
 693         0x00000000,
 694         (0x7e00 << 16) | (0xc90c >> 2),
 695         0x00000000,
 696         (0x4e00 << 16) | (0xc910 >> 2),
 697         0x00000000,
 698         (0x5e00 << 16) | (0xc910 >> 2),
 699         0x00000000,
 700         (0x6e00 << 16) | (0xc910 >> 2),
 701         0x00000000,
 702         (0x7e00 << 16) | (0xc910 >> 2),
 703         0x00000000,
 704         (0x0e00 << 16) | (0xc99c >> 2),
 705         0x00000000,
 706         (0x0e00 << 16) | (0x9834 >> 2),
 707         0x00000000,
 708         (0x0000 << 16) | (0x30f00 >> 2),
 709         0x00000000,
 710         (0x0000 << 16) | (0x30f04 >> 2),
 711         0x00000000,
 712         (0x0000 << 16) | (0x30f08 >> 2),
 713         0x00000000,
 714         (0x0000 << 16) | (0x30f0c >> 2),
 715         0x00000000,
 716         (0x0600 << 16) | (0x9b7c >> 2),
 717         0x00000000,
 718         (0x0e00 << 16) | (0x8a14 >> 2),
 719         0x00000000,
 720         (0x0e00 << 16) | (0x8a18 >> 2),
 721         0x00000000,
 722         (0x0600 << 16) | (0x30a00 >> 2),
 723         0x00000000,
 724         (0x0e00 << 16) | (0x8bf0 >> 2),
 725         0x00000000,
 726         (0x0e00 << 16) | (0x8bcc >> 2),
 727         0x00000000,
 728         (0x0e00 << 16) | (0x8b24 >> 2),
 729         0x00000000,
 730         (0x0e00 << 16) | (0x30a04 >> 2),
 731         0x00000000,
 732         (0x0600 << 16) | (0x30a10 >> 2),
 733         0x00000000,
 734         (0x0600 << 16) | (0x30a14 >> 2),
 735         0x00000000,
 736         (0x0600 << 16) | (0x30a18 >> 2),
 737         0x00000000,
 738         (0x0600 << 16) | (0x30a2c >> 2),
 739         0x00000000,
 740         (0x0e00 << 16) | (0xc700 >> 2),
 741         0x00000000,
 742         (0x0e00 << 16) | (0xc704 >> 2),
 743         0x00000000,
 744         (0x0e00 << 16) | (0xc708 >> 2),
 745         0x00000000,
 746         (0x0e00 << 16) | (0xc768 >> 2),
 747         0x00000000,
 748         (0x0400 << 16) | (0xc770 >> 2),
 749         0x00000000,
 750         (0x0400 << 16) | (0xc774 >> 2),
 751         0x00000000,
 752         (0x0400 << 16) | (0xc798 >> 2),
 753         0x00000000,
 754         (0x0400 << 16) | (0xc79c >> 2),
 755         0x00000000,
 756         (0x0e00 << 16) | (0x9100 >> 2),
 757         0x00000000,
 758         (0x0e00 << 16) | (0x3c010 >> 2),
 759         0x00000000,
 760         (0x0e00 << 16) | (0x8c00 >> 2),
 761         0x00000000,
 762         (0x0e00 << 16) | (0x8c04 >> 2),
 763         0x00000000,
 764         (0x0e00 << 16) | (0x8c20 >> 2),
 765         0x00000000,
 766         (0x0e00 << 16) | (0x8c38 >> 2),
 767         0x00000000,
 768         (0x0e00 << 16) | (0x8c3c >> 2),
 769         0x00000000,
 770         (0x0e00 << 16) | (0xae00 >> 2),
 771         0x00000000,
 772         (0x0e00 << 16) | (0x9604 >> 2),
 773         0x00000000,
 774         (0x0e00 << 16) | (0xac08 >> 2),
 775         0x00000000,
 776         (0x0e00 << 16) | (0xac0c >> 2),
 777         0x00000000,
 778         (0x0e00 << 16) | (0xac10 >> 2),
 779         0x00000000,
 780         (0x0e00 << 16) | (0xac14 >> 2),
 781         0x00000000,
 782         (0x0e00 << 16) | (0xac58 >> 2),
 783         0x00000000,
 784         (0x0e00 << 16) | (0xac68 >> 2),
 785         0x00000000,
 786         (0x0e00 << 16) | (0xac6c >> 2),
 787         0x00000000,
 788         (0x0e00 << 16) | (0xac70 >> 2),
 789         0x00000000,
 790         (0x0e00 << 16) | (0xac74 >> 2),
 791         0x00000000,
 792         (0x0e00 << 16) | (0xac78 >> 2),
 793         0x00000000,
 794         (0x0e00 << 16) | (0xac7c >> 2),
 795         0x00000000,
 796         (0x0e00 << 16) | (0xac80 >> 2),
 797         0x00000000,
 798         (0x0e00 << 16) | (0xac84 >> 2),
 799         0x00000000,
 800         (0x0e00 << 16) | (0xac88 >> 2),
 801         0x00000000,
 802         (0x0e00 << 16) | (0xac8c >> 2),
 803         0x00000000,
 804         (0x0e00 << 16) | (0x970c >> 2),
 805         0x00000000,
 806         (0x0e00 << 16) | (0x9714 >> 2),
 807         0x00000000,
 808         (0x0e00 << 16) | (0x9718 >> 2),
 809         0x00000000,
 810         (0x0e00 << 16) | (0x971c >> 2),
 811         0x00000000,
 812         (0x0e00 << 16) | (0x31068 >> 2),
 813         0x00000000,
 814         (0x4e00 << 16) | (0x31068 >> 2),
 815         0x00000000,
 816         (0x5e00 << 16) | (0x31068 >> 2),
 817         0x00000000,
 818         (0x6e00 << 16) | (0x31068 >> 2),
 819         0x00000000,
 820         (0x7e00 << 16) | (0x31068 >> 2),
 821         0x00000000,
 822         (0x0e00 << 16) | (0xcd10 >> 2),
 823         0x00000000,
 824         (0x0e00 << 16) | (0xcd14 >> 2),
 825         0x00000000,
 826         (0x0e00 << 16) | (0x88b0 >> 2),
 827         0x00000000,
 828         (0x0e00 << 16) | (0x88b4 >> 2),
 829         0x00000000,
 830         (0x0e00 << 16) | (0x88b8 >> 2),
 831         0x00000000,
 832         (0x0e00 << 16) | (0x88bc >> 2),
 833         0x00000000,
 834         (0x0400 << 16) | (0x89c0 >> 2),
 835         0x00000000,
 836         (0x0e00 << 16) | (0x88c4 >> 2),
 837         0x00000000,
 838         (0x0e00 << 16) | (0x88c8 >> 2),
 839         0x00000000,
 840         (0x0e00 << 16) | (0x88d0 >> 2),
 841         0x00000000,
 842         (0x0e00 << 16) | (0x88d4 >> 2),
 843         0x00000000,
 844         (0x0e00 << 16) | (0x88d8 >> 2),
 845         0x00000000,
 846         (0x0e00 << 16) | (0x8980 >> 2),
 847         0x00000000,
 848         (0x0e00 << 16) | (0x30938 >> 2),
 849         0x00000000,
 850         (0x0e00 << 16) | (0x3093c >> 2),
 851         0x00000000,
 852         (0x0e00 << 16) | (0x30940 >> 2),
 853         0x00000000,
 854         (0x0e00 << 16) | (0x89a0 >> 2),
 855         0x00000000,
 856         (0x0e00 << 16) | (0x30900 >> 2),
 857         0x00000000,
 858         (0x0e00 << 16) | (0x30904 >> 2),
 859         0x00000000,
 860         (0x0e00 << 16) | (0x89b4 >> 2),
 861         0x00000000,
 862         (0x0e00 << 16) | (0x3e1fc >> 2),
 863         0x00000000,
 864         (0x0e00 << 16) | (0x3c210 >> 2),
 865         0x00000000,
 866         (0x0e00 << 16) | (0x3c214 >> 2),
 867         0x00000000,
 868         (0x0e00 << 16) | (0x3c218 >> 2),
 869         0x00000000,
 870         (0x0e00 << 16) | (0x8904 >> 2),
 871         0x00000000,
 872         0x5,
 873         (0x0e00 << 16) | (0x8c28 >> 2),
 874         (0x0e00 << 16) | (0x8c2c >> 2),
 875         (0x0e00 << 16) | (0x8c30 >> 2),
 876         (0x0e00 << 16) | (0x8c34 >> 2),
 877         (0x0e00 << 16) | (0x9600 >> 2),
 878 };
 879
 880 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev);
 881 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
 882 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev);
 883 static void gfx_v7_0_init_pg(struct amdgpu_device *adev);
 884 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev);
 885
 886 /*
 887  * Core functions
 888  */
 889 /**
 890  * gfx_v7_0_init_microcode - load ucode images from disk
 891  *
 892  * @adev: amdgpu_device pointer
 893  *
 894  * Use the firmware interface to load the ucode images into
 895  * the driver (not loaded into hw).
 896  * Returns 0 on success, error on failure.
 897  */
 898 static int gfx_v7_0_init_microcode(struct amdgpu_device *adev)
 899 {
 900         const char *chip_name;
 901         char fw_name[30];
 902         int err;
 903
 904         DRM_DEBUG("\n");
 905
 906         switch (adev->asic_type) {
 907         case CHIP_BONAIRE:
 908                 chip_name = "bonaire";
 909                 break;
 910         case CHIP_HAWAII:
 911                 chip_name = "hawaii";
 912                 break;
 913         case CHIP_KAVERI:
 914                 chip_name = "kaveri";
 915                 break;
 916         case CHIP_KABINI:
 917                 chip_name = "kabini";
 918                 break;
 919         case CHIP_MULLINS:
 920                 chip_name = "mullins";
 921                 break;
 922         default: BUG();
 923         }
 924
 925         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
 926         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
 927         if (err)
 928                 goto out;
 929         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
 930         if (err)
 931                 goto out;
 932
 933         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
 934         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
 935         if (err)
 936                 goto out;
 937         err = amdgpu_ucode_validate(adev->gfx.me_fw);
 938         if (err)
 939                 goto out;
 940
 941         snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
 942         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
 943         if (err)
 944                 goto out;
 945         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
 946         if (err)
 947                 goto out;
 948
 949         snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", chip_name);
 950         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
 951         if (err)
 952                 goto out;
 953         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
 954         if (err)
 955                 goto out;
 956
 957         if (adev->asic_type == CHIP_KAVERI) {
 958                 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec2.bin", chip_name);
 959                 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
 960                 if (err)
 961                         goto out;
 962                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
 963                 if (err)
 964                         goto out;
 965         }
 966
 967         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
 968         err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 969         if (err)
 970                 goto out;
 971         err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
 972
 973 out:
 974         if (err) {
 975                 printk(KERN_ERR
 976                        "gfx7: Failed to load firmware \"%s\"\n",
 977                        fw_name);
 978                 release_firmware(adev->gfx.pfp_fw);
 979                 adev->gfx.pfp_fw = NULL;
 980                 release_firmware(adev->gfx.me_fw);
 981                 adev->gfx.me_fw = NULL;
 982                 release_firmware(adev->gfx.ce_fw);
 983                 adev->gfx.ce_fw = NULL;
 984                 release_firmware(adev->gfx.mec_fw);
 985                 adev->gfx.mec_fw = NULL;
 986                 release_firmware(adev->gfx.mec2_fw);
 987                 adev->gfx.mec2_fw = NULL;
 988                 release_firmware(adev->gfx.rlc_fw);
 989                 adev->gfx.rlc_fw = NULL;
 990         }
 991         return err;
 992 }
 993
 994 static void gfx_v7_0_free_microcode(struct amdgpu_device *adev)
 995 {
 996         release_firmware(adev->gfx.pfp_fw);
 997         adev->gfx.pfp_fw = NULL;
 998         release_firmware(adev->gfx.me_fw);
 999         adev->gfx.me_fw = NULL;
1000         release_firmware(adev->gfx.ce_fw);
1001         adev->gfx.ce_fw = NULL;
1002         release_firmware(adev->gfx.mec_fw);
1003         adev->gfx.mec_fw = NULL;
1004         release_firmware(adev->gfx.mec2_fw);
1005         adev->gfx.mec2_fw = NULL;
1006         release_firmware(adev->gfx.rlc_fw);
1007         adev->gfx.rlc_fw = NULL;
1008 }
1009
1010 /**
1011  * gfx_v7_0_tiling_mode_table_init - init the hw tiling table
1012  *
1013  * @adev: amdgpu_device pointer
1014  *
1015  * Starting with SI, the tiling setup is done globally in a
1016  * set of 32 tiling modes.  Rather than selecting each set of
1017  * parameters per surface as on older asics, we just select
1018  * which index in the tiling table we want to use, and the
1019  * surface uses those parameters (CIK).
1020  */
1021 static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev)
1022 {
1023         const u32 num_tile_mode_states =
1024                         ARRAY_SIZE(adev->gfx.config.tile_mode_array);
1025         const u32 num_secondary_tile_mode_states =
1026                         ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
1027         u32 reg_offset, split_equal_to_row_size;
1028         uint32_t *tile, *macrotile;
1029
1030         tile = adev->gfx.config.tile_mode_array;
1031         macrotile = adev->gfx.config.macrotile_mode_array;
1032
1033         switch (adev->gfx.config.mem_row_size_in_kb) {
1034         case 1:
1035                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
1036                 break;
1037         case 2:
1038         default:
1039                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
1040                 break;
1041         case 4:
1042                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
1043                 break;
1044         }
1045
1046         for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1047                 tile[reg_offset] = 0;
1048         for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1049                 macrotile[reg_offset] = 0;
1050
1051         switch (adev->asic_type) {
1052         case CHIP_BONAIRE:
1053                 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1054                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1055                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1056                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1057                 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1058                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1059                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1060                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1061                 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1062                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1063                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1064                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1065                 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1066                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1067                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1068                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1069                 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1070                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1071                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1072                            TILE_SPLIT(split_equal_to_row_size));
1073                 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1074                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1075                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1076                 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1077                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1078                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1079                            TILE_SPLIT(split_equal_to_row_size));
1080                 tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1081                 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1082                            PIPE_CONFIG(ADDR_SURF_P4_16x16));
1083                 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1084                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1085                            MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1086                 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1087                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1088                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1089                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1090                 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1091                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1092                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1093                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1094                 tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1095                 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1096                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1097                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1098                 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1099                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1100                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1101                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1102                 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1103                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1104                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1105                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1106                 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1107                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1108                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1109                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1110                 tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1111                 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1112                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1113                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1114                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1115                 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1116                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1117                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1118                 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1119                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1120                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1121                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1122                 tile[21] =  (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1123                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1124                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1125                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1126                 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1127                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1128                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1129                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1130                 tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1131                 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1132                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1133                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1134                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1135                 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1136                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1137                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1138                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1139                 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1140                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1141                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1142                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1143                 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1144                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1145                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1146                 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1147                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1148                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1149                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1150                 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1151                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1152                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1153                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1154                 tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1155
1156                 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1157                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1158                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1159                                 NUM_BANKS(ADDR_SURF_16_BANK));
1160                 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1161                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1162                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1163                                 NUM_BANKS(ADDR_SURF_16_BANK));
1164                 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1165                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1166                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1167                                 NUM_BANKS(ADDR_SURF_16_BANK));
1168                 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1169                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1170                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1171                                 NUM_BANKS(ADDR_SURF_16_BANK));
1172                 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1173                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1174                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1175                                 NUM_BANKS(ADDR_SURF_16_BANK));
1176                 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1177                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1178                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1179                                 NUM_BANKS(ADDR_SURF_8_BANK));
1180                 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1181                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1182                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1183                                 NUM_BANKS(ADDR_SURF_4_BANK));
1184                 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1185                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1186                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1187                                 NUM_BANKS(ADDR_SURF_16_BANK));
1188                 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1189                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1190                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1191                                 NUM_BANKS(ADDR_SURF_16_BANK));
1192                 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1193                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1194                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1195                                 NUM_BANKS(ADDR_SURF_16_BANK));
1196                 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1197                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1198                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1199                                 NUM_BANKS(ADDR_SURF_16_BANK));
1200                 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1201                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1202                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1203                                 NUM_BANKS(ADDR_SURF_16_BANK));
1204                 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1205                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1206                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1207                                 NUM_BANKS(ADDR_SURF_8_BANK));
1208                 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1209                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1210                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1211                                 NUM_BANKS(ADDR_SURF_4_BANK));
1212
1213                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1214                         WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1215                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1216                         if (reg_offset != 7)
1217                                 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1218                 break;
1219         case CHIP_HAWAII:
1220                 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1221                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1222                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1223                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1224                 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1225                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1226                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1227                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1228                 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1229                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1230                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1231                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1232                 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1233                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1234                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1235                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1236                 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1237                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1238                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1239                            TILE_SPLIT(split_equal_to_row_size));
1240                 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1241                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1242                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1243                            TILE_SPLIT(split_equal_to_row_size));
1244                 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1245                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1246                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1247                            TILE_SPLIT(split_equal_to_row_size));
1248                 tile[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1249                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1250                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1251                            TILE_SPLIT(split_equal_to_row_size));
1252                 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1253                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
1254                 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1255                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1256                            MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1257                 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1258                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1259                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1260                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1261                 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1262                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1263                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1264                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1265                 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
1266                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1267                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1268                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1269                 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1270                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1271                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1272                 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1273                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1274                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1275                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1276                 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1277                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1278                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1279                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1280                 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1281                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1282                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1283                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1284                 tile[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1285                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1286                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1287                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1288                 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1289                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1290                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1291                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1292                 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1293                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1294                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1295                 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1296                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1297                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1298                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1299                 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1300                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1301                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1302                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1303                 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1304                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1305                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1306                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1307                 tile[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1308                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1309                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1310                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1311                 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1312                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1313                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1314                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1315                 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1316                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1317                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1318                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1319                 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1320                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1321                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1322                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1323                 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1324                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1325                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1326                 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1327                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1328                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1329                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1330                 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1331                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1332                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1333                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1334                 tile[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1335                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1336                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1337                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1338
1339                 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1340                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1341                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1342                                 NUM_BANKS(ADDR_SURF_16_BANK));
1343                 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1344                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1345                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1346                                 NUM_BANKS(ADDR_SURF_16_BANK));
1347                 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1348                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1349                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1350                                 NUM_BANKS(ADDR_SURF_16_BANK));
1351                 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1352                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1353                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1354                                 NUM_BANKS(ADDR_SURF_16_BANK));
1355                 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1356                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1357                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1358                                 NUM_BANKS(ADDR_SURF_8_BANK));
1359                 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1360                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1361                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1362                                 NUM_BANKS(ADDR_SURF_4_BANK));
1363                 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1364                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1365                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1366                                 NUM_BANKS(ADDR_SURF_4_BANK));
1367                 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1368                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1369                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1370                                 NUM_BANKS(ADDR_SURF_16_BANK));
1371                 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1372                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1373                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1374                                 NUM_BANKS(ADDR_SURF_16_BANK));
1375                 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1376                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1377                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1378                                 NUM_BANKS(ADDR_SURF_16_BANK));
1379                 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1380                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1381                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1382                                 NUM_BANKS(ADDR_SURF_8_BANK));
1383                 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1384                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1385                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1386                                 NUM_BANKS(ADDR_SURF_16_BANK));
1387                 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1388                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1389                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1390                                 NUM_BANKS(ADDR_SURF_8_BANK));
1391                 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1392                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1393                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1394                                 NUM_BANKS(ADDR_SURF_4_BANK));
1395
1396                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1397                         WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1398                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1399                         if (reg_offset != 7)
1400                                 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1401                 break;
1402         case CHIP_KABINI:
1403         case CHIP_KAVERI:
1404         case CHIP_MULLINS:
1405         default:
1406                 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1407                            PIPE_CONFIG(ADDR_SURF_P2) |
1408                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1409                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1410                 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1411                            PIPE_CONFIG(ADDR_SURF_P2) |
1412                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1413                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1414                 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1415                            PIPE_CONFIG(ADDR_SURF_P2) |
1416                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1417                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1418                 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1419                            PIPE_CONFIG(ADDR_SURF_P2) |
1420                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1421                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1422                 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1423                            PIPE_CONFIG(ADDR_SURF_P2) |
1424                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1425                            TILE_SPLIT(split_equal_to_row_size));
1426                 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1427                            PIPE_CONFIG(ADDR_SURF_P2) |
1428                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1429                 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1430                            PIPE_CONFIG(ADDR_SURF_P2) |
1431                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1432                            TILE_SPLIT(split_equal_to_row_size));
1433                 tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1434                 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1435                            PIPE_CONFIG(ADDR_SURF_P2));
1436                 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1437                            PIPE_CONFIG(ADDR_SURF_P2) |
1438                            MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1439                 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1440                             PIPE_CONFIG(ADDR_SURF_P2) |
1441                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1442                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1443                 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1444                             PIPE_CONFIG(ADDR_SURF_P2) |
1445                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1446                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1447                 tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1448                 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1449                             PIPE_CONFIG(ADDR_SURF_P2) |
1450                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1451                 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1452                             PIPE_CONFIG(ADDR_SURF_P2) |
1453                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1454                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1455                 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1456                             PIPE_CONFIG(ADDR_SURF_P2) |
1457                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1458                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1459                 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1460                             PIPE_CONFIG(ADDR_SURF_P2) |
1461                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1462                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1463                 tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1464                 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1465                             PIPE_CONFIG(ADDR_SURF_P2) |
1466                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1467                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1468                 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1469                             PIPE_CONFIG(ADDR_SURF_P2) |
1470                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1471                 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1472                             PIPE_CONFIG(ADDR_SURF_P2) |
1473                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1474                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1475                 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1476                             PIPE_CONFIG(ADDR_SURF_P2) |
1477                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1478                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1479                 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1480                             PIPE_CONFIG(ADDR_SURF_P2) |
1481                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1482                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1483                 tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1484                 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1485                             PIPE_CONFIG(ADDR_SURF_P2) |
1486                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1487                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1488                 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1489                             PIPE_CONFIG(ADDR_SURF_P2) |
1490                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1491                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1492                 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1493                             PIPE_CONFIG(ADDR_SURF_P2) |
1494                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1495                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1496                 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1497                             PIPE_CONFIG(ADDR_SURF_P2) |
1498                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1499                 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1500                             PIPE_CONFIG(ADDR_SURF_P2) |
1501                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1502                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1503                 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1504                             PIPE_CONFIG(ADDR_SURF_P2) |
1505                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1506                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1507                 tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1508
1509                 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1510                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1511                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1512                                 NUM_BANKS(ADDR_SURF_8_BANK));
1513                 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1514                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1515                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1516                                 NUM_BANKS(ADDR_SURF_8_BANK));
1517                 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1518                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1519                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1520                                 NUM_BANKS(ADDR_SURF_8_BANK));
1521                 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1522                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1523                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1524                                 NUM_BANKS(ADDR_SURF_8_BANK));
1525                 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1526                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1527                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1528                                 NUM_BANKS(ADDR_SURF_8_BANK));
1529                 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1530                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1531                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1532                                 NUM_BANKS(ADDR_SURF_8_BANK));
1533                 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1534                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1535                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1536                                 NUM_BANKS(ADDR_SURF_8_BANK));
1537                 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1538                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1539                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1540                                 NUM_BANKS(ADDR_SURF_16_BANK));
1541                 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1542                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1543                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1544                                 NUM_BANKS(ADDR_SURF_16_BANK));
1545                 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1546                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1547                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1548                                 NUM_BANKS(ADDR_SURF_16_BANK));
1549                 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1550                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1551                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1552                                 NUM_BANKS(ADDR_SURF_16_BANK));
1553                 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1554                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1555                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1556                                 NUM_BANKS(ADDR_SURF_16_BANK));
1557                 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1558                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1559                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1560                                 NUM_BANKS(ADDR_SURF_16_BANK));
1561                 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1562                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1563                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1564                                 NUM_BANKS(ADDR_SURF_8_BANK));
1565
1566                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1567                         WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1568                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1569                         if (reg_offset != 7)
1570                                 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1571                 break;
1572         }
1573 }
1574
1575 /**
1576  * gfx_v7_0_select_se_sh - select which SE, SH to address
1577  *
1578  * @adev: amdgpu_device pointer
1579  * @se_num: shader engine to address
1580  * @sh_num: sh block to address
1581  *
1582  * Select which SE, SH combinations to address. Certain
1583  * registers are instanced per SE or SH.  0xffffffff means
1584  * broadcast to all SEs or SHs (CIK).
1585  */
1586 static void gfx_v7_0_select_se_sh(struct amdgpu_device *adev,
1587                                   u32 se_num, u32 sh_num, u32 instance)
1588 {
1589         u32 data;
1590
1591         if (instance == 0xffffffff)
1592                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1593         else
1594                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1595
1596         if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1597                 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1598                         GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
1599         else if (se_num == 0xffffffff)
1600                 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1601                         (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
1602         else if (sh_num == 0xffffffff)
1603                 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1604                         (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1605         else
1606                 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1607                         (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1608         WREG32(mmGRBM_GFX_INDEX, data);
1609 }
1610
1611 /**
1612  * gfx_v7_0_create_bitmask - create a bitmask
1613  *
1614  * @bit_width: length of the mask
1615  *
1616  * create a variable length bit mask (CIK).
1617  * Returns the bitmask.
1618  */
1619 static u32 gfx_v7_0_create_bitmask(u32 bit_width)
1620 {
1621         return (u32)((1ULL << bit_width) - 1);
1622 }
1623
1624 /**
1625  * gfx_v7_0_get_rb_active_bitmap - computes the mask of enabled RBs
1626  *
1627  * @adev: amdgpu_device pointer
1628  *
1629  * Calculates the bitmask of enabled RBs (CIK).
1630  * Returns the enabled RB bitmask.
1631  */
1632 static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1633 {
1634         u32 data, mask;
1635
1636         data = RREG32(mmCC_RB_BACKEND_DISABLE);
1637         data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1638
1639         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1640         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1641
1642         mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_backends_per_se /
1643                                        adev->gfx.config.max_sh_per_se);
1644
1645         return (~data) & mask;
1646 }
1647
1648 /**
1649  * gfx_v7_0_setup_rb - setup the RBs on the asic
1650  *
1651  * @adev: amdgpu_device pointer
1652  * @se_num: number of SEs (shader engines) for the asic
1653  * @sh_per_se: number of SH blocks per SE for the asic
1654  *
1655  * Configures per-SE/SH RB registers (CIK).
1656  */
1657 static void gfx_v7_0_setup_rb(struct amdgpu_device *adev)
1658 {
1659         int i, j;
1660         u32 data;
1661         u32 active_rbs = 0;
1662         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1663                                         adev->gfx.config.max_sh_per_se;
1664
1665         mutex_lock(&adev->grbm_idx_mutex);
1666         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1667                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1668                         gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
1669                         data = gfx_v7_0_get_rb_active_bitmap(adev);
1670                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1671                                                rb_bitmap_width_per_sh);
1672                 }
1673         }
1674         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1675         mutex_unlock(&adev->grbm_idx_mutex);
1676
1677         adev->gfx.config.backend_enable_mask = active_rbs;
1678         adev->gfx.config.num_rbs = hweight32(active_rbs);
1679 }
1680
1681 /**
1682  * gmc_v7_0_init_compute_vmid - gart enable
1683  *
1684  * @rdev: amdgpu_device pointer
1685  *
1686  * Initialize compute vmid sh_mem registers
1687  *
1688  */
1689 #define DEFAULT_SH_MEM_BASES    (0x6000)
1690 #define FIRST_COMPUTE_VMID      (8)
1691 #define LAST_COMPUTE_VMID       (16)
1692 static void gmc_v7_0_init_compute_vmid(struct amdgpu_device *adev)
1693 {
1694         int i;
1695         uint32_t sh_mem_config;
1696         uint32_t sh_mem_bases;
1697
1698         /*
1699          * Configure apertures:
1700          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
1701          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
1702          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
1703         */
1704         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1705         sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1706                         SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1707         sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT;
1708         mutex_lock(&adev->srbm_mutex);
1709         for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1710                 cik_srbm_select(adev, 0, 0, 0, i);
1711                 /* CP and shaders */
1712                 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
1713                 WREG32(mmSH_MEM_APE1_BASE, 1);
1714                 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1715                 WREG32(mmSH_MEM_BASES, sh_mem_bases);
1716         }
1717         cik_srbm_select(adev, 0, 0, 0, 0);
1718         mutex_unlock(&adev->srbm_mutex);
1719 }
1720
1721 /**
1722  * gfx_v7_0_gpu_init - setup the 3D engine
1723  *
1724  * @adev: amdgpu_device pointer
1725  *
1726  * Configures the 3D engine and tiling configuration
1727  * registers so that the 3D engine is usable.
1728  */
1729 static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
1730 {
1731         u32 tmp, sh_mem_cfg;
1732         int i;
1733
1734         WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
1735
1736         WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1737         WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1738         WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
1739
1740         gfx_v7_0_tiling_mode_table_init(adev);
1741
1742         gfx_v7_0_setup_rb(adev);
1743         gfx_v7_0_get_cu_info(adev);
1744
1745         /* set HW defaults for 3D engine */
1746         WREG32(mmCP_MEQ_THRESHOLDS,
1747                (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
1748                (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
1749
1750         mutex_lock(&adev->grbm_idx_mutex);
1751         /*
1752          * making sure that the following register writes will be broadcasted
1753          * to all the shaders
1754          */
1755         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1756
1757         /* XXX SH_MEM regs */
1758         /* where to put LDS, scratch, GPUVM in FSA64 space */
1759         sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1760                                    SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1761
1762         mutex_lock(&adev->srbm_mutex);
1763         for (i = 0; i < 16; i++) {
1764                 cik_srbm_select(adev, 0, 0, 0, i);
1765                 /* CP and shaders */
1766                 WREG32(mmSH_MEM_CONFIG, sh_mem_cfg);
1767                 WREG32(mmSH_MEM_APE1_BASE, 1);
1768                 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1769                 WREG32(mmSH_MEM_BASES, 0);
1770         }
1771         cik_srbm_select(adev, 0, 0, 0, 0);
1772         mutex_unlock(&adev->srbm_mutex);
1773
1774         gmc_v7_0_init_compute_vmid(adev);
1775
1776         WREG32(mmSX_DEBUG_1, 0x20);
1777
1778         WREG32(mmTA_CNTL_AUX, 0x00010000);
1779
1780         tmp = RREG32(mmSPI_CONFIG_CNTL);
1781         tmp |= 0x03000000;
1782         WREG32(mmSPI_CONFIG_CNTL, tmp);
1783
1784         WREG32(mmSQ_CONFIG, 1);
1785
1786         WREG32(mmDB_DEBUG, 0);
1787
1788         tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff;
1789         tmp |= 0x00000400;
1790         WREG32(mmDB_DEBUG2, tmp);
1791
1792         tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c;
1793         tmp |= 0x00020200;
1794         WREG32(mmDB_DEBUG3, tmp);
1795
1796         tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000;
1797         tmp |= 0x00018208;
1798         WREG32(mmCB_HW_CONTROL, tmp);
1799
1800         WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
1801
1802         WREG32(mmPA_SC_FIFO_SIZE,
1803                 ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1804                 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1805                 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1806                 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
1807
1808         WREG32(mmVGT_NUM_INSTANCES, 1);
1809
1810         WREG32(mmCP_PERFMON_CNTL, 0);
1811
1812         WREG32(mmSQ_CONFIG, 0);
1813
1814         WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS,
1815                 ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
1816                 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
1817
1818         WREG32(mmVGT_CACHE_INVALIDATION,
1819                 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
1820                 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
1821
1822         WREG32(mmVGT_GS_VERTEX_REUSE, 16);
1823         WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
1824
1825         WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
1826                         (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
1827         WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK);
1828         mutex_unlock(&adev->grbm_idx_mutex);
1829
1830         udelay(50);
1831 }
1832
1833 /*
1834  * GPU scratch registers helpers function.
1835  */
1836 /**
1837  * gfx_v7_0_scratch_init - setup driver info for CP scratch regs
1838  *
1839  * @adev: amdgpu_device pointer
1840  *
1841  * Set up the number and offset of the CP scratch registers.
1842  * NOTE: use of CP scratch registers is a legacy inferface and
1843  * is not used by default on newer asics (r6xx+).  On newer asics,
1844  * memory buffers are used for fences rather than scratch regs.
1845  */
1846 static void gfx_v7_0_scratch_init(struct amdgpu_device *adev)
1847 {
1848         int i;
1849
1850         adev->gfx.scratch.num_reg = 7;
1851         adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
1852         for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
1853                 adev->gfx.scratch.free[i] = true;
1854                 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
1855         }
1856 }
1857
1858 /**
1859  * gfx_v7_0_ring_test_ring - basic gfx ring test
1860  *
1861  * @adev: amdgpu_device pointer
1862  * @ring: amdgpu_ring structure holding ring information
1863  *
1864  * Allocate a scratch register and write to it using the gfx ring (CIK).
1865  * Provides a basic gfx ring test to verify that the ring is working.
1866  * Used by gfx_v7_0_cp_gfx_resume();
1867  * Returns 0 on success, error on failure.
1868  */
1869 static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring)
1870 {
1871         struct amdgpu_device *adev = ring->adev;
1872         uint32_t scratch;
1873         uint32_t tmp = 0;
1874         unsigned i;
1875         int r;
1876
1877         r = amdgpu_gfx_scratch_get(adev, &scratch);
1878         if (r) {
1879                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
1880                 return r;
1881         }
1882         WREG32(scratch, 0xCAFEDEAD);
1883         r = amdgpu_ring_alloc(ring, 3);
1884         if (r) {
1885                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r);
1886                 amdgpu_gfx_scratch_free(adev, scratch);
1887                 return r;
1888         }
1889         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
1890         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
1891         amdgpu_ring_write(ring, 0xDEADBEEF);
1892         amdgpu_ring_commit(ring);
1893
1894         for (i = 0; i < adev->usec_timeout; i++) {
1895                 tmp = RREG32(scratch);
1896                 if (tmp == 0xDEADBEEF)
1897                         break;
1898                 DRM_UDELAY(1);
1899         }
1900         if (i < adev->usec_timeout) {
1901                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
1902         } else {
1903                 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
1904                           ring->idx, scratch, tmp);
1905                 r = -EINVAL;
1906         }
1907         amdgpu_gfx_scratch_free(adev, scratch);
1908         return r;
1909 }
1910
1911 /**
1912  * gfx_v7_0_ring_emit_hdp - emit an hdp flush on the cp
1913  *
1914  * @adev: amdgpu_device pointer
1915  * @ridx: amdgpu ring index
1916  *
1917  * Emits an hdp flush on the cp.
1918  */
1919 static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
1920 {
1921         u32 ref_and_mask;
1922         int usepfp = ring->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1;
1923
1924         if (ring->type == AMDGPU_RING_TYPE_COMPUTE) {
1925                 switch (ring->me) {
1926                 case 1:
1927                         ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
1928                         break;
1929                 case 2:
1930                         ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
1931                         break;
1932                 default:
1933                         return;
1934                 }
1935         } else {
1936                 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
1937         }
1938
1939         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
1940         amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
1941                                  WAIT_REG_MEM_FUNCTION(3) |  /* == */
1942                                  WAIT_REG_MEM_ENGINE(usepfp)));   /* pfp or me */
1943         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
1944         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
1945         amdgpu_ring_write(ring, ref_and_mask);
1946         amdgpu_ring_write(ring, ref_and_mask);
1947         amdgpu_ring_write(ring, 0x20); /* poll interval */
1948 }
1949
1950 /**
1951  * gfx_v7_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp
1952  *
1953  * @adev: amdgpu_device pointer
1954  * @ridx: amdgpu ring index
1955  *
1956  * Emits an hdp invalidate on the cp.
1957  */
1958 static void gfx_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
1959 {
1960         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1961         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
1962                                  WRITE_DATA_DST_SEL(0) |
1963                                  WR_CONFIRM));
1964         amdgpu_ring_write(ring, mmHDP_DEBUG0);
1965         amdgpu_ring_write(ring, 0);
1966         amdgpu_ring_write(ring, 1);
1967 }
1968
1969 /**
1970  * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring
1971  *
1972  * @adev: amdgpu_device pointer
1973  * @fence: amdgpu fence object
1974  *
1975  * Emits a fence sequnce number on the gfx ring and flushes
1976  * GPU caches.
1977  */
1978 static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
1979                                          u64 seq, unsigned flags)
1980 {
1981         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
1982         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
1983         /* Workaround for cache flush problems. First send a dummy EOP
1984          * event down the pipe with seq one below.
1985          */
1986         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1987         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
1988                                  EOP_TC_ACTION_EN |
1989                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
1990                                  EVENT_INDEX(5)));
1991         amdgpu_ring_write(ring, addr & 0xfffffffc);
1992         amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
1993                                 DATA_SEL(1) | INT_SEL(0));
1994         amdgpu_ring_write(ring, lower_32_bits(seq - 1));
1995         amdgpu_ring_write(ring, upper_32_bits(seq - 1));
1996
1997         /* Then send the real EOP event down the pipe. */
1998         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1999         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2000                                  EOP_TC_ACTION_EN |
2001                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2002                                  EVENT_INDEX(5)));
2003         amdgpu_ring_write(ring, addr & 0xfffffffc);
2004         amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
2005                                 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2006         amdgpu_ring_write(ring, lower_32_bits(seq));
2007         amdgpu_ring_write(ring, upper_32_bits(seq));
2008 }
2009
2010 /**
2011  * gfx_v7_0_ring_emit_fence_compute - emit a fence on the compute ring
2012  *
2013  * @adev: amdgpu_device pointer
2014  * @fence: amdgpu fence object
2015  *
2016  * Emits a fence sequnce number on the compute ring and flushes
2017  * GPU caches.
2018  */
2019 static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
2020                                              u64 addr, u64 seq,
2021                                              unsigned flags)
2022 {
2023         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2024         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2025
2026         /* RELEASE_MEM - flush caches, send int */
2027         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
2028         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2029                                  EOP_TC_ACTION_EN |
2030                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2031                                  EVENT_INDEX(5)));
2032         amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2033         amdgpu_ring_write(ring, addr & 0xfffffffc);
2034         amdgpu_ring_write(ring, upper_32_bits(addr));
2035         amdgpu_ring_write(ring, lower_32_bits(seq));
2036         amdgpu_ring_write(ring, upper_32_bits(seq));
2037 }
2038
2039 /*
2040  * IB stuff
2041  */
2042 /**
2043  * gfx_v7_0_ring_emit_ib - emit an IB (Indirect Buffer) on the ring
2044  *
2045  * @ring: amdgpu_ring structure holding ring information
2046  * @ib: amdgpu indirect buffer object
2047  *
2048  * Emits an DE (drawing engine) or CE (constant engine) IB
2049  * on the gfx ring.  IBs are usually generated by userspace
2050  * acceleration drivers and submitted to the kernel for
2051  * sheduling on the ring.  This function schedules the IB
2052  * on the gfx ring for execution by the GPU.
2053  */
2054 static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
2055                                       struct amdgpu_ib *ib,
2056                                       unsigned vm_id, bool ctx_switch)
2057 {
2058         u32 header, control = 0;
2059         u32 next_rptr = ring->wptr + 5;
2060
2061         if (ctx_switch)
2062                 next_rptr += 2;
2063
2064         next_rptr += 4;
2065         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2066         amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
2067         amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
2068         amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
2069         amdgpu_ring_write(ring, next_rptr);
2070
2071         /* insert SWITCH_BUFFER packet before first IB in the ring frame */
2072         if (ctx_switch) {
2073                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2074                 amdgpu_ring_write(ring, 0);
2075         }
2076
2077         if (ib->flags & AMDGPU_IB_FLAG_CE)
2078                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
2079         else
2080                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2081
2082         control |= ib->length_dw | (vm_id << 24);
2083
2084         amdgpu_ring_write(ring, header);
2085         amdgpu_ring_write(ring,
2086 #ifdef __BIG_ENDIAN
2087                           (2 << 0) |
2088 #endif
2089                           (ib->gpu_addr & 0xFFFFFFFC));
2090         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2091         amdgpu_ring_write(ring, control);
2092 }
2093
2094 static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
2095                                           struct amdgpu_ib *ib,
2096                                           unsigned vm_id, bool ctx_switch)
2097 {
2098         u32 header, control = 0;
2099         u32 next_rptr = ring->wptr + 5;
2100
2101         control |= INDIRECT_BUFFER_VALID;
2102         next_rptr += 4;
2103         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2104         amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
2105         amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
2106         amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
2107         amdgpu_ring_write(ring, next_rptr);
2108
2109         header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2110
2111         control |= ib->length_dw | (vm_id << 24);
2112
2113         amdgpu_ring_write(ring, header);
2114         amdgpu_ring_write(ring,
2115 #ifdef __BIG_ENDIAN
2116                                           (2 << 0) |
2117 #endif
2118                                           (ib->gpu_addr & 0xFFFFFFFC));
2119         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2120         amdgpu_ring_write(ring, control);
2121 }
2122
2123 /**
2124  * gfx_v7_0_ring_test_ib - basic ring IB test
2125  *
2126  * @ring: amdgpu_ring structure holding ring information
2127  *
2128  * Allocate an IB and execute it on the gfx ring (CIK).
2129  * Provides a basic gfx ring test to verify that IBs are working.
2130  * Returns 0 on success, error on failure.
2131  */
2132 static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring)
2133 {
2134         struct amdgpu_device *adev = ring->adev;
2135         struct amdgpu_ib ib;
2136         struct fence *f = NULL;
2137         uint32_t scratch;
2138         uint32_t tmp = 0;
2139         unsigned i;
2140         int r;
2141
2142         r = amdgpu_gfx_scratch_get(adev, &scratch);
2143         if (r) {
2144                 DRM_ERROR("amdgpu: failed to get scratch reg (%d).\n", r);
2145                 return r;
2146         }
2147         WREG32(scratch, 0xCAFEDEAD);
2148         memset(&ib, 0, sizeof(ib));
2149         r = amdgpu_ib_get(adev, NULL, 256, &ib);
2150         if (r) {
2151                 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
2152                 goto err1;
2153         }
2154         ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
2155         ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
2156         ib.ptr[2] = 0xDEADBEEF;
2157         ib.length_dw = 3;
2158
2159         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
2160         if (r)
2161                 goto err2;
2162
2163         r = fence_wait(f, false);
2164         if (r) {
2165                 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
2166                 goto err2;
2167         }
2168         for (i = 0; i < adev->usec_timeout; i++) {
2169                 tmp = RREG32(scratch);
2170                 if (tmp == 0xDEADBEEF)
2171                         break;
2172                 DRM_UDELAY(1);
2173         }
2174         if (i < adev->usec_timeout) {
2175                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
2176                          ring->idx, i);
2177                 goto err2;
2178         } else {
2179                 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
2180                           scratch, tmp);
2181                 r = -EINVAL;
2182         }
2183
2184 err2:
2185         fence_put(f);
2186         amdgpu_ib_free(adev, &ib, NULL);
2187         fence_put(f);
2188 err1:
2189         amdgpu_gfx_scratch_free(adev, scratch);
2190         return r;
2191 }
2192
2193 /*
2194  * CP.
2195  * On CIK, gfx and compute now have independant command processors.
2196  *
2197  * GFX
2198  * Gfx consists of a single ring and can process both gfx jobs and
2199  * compute jobs.  The gfx CP consists of three microengines (ME):
2200  * PFP - Pre-Fetch Parser
2201  * ME - Micro Engine
2202  * CE - Constant Engine
2203  * The PFP and ME make up what is considered the Drawing Engine (DE).
2204  * The CE is an asynchronous engine used for updating buffer desciptors
2205  * used by the DE so that they can be loaded into cache in parallel
2206  * while the DE is processing state update packets.
2207  *
2208  * Compute
2209  * The compute CP consists of two microengines (ME):
2210  * MEC1 - Compute MicroEngine 1
2211  * MEC2 - Compute MicroEngine 2
2212  * Each MEC supports 4 compute pipes and each pipe supports 8 queues.
2213  * The queues are exposed to userspace and are programmed directly
2214  * by the compute runtime.
2215  */
2216 /**
2217  * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs
2218  *
2219  * @adev: amdgpu_device pointer
2220  * @enable: enable or disable the MEs
2221  *
2222  * Halts or unhalts the gfx MEs.
2223  */
2224 static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2225 {
2226         int i;
2227
2228         if (enable) {
2229                 WREG32(mmCP_ME_CNTL, 0);
2230         } else {
2231                 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK));
2232                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2233                         adev->gfx.gfx_ring[i].ready = false;
2234         }
2235         udelay(50);
2236 }
2237
2238 /**
2239  * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode
2240  *
2241  * @adev: amdgpu_device pointer
2242  *
2243  * Loads the gfx PFP, ME, and CE ucode.
2244  * Returns 0 for success, -EINVAL if the ucode is not available.
2245  */
2246 static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2247 {
2248         const struct gfx_firmware_header_v1_0 *pfp_hdr;
2249         const struct gfx_firmware_header_v1_0 *ce_hdr;
2250         const struct gfx_firmware_header_v1_0 *me_hdr;
2251         const __le32 *fw_data;
2252         unsigned i, fw_size;
2253
2254         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2255                 return -EINVAL;
2256
2257         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2258         ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2259         me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2260
2261         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2262         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2263         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2264         adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version);
2265         adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version);
2266         adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version);
2267         adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version);
2268         adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version);
2269         adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version);
2270
2271         gfx_v7_0_cp_gfx_enable(adev, false);
2272
2273         /* PFP */
2274         fw_data = (const __le32 *)
2275                 (adev->gfx.pfp_fw->data +
2276                  le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2277         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2278         WREG32(mmCP_PFP_UCODE_ADDR, 0);
2279         for (i = 0; i < fw_size; i++)
2280                 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2281         WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2282
2283         /* CE */
2284         fw_data = (const __le32 *)
2285                 (adev->gfx.ce_fw->data +
2286                  le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2287         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2288         WREG32(mmCP_CE_UCODE_ADDR, 0);
2289         for (i = 0; i < fw_size; i++)
2290                 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2291         WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2292
2293         /* ME */
2294         fw_data = (const __le32 *)
2295                 (adev->gfx.me_fw->data +
2296                  le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2297         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2298         WREG32(mmCP_ME_RAM_WADDR, 0);
2299         for (i = 0; i < fw_size; i++)
2300                 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2301         WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2302
2303         return 0;
2304 }
2305
2306 /**
2307  * gfx_v7_0_cp_gfx_start - start the gfx ring
2308  *
2309  * @adev: amdgpu_device pointer
2310  *
2311  * Enables the ring and loads the clear state context and other
2312  * packets required to init the ring.
2313  * Returns 0 for success, error for failure.
2314  */
2315 static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev)
2316 {
2317         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2318         const struct cs_section_def *sect = NULL;
2319         const struct cs_extent_def *ext = NULL;
2320         int r, i;
2321
2322         /* init the CP */
2323         WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2324         WREG32(mmCP_ENDIAN_SWAP, 0);
2325         WREG32(mmCP_DEVICE_ID, 1);
2326
2327         gfx_v7_0_cp_gfx_enable(adev, true);
2328
2329         r = amdgpu_ring_alloc(ring, gfx_v7_0_get_csb_size(adev) + 8);
2330         if (r) {
2331                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2332                 return r;
2333         }
2334
2335         /* init the CE partitions.  CE only used for gfx on CIK */
2336         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2337         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2338         amdgpu_ring_write(ring, 0x8000);
2339         amdgpu_ring_write(ring, 0x8000);
2340
2341         /* clear state buffer */
2342         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2343         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2344
2345         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2346         amdgpu_ring_write(ring, 0x80000000);
2347         amdgpu_ring_write(ring, 0x80000000);
2348
2349         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2350                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2351                         if (sect->id == SECT_CONTEXT) {
2352                                 amdgpu_ring_write(ring,
2353                                                   PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2354                                 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2355                                 for (i = 0; i < ext->reg_count; i++)
2356                                         amdgpu_ring_write(ring, ext->extent[i]);
2357                         }
2358                 }
2359         }
2360
2361         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2362         amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2363         switch (adev->asic_type) {
2364         case CHIP_BONAIRE:
2365                 amdgpu_ring_write(ring, 0x16000012);
2366                 amdgpu_ring_write(ring, 0x00000000);
2367                 break;
2368         case CHIP_KAVERI:
2369                 amdgpu_ring_write(ring, 0x00000000); /* XXX */
2370                 amdgpu_ring_write(ring, 0x00000000);
2371                 break;
2372         case CHIP_KABINI:
2373         case CHIP_MULLINS:
2374                 amdgpu_ring_write(ring, 0x00000000); /* XXX */
2375                 amdgpu_ring_write(ring, 0x00000000);
2376                 break;
2377         case CHIP_HAWAII:
2378                 amdgpu_ring_write(ring, 0x3a00161a);
2379                 amdgpu_ring_write(ring, 0x0000002e);
2380                 break;
2381         default:
2382                 amdgpu_ring_write(ring, 0x00000000);
2383                 amdgpu_ring_write(ring, 0x00000000);
2384                 break;
2385         }
2386
2387         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2388         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2389
2390         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2391         amdgpu_ring_write(ring, 0);
2392
2393         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2394         amdgpu_ring_write(ring, 0x00000316);
2395         amdgpu_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
2396         amdgpu_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
2397
2398         amdgpu_ring_commit(ring);
2399
2400         return 0;
2401 }
2402
2403 /**
2404  * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers
2405  *
2406  * @adev: amdgpu_device pointer
2407  *
2408  * Program the location and size of the gfx ring buffer
2409  * and test it to make sure it's working.
2410  * Returns 0 for success, error for failure.
2411  */
2412 static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev)
2413 {
2414         struct amdgpu_ring *ring;
2415         u32 tmp;
2416         u32 rb_bufsz;
2417         u64 rb_addr, rptr_addr;
2418         int r;
2419
2420         WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
2421         if (adev->asic_type != CHIP_HAWAII)
2422                 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2423
2424         /* Set the write pointer delay */
2425         WREG32(mmCP_RB_WPTR_DELAY, 0);
2426
2427         /* set the RB to use vmid 0 */
2428         WREG32(mmCP_RB_VMID, 0);
2429
2430         WREG32(mmSCRATCH_ADDR, 0);
2431
2432         /* ring 0 - compute and gfx */
2433         /* Set ring buffer size */
2434         ring = &adev->gfx.gfx_ring[0];
2435         rb_bufsz = order_base_2(ring->ring_size / 8);
2436         tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2437 #ifdef __BIG_ENDIAN
2438         tmp |= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT;
2439 #endif
2440         WREG32(mmCP_RB0_CNTL, tmp);
2441
2442         /* Initialize the ring buffer's read and write pointers */
2443         WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2444         ring->wptr = 0;
2445         WREG32(mmCP_RB0_WPTR, ring->wptr);
2446
2447         /* set the wb address wether it's enabled or not */
2448         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2449         WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2450         WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2451
2452         /* scratch register shadowing is no longer supported */
2453         WREG32(mmSCRATCH_UMSK, 0);
2454
2455         mdelay(1);
2456         WREG32(mmCP_RB0_CNTL, tmp);
2457
2458         rb_addr = ring->gpu_addr >> 8;
2459         WREG32(mmCP_RB0_BASE, rb_addr);
2460         WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2461
2462         /* start the ring */
2463         gfx_v7_0_cp_gfx_start(adev);
2464         ring->ready = true;
2465         r = amdgpu_ring_test_ring(ring);
2466         if (r) {
2467                 ring->ready = false;
2468                 return r;
2469         }
2470
2471         return 0;
2472 }
2473
2474 static u32 gfx_v7_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
2475 {
2476         return ring->adev->wb.wb[ring->rptr_offs];
2477 }
2478
2479 static u32 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
2480 {
2481         struct amdgpu_device *adev = ring->adev;
2482
2483         return RREG32(mmCP_RB0_WPTR);
2484 }
2485
2486 static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2487 {
2488         struct amdgpu_device *adev = ring->adev;
2489
2490         WREG32(mmCP_RB0_WPTR, ring->wptr);
2491         (void)RREG32(mmCP_RB0_WPTR);
2492 }
2493
2494 static u32 gfx_v7_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
2495 {
2496         return ring->adev->wb.wb[ring->rptr_offs];
2497 }
2498
2499 static u32 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
2500 {
2501         /* XXX check if swapping is necessary on BE */
2502         return ring->adev->wb.wb[ring->wptr_offs];
2503 }
2504
2505 static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2506 {
2507         struct amdgpu_device *adev = ring->adev;
2508
2509         /* XXX check if swapping is necessary on BE */
2510         adev->wb.wb[ring->wptr_offs] = ring->wptr;
2511         WDOORBELL32(ring->doorbell_index, ring->wptr);
2512 }
2513
2514 /**
2515  * gfx_v7_0_cp_compute_enable - enable/disable the compute CP MEs
2516  *
2517  * @adev: amdgpu_device pointer
2518  * @enable: enable or disable the MEs
2519  *
2520  * Halts or unhalts the compute MEs.
2521  */
2522 static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2523 {
2524         int i;
2525
2526         if (enable) {
2527                 WREG32(mmCP_MEC_CNTL, 0);
2528         } else {
2529                 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2530                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2531                         adev->gfx.compute_ring[i].ready = false;
2532         }
2533         udelay(50);
2534 }
2535
2536 /**
2537  * gfx_v7_0_cp_compute_load_microcode - load the compute CP ME ucode
2538  *
2539  * @adev: amdgpu_device pointer
2540  *
2541  * Loads the compute MEC1&2 ucode.
2542  * Returns 0 for success, -EINVAL if the ucode is not available.
2543  */
2544 static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2545 {
2546         const struct gfx_firmware_header_v1_0 *mec_hdr;
2547         const __le32 *fw_data;
2548         unsigned i, fw_size;
2549
2550         if (!adev->gfx.mec_fw)
2551                 return -EINVAL;
2552
2553         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2554         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2555         adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version);
2556         adev->gfx.mec_feature_version = le32_to_cpu(
2557                                         mec_hdr->ucode_feature_version);
2558
2559         gfx_v7_0_cp_compute_enable(adev, false);
2560
2561         /* MEC1 */
2562         fw_data = (const __le32 *)
2563                 (adev->gfx.mec_fw->data +
2564                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2565         fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
2566         WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2567         for (i = 0; i < fw_size; i++)
2568                 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++));
2569         WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2570
2571         if (adev->asic_type == CHIP_KAVERI) {
2572                 const struct gfx_firmware_header_v1_0 *mec2_hdr;
2573
2574                 if (!adev->gfx.mec2_fw)
2575                         return -EINVAL;
2576
2577                 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2578                 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
2579                 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version);
2580                 adev->gfx.mec2_feature_version = le32_to_cpu(
2581                                 mec2_hdr->ucode_feature_version);
2582
2583                 /* MEC2 */
2584                 fw_data = (const __le32 *)
2585                         (adev->gfx.mec2_fw->data +
2586                          le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
2587                 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
2588                 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2589                 for (i = 0; i < fw_size; i++)
2590                         WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++));
2591                 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2592         }
2593
2594         return 0;
2595 }
2596
2597 /**
2598  * gfx_v7_0_cp_compute_fini - stop the compute queues
2599  *
2600  * @adev: amdgpu_device pointer
2601  *
2602  * Stop the compute queues and tear down the driver queue
2603  * info.
2604  */
2605 static void gfx_v7_0_cp_compute_fini(struct amdgpu_device *adev)
2606 {
2607         int i, r;
2608
2609         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2610                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2611
2612                 if (ring->mqd_obj) {
2613                         r = amdgpu_bo_reserve(ring->mqd_obj, false);
2614                         if (unlikely(r != 0))
2615                                 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
2616
2617                         amdgpu_bo_unpin(ring->mqd_obj);
2618                         amdgpu_bo_unreserve(ring->mqd_obj);
2619
2620                         amdgpu_bo_unref(&ring->mqd_obj);
2621                         ring->mqd_obj = NULL;
2622                 }
2623         }
2624 }
2625
2626 static void gfx_v7_0_mec_fini(struct amdgpu_device *adev)
2627 {
2628         int r;
2629
2630         if (adev->gfx.mec.hpd_eop_obj) {
2631                 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
2632                 if (unlikely(r != 0))
2633                         dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
2634                 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
2635                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
2636
2637                 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
2638                 adev->gfx.mec.hpd_eop_obj = NULL;
2639         }
2640 }
2641
2642 #define MEC_HPD_SIZE 2048
2643
2644 static int gfx_v7_0_mec_init(struct amdgpu_device *adev)
2645 {
2646         int r;
2647         u32 *hpd;
2648
2649         /*
2650          * KV:    2 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 64 Queues total
2651          * CI/KB: 1 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 32 Queues total
2652          * Nonetheless, we assign only 1 pipe because all other pipes will
2653          * be handled by KFD
2654          */
2655         adev->gfx.mec.num_mec = 1;
2656         adev->gfx.mec.num_pipe = 1;
2657         adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
2658
2659         if (adev->gfx.mec.hpd_eop_obj == NULL) {
2660                 r = amdgpu_bo_create(adev,
2661                                      adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
2662                                      PAGE_SIZE, true,
2663                                      AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
2664                                      &adev->gfx.mec.hpd_eop_obj);
2665                 if (r) {
2666                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
2667                         return r;
2668                 }
2669         }
2670
2671         r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
2672         if (unlikely(r != 0)) {
2673                 gfx_v7_0_mec_fini(adev);
2674                 return r;
2675         }
2676         r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
2677                           &adev->gfx.mec.hpd_eop_gpu_addr);
2678         if (r) {
2679                 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
2680                 gfx_v7_0_mec_fini(adev);
2681                 return r;
2682         }
2683         r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
2684         if (r) {
2685                 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
2686                 gfx_v7_0_mec_fini(adev);
2687                 return r;
2688         }
2689
2690         /* clear memory.  Not sure if this is required or not */
2691         memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2);
2692
2693         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
2694         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
2695
2696         return 0;
2697 }
2698
2699 struct hqd_registers
2700 {
2701         u32 cp_mqd_base_addr;
2702         u32 cp_mqd_base_addr_hi;
2703         u32 cp_hqd_active;
2704         u32 cp_hqd_vmid;
2705         u32 cp_hqd_persistent_state;
2706         u32 cp_hqd_pipe_priority;
2707         u32 cp_hqd_queue_priority;
2708         u32 cp_hqd_quantum;
2709         u32 cp_hqd_pq_base;
2710         u32 cp_hqd_pq_base_hi;
2711         u32 cp_hqd_pq_rptr;
2712         u32 cp_hqd_pq_rptr_report_addr;
2713         u32 cp_hqd_pq_rptr_report_addr_hi;
2714         u32 cp_hqd_pq_wptr_poll_addr;
2715         u32 cp_hqd_pq_wptr_poll_addr_hi;
2716         u32 cp_hqd_pq_doorbell_control;
2717         u32 cp_hqd_pq_wptr;
2718         u32 cp_hqd_pq_control;
2719         u32 cp_hqd_ib_base_addr;
2720         u32 cp_hqd_ib_base_addr_hi;
2721         u32 cp_hqd_ib_rptr;
2722         u32 cp_hqd_ib_control;
2723         u32 cp_hqd_iq_timer;
2724         u32 cp_hqd_iq_rptr;
2725         u32 cp_hqd_dequeue_request;
2726         u32 cp_hqd_dma_offload;
2727         u32 cp_hqd_sema_cmd;
2728         u32 cp_hqd_msg_type;
2729         u32 cp_hqd_atomic0_preop_lo;
2730         u32 cp_hqd_atomic0_preop_hi;
2731         u32 cp_hqd_atomic1_preop_lo;
2732         u32 cp_hqd_atomic1_preop_hi;
2733         u32 cp_hqd_hq_scheduler0;
2734         u32 cp_hqd_hq_scheduler1;
2735         u32 cp_mqd_control;
2736 };
2737
2738 struct bonaire_mqd
2739 {
2740         u32 header;
2741         u32 dispatch_initiator;
2742         u32 dimensions[3];
2743         u32 start_idx[3];
2744         u32 num_threads[3];
2745         u32 pipeline_stat_enable;
2746         u32 perf_counter_enable;
2747         u32 pgm[2];
2748         u32 tba[2];
2749         u32 tma[2];
2750         u32 pgm_rsrc[2];
2751         u32 vmid;
2752         u32 resource_limits;
2753         u32 static_thread_mgmt01[2];
2754         u32 tmp_ring_size;
2755         u32 static_thread_mgmt23[2];
2756         u32 restart[3];
2757         u32 thread_trace_enable;
2758         u32 reserved1;
2759         u32 user_data[16];
2760         u32 vgtcs_invoke_count[2];
2761         struct hqd_registers queue_state;
2762         u32 dequeue_cntr;
2763         u32 interrupt_queue[64];
2764 };
2765
2766 /**
2767  * gfx_v7_0_cp_compute_resume - setup the compute queue registers
2768  *
2769  * @adev: amdgpu_device pointer
2770  *
2771  * Program the compute queues and test them to make sure they
2772  * are working.
2773  * Returns 0 for success, error for failure.
2774  */
2775 static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev)
2776 {
2777         int r, i, j;
2778         u32 tmp;
2779         bool use_doorbell = true;
2780         u64 hqd_gpu_addr;
2781         u64 mqd_gpu_addr;
2782         u64 eop_gpu_addr;
2783         u64 wb_gpu_addr;
2784         u32 *buf;
2785         struct bonaire_mqd *mqd;
2786
2787         gfx_v7_0_cp_compute_enable(adev, true);
2788
2789         /* fix up chicken bits */
2790         tmp = RREG32(mmCP_CPF_DEBUG);
2791         tmp |= (1 << 23);
2792         WREG32(mmCP_CPF_DEBUG, tmp);
2793
2794         /* init the pipes */
2795         mutex_lock(&adev->srbm_mutex);
2796         for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
2797                 int me = (i < 4) ? 1 : 2;
2798                 int pipe = (i < 4) ? i : (i - 4);
2799
2800                 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE * 2);
2801
2802                 cik_srbm_select(adev, me, pipe, 0, 0);
2803
2804                 /* write the EOP addr */
2805                 WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8);
2806                 WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);
2807
2808                 /* set the VMID assigned */
2809                 WREG32(mmCP_HPD_EOP_VMID, 0);
2810
2811                 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2812                 tmp = RREG32(mmCP_HPD_EOP_CONTROL);
2813                 tmp &= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK;
2814                 tmp |= order_base_2(MEC_HPD_SIZE / 8);
2815                 WREG32(mmCP_HPD_EOP_CONTROL, tmp);
2816         }
2817         cik_srbm_select(adev, 0, 0, 0, 0);
2818         mutex_unlock(&adev->srbm_mutex);
2819
2820         /* init the queues.  Just two for now. */
2821         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2822                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2823
2824                 if (ring->mqd_obj == NULL) {
2825                         r = amdgpu_bo_create(adev,
2826                                              sizeof(struct bonaire_mqd),
2827                                              PAGE_SIZE, true,
2828                                              AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
2829                                              &ring->mqd_obj);
2830                         if (r) {
2831                                 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
2832                                 return r;
2833                         }
2834                 }
2835
2836                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2837                 if (unlikely(r != 0)) {
2838                         gfx_v7_0_cp_compute_fini(adev);
2839                         return r;
2840                 }
2841                 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
2842                                   &mqd_gpu_addr);
2843                 if (r) {
2844                         dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
2845                         gfx_v7_0_cp_compute_fini(adev);
2846                         return r;
2847                 }
2848                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
2849                 if (r) {
2850                         dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
2851                         gfx_v7_0_cp_compute_fini(adev);
2852                         return r;
2853                 }
2854
2855                 /* init the mqd struct */
2856                 memset(buf, 0, sizeof(struct bonaire_mqd));
2857
2858                 mqd = (struct bonaire_mqd *)buf;
2859                 mqd->header = 0xC0310800;
2860                 mqd->static_thread_mgmt01[0] = 0xffffffff;
2861                 mqd->static_thread_mgmt01[1] = 0xffffffff;
2862                 mqd->static_thread_mgmt23[0] = 0xffffffff;
2863                 mqd->static_thread_mgmt23[1] = 0xffffffff;
2864
2865                 mutex_lock(&adev->srbm_mutex);
2866                 cik_srbm_select(adev, ring->me,
2867                                 ring->pipe,
2868                                 ring->queue, 0);
2869
2870                 /* disable wptr polling */
2871                 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
2872                 tmp &= ~CP_PQ_WPTR_POLL_CNTL__EN_MASK;
2873                 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
2874
2875                 /* enable doorbell? */
2876                 mqd->queue_state.cp_hqd_pq_doorbell_control =
2877                         RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
2878                 if (use_doorbell)
2879                         mqd->queue_state.cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2880                 else
2881                         mqd->queue_state.cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2882                 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
2883                        mqd->queue_state.cp_hqd_pq_doorbell_control);
2884
2885                 /* disable the queue if it's active */
2886                 mqd->queue_state.cp_hqd_dequeue_request = 0;
2887                 mqd->queue_state.cp_hqd_pq_rptr = 0;
2888                 mqd->queue_state.cp_hqd_pq_wptr= 0;
2889                 if (RREG32(mmCP_HQD_ACTIVE) & 1) {
2890                         WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
2891                         for (j = 0; j < adev->usec_timeout; j++) {
2892                                 if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
2893                                         break;
2894                                 udelay(1);
2895                         }
2896                         WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request);
2897                         WREG32(mmCP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr);
2898                         WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
2899                 }
2900
2901                 /* set the pointer to the MQD */
2902                 mqd->queue_state.cp_mqd_base_addr = mqd_gpu_addr & 0xfffffffc;
2903                 mqd->queue_state.cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
2904                 WREG32(mmCP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr);
2905                 WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi);
2906                 /* set MQD vmid to 0 */
2907                 mqd->queue_state.cp_mqd_control = RREG32(mmCP_MQD_CONTROL);
2908                 mqd->queue_state.cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK;
2909                 WREG32(mmCP_MQD_CONTROL, mqd->queue_state.cp_mqd_control);
2910
2911                 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2912                 hqd_gpu_addr = ring->gpu_addr >> 8;
2913                 mqd->queue_state.cp_hqd_pq_base = hqd_gpu_addr;
2914                 mqd->queue_state.cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
2915                 WREG32(mmCP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base);
2916                 WREG32(mmCP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi);
2917
2918                 /* set up the HQD, this is similar to CP_RB0_CNTL */
2919                 mqd->queue_state.cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL);
2920                 mqd->queue_state.cp_hqd_pq_control &=
2921                         ~(CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK |
2922                                         CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK);
2923
2924                 mqd->queue_state.cp_hqd_pq_control |=
2925                         order_base_2(ring->ring_size / 8);
2926                 mqd->queue_state.cp_hqd_pq_control |=
2927                         (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8);
2928 #ifdef __BIG_ENDIAN
2929                 mqd->queue_state.cp_hqd_pq_control |=
2930                         2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT;
2931 #endif
2932                 mqd->queue_state.cp_hqd_pq_control &=
2933                         ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK |
2934                                 CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK |
2935                                 CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK);
2936                 mqd->queue_state.cp_hqd_pq_control |=
2937                         CP_HQD_PQ_CONTROL__PRIV_STATE_MASK |
2938                         CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK; /* assuming kernel queue control */
2939                 WREG32(mmCP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control);
2940
2941                 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2942                 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2943                 mqd->queue_state.cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
2944                 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2945                 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr);
2946                 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
2947                        mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi);
2948
2949                 /* set the wb address wether it's enabled or not */
2950                 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2951                 mqd->queue_state.cp_hqd_pq_rptr_report_addr = wb_gpu_addr & 0xfffffffc;
2952                 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi =
2953                         upper_32_bits(wb_gpu_addr) & 0xffff;
2954                 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR,
2955                        mqd->queue_state.cp_hqd_pq_rptr_report_addr);
2956                 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
2957                        mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi);
2958
2959                 /* enable the doorbell if requested */
2960                 if (use_doorbell) {
2961                         mqd->queue_state.cp_hqd_pq_doorbell_control =
2962                                 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
2963                         mqd->queue_state.cp_hqd_pq_doorbell_control &=
2964                                 ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK;
2965                         mqd->queue_state.cp_hqd_pq_doorbell_control |=
2966                                 (ring->doorbell_index <<
2967                                  CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT);
2968                         mqd->queue_state.cp_hqd_pq_doorbell_control |=
2969                                 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2970                         mqd->queue_state.cp_hqd_pq_doorbell_control &=
2971                                 ~(CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK |
2972                                 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK);
2973
2974                 } else {
2975                         mqd->queue_state.cp_hqd_pq_doorbell_control = 0;
2976                 }
2977                 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
2978                        mqd->queue_state.cp_hqd_pq_doorbell_control);
2979
2980                 /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2981                 ring->wptr = 0;
2982                 mqd->queue_state.cp_hqd_pq_wptr = ring->wptr;
2983                 WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
2984                 mqd->queue_state.cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
2985
2986                 /* set the vmid for the queue */
2987                 mqd->queue_state.cp_hqd_vmid = 0;
2988                 WREG32(mmCP_HQD_VMID, mqd->queue_state.cp_hqd_vmid);
2989
2990                 /* activate the queue */
2991                 mqd->queue_state.cp_hqd_active = 1;
2992                 WREG32(mmCP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active);
2993
2994                 cik_srbm_select(adev, 0, 0, 0, 0);
2995                 mutex_unlock(&adev->srbm_mutex);
2996
2997                 amdgpu_bo_kunmap(ring->mqd_obj);
2998                 amdgpu_bo_unreserve(ring->mqd_obj);
2999
3000                 ring->ready = true;
3001                 r = amdgpu_ring_test_ring(ring);
3002                 if (r)
3003                         ring->ready = false;
3004         }
3005
3006         return 0;
3007 }
3008
3009 static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable)
3010 {
3011         gfx_v7_0_cp_gfx_enable(adev, enable);
3012         gfx_v7_0_cp_compute_enable(adev, enable);
3013 }
3014
3015 static int gfx_v7_0_cp_load_microcode(struct amdgpu_device *adev)
3016 {
3017         int r;
3018
3019         r = gfx_v7_0_cp_gfx_load_microcode(adev);
3020         if (r)
3021                 return r;
3022         r = gfx_v7_0_cp_compute_load_microcode(adev);
3023         if (r)
3024                 return r;
3025
3026         return 0;
3027 }
3028
3029 static void gfx_v7_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
3030                                                bool enable)
3031 {
3032         u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
3033
3034         if (enable)
3035                 tmp |= (CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3036                                 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3037         else
3038                 tmp &= ~(CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3039                                 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3040         WREG32(mmCP_INT_CNTL_RING0, tmp);
3041 }
3042
3043 static int gfx_v7_0_cp_resume(struct amdgpu_device *adev)
3044 {
3045         int r;
3046
3047         gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3048
3049         r = gfx_v7_0_cp_load_microcode(adev);
3050         if (r)
3051                 return r;
3052
3053         r = gfx_v7_0_cp_gfx_resume(adev);
3054         if (r)
3055                 return r;
3056         r = gfx_v7_0_cp_compute_resume(adev);
3057         if (r)
3058                 return r;
3059
3060         gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3061
3062         return 0;
3063 }
3064
3065 /**
3066  * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3067  *
3068  * @ring: the ring to emmit the commands to
3069  *
3070  * Sync the command pipeline with the PFP. E.g. wait for everything
3071  * to be completed.
3072  */
3073 static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
3074 {
3075         int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
3076         uint32_t seq = ring->fence_drv.sync_seq;
3077         uint64_t addr = ring->fence_drv.gpu_addr;
3078
3079         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3080         amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
3081                                  WAIT_REG_MEM_FUNCTION(3) | /* equal */
3082                                  WAIT_REG_MEM_ENGINE(usepfp)));   /* pfp or me */
3083         amdgpu_ring_write(ring, addr & 0xfffffffc);
3084         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
3085         amdgpu_ring_write(ring, seq);
3086         amdgpu_ring_write(ring, 0xffffffff);
3087         amdgpu_ring_write(ring, 4); /* poll interval */
3088
3089         if (usepfp) {
3090                 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3091                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3092                 amdgpu_ring_write(ring, 0);
3093                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3094                 amdgpu_ring_write(ring, 0);
3095         }
3096 }
3097
3098 /*
3099  * vm
3100  * VMID 0 is the physical GPU addresses as used by the kernel.
3101  * VMIDs 1-15 are used for userspace clients and are handled
3102  * by the amdgpu vm/hsa code.
3103  */
3104 /**
3105  * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3106  *
3107  * @adev: amdgpu_device pointer
3108  *
3109  * Update the page table base and flush the VM TLB
3110  * using the CP (CIK).
3111  */
3112 static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3113                                         unsigned vm_id, uint64_t pd_addr)
3114 {
3115         int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
3116
3117         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3118         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
3119                                  WRITE_DATA_DST_SEL(0)));
3120         if (vm_id < 8) {
3121                 amdgpu_ring_write(ring,
3122                                   (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
3123         } else {
3124                 amdgpu_ring_write(ring,
3125                                   (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
3126         }
3127         amdgpu_ring_write(ring, 0);
3128         amdgpu_ring_write(ring, pd_addr >> 12);
3129
3130         /* bits 0-15 are the VM contexts0-15 */
3131         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3132         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3133                                  WRITE_DATA_DST_SEL(0)));
3134         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3135         amdgpu_ring_write(ring, 0);
3136         amdgpu_ring_write(ring, 1 << vm_id);
3137
3138         /* wait for the invalidate to complete */
3139         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3140         amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
3141                                  WAIT_REG_MEM_FUNCTION(0) |  /* always */
3142                                  WAIT_REG_MEM_ENGINE(0))); /* me */
3143         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3144         amdgpu_ring_write(ring, 0);
3145         amdgpu_ring_write(ring, 0); /* ref */
3146         amdgpu_ring_write(ring, 0); /* mask */
3147         amdgpu_ring_write(ring, 0x20); /* poll interval */
3148
3149         /* compute doesn't have PFP */
3150         if (usepfp) {
3151                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3152                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3153                 amdgpu_ring_write(ring, 0x0);
3154
3155                 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3156                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3157                 amdgpu_ring_write(ring, 0);
3158                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3159                 amdgpu_ring_write(ring, 0);
3160         }
3161 }
3162
3163 /*
3164  * RLC
3165  * The RLC is a multi-purpose microengine that handles a
3166  * variety of functions.
3167  */
3168 static void gfx_v7_0_rlc_fini(struct amdgpu_device *adev)
3169 {
3170         int r;
3171
3172         /* save restore block */
3173         if (adev->gfx.rlc.save_restore_obj) {
3174                 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
3175                 if (unlikely(r != 0))
3176                         dev_warn(adev->dev, "(%d) reserve RLC sr bo failed\n", r);
3177                 amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj);
3178                 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3179
3180                 amdgpu_bo_unref(&adev->gfx.rlc.save_restore_obj);
3181                 adev->gfx.rlc.save_restore_obj = NULL;
3182         }
3183
3184         /* clear state block */
3185         if (adev->gfx.rlc.clear_state_obj) {
3186                 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
3187                 if (unlikely(r != 0))
3188                         dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r);
3189                 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
3190                 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3191
3192                 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
3193                 adev->gfx.rlc.clear_state_obj = NULL;
3194         }
3195
3196         /* clear state block */
3197         if (adev->gfx.rlc.cp_table_obj) {
3198                 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
3199                 if (unlikely(r != 0))
3200                         dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
3201                 amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj);
3202                 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3203
3204                 amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj);
3205                 adev->gfx.rlc.cp_table_obj = NULL;
3206         }
3207 }
3208
3209 static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
3210 {
3211         const u32 *src_ptr;
3212         volatile u32 *dst_ptr;
3213         u32 dws, i;
3214         const struct cs_section_def *cs_data;
3215         int r;
3216
3217         /* allocate rlc buffers */
3218         if (adev->flags & AMD_IS_APU) {
3219                 if (adev->asic_type == CHIP_KAVERI) {
3220                         adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list;
3221                         adev->gfx.rlc.reg_list_size =
3222                                 (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list);
3223                 } else {
3224                         adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list;
3225                         adev->gfx.rlc.reg_list_size =
3226                                 (u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list);
3227                 }
3228         }
3229         adev->gfx.rlc.cs_data = ci_cs_data;
3230         adev->gfx.rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */
3231         adev->gfx.rlc.cp_table_size += 64 * 1024; /* GDS */
3232
3233         src_ptr = adev->gfx.rlc.reg_list;
3234         dws = adev->gfx.rlc.reg_list_size;
3235         dws += (5 * 16) + 48 + 48 + 64;
3236
3237         cs_data = adev->gfx.rlc.cs_data;
3238
3239         if (src_ptr) {
3240                 /* save restore block */
3241                 if (adev->gfx.rlc.save_restore_obj == NULL) {
3242                         r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
3243                                              AMDGPU_GEM_DOMAIN_VRAM,
3244                                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
3245                                              NULL, NULL,
3246                                              &adev->gfx.rlc.save_restore_obj);
3247                         if (r) {
3248                                 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r);
3249                                 return r;
3250                         }
3251                 }
3252
3253                 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
3254                 if (unlikely(r != 0)) {
3255                         gfx_v7_0_rlc_fini(adev);
3256                         return r;
3257                 }
3258                 r = amdgpu_bo_pin(adev->gfx.rlc.save_restore_obj, AMDGPU_GEM_DOMAIN_VRAM,
3259                                   &adev->gfx.rlc.save_restore_gpu_addr);
3260                 if (r) {
3261                         amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3262                         dev_warn(adev->dev, "(%d) pin RLC sr bo failed\n", r);
3263                         gfx_v7_0_rlc_fini(adev);
3264                         return r;
3265                 }
3266
3267                 r = amdgpu_bo_kmap(adev->gfx.rlc.save_restore_obj, (void **)&adev->gfx.rlc.sr_ptr);
3268                 if (r) {
3269                         dev_warn(adev->dev, "(%d) map RLC sr bo failed\n", r);
3270                         gfx_v7_0_rlc_fini(adev);
3271                         return r;
3272                 }
3273                 /* write the sr buffer */
3274                 dst_ptr = adev->gfx.rlc.sr_ptr;
3275                 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
3276                         dst_ptr[i] = cpu_to_le32(src_ptr[i]);
3277                 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
3278                 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3279         }
3280
3281         if (cs_data) {
3282                 /* clear state block */
3283                 adev->gfx.rlc.clear_state_size = dws = gfx_v7_0_get_csb_size(adev);
3284
3285                 if (adev->gfx.rlc.clear_state_obj == NULL) {
3286                         r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
3287                                              AMDGPU_GEM_DOMAIN_VRAM,
3288                                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
3289                                              NULL, NULL,
3290                                              &adev->gfx.rlc.clear_state_obj);
3291                         if (r) {
3292                                 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
3293                                 gfx_v7_0_rlc_fini(adev);
3294                                 return r;
3295                         }
3296                 }
3297                 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
3298                 if (unlikely(r != 0)) {
3299                         gfx_v7_0_rlc_fini(adev);
3300                         return r;
3301                 }
3302                 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM,
3303                                   &adev->gfx.rlc.clear_state_gpu_addr);
3304                 if (r) {
3305                         amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3306                         dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r);
3307                         gfx_v7_0_rlc_fini(adev);
3308                         return r;
3309                 }
3310
3311                 r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr);
3312                 if (r) {
3313                         dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r);
3314                         gfx_v7_0_rlc_fini(adev);
3315                         return r;
3316                 }
3317                 /* set up the cs buffer */
3318                 dst_ptr = adev->gfx.rlc.cs_ptr;
3319                 gfx_v7_0_get_csb_buffer(adev, dst_ptr);
3320                 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
3321                 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3322         }
3323
3324         if (adev->gfx.rlc.cp_table_size) {
3325                 if (adev->gfx.rlc.cp_table_obj == NULL) {
3326                         r = amdgpu_bo_create(adev, adev->gfx.rlc.cp_table_size, PAGE_SIZE, true,
3327                                              AMDGPU_GEM_DOMAIN_VRAM,
3328                                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
3329                                              NULL, NULL,
3330                                              &adev->gfx.rlc.cp_table_obj);
3331                         if (r) {
3332                                 dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r);
3333                                 gfx_v7_0_rlc_fini(adev);
3334                                 return r;
3335                         }
3336                 }
3337
3338                 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
3339                 if (unlikely(r != 0)) {
3340                         dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
3341                         gfx_v7_0_rlc_fini(adev);
3342                         return r;
3343                 }
3344                 r = amdgpu_bo_pin(adev->gfx.rlc.cp_table_obj, AMDGPU_GEM_DOMAIN_VRAM,
3345                                   &adev->gfx.rlc.cp_table_gpu_addr);
3346                 if (r) {
3347                         amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3348                         dev_warn(adev->dev, "(%d) pin RLC cp_table bo failed\n", r);
3349                         gfx_v7_0_rlc_fini(adev);
3350                         return r;
3351                 }
3352                 r = amdgpu_bo_kmap(adev->gfx.rlc.cp_table_obj, (void **)&adev->gfx.rlc.cp_table_ptr);
3353                 if (r) {
3354                         dev_warn(adev->dev, "(%d) map RLC cp table bo failed\n", r);
3355                         gfx_v7_0_rlc_fini(adev);
3356                         return r;
3357                 }
3358
3359                 gfx_v7_0_init_cp_pg_table(adev);
3360
3361                 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
3362                 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3363
3364         }
3365
3366         return 0;
3367 }
3368
3369 static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
3370 {
3371         u32 tmp;
3372
3373         tmp = RREG32(mmRLC_LB_CNTL);
3374         if (enable)
3375                 tmp |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3376         else
3377                 tmp &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3378         WREG32(mmRLC_LB_CNTL, tmp);
3379 }
3380
3381 static void gfx_v7_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
3382 {
3383         u32 i, j, k;
3384         u32 mask;
3385
3386         mutex_lock(&adev->grbm_idx_mutex);
3387         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3388                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3389                         gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
3390                         for (k = 0; k < adev->usec_timeout; k++) {
3391                                 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
3392                                         break;
3393                                 udelay(1);
3394                         }
3395                 }
3396         }
3397         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3398         mutex_unlock(&adev->grbm_idx_mutex);
3399
3400         mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
3401                 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
3402                 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
3403                 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
3404         for (k = 0; k < adev->usec_timeout; k++) {
3405                 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
3406                         break;
3407                 udelay(1);
3408         }
3409 }
3410
3411 static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
3412 {
3413         u32 tmp;
3414
3415         tmp = RREG32(mmRLC_CNTL);
3416         if (tmp != rlc)
3417                 WREG32(mmRLC_CNTL, rlc);
3418 }
3419
3420 static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev)
3421 {
3422         u32 data, orig;
3423
3424         orig = data = RREG32(mmRLC_CNTL);
3425
3426         if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
3427                 u32 i;
3428
3429                 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
3430                 WREG32(mmRLC_CNTL, data);
3431
3432                 for (i = 0; i < adev->usec_timeout; i++) {
3433                         if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0)
3434                                 break;
3435                         udelay(1);
3436                 }
3437
3438                 gfx_v7_0_wait_for_rlc_serdes(adev);
3439         }
3440
3441         return orig;
3442 }
3443
3444 static void gfx_v7_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
3445 {
3446         u32 tmp, i, mask;
3447
3448         tmp = 0x1 | (1 << 1);
3449         WREG32(mmRLC_GPR_REG2, tmp);
3450
3451         mask = RLC_GPM_STAT__GFX_POWER_STATUS_MASK |
3452                 RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK;
3453         for (i = 0; i < adev->usec_timeout; i++) {
3454                 if ((RREG32(mmRLC_GPM_STAT) & mask) == mask)
3455                         break;
3456                 udelay(1);
3457         }
3458
3459         for (i = 0; i < adev->usec_timeout; i++) {
3460                 if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0)
3461                         break;
3462                 udelay(1);
3463         }
3464 }
3465
3466 static void gfx_v7_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
3467 {
3468         u32 tmp;
3469
3470         tmp = 0x1 | (0 << 1);
3471         WREG32(mmRLC_GPR_REG2, tmp);
3472 }
3473
3474 /**
3475  * gfx_v7_0_rlc_stop - stop the RLC ME
3476  *
3477  * @adev: amdgpu_device pointer
3478  *
3479  * Halt the RLC ME (MicroEngine) (CIK).
3480  */
3481 static void gfx_v7_0_rlc_stop(struct amdgpu_device *adev)
3482 {
3483         WREG32(mmRLC_CNTL, 0);
3484
3485         gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3486
3487         gfx_v7_0_wait_for_rlc_serdes(adev);
3488 }
3489
3490 /**
3491  * gfx_v7_0_rlc_start - start the RLC ME
3492  *
3493  * @adev: amdgpu_device pointer
3494  *
3495  * Unhalt the RLC ME (MicroEngine) (CIK).
3496  */
3497 static void gfx_v7_0_rlc_start(struct amdgpu_device *adev)
3498 {
3499         WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
3500
3501         gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3502
3503         udelay(50);
3504 }
3505
3506 static void gfx_v7_0_rlc_reset(struct amdgpu_device *adev)
3507 {
3508         u32 tmp = RREG32(mmGRBM_SOFT_RESET);
3509
3510         tmp |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3511         WREG32(mmGRBM_SOFT_RESET, tmp);
3512         udelay(50);
3513         tmp &= ~GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3514         WREG32(mmGRBM_SOFT_RESET, tmp);
3515         udelay(50);
3516 }
3517
3518 /**
3519  * gfx_v7_0_rlc_resume - setup the RLC hw
3520  *
3521  * @adev: amdgpu_device pointer
3522  *
3523  * Initialize the RLC registers, load the ucode,
3524  * and start the RLC (CIK).
3525  * Returns 0 for success, -EINVAL if the ucode is not available.
3526  */
3527 static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev)
3528 {
3529         const struct rlc_firmware_header_v1_0 *hdr;
3530         const __le32 *fw_data;
3531         unsigned i, fw_size;
3532         u32 tmp;
3533
3534         if (!adev->gfx.rlc_fw)
3535                 return -EINVAL;
3536
3537         hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
3538         amdgpu_ucode_print_rlc_hdr(&hdr->header);
3539         adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version);
3540         adev->gfx.rlc_feature_version = le32_to_cpu(
3541                                         hdr->ucode_feature_version);
3542
3543         gfx_v7_0_rlc_stop(adev);
3544
3545         /* disable CG */
3546         tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc;
3547         WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);
3548
3549         gfx_v7_0_rlc_reset(adev);
3550
3551         gfx_v7_0_init_pg(adev);
3552
3553         WREG32(mmRLC_LB_CNTR_INIT, 0);
3554         WREG32(mmRLC_LB_CNTR_MAX, 0x00008000);
3555
3556         mutex_lock(&adev->grbm_idx_mutex);
3557         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3558         WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
3559         WREG32(mmRLC_LB_PARAMS, 0x00600408);
3560         WREG32(mmRLC_LB_CNTL, 0x80000004);
3561         mutex_unlock(&adev->grbm_idx_mutex);
3562
3563         WREG32(mmRLC_MC_CNTL, 0);
3564         WREG32(mmRLC_UCODE_CNTL, 0);
3565
3566         fw_data = (const __le32 *)
3567                 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3568         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
3569         WREG32(mmRLC_GPM_UCODE_ADDR, 0);
3570         for (i = 0; i < fw_size; i++)
3571                 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
3572         WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
3573
3574         /* XXX - find out what chips support lbpw */
3575         gfx_v7_0_enable_lbpw(adev, false);
3576
3577         if (adev->asic_type == CHIP_BONAIRE)
3578                 WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0);
3579
3580         gfx_v7_0_rlc_start(adev);
3581
3582         return 0;
3583 }
3584
3585 static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
3586 {
3587         u32 data, orig, tmp, tmp2;
3588
3589         orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
3590
3591         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
3592                 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3593
3594                 tmp = gfx_v7_0_halt_rlc(adev);
3595
3596                 mutex_lock(&adev->grbm_idx_mutex);
3597                 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3598                 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3599                 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3600                 tmp2 = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3601                         RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK |
3602                         RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK;
3603                 WREG32(mmRLC_SERDES_WR_CTRL, tmp2);
3604                 mutex_unlock(&adev->grbm_idx_mutex);
3605
3606                 gfx_v7_0_update_rlc(adev, tmp);
3607
3608                 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3609         } else {
3610                 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3611
3612                 RREG32(mmCB_CGTT_SCLK_CTRL);
3613                 RREG32(mmCB_CGTT_SCLK_CTRL);
3614                 RREG32(mmCB_CGTT_SCLK_CTRL);
3615                 RREG32(mmCB_CGTT_SCLK_CTRL);
3616
3617                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3618         }
3619
3620         if (orig != data)
3621                 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
3622
3623 }
3624
3625 static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
3626 {
3627         u32 data, orig, tmp = 0;
3628
3629         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3630                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3631                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
3632                                 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
3633                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3634                                 if (orig != data)
3635                                         WREG32(mmCP_MEM_SLP_CNTL, data);
3636                         }
3637                 }
3638
3639                 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3640                 data |= 0x00000001;
3641                 data &= 0xfffffffd;
3642                 if (orig != data)
3643                         WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3644
3645                 tmp = gfx_v7_0_halt_rlc(adev);
3646
3647                 mutex_lock(&adev->grbm_idx_mutex);
3648                 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3649                 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3650                 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3651                 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3652                         RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK;
3653                 WREG32(mmRLC_SERDES_WR_CTRL, data);
3654                 mutex_unlock(&adev->grbm_idx_mutex);
3655
3656                 gfx_v7_0_update_rlc(adev, tmp);
3657
3658                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) {
3659                         orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3660                         data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK;
3661                         data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
3662                         data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
3663                         data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
3664                         if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) &&
3665                             (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS))
3666                                 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3667                         data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK;
3668                         data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
3669                         data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
3670                         if (orig != data)
3671                                 WREG32(mmCGTS_SM_CTRL_REG, data);
3672                 }
3673         } else {
3674                 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3675                 data |= 0x00000003;
3676                 if (orig != data)
3677                         WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3678
3679                 data = RREG32(mmRLC_MEM_SLP_CNTL);
3680                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3681                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3682                         WREG32(mmRLC_MEM_SLP_CNTL, data);
3683                 }
3684
3685                 data = RREG32(mmCP_MEM_SLP_CNTL);
3686                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3687                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3688                         WREG32(mmCP_MEM_SLP_CNTL, data);
3689                 }
3690
3691                 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3692                 data |= CGTS_SM_CTRL_REG__OVERRIDE_MASK | CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3693                 if (orig != data)
3694                         WREG32(mmCGTS_SM_CTRL_REG, data);
3695
3696                 tmp = gfx_v7_0_halt_rlc(adev);
3697
3698                 mutex_lock(&adev->grbm_idx_mutex);
3699                 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3700                 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3701                 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3702                 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK;
3703                 WREG32(mmRLC_SERDES_WR_CTRL, data);
3704                 mutex_unlock(&adev->grbm_idx_mutex);
3705
3706                 gfx_v7_0_update_rlc(adev, tmp);
3707         }
3708 }
3709
3710 static void gfx_v7_0_update_cg(struct amdgpu_device *adev,
3711                                bool enable)
3712 {
3713         gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3714         /* order matters! */
3715         if (enable) {
3716                 gfx_v7_0_enable_mgcg(adev, true);
3717                 gfx_v7_0_enable_cgcg(adev, true);
3718         } else {
3719                 gfx_v7_0_enable_cgcg(adev, false);
3720                 gfx_v7_0_enable_mgcg(adev, false);
3721         }
3722         gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3723 }
3724
3725 static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
3726                                                 bool enable)
3727 {
3728         u32 data, orig;
3729
3730         orig = data = RREG32(mmRLC_PG_CNTL);
3731         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
3732                 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3733         else
3734                 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3735         if (orig != data)
3736                 WREG32(mmRLC_PG_CNTL, data);
3737 }
3738
3739 static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
3740                                                 bool enable)
3741 {
3742         u32 data, orig;
3743
3744         orig = data = RREG32(mmRLC_PG_CNTL);
3745         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
3746                 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3747         else
3748                 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3749         if (orig != data)
3750                 WREG32(mmRLC_PG_CNTL, data);
3751 }
3752
3753 static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
3754 {
3755         u32 data, orig;
3756
3757         orig = data = RREG32(mmRLC_PG_CNTL);
3758         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
3759                 data &= ~0x8000;
3760         else
3761                 data |= 0x8000;
3762         if (orig != data)
3763                 WREG32(mmRLC_PG_CNTL, data);
3764 }
3765
3766 static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
3767 {
3768         u32 data, orig;
3769
3770         orig = data = RREG32(mmRLC_PG_CNTL);
3771         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GDS))
3772                 data &= ~0x2000;
3773         else
3774                 data |= 0x2000;
3775         if (orig != data)
3776                 WREG32(mmRLC_PG_CNTL, data);
3777 }
3778
3779 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev)
3780 {
3781         const __le32 *fw_data;
3782         volatile u32 *dst_ptr;
3783         int me, i, max_me = 4;
3784         u32 bo_offset = 0;
3785         u32 table_offset, table_size;
3786
3787         if (adev->asic_type == CHIP_KAVERI)
3788                 max_me = 5;
3789
3790         if (adev->gfx.rlc.cp_table_ptr == NULL)
3791                 return;
3792
3793         /* write the cp table buffer */
3794         dst_ptr = adev->gfx.rlc.cp_table_ptr;
3795         for (me = 0; me < max_me; me++) {
3796                 if (me == 0) {
3797                         const struct gfx_firmware_header_v1_0 *hdr =
3798                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
3799                         fw_data = (const __le32 *)
3800                                 (adev->gfx.ce_fw->data +
3801                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3802                         table_offset = le32_to_cpu(hdr->jt_offset);
3803                         table_size = le32_to_cpu(hdr->jt_size);
3804                 } else if (me == 1) {
3805                         const struct gfx_firmware_header_v1_0 *hdr =
3806                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
3807                         fw_data = (const __le32 *)
3808                                 (adev->gfx.pfp_fw->data +
3809                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3810                         table_offset = le32_to_cpu(hdr->jt_offset);
3811                         table_size = le32_to_cpu(hdr->jt_size);
3812                 } else if (me == 2) {
3813                         const struct gfx_firmware_header_v1_0 *hdr =
3814                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3815                         fw_data = (const __le32 *)
3816                                 (adev->gfx.me_fw->data +
3817                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3818                         table_offset = le32_to_cpu(hdr->jt_offset);
3819                         table_size = le32_to_cpu(hdr->jt_size);
3820                 } else if (me == 3) {
3821                         const struct gfx_firmware_header_v1_0 *hdr =
3822                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3823                         fw_data = (const __le32 *)
3824                                 (adev->gfx.mec_fw->data +
3825                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3826                         table_offset = le32_to_cpu(hdr->jt_offset);
3827                         table_size = le32_to_cpu(hdr->jt_size);
3828                 } else {
3829                         const struct gfx_firmware_header_v1_0 *hdr =
3830                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
3831                         fw_data = (const __le32 *)
3832                                 (adev->gfx.mec2_fw->data +
3833                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3834                         table_offset = le32_to_cpu(hdr->jt_offset);
3835                         table_size = le32_to_cpu(hdr->jt_size);
3836                 }
3837
3838                 for (i = 0; i < table_size; i ++) {
3839                         dst_ptr[bo_offset + i] =
3840                                 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
3841                 }
3842
3843                 bo_offset += table_size;
3844         }
3845 }
3846
3847 static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev,
3848                                      bool enable)
3849 {
3850         u32 data, orig;
3851
3852         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
3853                 orig = data = RREG32(mmRLC_PG_CNTL);
3854                 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
3855                 if (orig != data)
3856                         WREG32(mmRLC_PG_CNTL, data);
3857
3858                 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
3859                 data |= RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
3860                 if (orig != data)
3861                         WREG32(mmRLC_AUTO_PG_CTRL, data);
3862         } else {
3863                 orig = data = RREG32(mmRLC_PG_CNTL);
3864                 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
3865                 if (orig != data)
3866                         WREG32(mmRLC_PG_CNTL, data);
3867
3868                 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
3869                 data &= ~RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
3870                 if (orig != data)
3871                         WREG32(mmRLC_AUTO_PG_CTRL, data);
3872
3873                 data = RREG32(mmDB_RENDER_CONTROL);
3874         }
3875 }
3876
3877 static void gfx_v7_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
3878                                                  u32 bitmap)
3879 {
3880         u32 data;
3881
3882         if (!bitmap)
3883                 return;
3884
3885         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
3886         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
3887
3888         WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
3889 }
3890
3891 static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev)
3892 {
3893         u32 data, mask;
3894
3895         data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
3896         data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
3897
3898         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
3899         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
3900
3901         mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_cu_per_sh);
3902
3903         return (~data) & mask;
3904 }
3905
3906 static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev)
3907 {
3908         u32 tmp;
3909
3910         WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
3911
3912         tmp = RREG32(mmRLC_MAX_PG_CU);
3913         tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
3914         tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
3915         WREG32(mmRLC_MAX_PG_CU, tmp);
3916 }
3917
3918 static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
3919                                             bool enable)
3920 {
3921         u32 data, orig;
3922
3923         orig = data = RREG32(mmRLC_PG_CNTL);
3924         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
3925                 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
3926         else
3927                 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
3928         if (orig != data)
3929                 WREG32(mmRLC_PG_CNTL, data);
3930 }
3931
3932 static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
3933                                              bool enable)
3934 {
3935         u32 data, orig;
3936
3937         orig = data = RREG32(mmRLC_PG_CNTL);
3938         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
3939                 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
3940         else
3941                 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
3942         if (orig != data)
3943                 WREG32(mmRLC_PG_CNTL, data);
3944 }
3945
3946 #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
3947 #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET    0x3D
3948
3949 static void gfx_v7_0_init_gfx_cgpg(struct amdgpu_device *adev)
3950 {
3951         u32 data, orig;
3952         u32 i;
3953
3954         if (adev->gfx.rlc.cs_data) {
3955                 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
3956                 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
3957                 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
3958                 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size);
3959         } else {
3960                 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
3961                 for (i = 0; i < 3; i++)
3962                         WREG32(mmRLC_GPM_SCRATCH_DATA, 0);
3963         }
3964         if (adev->gfx.rlc.reg_list) {
3965                 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET);
3966                 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
3967                         WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]);
3968         }
3969
3970         orig = data = RREG32(mmRLC_PG_CNTL);
3971         data |= RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK;
3972         if (orig != data)
3973                 WREG32(mmRLC_PG_CNTL, data);
3974
3975         WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
3976         WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
3977
3978         data = RREG32(mmCP_RB_WPTR_POLL_CNTL);
3979         data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
3980         data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3981         WREG32(mmCP_RB_WPTR_POLL_CNTL, data);
3982
3983         data = 0x10101010;
3984         WREG32(mmRLC_PG_DELAY, data);
3985
3986         data = RREG32(mmRLC_PG_DELAY_2);
3987         data &= ~0xff;
3988         data |= 0x3;
3989         WREG32(mmRLC_PG_DELAY_2, data);
3990
3991         data = RREG32(mmRLC_AUTO_PG_CTRL);
3992         data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
3993         data |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
3994         WREG32(mmRLC_AUTO_PG_CTRL, data);
3995
3996 }
3997
3998 static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
3999 {
4000         gfx_v7_0_enable_gfx_cgpg(adev, enable);
4001         gfx_v7_0_enable_gfx_static_mgpg(adev, enable);
4002         gfx_v7_0_enable_gfx_dynamic_mgpg(adev, enable);
4003 }
4004
4005 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev)
4006 {
4007         u32 count = 0;
4008         const struct cs_section_def *sect = NULL;
4009         const struct cs_extent_def *ext = NULL;
4010
4011         if (adev->gfx.rlc.cs_data == NULL)
4012                 return 0;
4013
4014         /* begin clear state */
4015         count += 2;
4016         /* context control state */
4017         count += 3;
4018
4019         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4020                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4021                         if (sect->id == SECT_CONTEXT)
4022                                 count += 2 + ext->reg_count;
4023                         else
4024                                 return 0;
4025                 }
4026         }
4027         /* pa_sc_raster_config/pa_sc_raster_config1 */
4028         count += 4;
4029         /* end clear state */
4030         count += 2;
4031         /* clear state */
4032         count += 2;
4033
4034         return count;
4035 }
4036
4037 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev,
4038                                     volatile u32 *buffer)
4039 {
4040         u32 count = 0, i;
4041         const struct cs_section_def *sect = NULL;
4042         const struct cs_extent_def *ext = NULL;
4043
4044         if (adev->gfx.rlc.cs_data == NULL)
4045                 return;
4046         if (buffer == NULL)
4047                 return;
4048
4049         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4050         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4051
4052         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4053         buffer[count++] = cpu_to_le32(0x80000000);
4054         buffer[count++] = cpu_to_le32(0x80000000);
4055
4056         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4057                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4058                         if (sect->id == SECT_CONTEXT) {
4059                                 buffer[count++] =
4060                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4061                                 buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
4062                                 for (i = 0; i < ext->reg_count; i++)
4063                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
4064                         } else {
4065                                 return;
4066                         }
4067                 }
4068         }
4069
4070         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
4071         buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
4072         switch (adev->asic_type) {
4073         case CHIP_BONAIRE:
4074                 buffer[count++] = cpu_to_le32(0x16000012);
4075                 buffer[count++] = cpu_to_le32(0x00000000);
4076                 break;
4077         case CHIP_KAVERI:
4078                 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4079                 buffer[count++] = cpu_to_le32(0x00000000);
4080                 break;
4081         case CHIP_KABINI:
4082         case CHIP_MULLINS:
4083                 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4084                 buffer[count++] = cpu_to_le32(0x00000000);
4085                 break;
4086         case CHIP_HAWAII:
4087                 buffer[count++] = cpu_to_le32(0x3a00161a);
4088                 buffer[count++] = cpu_to_le32(0x0000002e);
4089                 break;
4090         default:
4091                 buffer[count++] = cpu_to_le32(0x00000000);
4092                 buffer[count++] = cpu_to_le32(0x00000000);
4093                 break;
4094         }
4095
4096         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4097         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4098
4099         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4100         buffer[count++] = cpu_to_le32(0);
4101 }
4102
4103 static void gfx_v7_0_init_pg(struct amdgpu_device *adev)
4104 {
4105         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4106                               AMD_PG_SUPPORT_GFX_SMG |
4107                               AMD_PG_SUPPORT_GFX_DMG |
4108                               AMD_PG_SUPPORT_CP |
4109                               AMD_PG_SUPPORT_GDS |
4110                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
4111                 gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true);
4112                 gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true);
4113                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
4114                         gfx_v7_0_init_gfx_cgpg(adev);
4115                         gfx_v7_0_enable_cp_pg(adev, true);
4116                         gfx_v7_0_enable_gds_pg(adev, true);
4117                 }
4118                 gfx_v7_0_init_ao_cu_mask(adev);
4119                 gfx_v7_0_update_gfx_pg(adev, true);
4120         }
4121 }
4122
4123 static void gfx_v7_0_fini_pg(struct amdgpu_device *adev)
4124 {
4125         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4126                               AMD_PG_SUPPORT_GFX_SMG |
4127                               AMD_PG_SUPPORT_GFX_DMG |
4128                               AMD_PG_SUPPORT_CP |
4129                               AMD_PG_SUPPORT_GDS |
4130                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
4131                 gfx_v7_0_update_gfx_pg(adev, false);
4132                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
4133                         gfx_v7_0_enable_cp_pg(adev, false);
4134                         gfx_v7_0_enable_gds_pg(adev, false);
4135                 }
4136         }
4137 }
4138
4139 /**
4140  * gfx_v7_0_get_gpu_clock_counter - return GPU clock counter snapshot
4141  *
4142  * @adev: amdgpu_device pointer
4143  *
4144  * Fetches a GPU clock counter snapshot (SI).
4145  * Returns the 64 bit clock counter snapshot.
4146  */
4147 static uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev)
4148 {
4149         uint64_t clock;
4150
4151         mutex_lock(&adev->gfx.gpu_clock_mutex);
4152         WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4153         clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
4154                 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4155         mutex_unlock(&adev->gfx.gpu_clock_mutex);
4156         return clock;
4157 }
4158
4159 static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4160                                           uint32_t vmid,
4161                                           uint32_t gds_base, uint32_t gds_size,
4162                                           uint32_t gws_base, uint32_t gws_size,
4163                                           uint32_t oa_base, uint32_t oa_size)
4164 {
4165         gds_base = gds_base >> AMDGPU_GDS_SHIFT;
4166         gds_size = gds_size >> AMDGPU_GDS_SHIFT;
4167
4168         gws_base = gws_base >> AMDGPU_GWS_SHIFT;
4169         gws_size = gws_size >> AMDGPU_GWS_SHIFT;
4170
4171         oa_base = oa_base >> AMDGPU_OA_SHIFT;
4172         oa_size = oa_size >> AMDGPU_OA_SHIFT;
4173
4174         /* GDS Base */
4175         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4176         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4177                                 WRITE_DATA_DST_SEL(0)));
4178         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
4179         amdgpu_ring_write(ring, 0);
4180         amdgpu_ring_write(ring, gds_base);
4181
4182         /* GDS Size */
4183         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4184         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4185                                 WRITE_DATA_DST_SEL(0)));
4186         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
4187         amdgpu_ring_write(ring, 0);
4188         amdgpu_ring_write(ring, gds_size);
4189
4190         /* GWS */
4191         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4192         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4193                                 WRITE_DATA_DST_SEL(0)));
4194         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
4195         amdgpu_ring_write(ring, 0);
4196         amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
4197
4198         /* OA */
4199         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4200         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4201                                 WRITE_DATA_DST_SEL(0)));
4202         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
4203         amdgpu_ring_write(ring, 0);
4204         amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
4205 }
4206
4207 static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = {
4208         .get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter,
4209         .select_se_sh = &gfx_v7_0_select_se_sh,
4210 };
4211
4212 static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = {
4213         .enter_safe_mode = gfx_v7_0_enter_rlc_safe_mode,
4214         .exit_safe_mode = gfx_v7_0_exit_rlc_safe_mode
4215 };
4216
4217 static int gfx_v7_0_early_init(void *handle)
4218 {
4219         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4220
4221         adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS;
4222         adev->gfx.num_compute_rings = GFX7_NUM_COMPUTE_RINGS;
4223         adev->gfx.funcs = &gfx_v7_0_gfx_funcs;
4224         adev->gfx.rlc.funcs = &gfx_v7_0_rlc_funcs;
4225         gfx_v7_0_set_ring_funcs(adev);
4226         gfx_v7_0_set_irq_funcs(adev);
4227         gfx_v7_0_set_gds_init(adev);
4228
4229         return 0;
4230 }
4231
4232 static int gfx_v7_0_late_init(void *handle)
4233 {
4234         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4235         int r;
4236
4237         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4238         if (r)
4239                 return r;
4240
4241         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4242         if (r)
4243                 return r;
4244
4245         return 0;
4246 }
4247
4248 static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev)
4249 {
4250         u32 gb_addr_config;
4251         u32 mc_shared_chmap, mc_arb_ramcfg;
4252         u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
4253         u32 tmp;
4254
4255         switch (adev->asic_type) {
4256         case CHIP_BONAIRE:
4257                 adev->gfx.config.max_shader_engines = 2;
4258                 adev->gfx.config.max_tile_pipes = 4;
4259                 adev->gfx.config.max_cu_per_sh = 7;
4260                 adev->gfx.config.max_sh_per_se = 1;
4261                 adev->gfx.config.max_backends_per_se = 2;
4262                 adev->gfx.config.max_texture_channel_caches = 4;
4263                 adev->gfx.config.max_gprs = 256;
4264                 adev->gfx.config.max_gs_threads = 32;
4265                 adev->gfx.config.max_hw_contexts = 8;
4266
4267                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4268                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4269                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4270                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4271                 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4272                 break;
4273         case CHIP_HAWAII:
4274                 adev->gfx.config.max_shader_engines = 4;
4275                 adev->gfx.config.max_tile_pipes = 16;
4276                 adev->gfx.config.max_cu_per_sh = 11;
4277                 adev->gfx.config.max_sh_per_se = 1;
4278                 adev->gfx.config.max_backends_per_se = 4;
4279                 adev->gfx.config.max_texture_channel_caches = 16;
4280                 adev->gfx.config.max_gprs = 256;
4281                 adev->gfx.config.max_gs_threads = 32;
4282                 adev->gfx.config.max_hw_contexts = 8;
4283
4284                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4285                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4286                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4287                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4288                 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN;
4289                 break;
4290         case CHIP_KAVERI:
4291                 adev->gfx.config.max_shader_engines = 1;
4292                 adev->gfx.config.max_tile_pipes = 4;
4293                 if ((adev->pdev->device == 0x1304) ||
4294                     (adev->pdev->device == 0x1305) ||
4295                     (adev->pdev->device == 0x130C) ||
4296                     (adev->pdev->device == 0x130F) ||
4297                     (adev->pdev->device == 0x1310) ||
4298                     (adev->pdev->device == 0x1311) ||
4299                     (adev->pdev->device == 0x131C)) {
4300                         adev->gfx.config.max_cu_per_sh = 8;
4301                         adev->gfx.config.max_backends_per_se = 2;
4302                 } else if ((adev->pdev->device == 0x1309) ||
4303                            (adev->pdev->device == 0x130A) ||
4304                            (adev->pdev->device == 0x130D) ||
4305                            (adev->pdev->device == 0x1313) ||
4306                            (adev->pdev->device == 0x131D)) {
4307                         adev->gfx.config.max_cu_per_sh = 6;
4308                         adev->gfx.config.max_backends_per_se = 2;
4309                 } else if ((adev->pdev->device == 0x1306) ||
4310                            (adev->pdev->device == 0x1307) ||
4311                            (adev->pdev->device == 0x130B) ||
4312                            (adev->pdev->device == 0x130E) ||
4313                            (adev->pdev->device == 0x1315) ||
4314                            (adev->pdev->device == 0x131B)) {
4315                         adev->gfx.config.max_cu_per_sh = 4;
4316                         adev->gfx.config.max_backends_per_se = 1;
4317                 } else {
4318                         adev->gfx.config.max_cu_per_sh = 3;
4319                         adev->gfx.config.max_backends_per_se = 1;
4320                 }
4321                 adev->gfx.config.max_sh_per_se = 1;
4322                 adev->gfx.config.max_texture_channel_caches = 4;
4323                 adev->gfx.config.max_gprs = 256;
4324                 adev->gfx.config.max_gs_threads = 16;
4325                 adev->gfx.config.max_hw_contexts = 8;
4326
4327                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4328                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4329                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4330                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4331                 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4332                 break;
4333         case CHIP_KABINI:
4334         case CHIP_MULLINS:
4335         default:
4336                 adev->gfx.config.max_shader_engines = 1;
4337                 adev->gfx.config.max_tile_pipes = 2;
4338                 adev->gfx.config.max_cu_per_sh = 2;
4339                 adev->gfx.config.max_sh_per_se = 1;
4340                 adev->gfx.config.max_backends_per_se = 1;
4341                 adev->gfx.config.max_texture_channel_caches = 2;
4342                 adev->gfx.config.max_gprs = 256;
4343                 adev->gfx.config.max_gs_threads = 16;
4344                 adev->gfx.config.max_hw_contexts = 8;
4345
4346                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4347                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4348                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4349                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4350                 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4351                 break;
4352         }
4353
4354         mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
4355         adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
4356         mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
4357
4358         adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
4359         adev->gfx.config.mem_max_burst_length_bytes = 256;
4360         if (adev->flags & AMD_IS_APU) {
4361                 /* Get memory bank mapping mode. */
4362                 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
4363                 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4364                 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4365
4366                 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
4367                 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4368                 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4369
4370                 /* Validate settings in case only one DIMM installed. */
4371                 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
4372                         dimm00_addr_map = 0;
4373                 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
4374                         dimm01_addr_map = 0;
4375                 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
4376                         dimm10_addr_map = 0;
4377                 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
4378                         dimm11_addr_map = 0;
4379
4380                 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
4381                 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
4382                 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
4383                         adev->gfx.config.mem_row_size_in_kb = 2;
4384                 else
4385                         adev->gfx.config.mem_row_size_in_kb = 1;
4386         } else {
4387                 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
4388                 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
4389                 if (adev->gfx.config.mem_row_size_in_kb > 4)
4390                         adev->gfx.config.mem_row_size_in_kb = 4;
4391         }
4392         /* XXX use MC settings? */
4393         adev->gfx.config.shader_engine_tile_size = 32;
4394         adev->gfx.config.num_gpus = 1;
4395         adev->gfx.config.multi_gpu_tile_size = 64;
4396
4397         /* fix up row size */
4398         gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
4399         switch (adev->gfx.config.mem_row_size_in_kb) {
4400         case 1:
4401         default:
4402                 gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4403                 break;
4404         case 2:
4405                 gb_addr_config |= (1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4406                 break;
4407         case 4:
4408                 gb_addr_config |= (2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4409                 break;
4410         }
4411         adev->gfx.config.gb_addr_config = gb_addr_config;
4412 }
4413
4414 static int gfx_v7_0_sw_init(void *handle)
4415 {
4416         struct amdgpu_ring *ring;
4417         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4418         int i, r;
4419
4420         /* EOP Event */
4421         r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
4422         if (r)
4423                 return r;
4424
4425         /* Privileged reg */
4426         r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
4427         if (r)
4428                 return r;
4429
4430         /* Privileged inst */
4431         r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
4432         if (r)
4433                 return r;
4434
4435         gfx_v7_0_scratch_init(adev);
4436
4437         r = gfx_v7_0_init_microcode(adev);
4438         if (r) {
4439                 DRM_ERROR("Failed to load gfx firmware!\n");
4440                 return r;
4441         }
4442
4443         r = gfx_v7_0_rlc_init(adev);
4444         if (r) {
4445                 DRM_ERROR("Failed to init rlc BOs!\n");
4446                 return r;
4447         }
4448
4449         /* allocate mec buffers */
4450         r = gfx_v7_0_mec_init(adev);
4451         if (r) {
4452                 DRM_ERROR("Failed to init MEC BOs!\n");
4453                 return r;
4454         }
4455
4456         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4457                 ring = &adev->gfx.gfx_ring[i];
4458                 ring->ring_obj = NULL;
4459                 sprintf(ring->name, "gfx");
4460                 r = amdgpu_ring_init(adev, ring, 1024,
4461                                      PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
4462                                      &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
4463                                      AMDGPU_RING_TYPE_GFX);
4464                 if (r)
4465                         return r;
4466         }
4467
4468         /* set up the compute queues */
4469         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4470                 unsigned irq_type;
4471
4472                 /* max 32 queues per MEC */
4473                 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
4474                         DRM_ERROR("Too many (%d) compute rings!\n", i);
4475                         break;
4476                 }
4477                 ring = &adev->gfx.compute_ring[i];
4478                 ring->ring_obj = NULL;
4479                 ring->use_doorbell = true;
4480                 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i;
4481                 ring->me = 1; /* first MEC */
4482                 ring->pipe = i / 8;
4483                 ring->queue = i % 8;
4484                 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4485                 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
4486                 /* type-2 packets are deprecated on MEC, use type-3 instead */
4487                 r = amdgpu_ring_init(adev, ring, 1024,
4488                                      PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
4489                                      &adev->gfx.eop_irq, irq_type,
4490                                      AMDGPU_RING_TYPE_COMPUTE);
4491                 if (r)
4492                         return r;
4493         }
4494
4495         /* reserve GDS, GWS and OA resource for gfx */
4496         r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size,
4497                         PAGE_SIZE, true,
4498                         AMDGPU_GEM_DOMAIN_GDS, 0,
4499                         NULL, NULL, &adev->gds.gds_gfx_bo);
4500         if (r)
4501                 return r;
4502
4503         r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size,
4504                 PAGE_SIZE, true,
4505                 AMDGPU_GEM_DOMAIN_GWS, 0,
4506                 NULL, NULL, &adev->gds.gws_gfx_bo);
4507         if (r)
4508                 return r;
4509
4510         r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size,
4511                         PAGE_SIZE, true,
4512                         AMDGPU_GEM_DOMAIN_OA, 0,
4513                         NULL, NULL, &adev->gds.oa_gfx_bo);
4514         if (r)
4515                 return r;
4516
4517         adev->gfx.ce_ram_size = 0x8000;
4518
4519         gfx_v7_0_gpu_early_init(adev);
4520
4521         return r;
4522 }
4523
4524 static int gfx_v7_0_sw_fini(void *handle)
4525 {
4526         int i;
4527         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4528
4529         amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
4530         amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
4531         amdgpu_bo_unref(&adev->gds.gds_gfx_bo);
4532
4533         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4534                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4535         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4536                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4537
4538         gfx_v7_0_cp_compute_fini(adev);
4539         gfx_v7_0_rlc_fini(adev);
4540         gfx_v7_0_mec_fini(adev);
4541         gfx_v7_0_free_microcode(adev);
4542
4543         return 0;
4544 }
4545
4546 static int gfx_v7_0_hw_init(void *handle)
4547 {
4548         int r;
4549         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4550
4551         gfx_v7_0_gpu_init(adev);
4552
4553         /* init rlc */
4554         r = gfx_v7_0_rlc_resume(adev);
4555         if (r)
4556                 return r;
4557
4558         r = gfx_v7_0_cp_resume(adev);
4559         if (r)
4560                 return r;
4561
4562         return r;
4563 }
4564
4565 static int gfx_v7_0_hw_fini(void *handle)
4566 {
4567         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4568
4569         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4570         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
4571         gfx_v7_0_cp_enable(adev, false);
4572         gfx_v7_0_rlc_stop(adev);
4573         gfx_v7_0_fini_pg(adev);
4574
4575         return 0;
4576 }
4577
4578 static int gfx_v7_0_suspend(void *handle)
4579 {
4580         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4581
4582         return gfx_v7_0_hw_fini(adev);
4583 }
4584
4585 static int gfx_v7_0_resume(void *handle)
4586 {
4587         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4588
4589         return gfx_v7_0_hw_init(adev);
4590 }
4591
4592 static bool gfx_v7_0_is_idle(void *handle)
4593 {
4594         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4595
4596         if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
4597                 return false;
4598         else
4599                 return true;
4600 }
4601
4602 static int gfx_v7_0_wait_for_idle(void *handle)
4603 {
4604         unsigned i;
4605         u32 tmp;
4606         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4607
4608         for (i = 0; i < adev->usec_timeout; i++) {
4609                 /* read MC_STATUS */
4610                 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
4611
4612                 if (!tmp)
4613                         return 0;
4614                 udelay(1);
4615         }
4616         return -ETIMEDOUT;
4617 }
4618
4619 static int gfx_v7_0_soft_reset(void *handle)
4620 {
4621         u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
4622         u32 tmp;
4623         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4624
4625         /* GRBM_STATUS */
4626         tmp = RREG32(mmGRBM_STATUS);
4627         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
4628                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
4629                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
4630                    GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
4631                    GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
4632                    GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK))
4633                 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK |
4634                         GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK;
4635
4636         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
4637                 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK;
4638                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4639         }
4640
4641         /* GRBM_STATUS2 */
4642         tmp = RREG32(mmGRBM_STATUS2);
4643         if (tmp & GRBM_STATUS2__RLC_BUSY_MASK)
4644                 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
4645
4646         /* SRBM_STATUS */
4647         tmp = RREG32(mmSRBM_STATUS);
4648         if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK)
4649                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4650
4651         if (grbm_soft_reset || srbm_soft_reset) {
4652                 /* disable CG/PG */
4653                 gfx_v7_0_fini_pg(adev);
4654                 gfx_v7_0_update_cg(adev, false);
4655
4656                 /* stop the rlc */
4657                 gfx_v7_0_rlc_stop(adev);
4658
4659                 /* Disable GFX parsing/prefetching */
4660                 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);
4661
4662                 /* Disable MEC parsing/prefetching */
4663                 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);
4664
4665                 if (grbm_soft_reset) {
4666                         tmp = RREG32(mmGRBM_SOFT_RESET);
4667                         tmp |= grbm_soft_reset;
4668                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
4669                         WREG32(mmGRBM_SOFT_RESET, tmp);
4670                         tmp = RREG32(mmGRBM_SOFT_RESET);
4671
4672                         udelay(50);
4673
4674                         tmp &= ~grbm_soft_reset;
4675                         WREG32(mmGRBM_SOFT_RESET, tmp);
4676                         tmp = RREG32(mmGRBM_SOFT_RESET);
4677                 }
4678
4679                 if (srbm_soft_reset) {
4680                         tmp = RREG32(mmSRBM_SOFT_RESET);
4681                         tmp |= srbm_soft_reset;
4682                         dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
4683                         WREG32(mmSRBM_SOFT_RESET, tmp);
4684                         tmp = RREG32(mmSRBM_SOFT_RESET);
4685
4686                         udelay(50);
4687
4688                         tmp &= ~srbm_soft_reset;
4689                         WREG32(mmSRBM_SOFT_RESET, tmp);
4690                         tmp = RREG32(mmSRBM_SOFT_RESET);
4691                 }
4692                 /* Wait a little for things to settle down */
4693                 udelay(50);
4694         }
4695         return 0;
4696 }
4697
4698 static void gfx_v7_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4699                                                  enum amdgpu_interrupt_state state)
4700 {
4701         u32 cp_int_cntl;
4702
4703         switch (state) {
4704         case AMDGPU_IRQ_STATE_DISABLE:
4705                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4706                 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4707                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4708                 break;
4709         case AMDGPU_IRQ_STATE_ENABLE:
4710                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4711                 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4712                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4713                 break;
4714         default:
4715                 break;
4716         }
4717 }
4718
4719 static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4720                                                      int me, int pipe,
4721                                                      enum amdgpu_interrupt_state state)
4722 {
4723         u32 mec_int_cntl, mec_int_cntl_reg;
4724
4725         /*
4726          * amdgpu controls only pipe 0 of MEC1. That's why this function only
4727          * handles the setting of interrupts for this specific pipe. All other
4728          * pipes' interrupts are set by amdkfd.
4729          */
4730
4731         if (me == 1) {
4732                 switch (pipe) {
4733                 case 0:
4734                         mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
4735                         break;
4736                 default:
4737                         DRM_DEBUG("invalid pipe %d\n", pipe);
4738                         return;
4739                 }
4740         } else {
4741                 DRM_DEBUG("invalid me %d\n", me);
4742                 return;
4743         }
4744
4745         switch (state) {
4746         case AMDGPU_IRQ_STATE_DISABLE:
4747                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4748                 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4749                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4750                 break;
4751         case AMDGPU_IRQ_STATE_ENABLE:
4752                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4753                 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4754                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4755                 break;
4756         default:
4757                 break;
4758         }
4759 }
4760
4761 static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4762                                              struct amdgpu_irq_src *src,
4763                                              unsigned type,
4764                                              enum amdgpu_interrupt_state state)
4765 {
4766         u32 cp_int_cntl;
4767
4768         switch (state) {
4769         case AMDGPU_IRQ_STATE_DISABLE:
4770                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4771                 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
4772                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4773                 break;
4774         case AMDGPU_IRQ_STATE_ENABLE:
4775                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4776                 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
4777                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4778                 break;
4779         default:
4780                 break;
4781         }
4782
4783         return 0;
4784 }
4785
4786 static int gfx_v7_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4787                                               struct amdgpu_irq_src *src,
4788                                               unsigned type,
4789                                               enum amdgpu_interrupt_state state)
4790 {
4791         u32 cp_int_cntl;
4792
4793         switch (state) {
4794         case AMDGPU_IRQ_STATE_DISABLE:
4795                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4796                 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
4797                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4798                 break;
4799         case AMDGPU_IRQ_STATE_ENABLE:
4800                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4801                 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
4802                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4803                 break;
4804         default:
4805                 break;
4806         }
4807
4808         return 0;
4809 }
4810
4811 static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4812                                             struct amdgpu_irq_src *src,
4813                                             unsigned type,
4814                                             enum amdgpu_interrupt_state state)
4815 {
4816         switch (type) {
4817         case AMDGPU_CP_IRQ_GFX_EOP:
4818                 gfx_v7_0_set_gfx_eop_interrupt_state(adev, state);
4819                 break;
4820         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4821                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4822                 break;
4823         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4824                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4825                 break;
4826         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4827                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4828                 break;
4829         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4830                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4831                 break;
4832         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4833                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4834                 break;
4835         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4836                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4837                 break;
4838         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4839                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4840                 break;
4841         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4842                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4843                 break;
4844         default:
4845                 break;
4846         }
4847         return 0;
4848 }
4849
4850 static int gfx_v7_0_eop_irq(struct amdgpu_device *adev,
4851                             struct amdgpu_irq_src *source,
4852                             struct amdgpu_iv_entry *entry)
4853 {
4854         u8 me_id, pipe_id;
4855         struct amdgpu_ring *ring;
4856         int i;
4857
4858         DRM_DEBUG("IH: CP EOP\n");
4859         me_id = (entry->ring_id & 0x0c) >> 2;
4860         pipe_id = (entry->ring_id & 0x03) >> 0;
4861         switch (me_id) {
4862         case 0:
4863                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4864                 break;
4865         case 1:
4866         case 2:
4867                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4868                         ring = &adev->gfx.compute_ring[i];
4869                         if ((ring->me == me_id) && (ring->pipe == pipe_id))
4870                                 amdgpu_fence_process(ring);
4871                 }
4872                 break;
4873         }
4874         return 0;
4875 }
4876
4877 static int gfx_v7_0_priv_reg_irq(struct amdgpu_device *adev,
4878                                  struct amdgpu_irq_src *source,
4879                                  struct amdgpu_iv_entry *entry)
4880 {
4881         DRM_ERROR("Illegal register access in command stream\n");
4882         schedule_work(&adev->reset_work);
4883         return 0;
4884 }
4885
4886 static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev,
4887                                   struct amdgpu_irq_src *source,
4888                                   struct amdgpu_iv_entry *entry)
4889 {
4890         DRM_ERROR("Illegal instruction in command stream\n");
4891         // XXX soft reset the gfx block only
4892         schedule_work(&adev->reset_work);
4893         return 0;
4894 }
4895
4896 static int gfx_v7_0_set_clockgating_state(void *handle,
4897                                           enum amd_clockgating_state state)
4898 {
4899         bool gate = false;
4900         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4901
4902         if (state == AMD_CG_STATE_GATE)
4903                 gate = true;
4904
4905         gfx_v7_0_enable_gui_idle_interrupt(adev, false);
4906         /* order matters! */
4907         if (gate) {
4908                 gfx_v7_0_enable_mgcg(adev, true);
4909                 gfx_v7_0_enable_cgcg(adev, true);
4910         } else {
4911                 gfx_v7_0_enable_cgcg(adev, false);
4912                 gfx_v7_0_enable_mgcg(adev, false);
4913         }
4914         gfx_v7_0_enable_gui_idle_interrupt(adev, true);
4915
4916         return 0;
4917 }
4918
4919 static int gfx_v7_0_set_powergating_state(void *handle,
4920                                           enum amd_powergating_state state)
4921 {
4922         bool gate = false;
4923         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4924
4925         if (state == AMD_PG_STATE_GATE)
4926                 gate = true;
4927
4928         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4929                               AMD_PG_SUPPORT_GFX_SMG |
4930                               AMD_PG_SUPPORT_GFX_DMG |
4931                               AMD_PG_SUPPORT_CP |
4932                               AMD_PG_SUPPORT_GDS |
4933                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
4934                 gfx_v7_0_update_gfx_pg(adev, gate);
4935                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
4936                         gfx_v7_0_enable_cp_pg(adev, gate);
4937                         gfx_v7_0_enable_gds_pg(adev, gate);
4938                 }
4939         }
4940
4941         return 0;
4942 }
4943
4944 const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
4945         .name = "gfx_v7_0",
4946         .early_init = gfx_v7_0_early_init,
4947         .late_init = gfx_v7_0_late_init,
4948         .sw_init = gfx_v7_0_sw_init,
4949         .sw_fini = gfx_v7_0_sw_fini,
4950         .hw_init = gfx_v7_0_hw_init,
4951         .hw_fini = gfx_v7_0_hw_fini,
4952         .suspend = gfx_v7_0_suspend,
4953         .resume = gfx_v7_0_resume,
4954         .is_idle = gfx_v7_0_is_idle,
4955         .wait_for_idle = gfx_v7_0_wait_for_idle,
4956         .soft_reset = gfx_v7_0_soft_reset,
4957         .set_clockgating_state = gfx_v7_0_set_clockgating_state,
4958         .set_powergating_state = gfx_v7_0_set_powergating_state,
4959 };
4960
4961 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
4962         .get_rptr = gfx_v7_0_ring_get_rptr_gfx,
4963         .get_wptr = gfx_v7_0_ring_get_wptr_gfx,
4964         .set_wptr = gfx_v7_0_ring_set_wptr_gfx,
4965         .parse_cs = NULL,
4966         .emit_ib = gfx_v7_0_ring_emit_ib_gfx,
4967         .emit_fence = gfx_v7_0_ring_emit_fence_gfx,
4968         .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
4969         .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
4970         .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
4971         .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
4972         .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate,
4973         .test_ring = gfx_v7_0_ring_test_ring,
4974         .test_ib = gfx_v7_0_ring_test_ib,
4975         .insert_nop = amdgpu_ring_insert_nop,
4976         .pad_ib = amdgpu_ring_generic_pad_ib,
4977 };
4978
4979 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
4980         .get_rptr = gfx_v7_0_ring_get_rptr_compute,
4981         .get_wptr = gfx_v7_0_ring_get_wptr_compute,
4982         .set_wptr = gfx_v7_0_ring_set_wptr_compute,
4983         .parse_cs = NULL,
4984         .emit_ib = gfx_v7_0_ring_emit_ib_compute,
4985         .emit_fence = gfx_v7_0_ring_emit_fence_compute,
4986         .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
4987         .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
4988         .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
4989         .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
4990         .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate,
4991         .test_ring = gfx_v7_0_ring_test_ring,
4992         .test_ib = gfx_v7_0_ring_test_ib,
4993         .insert_nop = amdgpu_ring_insert_nop,
4994         .pad_ib = amdgpu_ring_generic_pad_ib,
4995 };
4996
4997 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev)
4998 {
4999         int i;
5000
5001         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5002                 adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx;
5003         for (i = 0; i < adev->gfx.num_compute_rings; i++)
5004                 adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute;
5005 }
5006
5007 static const struct amdgpu_irq_src_funcs gfx_v7_0_eop_irq_funcs = {
5008         .set = gfx_v7_0_set_eop_interrupt_state,
5009         .process = gfx_v7_0_eop_irq,
5010 };
5011
5012 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_reg_irq_funcs = {
5013         .set = gfx_v7_0_set_priv_reg_fault_state,
5014         .process = gfx_v7_0_priv_reg_irq,
5015 };
5016
5017 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_inst_irq_funcs = {
5018         .set = gfx_v7_0_set_priv_inst_fault_state,
5019         .process = gfx_v7_0_priv_inst_irq,
5020 };
5021
5022 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev)
5023 {
5024         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
5025         adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs;
5026
5027         adev->gfx.priv_reg_irq.num_types = 1;
5028         adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs;
5029
5030         adev->gfx.priv_inst_irq.num_types = 1;
5031         adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs;
5032 }
5033
5034 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev)
5035 {
5036         /* init asci gds info */
5037         adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
5038         adev->gds.gws.total_size = 64;
5039         adev->gds.oa.total_size = 16;
5040
5041         if (adev->gds.mem.total_size == 64 * 1024) {
5042                 adev->gds.mem.gfx_partition_size = 4096;
5043                 adev->gds.mem.cs_partition_size = 4096;
5044
5045                 adev->gds.gws.gfx_partition_size = 4;
5046                 adev->gds.gws.cs_partition_size = 4;
5047
5048                 adev->gds.oa.gfx_partition_size = 4;
5049                 adev->gds.oa.cs_partition_size = 1;
5050         } else {
5051                 adev->gds.mem.gfx_partition_size = 1024;
5052                 adev->gds.mem.cs_partition_size = 1024;
5053
5054                 adev->gds.gws.gfx_partition_size = 16;
5055                 adev->gds.gws.cs_partition_size = 16;
5056
5057                 adev->gds.oa.gfx_partition_size = 4;
5058                 adev->gds.oa.cs_partition_size = 4;
5059         }
5060 }
5061
5062
5063 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev)
5064 {
5065         int i, j, k, counter, active_cu_number = 0;
5066         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
5067         struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
5068         unsigned disable_masks[4 * 2];
5069
5070         memset(cu_info, 0, sizeof(*cu_info));
5071
5072         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
5073
5074         mutex_lock(&adev->grbm_idx_mutex);
5075         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5076                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5077                         mask = 1;
5078                         ao_bitmap = 0;
5079                         counter = 0;
5080                         gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
5081                         if (i < 4 && j < 2)
5082                                 gfx_v7_0_set_user_cu_inactive_bitmap(
5083                                         adev, disable_masks[i * 2 + j]);
5084                         bitmap = gfx_v7_0_get_cu_active_bitmap(adev);
5085                         cu_info->bitmap[i][j] = bitmap;
5086
5087                         for (k = 0; k < 16; k ++) {
5088                                 if (bitmap & mask) {
5089                                         if (counter < 2)
5090                                                 ao_bitmap |= mask;
5091                                         counter ++;
5092                                 }
5093                                 mask <<= 1;
5094                         }
5095                         active_cu_number += counter;
5096                         ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
5097                 }
5098         }
5099         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5100         mutex_unlock(&adev->grbm_idx_mutex);
5101
5102         cu_info->number = active_cu_number;
5103         cu_info->ao_cu_mask = ao_cu_mask;
5104 }