2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
29 #include "amdgpu_ucode.h"
31 #include "bif/bif_4_1_d.h"
32 #include "bif/bif_4_1_sh_mask.h"
34 #include "gmc/gmc_7_1_d.h"
35 #include "gmc/gmc_7_1_sh_mask.h"
37 #include "oss/oss_2_0_d.h"
38 #include "oss/oss_2_0_sh_mask.h"
40 static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev);
41 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev);
42 static int gmc_v7_0_wait_for_idle(void *handle);
44 MODULE_FIRMWARE("radeon/bonaire_mc.bin");
45 MODULE_FIRMWARE("radeon/hawaii_mc.bin");
46 MODULE_FIRMWARE("amdgpu/topaz_mc.bin");
48 static const u32 golden_settings_iceland_a11[] =
50 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
51 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
52 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
53 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
56 static const u32 iceland_mgcg_cgcg_init[] =
58 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
61 static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev)
63 switch (adev->asic_type) {
65 amdgpu_program_register_sequence(adev,
66 iceland_mgcg_cgcg_init,
67 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
68 amdgpu_program_register_sequence(adev,
69 golden_settings_iceland_a11,
70 (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
77 static void gmc_v7_0_mc_stop(struct amdgpu_device *adev,
78 struct amdgpu_mode_mc_save *save)
82 if (adev->mode_info.num_crtc)
83 amdgpu_display_stop_mc_access(adev, save);
85 gmc_v7_0_wait_for_idle((void *)adev);
87 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
88 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
89 /* Block CPU access */
90 WREG32(mmBIF_FB_EN, 0);
92 blackout = REG_SET_FIELD(blackout,
93 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
94 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
96 /* wait for the MC to settle */
100 static void gmc_v7_0_mc_resume(struct amdgpu_device *adev,
101 struct amdgpu_mode_mc_save *save)
105 /* unblackout the MC */
106 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
107 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
108 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
109 /* allow CPU access */
110 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
111 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
112 WREG32(mmBIF_FB_EN, tmp);
114 if (adev->mode_info.num_crtc)
115 amdgpu_display_resume_mc_access(adev, save);
119 * gmc_v7_0_init_microcode - load ucode images from disk
121 * @adev: amdgpu_device pointer
123 * Use the firmware interface to load the ucode images into
124 * the driver (not loaded into hw).
125 * Returns 0 on success, error on failure.
127 static int gmc_v7_0_init_microcode(struct amdgpu_device *adev)
129 const char *chip_name;
135 switch (adev->asic_type) {
137 chip_name = "bonaire";
140 chip_name = "hawaii";
152 if (adev->asic_type == CHIP_TOPAZ)
153 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
155 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
157 err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
160 err = amdgpu_ucode_validate(adev->mc.fw);
165 "cik_mc: Failed to load firmware \"%s\"\n",
167 release_firmware(adev->mc.fw);
174 * gmc_v7_0_mc_load_microcode - load MC ucode into the hw
176 * @adev: amdgpu_device pointer
178 * Load the GDDR MC ucode into the hw (CIK).
179 * Returns 0 on success, error on failure.
181 static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev)
183 const struct mc_firmware_header_v1_0 *hdr;
184 const __le32 *fw_data = NULL;
185 const __le32 *io_mc_regs = NULL;
186 u32 running, blackout = 0;
187 int i, ucode_size, regs_size;
192 hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
193 amdgpu_ucode_print_mc_hdr(&hdr->header);
195 adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
196 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
197 io_mc_regs = (const __le32 *)
198 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
199 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
200 fw_data = (const __le32 *)
201 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
203 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
207 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
208 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
211 /* reset the engine and set to writable */
212 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
213 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
215 /* load mc io regs */
216 for (i = 0; i < regs_size; i++) {
217 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
218 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
220 /* load the MC ucode */
221 for (i = 0; i < ucode_size; i++)
222 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
224 /* put the engine back into the active state */
225 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
226 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
227 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
229 /* wait for training to complete */
230 for (i = 0; i < adev->usec_timeout; i++) {
231 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
232 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
236 for (i = 0; i < adev->usec_timeout; i++) {
237 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
238 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
244 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
250 static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev,
251 struct amdgpu_mc *mc)
253 if (mc->mc_vram_size > 0xFFC0000000ULL) {
254 /* leave room for at least 1024M GTT */
255 dev_warn(adev->dev, "limiting VRAM\n");
256 mc->real_vram_size = 0xFFC0000000ULL;
257 mc->mc_vram_size = 0xFFC0000000ULL;
259 amdgpu_vram_location(adev, &adev->mc, 0);
260 adev->mc.gtt_base_align = 0;
261 amdgpu_gtt_location(adev, mc);
265 * gmc_v7_0_mc_program - program the GPU memory controller
267 * @adev: amdgpu_device pointer
269 * Set the location of vram, gart, and AGP in the GPU's
270 * physical address space (CIK).
272 static void gmc_v7_0_mc_program(struct amdgpu_device *adev)
274 struct amdgpu_mode_mc_save save;
279 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
280 WREG32((0xb05 + j), 0x00000000);
281 WREG32((0xb06 + j), 0x00000000);
282 WREG32((0xb07 + j), 0x00000000);
283 WREG32((0xb08 + j), 0x00000000);
284 WREG32((0xb09 + j), 0x00000000);
286 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
288 if (adev->mode_info.num_crtc)
289 amdgpu_display_set_vga_render_state(adev, false);
291 gmc_v7_0_mc_stop(adev, &save);
292 if (gmc_v7_0_wait_for_idle((void *)adev)) {
293 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
295 /* Update configuration */
296 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
297 adev->mc.vram_start >> 12);
298 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
299 adev->mc.vram_end >> 12);
300 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
301 adev->vram_scratch.gpu_addr >> 12);
302 tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
303 tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
304 WREG32(mmMC_VM_FB_LOCATION, tmp);
305 /* XXX double check these! */
306 WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
307 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
308 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
309 WREG32(mmMC_VM_AGP_BASE, 0);
310 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
311 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
312 if (gmc_v7_0_wait_for_idle((void *)adev)) {
313 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
315 gmc_v7_0_mc_resume(adev, &save);
317 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
319 tmp = RREG32(mmHDP_MISC_CNTL);
320 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
321 WREG32(mmHDP_MISC_CNTL, tmp);
323 tmp = RREG32(mmHDP_HOST_PATH_CNTL);
324 WREG32(mmHDP_HOST_PATH_CNTL, tmp);
328 * gmc_v7_0_mc_init - initialize the memory controller driver params
330 * @adev: amdgpu_device pointer
332 * Look up the amount of vram, vram width, and decide how to place
333 * vram and gart within the GPU's physical address space (CIK).
334 * Returns 0 for success.
336 static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
339 int chansize, numchan;
341 /* Get VRAM informations */
342 tmp = RREG32(mmMC_ARB_RAMCFG);
343 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
348 tmp = RREG32(mmMC_SHARED_CHMAP);
349 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
379 adev->mc.vram_width = numchan * chansize;
380 /* Could aper size report 0 ? */
381 adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
382 adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
383 /* size in MB on si */
384 adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
385 adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
386 adev->mc.visible_vram_size = adev->mc.aper_size;
388 /* In case the PCI BAR is larger than the actual amount of vram */
389 if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
390 adev->mc.visible_vram_size = adev->mc.real_vram_size;
392 /* unless the user had overridden it, set the gart
393 * size equal to the 1024 or vram, whichever is larger.
395 if (amdgpu_gart_size == -1)
396 adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size);
398 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
400 gmc_v7_0_vram_gtt_location(adev, &adev->mc);
407 * VMID 0 is the physical GPU addresses as used by the kernel.
408 * VMIDs 1-15 are used for userspace clients and are handled
409 * by the amdgpu vm/hsa code.
413 * gmc_v7_0_gart_flush_gpu_tlb - gart tlb flush callback
415 * @adev: amdgpu_device pointer
416 * @vmid: vm instance to flush
418 * Flush the TLB for the requested page table (CIK).
420 static void gmc_v7_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
423 /* flush hdp cache */
424 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
426 /* bits 0-15 are the VM contexts0-15 */
427 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
431 * gmc_v7_0_gart_set_pte_pde - update the page tables using MMIO
433 * @adev: amdgpu_device pointer
434 * @cpu_pt_addr: cpu address of the page table
435 * @gpu_page_idx: entry in the page table to update
436 * @addr: dst addr to write into pte/pde
437 * @flags: access flags
439 * Update the page tables using the CPU.
441 static int gmc_v7_0_gart_set_pte_pde(struct amdgpu_device *adev,
443 uint32_t gpu_page_idx,
447 void __iomem *ptr = (void *)cpu_pt_addr;
450 value = addr & 0xFFFFFFFFFFFFF000ULL;
452 writeq(value, ptr + (gpu_page_idx * 8));
458 * gmc_v8_0_set_fault_enable_default - update VM fault handling
460 * @adev: amdgpu_device pointer
461 * @value: true redirects VM faults to the default page
463 static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev,
468 tmp = RREG32(mmVM_CONTEXT1_CNTL);
469 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
470 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
471 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
472 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
473 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
474 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
475 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
476 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
477 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
478 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
479 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
480 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
481 WREG32(mmVM_CONTEXT1_CNTL, tmp);
485 * gmc_v7_0_gart_enable - gart enable
487 * @adev: amdgpu_device pointer
489 * This sets up the TLBs, programs the page tables for VMID0,
490 * sets up the hw for VMIDs 1-15 which are allocated on
491 * demand, and sets up the global locations for the LDS, GDS,
492 * and GPUVM for FSA64 clients (CIK).
493 * Returns 0 for success, errors for failure.
495 static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
500 if (adev->gart.robj == NULL) {
501 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
504 r = amdgpu_gart_table_vram_pin(adev);
507 /* Setup TLB control */
508 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
509 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
510 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
511 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
512 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
513 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
514 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
516 tmp = RREG32(mmVM_L2_CNTL);
517 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
518 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
519 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
520 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
521 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
522 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
523 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
524 WREG32(mmVM_L2_CNTL, tmp);
525 tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
526 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
527 WREG32(mmVM_L2_CNTL2, tmp);
528 tmp = RREG32(mmVM_L2_CNTL3);
529 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
530 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4);
531 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4);
532 WREG32(mmVM_L2_CNTL3, tmp);
534 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);
535 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12);
536 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
537 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
538 (u32)(adev->dummy_page.addr >> 12));
539 WREG32(mmVM_CONTEXT0_CNTL2, 0);
540 tmp = RREG32(mmVM_CONTEXT0_CNTL);
541 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
542 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
543 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
544 WREG32(mmVM_CONTEXT0_CNTL, tmp);
550 /* empty context1-15 */
551 /* FIXME start with 4G, once using 2 level pt switch to full
554 /* set vm size, must be a multiple of 4 */
555 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
556 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
557 for (i = 1; i < 16; i++) {
559 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
560 adev->gart.table_addr >> 12);
562 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
563 adev->gart.table_addr >> 12);
566 /* enable context1-15 */
567 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
568 (u32)(adev->dummy_page.addr >> 12));
569 WREG32(mmVM_CONTEXT1_CNTL2, 4);
570 tmp = RREG32(mmVM_CONTEXT1_CNTL);
571 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
572 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
573 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
574 amdgpu_vm_block_size - 9);
575 WREG32(mmVM_CONTEXT1_CNTL, tmp);
576 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
577 gmc_v7_0_set_fault_enable_default(adev, false);
579 gmc_v7_0_set_fault_enable_default(adev, true);
581 if (adev->asic_type == CHIP_KAVERI) {
582 tmp = RREG32(mmCHUB_CONTROL);
584 WREG32(mmCHUB_CONTROL, tmp);
587 gmc_v7_0_gart_flush_gpu_tlb(adev, 0);
588 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
589 (unsigned)(adev->mc.gtt_size >> 20),
590 (unsigned long long)adev->gart.table_addr);
591 adev->gart.ready = true;
595 static int gmc_v7_0_gart_init(struct amdgpu_device *adev)
599 if (adev->gart.robj) {
600 WARN(1, "R600 PCIE GART already initialized\n");
603 /* Initialize common gart structure */
604 r = amdgpu_gart_init(adev);
607 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
608 return amdgpu_gart_table_vram_alloc(adev);
612 * gmc_v7_0_gart_disable - gart disable
614 * @adev: amdgpu_device pointer
616 * This disables all VM page table (CIK).
618 static void gmc_v7_0_gart_disable(struct amdgpu_device *adev)
622 /* Disable all tables */
623 WREG32(mmVM_CONTEXT0_CNTL, 0);
624 WREG32(mmVM_CONTEXT1_CNTL, 0);
625 /* Setup TLB control */
626 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
627 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
628 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
629 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
630 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
632 tmp = RREG32(mmVM_L2_CNTL);
633 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
634 WREG32(mmVM_L2_CNTL, tmp);
635 WREG32(mmVM_L2_CNTL2, 0);
636 amdgpu_gart_table_vram_unpin(adev);
640 * gmc_v7_0_gart_fini - vm fini callback
642 * @adev: amdgpu_device pointer
644 * Tears down the driver GART/VM setup (CIK).
646 static void gmc_v7_0_gart_fini(struct amdgpu_device *adev)
648 amdgpu_gart_table_vram_free(adev);
649 amdgpu_gart_fini(adev);
654 * VMID 0 is the physical GPU addresses as used by the kernel.
655 * VMIDs 1-15 are used for userspace clients and are handled
656 * by the amdgpu vm/hsa code.
659 * gmc_v7_0_vm_init - cik vm init callback
661 * @adev: amdgpu_device pointer
663 * Inits cik specific vm parameters (number of VMs, base of vram for
665 * Returns 0 for success.
667 static int gmc_v7_0_vm_init(struct amdgpu_device *adev)
671 * VMID 0 is reserved for System
672 * amdgpu graphics/compute will use VMIDs 1-7
673 * amdkfd will use VMIDs 8-15
675 adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
676 amdgpu_vm_manager_init(adev);
678 /* base offset of vram pages */
679 if (adev->flags & AMD_IS_APU) {
680 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
682 adev->vm_manager.vram_base_offset = tmp;
684 adev->vm_manager.vram_base_offset = 0;
690 * gmc_v7_0_vm_fini - cik vm fini callback
692 * @adev: amdgpu_device pointer
694 * Tear down any asic specific VM setup (CIK).
696 static void gmc_v7_0_vm_fini(struct amdgpu_device *adev)
701 * gmc_v7_0_vm_decode_fault - print human readable fault info
703 * @adev: amdgpu_device pointer
704 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
705 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
707 * Print human readable fault information (CIK).
709 static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev,
710 u32 status, u32 addr, u32 mc_client)
713 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
714 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
716 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
717 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
719 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
722 printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
723 protections, vmid, addr,
724 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
726 "write" : "read", block, mc_client, mc_id);
730 static const u32 mc_cg_registers[] = {
731 mmMC_HUB_MISC_HUB_CG,
732 mmMC_HUB_MISC_SIP_CG,
736 mmMC_CITF_MISC_WR_CG,
737 mmMC_CITF_MISC_RD_CG,
738 mmMC_CITF_MISC_VM_CG,
742 static const u32 mc_cg_ls_en[] = {
743 MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
744 MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
745 MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
746 MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
747 ATC_MISC_CG__MEM_LS_ENABLE_MASK,
748 MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
749 MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
750 MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
751 VM_L2_CG__MEM_LS_ENABLE_MASK,
754 static const u32 mc_cg_en[] = {
755 MC_HUB_MISC_HUB_CG__ENABLE_MASK,
756 MC_HUB_MISC_SIP_CG__ENABLE_MASK,
757 MC_HUB_MISC_VM_CG__ENABLE_MASK,
758 MC_XPB_CLK_GAT__ENABLE_MASK,
759 ATC_MISC_CG__ENABLE_MASK,
760 MC_CITF_MISC_WR_CG__ENABLE_MASK,
761 MC_CITF_MISC_RD_CG__ENABLE_MASK,
762 MC_CITF_MISC_VM_CG__ENABLE_MASK,
763 VM_L2_CG__ENABLE_MASK,
766 static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev,
772 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
773 orig = data = RREG32(mc_cg_registers[i]);
774 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
775 data |= mc_cg_ls_en[i];
777 data &= ~mc_cg_ls_en[i];
779 WREG32(mc_cg_registers[i], data);
783 static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev,
789 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
790 orig = data = RREG32(mc_cg_registers[i]);
791 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
794 data &= ~mc_cg_en[i];
796 WREG32(mc_cg_registers[i], data);
800 static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev,
805 orig = data = RREG32_PCIE(ixPCIE_CNTL2);
807 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
808 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
809 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
810 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
811 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
813 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
814 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
815 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
816 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
820 WREG32_PCIE(ixPCIE_CNTL2, data);
823 static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev,
828 orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
830 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
831 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
833 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
836 WREG32(mmHDP_HOST_PATH_CNTL, data);
839 static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev,
844 orig = data = RREG32(mmHDP_MEM_POWER_LS);
846 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
847 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
849 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
852 WREG32(mmHDP_MEM_POWER_LS, data);
855 static int gmc_v7_0_convert_vram_type(int mc_seq_vram_type)
857 switch (mc_seq_vram_type) {
858 case MC_SEQ_MISC0__MT__GDDR1:
859 return AMDGPU_VRAM_TYPE_GDDR1;
860 case MC_SEQ_MISC0__MT__DDR2:
861 return AMDGPU_VRAM_TYPE_DDR2;
862 case MC_SEQ_MISC0__MT__GDDR3:
863 return AMDGPU_VRAM_TYPE_GDDR3;
864 case MC_SEQ_MISC0__MT__GDDR4:
865 return AMDGPU_VRAM_TYPE_GDDR4;
866 case MC_SEQ_MISC0__MT__GDDR5:
867 return AMDGPU_VRAM_TYPE_GDDR5;
868 case MC_SEQ_MISC0__MT__HBM:
869 return AMDGPU_VRAM_TYPE_HBM;
870 case MC_SEQ_MISC0__MT__DDR3:
871 return AMDGPU_VRAM_TYPE_DDR3;
873 return AMDGPU_VRAM_TYPE_UNKNOWN;
877 static int gmc_v7_0_early_init(void *handle)
879 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
881 gmc_v7_0_set_gart_funcs(adev);
882 gmc_v7_0_set_irq_funcs(adev);
887 static int gmc_v7_0_late_init(void *handle)
889 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
891 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
892 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
897 static int gmc_v7_0_sw_init(void *handle)
901 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
903 if (adev->flags & AMD_IS_APU) {
904 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
906 u32 tmp = RREG32(mmMC_SEQ_MISC0);
907 tmp &= MC_SEQ_MISC0__MT__MASK;
908 adev->mc.vram_type = gmc_v7_0_convert_vram_type(tmp);
911 r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
915 r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault);
919 /* Adjust VM size here.
920 * Currently set to 4GB ((1 << 20) 4k pages).
921 * Max GPUVM size for cayman and SI is 40 bits.
923 adev->vm_manager.max_pfn = amdgpu_vm_size << 18;
925 /* Set the internal MC address mask
926 * This is the max address of the GPU's
927 * internal address space.
929 adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
931 /* set DMA mask + need_dma32 flags.
932 * PCIE - can handle 40-bits.
933 * IGP - can handle 40-bits
934 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
936 adev->need_dma32 = false;
937 dma_bits = adev->need_dma32 ? 32 : 40;
938 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
940 adev->need_dma32 = true;
942 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
944 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
946 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
947 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
950 r = gmc_v7_0_init_microcode(adev);
952 DRM_ERROR("Failed to load mc firmware!\n");
956 r = gmc_v7_0_mc_init(adev);
961 r = amdgpu_bo_init(adev);
965 r = gmc_v7_0_gart_init(adev);
969 if (!adev->vm_manager.enabled) {
970 r = gmc_v7_0_vm_init(adev);
972 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
975 adev->vm_manager.enabled = true;
981 static int gmc_v7_0_sw_fini(void *handle)
983 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
985 if (adev->vm_manager.enabled) {
986 amdgpu_vm_manager_fini(adev);
987 gmc_v7_0_vm_fini(adev);
988 adev->vm_manager.enabled = false;
990 gmc_v7_0_gart_fini(adev);
991 amdgpu_gem_force_release(adev);
992 amdgpu_bo_fini(adev);
997 static int gmc_v7_0_hw_init(void *handle)
1000 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1002 gmc_v7_0_init_golden_registers(adev);
1004 gmc_v7_0_mc_program(adev);
1006 if (!(adev->flags & AMD_IS_APU)) {
1007 r = gmc_v7_0_mc_load_microcode(adev);
1009 DRM_ERROR("Failed to load MC firmware!\n");
1014 r = gmc_v7_0_gart_enable(adev);
1021 static int gmc_v7_0_hw_fini(void *handle)
1023 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1025 amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
1026 gmc_v7_0_gart_disable(adev);
1031 static int gmc_v7_0_suspend(void *handle)
1033 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1035 if (adev->vm_manager.enabled) {
1036 gmc_v7_0_vm_fini(adev);
1037 adev->vm_manager.enabled = false;
1039 gmc_v7_0_hw_fini(adev);
1044 static int gmc_v7_0_resume(void *handle)
1047 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1049 r = gmc_v7_0_hw_init(adev);
1053 if (!adev->vm_manager.enabled) {
1054 r = gmc_v7_0_vm_init(adev);
1056 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
1059 adev->vm_manager.enabled = true;
1065 static bool gmc_v7_0_is_idle(void *handle)
1067 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1068 u32 tmp = RREG32(mmSRBM_STATUS);
1070 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1071 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1077 static int gmc_v7_0_wait_for_idle(void *handle)
1081 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1083 for (i = 0; i < adev->usec_timeout; i++) {
1084 /* read MC_STATUS */
1085 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1086 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1087 SRBM_STATUS__MCC_BUSY_MASK |
1088 SRBM_STATUS__MCD_BUSY_MASK |
1089 SRBM_STATUS__VMC_BUSY_MASK);
1098 static int gmc_v7_0_soft_reset(void *handle)
1100 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1101 struct amdgpu_mode_mc_save save;
1102 u32 srbm_soft_reset = 0;
1103 u32 tmp = RREG32(mmSRBM_STATUS);
1105 if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1106 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1107 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1109 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1110 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1111 if (!(adev->flags & AMD_IS_APU))
1112 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1113 SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1116 if (srbm_soft_reset) {
1117 gmc_v7_0_mc_stop(adev, &save);
1118 if (gmc_v7_0_wait_for_idle((void *)adev)) {
1119 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1123 tmp = RREG32(mmSRBM_SOFT_RESET);
1124 tmp |= srbm_soft_reset;
1125 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1126 WREG32(mmSRBM_SOFT_RESET, tmp);
1127 tmp = RREG32(mmSRBM_SOFT_RESET);
1131 tmp &= ~srbm_soft_reset;
1132 WREG32(mmSRBM_SOFT_RESET, tmp);
1133 tmp = RREG32(mmSRBM_SOFT_RESET);
1135 /* Wait a little for things to settle down */
1138 gmc_v7_0_mc_resume(adev, &save);
1145 static int gmc_v7_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1146 struct amdgpu_irq_src *src,
1148 enum amdgpu_interrupt_state state)
1151 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1152 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1153 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1154 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1155 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1156 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1159 case AMDGPU_IRQ_STATE_DISABLE:
1160 /* system context */
1161 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1163 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1165 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1167 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1169 case AMDGPU_IRQ_STATE_ENABLE:
1170 /* system context */
1171 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1173 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1175 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1177 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1186 static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev,
1187 struct amdgpu_irq_src *source,
1188 struct amdgpu_iv_entry *entry)
1190 u32 addr, status, mc_client;
1192 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1193 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1194 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1195 /* reset addr and status */
1196 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1198 if (!addr && !status)
1201 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1202 gmc_v7_0_set_fault_enable_default(adev, false);
1204 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1205 entry->src_id, entry->src_data);
1206 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1208 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1210 gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client);
1215 static int gmc_v7_0_set_clockgating_state(void *handle,
1216 enum amd_clockgating_state state)
1219 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1221 if (state == AMD_CG_STATE_GATE)
1224 if (!(adev->flags & AMD_IS_APU)) {
1225 gmc_v7_0_enable_mc_mgcg(adev, gate);
1226 gmc_v7_0_enable_mc_ls(adev, gate);
1228 gmc_v7_0_enable_bif_mgls(adev, gate);
1229 gmc_v7_0_enable_hdp_mgcg(adev, gate);
1230 gmc_v7_0_enable_hdp_ls(adev, gate);
1235 static int gmc_v7_0_set_powergating_state(void *handle,
1236 enum amd_powergating_state state)
1241 const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
1243 .early_init = gmc_v7_0_early_init,
1244 .late_init = gmc_v7_0_late_init,
1245 .sw_init = gmc_v7_0_sw_init,
1246 .sw_fini = gmc_v7_0_sw_fini,
1247 .hw_init = gmc_v7_0_hw_init,
1248 .hw_fini = gmc_v7_0_hw_fini,
1249 .suspend = gmc_v7_0_suspend,
1250 .resume = gmc_v7_0_resume,
1251 .is_idle = gmc_v7_0_is_idle,
1252 .wait_for_idle = gmc_v7_0_wait_for_idle,
1253 .soft_reset = gmc_v7_0_soft_reset,
1254 .set_clockgating_state = gmc_v7_0_set_clockgating_state,
1255 .set_powergating_state = gmc_v7_0_set_powergating_state,
1258 static const struct amdgpu_gart_funcs gmc_v7_0_gart_funcs = {
1259 .flush_gpu_tlb = gmc_v7_0_gart_flush_gpu_tlb,
1260 .set_pte_pde = gmc_v7_0_gart_set_pte_pde,
1263 static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = {
1264 .set = gmc_v7_0_vm_fault_interrupt_state,
1265 .process = gmc_v7_0_process_interrupt,
1268 static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev)
1270 if (adev->gart.gart_funcs == NULL)
1271 adev->gart.gart_funcs = &gmc_v7_0_gart_funcs;
1274 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev)
1276 adev->mc.vm_fault.num_types = 1;
1277 adev->mc.vm_fault.funcs = &gmc_v7_0_irq_funcs;