drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29 #include "vi.h"
  30 #include "vid.h"
  31
  32 #include "oss/oss_2_4_d.h"
  33 #include "oss/oss_2_4_sh_mask.h"
  34
  35 #include "gmc/gmc_7_1_d.h"
  36 #include "gmc/gmc_7_1_sh_mask.h"
  37
  38 #include "gca/gfx_8_0_d.h"
  39 #include "gca/gfx_8_0_enum.h"
  40 #include "gca/gfx_8_0_sh_mask.h"
  41
  42 #include "bif/bif_5_0_d.h"
  43 #include "bif/bif_5_0_sh_mask.h"
  44
  45 #include "iceland_sdma_pkt_open.h"
  46
  47 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev);
  48 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev);
  49 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev);
  50 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev);
  51
  52 MODULE_FIRMWARE("amdgpu/topaz_sdma.bin");
  53 MODULE_FIRMWARE("amdgpu/topaz_sdma1.bin");
  54
  55 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  56 {
  57         SDMA0_REGISTER_OFFSET,
  58         SDMA1_REGISTER_OFFSET
  59 };
  60
  61 static const u32 golden_settings_iceland_a11[] =
  62 {
  63         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  64         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
  65         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
  66         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
  67 };
  68
  69 static const u32 iceland_mgcg_cgcg_init[] =
  70 {
  71         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
  72         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
  73 };
  74
  75 /*
  76  * sDMA - System DMA
  77  * Starting with CIK, the GPU has new asynchronous
  78  * DMA engines.  These engines are used for compute
  79  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
  80  * and each one supports 1 ring buffer used for gfx
  81  * and 2 queues used for compute.
  82  *
  83  * The programming model is very similar to the CP
  84  * (ring buffer, IBs, etc.), but sDMA has it's own
  85  * packet format that is different from the PM4 format
  86  * used by the CP. sDMA supports copying data, writing
  87  * embedded data, solid fills, and a number of other
  88  * things.  It also has support for tiling/detiling of
  89  * buffers.
  90  */
  91
  92 static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev)
  93 {
  94         switch (adev->asic_type) {
  95         case CHIP_TOPAZ:
  96                 amdgpu_program_register_sequence(adev,
  97                                                  iceland_mgcg_cgcg_init,
  98                                                  (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
  99                 amdgpu_program_register_sequence(adev,
 100                                                  golden_settings_iceland_a11,
 101                                                  (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
 102                 break;
 103         default:
 104                 break;
 105         }
 106 }
 107
 108 static void sdma_v2_4_free_microcode(struct amdgpu_device *adev)
 109 {
 110         int i;
 111         for (i = 0; i < adev->sdma.num_instances; i++) {
 112                 release_firmware(adev->sdma.instance[i].fw);
 113                 adev->sdma.instance[i].fw = NULL;
 114         }
 115 }
 116
 117 /**
 118  * sdma_v2_4_init_microcode - load ucode images from disk
 119  *
 120  * @adev: amdgpu_device pointer
 121  *
 122  * Use the firmware interface to load the ucode images into
 123  * the driver (not loaded into hw).
 124  * Returns 0 on success, error on failure.
 125  */
 126 static int sdma_v2_4_init_microcode(struct amdgpu_device *adev)
 127 {
 128         const char *chip_name;
 129         char fw_name[30];
 130         int err = 0, i;
 131         struct amdgpu_firmware_info *info = NULL;
 132         const struct common_firmware_header *header = NULL;
 133         const struct sdma_firmware_header_v1_0 *hdr;
 134
 135         DRM_DEBUG("\n");
 136
 137         switch (adev->asic_type) {
 138         case CHIP_TOPAZ:
 139                 chip_name = "topaz";
 140                 break;
 141         default: BUG();
 142         }
 143
 144         for (i = 0; i < adev->sdma.num_instances; i++) {
 145                 if (i == 0)
 146                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 147                 else
 148                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
 149                 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 150                 if (err)
 151                         goto out;
 152                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 153                 if (err)
 154                         goto out;
 155                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 156                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 157                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 158                 if (adev->sdma.instance[i].feature_version >= 20)
 159                         adev->sdma.instance[i].burst_nop = true;
 160
 161                 if (adev->firmware.smu_load) {
 162                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 163                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 164                         info->fw = adev->sdma.instance[i].fw;
 165                         header = (const struct common_firmware_header *)info->fw->data;
 166                         adev->firmware.fw_size +=
 167                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 168                 }
 169         }
 170
 171 out:
 172         if (err) {
 173                 printk(KERN_ERR
 174                        "sdma_v2_4: Failed to load firmware \"%s\"\n",
 175                        fw_name);
 176                 for (i = 0; i < adev->sdma.num_instances; i++) {
 177                         release_firmware(adev->sdma.instance[i].fw);
 178                         adev->sdma.instance[i].fw = NULL;
 179                 }
 180         }
 181         return err;
 182 }
 183
 184 /**
 185  * sdma_v2_4_ring_get_rptr - get the current read pointer
 186  *
 187  * @ring: amdgpu ring pointer
 188  *
 189  * Get the current rptr from the hardware (VI+).
 190  */
 191 static uint32_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)
 192 {
 193         /* XXX check if swapping is necessary on BE */
 194         return ring->adev->wb.wb[ring->rptr_offs] >> 2;
 195 }
 196
 197 /**
 198  * sdma_v2_4_ring_get_wptr - get the current write pointer
 199  *
 200  * @ring: amdgpu ring pointer
 201  *
 202  * Get the current wptr from the hardware (VI+).
 203  */
 204 static uint32_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
 205 {
 206         struct amdgpu_device *adev = ring->adev;
 207         int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
 208         u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
 209
 210         return wptr;
 211 }
 212
 213 /**
 214  * sdma_v2_4_ring_set_wptr - commit the write pointer
 215  *
 216  * @ring: amdgpu ring pointer
 217  *
 218  * Write the wptr back to the hardware (VI+).
 219  */
 220 static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring)
 221 {
 222         struct amdgpu_device *adev = ring->adev;
 223         int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
 224
 225         WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);
 226 }
 227
 228 static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 229 {
 230         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 231         int i;
 232
 233         for (i = 0; i < count; i++)
 234                 if (sdma && sdma->burst_nop && (i == 0))
 235                         amdgpu_ring_write(ring, ring->nop |
 236                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 237                 else
 238                         amdgpu_ring_write(ring, ring->nop);
 239 }
 240
 241 /**
 242  * sdma_v2_4_ring_emit_ib - Schedule an IB on the DMA engine
 243  *
 244  * @ring: amdgpu ring pointer
 245  * @ib: IB object to schedule
 246  *
 247  * Schedule an IB in the DMA ring (VI).
 248  */
 249 static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring,
 250                                    struct amdgpu_ib *ib,
 251                                    unsigned vm_id, bool ctx_switch)
 252 {
 253         u32 vmid = vm_id & 0xf;
 254
 255         /* IB packet must end on a 8 DW boundary */
 256         sdma_v2_4_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8);
 257
 258         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 259                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
 260         /* base must be 32 byte aligned */
 261         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 262         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 263         amdgpu_ring_write(ring, ib->length_dw);
 264         amdgpu_ring_write(ring, 0);
 265         amdgpu_ring_write(ring, 0);
 266
 267 }
 268
 269 /**
 270  * sdma_v2_4_hdp_flush_ring_emit - emit an hdp flush on the DMA ring
 271  *
 272  * @ring: amdgpu ring pointer
 273  *
 274  * Emit an hdp flush packet on the requested DMA ring.
 275  */
 276 static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 277 {
 278         u32 ref_and_mask = 0;
 279
 280         if (ring == &ring->adev->sdma.instance[0].ring)
 281                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
 282         else
 283                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
 284
 285         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 286                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 287                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 288         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
 289         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
 290         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 291         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 292         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 293                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 294 }
 295
 296 static void sdma_v2_4_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
 297 {
 298         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 299                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 300         amdgpu_ring_write(ring, mmHDP_DEBUG0);
 301         amdgpu_ring_write(ring, 1);
 302 }
 303 /**
 304  * sdma_v2_4_ring_emit_fence - emit a fence on the DMA ring
 305  *
 306  * @ring: amdgpu ring pointer
 307  * @fence: amdgpu fence object
 308  *
 309  * Add a DMA fence packet to the ring to write
 310  * the fence seq number and DMA trap packet to generate
 311  * an interrupt if needed (VI).
 312  */
 313 static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 314                                       unsigned flags)
 315 {
 316         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 317         /* write the fence */
 318         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 319         amdgpu_ring_write(ring, lower_32_bits(addr));
 320         amdgpu_ring_write(ring, upper_32_bits(addr));
 321         amdgpu_ring_write(ring, lower_32_bits(seq));
 322
 323         /* optionally write high bits as well */
 324         if (write64bit) {
 325                 addr += 4;
 326                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 327                 amdgpu_ring_write(ring, lower_32_bits(addr));
 328                 amdgpu_ring_write(ring, upper_32_bits(addr));
 329                 amdgpu_ring_write(ring, upper_32_bits(seq));
 330         }
 331
 332         /* generate an interrupt */
 333         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 334         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 335 }
 336
 337 /**
 338  * sdma_v2_4_gfx_stop - stop the gfx async dma engines
 339  *
 340  * @adev: amdgpu_device pointer
 341  *
 342  * Stop the gfx async dma ring buffers (VI).
 343  */
 344 static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev)
 345 {
 346         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 347         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 348         u32 rb_cntl, ib_cntl;
 349         int i;
 350
 351         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 352             (adev->mman.buffer_funcs_ring == sdma1))
 353                 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
 354
 355         for (i = 0; i < adev->sdma.num_instances; i++) {
 356                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 357                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 358                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 359                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 360                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 361                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 362         }
 363         sdma0->ready = false;
 364         sdma1->ready = false;
 365 }
 366
 367 /**
 368  * sdma_v2_4_rlc_stop - stop the compute async dma engines
 369  *
 370  * @adev: amdgpu_device pointer
 371  *
 372  * Stop the compute async dma queues (VI).
 373  */
 374 static void sdma_v2_4_rlc_stop(struct amdgpu_device *adev)
 375 {
 376         /* XXX todo */
 377 }
 378
 379 /**
 380  * sdma_v2_4_enable - stop the async dma engines
 381  *
 382  * @adev: amdgpu_device pointer
 383  * @enable: enable/disable the DMA MEs.
 384  *
 385  * Halt or unhalt the async dma engines (VI).
 386  */
 387 static void sdma_v2_4_enable(struct amdgpu_device *adev, bool enable)
 388 {
 389         u32 f32_cntl;
 390         int i;
 391
 392         if (!enable) {
 393                 sdma_v2_4_gfx_stop(adev);
 394                 sdma_v2_4_rlc_stop(adev);
 395         }
 396
 397         for (i = 0; i < adev->sdma.num_instances; i++) {
 398                 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
 399                 if (enable)
 400                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
 401                 else
 402                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
 403                 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
 404         }
 405 }
 406
 407 /**
 408  * sdma_v2_4_gfx_resume - setup and start the async dma engines
 409  *
 410  * @adev: amdgpu_device pointer
 411  *
 412  * Set up the gfx DMA ring buffers and enable them (VI).
 413  * Returns 0 for success, error for failure.
 414  */
 415 static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev)
 416 {
 417         struct amdgpu_ring *ring;
 418         u32 rb_cntl, ib_cntl;
 419         u32 rb_bufsz;
 420         u32 wb_offset;
 421         int i, j, r;
 422
 423         for (i = 0; i < adev->sdma.num_instances; i++) {
 424                 ring = &adev->sdma.instance[i].ring;
 425                 wb_offset = (ring->rptr_offs * 4);
 426
 427                 mutex_lock(&adev->srbm_mutex);
 428                 for (j = 0; j < 16; j++) {
 429                         vi_srbm_select(adev, 0, 0, 0, j);
 430                         /* SDMA GFX */
 431                         WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
 432                         WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
 433                 }
 434                 vi_srbm_select(adev, 0, 0, 0, 0);
 435                 mutex_unlock(&adev->srbm_mutex);
 436
 437                 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
 438                        adev->gfx.config.gb_addr_config & 0x70);
 439
 440                 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 441
 442                 /* Set ring buffer size in dwords */
 443                 rb_bufsz = order_base_2(ring->ring_size / 4);
 444                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 445                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 446 #ifdef __BIG_ENDIAN
 447                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 448                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 449                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 450 #endif
 451                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 452
 453                 /* Initialize the ring buffer's read and write pointers */
 454                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
 455                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
 456                 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
 457                 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
 458
 459                 /* set the wb address whether it's enabled or not */
 460                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
 461                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 462                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
 463                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 464
 465                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 466
 467                 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 468                 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 469
 470                 ring->wptr = 0;
 471                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
 472
 473                 /* enable DMA RB */
 474                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 475                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 476
 477                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 478                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 479 #ifdef __BIG_ENDIAN
 480                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 481 #endif
 482                 /* enable DMA IBs */
 483                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 484
 485                 ring->ready = true;
 486         }
 487
 488         sdma_v2_4_enable(adev, true);
 489         for (i = 0; i < adev->sdma.num_instances; i++) {
 490                 ring = &adev->sdma.instance[i].ring;
 491                 r = amdgpu_ring_test_ring(ring);
 492                 if (r) {
 493                         ring->ready = false;
 494                         return r;
 495                 }
 496
 497                 if (adev->mman.buffer_funcs_ring == ring)
 498                         amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
 499         }
 500
 501         return 0;
 502 }
 503
 504 /**
 505  * sdma_v2_4_rlc_resume - setup and start the async dma engines
 506  *
 507  * @adev: amdgpu_device pointer
 508  *
 509  * Set up the compute DMA queues and enable them (VI).
 510  * Returns 0 for success, error for failure.
 511  */
 512 static int sdma_v2_4_rlc_resume(struct amdgpu_device *adev)
 513 {
 514         /* XXX todo */
 515         return 0;
 516 }
 517
 518 /**
 519  * sdma_v2_4_load_microcode - load the sDMA ME ucode
 520  *
 521  * @adev: amdgpu_device pointer
 522  *
 523  * Loads the sDMA0/1 ucode.
 524  * Returns 0 for success, -EINVAL if the ucode is not available.
 525  */
 526 static int sdma_v2_4_load_microcode(struct amdgpu_device *adev)
 527 {
 528         const struct sdma_firmware_header_v1_0 *hdr;
 529         const __le32 *fw_data;
 530         u32 fw_size;
 531         int i, j;
 532
 533         /* halt the MEs */
 534         sdma_v2_4_enable(adev, false);
 535
 536         for (i = 0; i < adev->sdma.num_instances; i++) {
 537                 if (!adev->sdma.instance[i].fw)
 538                         return -EINVAL;
 539                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 540                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 541                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 542                 fw_data = (const __le32 *)
 543                         (adev->sdma.instance[i].fw->data +
 544                          le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 545                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
 546                 for (j = 0; j < fw_size; j++)
 547                         WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
 548                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
 549         }
 550
 551         return 0;
 552 }
 553
 554 /**
 555  * sdma_v2_4_start - setup and start the async dma engines
 556  *
 557  * @adev: amdgpu_device pointer
 558  *
 559  * Set up the DMA engines and enable them (VI).
 560  * Returns 0 for success, error for failure.
 561  */
 562 static int sdma_v2_4_start(struct amdgpu_device *adev)
 563 {
 564         int r;
 565
 566         if (!adev->pp_enabled) {
 567                 if (!adev->firmware.smu_load) {
 568                         r = sdma_v2_4_load_microcode(adev);
 569                         if (r)
 570                                 return r;
 571                 } else {
 572                         r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
 573                                                         AMDGPU_UCODE_ID_SDMA0);
 574                         if (r)
 575                                 return -EINVAL;
 576                         r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
 577                                                         AMDGPU_UCODE_ID_SDMA1);
 578                         if (r)
 579                                 return -EINVAL;
 580                 }
 581         }
 582
 583         /* halt the engine before programing */
 584         sdma_v2_4_enable(adev, false);
 585
 586         /* start the gfx rings and rlc compute queues */
 587         r = sdma_v2_4_gfx_resume(adev);
 588         if (r)
 589                 return r;
 590         r = sdma_v2_4_rlc_resume(adev);
 591         if (r)
 592                 return r;
 593
 594         return 0;
 595 }
 596
 597 /**
 598  * sdma_v2_4_ring_test_ring - simple async dma engine test
 599  *
 600  * @ring: amdgpu_ring structure holding ring information
 601  *
 602  * Test the DMA engine by writing using it to write an
 603  * value to memory. (VI).
 604  * Returns 0 for success, error for failure.
 605  */
 606 static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring)
 607 {
 608         struct amdgpu_device *adev = ring->adev;
 609         unsigned i;
 610         unsigned index;
 611         int r;
 612         u32 tmp;
 613         u64 gpu_addr;
 614
 615         r = amdgpu_wb_get(adev, &index);
 616         if (r) {
 617                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 618                 return r;
 619         }
 620
 621         gpu_addr = adev->wb.gpu_addr + (index * 4);
 622         tmp = 0xCAFEDEAD;
 623         adev->wb.wb[index] = cpu_to_le32(tmp);
 624
 625         r = amdgpu_ring_alloc(ring, 5);
 626         if (r) {
 627                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 628                 amdgpu_wb_free(adev, index);
 629                 return r;
 630         }
 631
 632         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 633                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 634         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 635         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 636         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
 637         amdgpu_ring_write(ring, 0xDEADBEEF);
 638         amdgpu_ring_commit(ring);
 639
 640         for (i = 0; i < adev->usec_timeout; i++) {
 641                 tmp = le32_to_cpu(adev->wb.wb[index]);
 642                 if (tmp == 0xDEADBEEF)
 643                         break;
 644                 DRM_UDELAY(1);
 645         }
 646
 647         if (i < adev->usec_timeout) {
 648                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
 649         } else {
 650                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 651                           ring->idx, tmp);
 652                 r = -EINVAL;
 653         }
 654         amdgpu_wb_free(adev, index);
 655
 656         return r;
 657 }
 658
 659 /**
 660  * sdma_v2_4_ring_test_ib - test an IB on the DMA engine
 661  *
 662  * @ring: amdgpu_ring structure holding ring information
 663  *
 664  * Test a simple IB in the DMA ring (VI).
 665  * Returns 0 on success, error on failure.
 666  */
 667 static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 668 {
 669         struct amdgpu_device *adev = ring->adev;
 670         struct amdgpu_ib ib;
 671         struct fence *f = NULL;
 672         unsigned index;
 673         u32 tmp = 0;
 674         u64 gpu_addr;
 675         long r;
 676
 677         r = amdgpu_wb_get(adev, &index);
 678         if (r) {
 679                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 680                 return r;
 681         }
 682
 683         gpu_addr = adev->wb.gpu_addr + (index * 4);
 684         tmp = 0xCAFEDEAD;
 685         adev->wb.wb[index] = cpu_to_le32(tmp);
 686         memset(&ib, 0, sizeof(ib));
 687         r = amdgpu_ib_get(adev, NULL, 256, &ib);
 688         if (r) {
 689                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 690                 goto err0;
 691         }
 692
 693         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 694                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 695         ib.ptr[1] = lower_32_bits(gpu_addr);
 696         ib.ptr[2] = upper_32_bits(gpu_addr);
 697         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
 698         ib.ptr[4] = 0xDEADBEEF;
 699         ib.ptr[5] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 700         ib.ptr[6] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 701         ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 702         ib.length_dw = 8;
 703
 704         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
 705         if (r)
 706                 goto err1;
 707
 708         r = fence_wait_timeout(f, false, timeout);
 709         if (r == 0) {
 710                 DRM_ERROR("amdgpu: IB test timed out\n");
 711                 r = -ETIMEDOUT;
 712                 goto err1;
 713         } else if (r < 0) {
 714                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 715                 goto err1;
 716         }
 717         tmp = le32_to_cpu(adev->wb.wb[index]);
 718         if (tmp == 0xDEADBEEF) {
 719                 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
 720                 r = 0;
 721         } else {
 722                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
 723                 r = -EINVAL;
 724         }
 725
 726 err1:
 727         amdgpu_ib_free(adev, &ib, NULL);
 728         fence_put(f);
 729 err0:
 730         amdgpu_wb_free(adev, index);
 731         return r;
 732 }
 733
 734 /**
 735  * sdma_v2_4_vm_copy_pte - update PTEs by copying them from the GART
 736  *
 737  * @ib: indirect buffer to fill with commands
 738  * @pe: addr of the page entry
 739  * @src: src addr to copy from
 740  * @count: number of page entries to update
 741  *
 742  * Update PTEs by copying them from the GART using sDMA (CIK).
 743  */
 744 static void sdma_v2_4_vm_copy_pte(struct amdgpu_ib *ib,
 745                                   uint64_t pe, uint64_t src,
 746                                   unsigned count)
 747 {
 748         unsigned bytes = count * 8;
 749
 750         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
 751                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 752         ib->ptr[ib->length_dw++] = bytes;
 753         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 754         ib->ptr[ib->length_dw++] = lower_32_bits(src);
 755         ib->ptr[ib->length_dw++] = upper_32_bits(src);
 756         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 757         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 758 }
 759
 760 /**
 761  * sdma_v2_4_vm_write_pte - update PTEs by writing them manually
 762  *
 763  * @ib: indirect buffer to fill with commands
 764  * @pe: addr of the page entry
 765  * @value: dst addr to write into pe
 766  * @count: number of page entries to update
 767  * @incr: increase next addr by incr bytes
 768  *
 769  * Update PTEs by writing them manually using sDMA (CIK).
 770  */
 771 static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
 772                                    uint64_t value, unsigned count,
 773                                    uint32_t incr)
 774 {
 775         unsigned ndw = count * 2;
 776
 777         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 778                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 779         ib->ptr[ib->length_dw++] = pe;
 780         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 781         ib->ptr[ib->length_dw++] = ndw;
 782         for (; ndw > 0; ndw -= 2, --count, pe += 8) {
 783                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
 784                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
 785                 value += incr;
 786         }
 787 }
 788
 789 /**
 790  * sdma_v2_4_vm_set_pte_pde - update the page tables using sDMA
 791  *
 792  * @ib: indirect buffer to fill with commands
 793  * @pe: addr of the page entry
 794  * @addr: dst addr to write into pe
 795  * @count: number of page entries to update
 796  * @incr: increase next addr by incr bytes
 797  * @flags: access flags
 798  *
 799  * Update the page tables using sDMA (CIK).
 800  */
 801 static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
 802                                      uint64_t addr, unsigned count,
 803                                      uint32_t incr, uint32_t flags)
 804 {
 805         /* for physically contiguous pages (vram) */
 806         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
 807         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
 808         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 809         ib->ptr[ib->length_dw++] = flags; /* mask */
 810         ib->ptr[ib->length_dw++] = 0;
 811         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
 812         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
 813         ib->ptr[ib->length_dw++] = incr; /* increment size */
 814         ib->ptr[ib->length_dw++] = 0;
 815         ib->ptr[ib->length_dw++] = count; /* number of entries */
 816 }
 817
 818 /**
 819  * sdma_v2_4_ring_pad_ib - pad the IB to the required number of dw
 820  *
 821  * @ib: indirect buffer to fill with padding
 822  *
 823  */
 824 static void sdma_v2_4_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
 825 {
 826         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 827         u32 pad_count;
 828         int i;
 829
 830         pad_count = (8 - (ib->length_dw & 0x7)) % 8;
 831         for (i = 0; i < pad_count; i++)
 832                 if (sdma && sdma->burst_nop && (i == 0))
 833                         ib->ptr[ib->length_dw++] =
 834                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
 835                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
 836                 else
 837                         ib->ptr[ib->length_dw++] =
 838                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 839 }
 840
 841 /**
 842  * sdma_v2_4_ring_emit_pipeline_sync - sync the pipeline
 843  *
 844  * @ring: amdgpu_ring pointer
 845  *
 846  * Make sure all previous operations are completed (CIK).
 847  */
 848 static void sdma_v2_4_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
 849 {
 850         uint32_t seq = ring->fence_drv.sync_seq;
 851         uint64_t addr = ring->fence_drv.gpu_addr;
 852
 853         /* wait for idle */
 854         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 855                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
 856                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
 857                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
 858         amdgpu_ring_write(ring, addr & 0xfffffffc);
 859         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
 860         amdgpu_ring_write(ring, seq); /* reference */
 861         amdgpu_ring_write(ring, 0xfffffff); /* mask */
 862         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 863                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
 864 }
 865
 866 /**
 867  * sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA
 868  *
 869  * @ring: amdgpu_ring pointer
 870  * @vm: amdgpu_vm pointer
 871  *
 872  * Update the page table base and flush the VM TLB
 873  * using sDMA (VI).
 874  */
 875 static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
 876                                          unsigned vm_id, uint64_t pd_addr)
 877 {
 878         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 879                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 880         if (vm_id < 8) {
 881                 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
 882         } else {
 883                 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
 884         }
 885         amdgpu_ring_write(ring, pd_addr >> 12);
 886
 887         /* flush TLB */
 888         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 889                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 890         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
 891         amdgpu_ring_write(ring, 1 << vm_id);
 892
 893         /* wait for flush */
 894         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 895                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
 896                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
 897         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
 898         amdgpu_ring_write(ring, 0);
 899         amdgpu_ring_write(ring, 0); /* reference */
 900         amdgpu_ring_write(ring, 0); /* mask */
 901         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 902                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 903 }
 904
 905 static unsigned sdma_v2_4_ring_get_emit_ib_size(struct amdgpu_ring *ring)
 906 {
 907         return
 908                 7 + 6; /* sdma_v2_4_ring_emit_ib */
 909 }
 910
 911 static unsigned sdma_v2_4_ring_get_dma_frame_size(struct amdgpu_ring *ring)
 912 {
 913         return
 914                 6 + /* sdma_v2_4_ring_emit_hdp_flush */
 915                 3 + /* sdma_v2_4_ring_emit_hdp_invalidate */
 916                 6 + /* sdma_v2_4_ring_emit_pipeline_sync */
 917                 12 + /* sdma_v2_4_ring_emit_vm_flush */
 918                 10 + 10 + 10; /* sdma_v2_4_ring_emit_fence x3 for user fence, vm fence */
 919 }
 920
 921 static int sdma_v2_4_early_init(void *handle)
 922 {
 923         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 924
 925         adev->sdma.num_instances = SDMA_MAX_INSTANCE;
 926
 927         sdma_v2_4_set_ring_funcs(adev);
 928         sdma_v2_4_set_buffer_funcs(adev);
 929         sdma_v2_4_set_vm_pte_funcs(adev);
 930         sdma_v2_4_set_irq_funcs(adev);
 931
 932         return 0;
 933 }
 934
 935 static int sdma_v2_4_sw_init(void *handle)
 936 {
 937         struct amdgpu_ring *ring;
 938         int r, i;
 939         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 940
 941         /* SDMA trap event */
 942         r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
 943         if (r)
 944                 return r;
 945
 946         /* SDMA Privileged inst */
 947         r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
 948         if (r)
 949                 return r;
 950
 951         /* SDMA Privileged inst */
 952         r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
 953         if (r)
 954                 return r;
 955
 956         r = sdma_v2_4_init_microcode(adev);
 957         if (r) {
 958                 DRM_ERROR("Failed to load sdma firmware!\n");
 959                 return r;
 960         }
 961
 962         for (i = 0; i < adev->sdma.num_instances; i++) {
 963                 ring = &adev->sdma.instance[i].ring;
 964                 ring->ring_obj = NULL;
 965                 ring->use_doorbell = false;
 966                 sprintf(ring->name, "sdma%d", i);
 967                 r = amdgpu_ring_init(adev, ring, 1024,
 968                                      SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
 969                                      &adev->sdma.trap_irq,
 970                                      (i == 0) ?
 971                                      AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1,
 972                                      AMDGPU_RING_TYPE_SDMA);
 973                 if (r)
 974                         return r;
 975         }
 976
 977         return r;
 978 }
 979
 980 static int sdma_v2_4_sw_fini(void *handle)
 981 {
 982         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 983         int i;
 984
 985         for (i = 0; i < adev->sdma.num_instances; i++)
 986                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
 987
 988         sdma_v2_4_free_microcode(adev);
 989         return 0;
 990 }
 991
 992 static int sdma_v2_4_hw_init(void *handle)
 993 {
 994         int r;
 995         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 996
 997         sdma_v2_4_init_golden_registers(adev);
 998
 999         r = sdma_v2_4_start(adev);
1000         if (r)
1001                 return r;
1002
1003         return r;
1004 }
1005
1006 static int sdma_v2_4_hw_fini(void *handle)
1007 {
1008         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1009
1010         sdma_v2_4_enable(adev, false);
1011
1012         return 0;
1013 }
1014
1015 static int sdma_v2_4_suspend(void *handle)
1016 {
1017         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1018
1019         return sdma_v2_4_hw_fini(adev);
1020 }
1021
1022 static int sdma_v2_4_resume(void *handle)
1023 {
1024         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1025
1026         return sdma_v2_4_hw_init(adev);
1027 }
1028
1029 static bool sdma_v2_4_is_idle(void *handle)
1030 {
1031         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1032         u32 tmp = RREG32(mmSRBM_STATUS2);
1033
1034         if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1035                    SRBM_STATUS2__SDMA1_BUSY_MASK))
1036             return false;
1037
1038         return true;
1039 }
1040
1041 static int sdma_v2_4_wait_for_idle(void *handle)
1042 {
1043         unsigned i;
1044         u32 tmp;
1045         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1046
1047         for (i = 0; i < adev->usec_timeout; i++) {
1048                 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1049                                 SRBM_STATUS2__SDMA1_BUSY_MASK);
1050
1051                 if (!tmp)
1052                         return 0;
1053                 udelay(1);
1054         }
1055         return -ETIMEDOUT;
1056 }
1057
1058 static int sdma_v2_4_soft_reset(void *handle)
1059 {
1060         u32 srbm_soft_reset = 0;
1061         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1062         u32 tmp = RREG32(mmSRBM_STATUS2);
1063
1064         if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1065                 /* sdma0 */
1066                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1067                 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1068                 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1069                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1070         }
1071         if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1072                 /* sdma1 */
1073                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1074                 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1075                 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1076                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1077         }
1078
1079         if (srbm_soft_reset) {
1080                 tmp = RREG32(mmSRBM_SOFT_RESET);
1081                 tmp |= srbm_soft_reset;
1082                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1083                 WREG32(mmSRBM_SOFT_RESET, tmp);
1084                 tmp = RREG32(mmSRBM_SOFT_RESET);
1085
1086                 udelay(50);
1087
1088                 tmp &= ~srbm_soft_reset;
1089                 WREG32(mmSRBM_SOFT_RESET, tmp);
1090                 tmp = RREG32(mmSRBM_SOFT_RESET);
1091
1092                 /* Wait a little for things to settle down */
1093                 udelay(50);
1094         }
1095
1096         return 0;
1097 }
1098
1099 static int sdma_v2_4_set_trap_irq_state(struct amdgpu_device *adev,
1100                                         struct amdgpu_irq_src *src,
1101                                         unsigned type,
1102                                         enum amdgpu_interrupt_state state)
1103 {
1104         u32 sdma_cntl;
1105
1106         switch (type) {
1107         case AMDGPU_SDMA_IRQ_TRAP0:
1108                 switch (state) {
1109                 case AMDGPU_IRQ_STATE_DISABLE:
1110                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1111                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1112                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1113                         break;
1114                 case AMDGPU_IRQ_STATE_ENABLE:
1115                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1116                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1117                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1118                         break;
1119                 default:
1120                         break;
1121                 }
1122                 break;
1123         case AMDGPU_SDMA_IRQ_TRAP1:
1124                 switch (state) {
1125                 case AMDGPU_IRQ_STATE_DISABLE:
1126                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1127                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1128                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1129                         break;
1130                 case AMDGPU_IRQ_STATE_ENABLE:
1131                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1132                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1133                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1134                         break;
1135                 default:
1136                         break;
1137                 }
1138                 break;
1139         default:
1140                 break;
1141         }
1142         return 0;
1143 }
1144
1145 static int sdma_v2_4_process_trap_irq(struct amdgpu_device *adev,
1146                                       struct amdgpu_irq_src *source,
1147                                       struct amdgpu_iv_entry *entry)
1148 {
1149         u8 instance_id, queue_id;
1150
1151         instance_id = (entry->ring_id & 0x3) >> 0;
1152         queue_id = (entry->ring_id & 0xc) >> 2;
1153         DRM_DEBUG("IH: SDMA trap\n");
1154         switch (instance_id) {
1155         case 0:
1156                 switch (queue_id) {
1157                 case 0:
1158                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1159                         break;
1160                 case 1:
1161                         /* XXX compute */
1162                         break;
1163                 case 2:
1164                         /* XXX compute */
1165                         break;
1166                 }
1167                 break;
1168         case 1:
1169                 switch (queue_id) {
1170                 case 0:
1171                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1172                         break;
1173                 case 1:
1174                         /* XXX compute */
1175                         break;
1176                 case 2:
1177                         /* XXX compute */
1178                         break;
1179                 }
1180                 break;
1181         }
1182         return 0;
1183 }
1184
1185 static int sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device *adev,
1186                                               struct amdgpu_irq_src *source,
1187                                               struct amdgpu_iv_entry *entry)
1188 {
1189         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1190         schedule_work(&adev->reset_work);
1191         return 0;
1192 }
1193
1194 static int sdma_v2_4_set_clockgating_state(void *handle,
1195                                           enum amd_clockgating_state state)
1196 {
1197         /* XXX handled via the smc on VI */
1198         return 0;
1199 }
1200
1201 static int sdma_v2_4_set_powergating_state(void *handle,
1202                                           enum amd_powergating_state state)
1203 {
1204         return 0;
1205 }
1206
1207 const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
1208         .name = "sdma_v2_4",
1209         .early_init = sdma_v2_4_early_init,
1210         .late_init = NULL,
1211         .sw_init = sdma_v2_4_sw_init,
1212         .sw_fini = sdma_v2_4_sw_fini,
1213         .hw_init = sdma_v2_4_hw_init,
1214         .hw_fini = sdma_v2_4_hw_fini,
1215         .suspend = sdma_v2_4_suspend,
1216         .resume = sdma_v2_4_resume,
1217         .is_idle = sdma_v2_4_is_idle,
1218         .wait_for_idle = sdma_v2_4_wait_for_idle,
1219         .soft_reset = sdma_v2_4_soft_reset,
1220         .set_clockgating_state = sdma_v2_4_set_clockgating_state,
1221         .set_powergating_state = sdma_v2_4_set_powergating_state,
1222 };
1223
1224 static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
1225         .get_rptr = sdma_v2_4_ring_get_rptr,
1226         .get_wptr = sdma_v2_4_ring_get_wptr,
1227         .set_wptr = sdma_v2_4_ring_set_wptr,
1228         .parse_cs = NULL,
1229         .emit_ib = sdma_v2_4_ring_emit_ib,
1230         .emit_fence = sdma_v2_4_ring_emit_fence,
1231         .emit_pipeline_sync = sdma_v2_4_ring_emit_pipeline_sync,
1232         .emit_vm_flush = sdma_v2_4_ring_emit_vm_flush,
1233         .emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush,
1234         .emit_hdp_invalidate = sdma_v2_4_ring_emit_hdp_invalidate,
1235         .test_ring = sdma_v2_4_ring_test_ring,
1236         .test_ib = sdma_v2_4_ring_test_ib,
1237         .insert_nop = sdma_v2_4_ring_insert_nop,
1238         .pad_ib = sdma_v2_4_ring_pad_ib,
1239         .get_emit_ib_size = sdma_v2_4_ring_get_emit_ib_size,
1240         .get_dma_frame_size = sdma_v2_4_ring_get_dma_frame_size,
1241 };
1242
1243 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev)
1244 {
1245         int i;
1246
1247         for (i = 0; i < adev->sdma.num_instances; i++)
1248                 adev->sdma.instance[i].ring.funcs = &sdma_v2_4_ring_funcs;
1249 }
1250
1251 static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = {
1252         .set = sdma_v2_4_set_trap_irq_state,
1253         .process = sdma_v2_4_process_trap_irq,
1254 };
1255
1256 static const struct amdgpu_irq_src_funcs sdma_v2_4_illegal_inst_irq_funcs = {
1257         .process = sdma_v2_4_process_illegal_inst_irq,
1258 };
1259
1260 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev)
1261 {
1262         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1263         adev->sdma.trap_irq.funcs = &sdma_v2_4_trap_irq_funcs;
1264         adev->sdma.illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs;
1265 }
1266
1267 /**
1268  * sdma_v2_4_emit_copy_buffer - copy buffer using the sDMA engine
1269  *
1270  * @ring: amdgpu_ring structure holding ring information
1271  * @src_offset: src GPU address
1272  * @dst_offset: dst GPU address
1273  * @byte_count: number of bytes to xfer
1274  *
1275  * Copy GPU buffers using the DMA engine (VI).
1276  * Used by the amdgpu ttm implementation to move pages if
1277  * registered as the asic copy callback.
1278  */
1279 static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ib *ib,
1280                                        uint64_t src_offset,
1281                                        uint64_t dst_offset,
1282                                        uint32_t byte_count)
1283 {
1284         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1285                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1286         ib->ptr[ib->length_dw++] = byte_count;
1287         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1288         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1289         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1290         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1291         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1292 }
1293
1294 /**
1295  * sdma_v2_4_emit_fill_buffer - fill buffer using the sDMA engine
1296  *
1297  * @ring: amdgpu_ring structure holding ring information
1298  * @src_data: value to write to buffer
1299  * @dst_offset: dst GPU address
1300  * @byte_count: number of bytes to xfer
1301  *
1302  * Fill GPU buffers using the DMA engine (VI).
1303  */
1304 static void sdma_v2_4_emit_fill_buffer(struct amdgpu_ib *ib,
1305                                        uint32_t src_data,
1306                                        uint64_t dst_offset,
1307                                        uint32_t byte_count)
1308 {
1309         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1310         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1311         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1312         ib->ptr[ib->length_dw++] = src_data;
1313         ib->ptr[ib->length_dw++] = byte_count;
1314 }
1315
1316 static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = {
1317         .copy_max_bytes = 0x1fffff,
1318         .copy_num_dw = 7,
1319         .emit_copy_buffer = sdma_v2_4_emit_copy_buffer,
1320
1321         .fill_max_bytes = 0x1fffff,
1322         .fill_num_dw = 7,
1323         .emit_fill_buffer = sdma_v2_4_emit_fill_buffer,
1324 };
1325
1326 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev)
1327 {
1328         if (adev->mman.buffer_funcs == NULL) {
1329                 adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs;
1330                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1331         }
1332 }
1333
1334 static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = {
1335         .copy_pte = sdma_v2_4_vm_copy_pte,
1336         .write_pte = sdma_v2_4_vm_write_pte,
1337         .set_pte_pde = sdma_v2_4_vm_set_pte_pde,
1338 };
1339
1340 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev)
1341 {
1342         unsigned i;
1343
1344         if (adev->vm_manager.vm_pte_funcs == NULL) {
1345                 adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs;
1346                 for (i = 0; i < adev->sdma.num_instances; i++)
1347                         adev->vm_manager.vm_pte_rings[i] =
1348                                 &adev->sdma.instance[i].ring;
1349
1350                 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
1351         }
1352 }