drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29 #include "vi.h"
  30 #include "vid.h"
  31
  32 #include "oss/oss_3_0_d.h"
  33 #include "oss/oss_3_0_sh_mask.h"
  34
  35 #include "gmc/gmc_8_1_d.h"
  36 #include "gmc/gmc_8_1_sh_mask.h"
  37
  38 #include "gca/gfx_8_0_d.h"
  39 #include "gca/gfx_8_0_enum.h"
  40 #include "gca/gfx_8_0_sh_mask.h"
  41
  42 #include "bif/bif_5_0_d.h"
  43 #include "bif/bif_5_0_sh_mask.h"
  44
  45 #include "tonga_sdma_pkt_open.h"
  46
  47 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev);
  48 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev);
  49 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  50 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev);
  51
  52 MODULE_FIRMWARE("amdgpu/tonga_sdma.bin");
  53 MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin");
  54 MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin");
  55 MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin");
  56 MODULE_FIRMWARE("amdgpu/fiji_sdma.bin");
  57 MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin");
  58 MODULE_FIRMWARE("amdgpu/stoney_sdma.bin");
  59
  60 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  61 {
  62         SDMA0_REGISTER_OFFSET,
  63         SDMA1_REGISTER_OFFSET
  64 };
  65
  66 static const u32 golden_settings_tonga_a11[] =
  67 {
  68         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  69         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
  70         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  71         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  72         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  73         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
  74         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
  75         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  76         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  77         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  78 };
  79
  80 static const u32 tonga_mgcg_cgcg_init[] =
  81 {
  82         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
  83         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
  84 };
  85
  86 static const u32 golden_settings_fiji_a10[] =
  87 {
  88         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  89         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  90         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  91         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  92         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
  93         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  94         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  95         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  96 };
  97
  98 static const u32 fiji_mgcg_cgcg_init[] =
  99 {
 100         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
 101         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
 102 };
 103
 104 static const u32 cz_golden_settings_a11[] =
 105 {
 106         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
 107         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
 108         mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
 109         mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
 110         mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
 111         mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
 112         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
 113         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
 114         mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100,
 115         mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800,
 116         mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100,
 117         mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100,
 118 };
 119
 120 static const u32 cz_mgcg_cgcg_init[] =
 121 {
 122         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
 123         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
 124 };
 125
 126 static const u32 stoney_golden_settings_a11[] =
 127 {
 128         mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
 129         mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
 130         mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
 131         mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
 132 };
 133
 134 static const u32 stoney_mgcg_cgcg_init[] =
 135 {
 136         mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100,
 137 };
 138
 139 /*
 140  * sDMA - System DMA
 141  * Starting with CIK, the GPU has new asynchronous
 142  * DMA engines.  These engines are used for compute
 143  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
 144  * and each one supports 1 ring buffer used for gfx
 145  * and 2 queues used for compute.
 146  *
 147  * The programming model is very similar to the CP
 148  * (ring buffer, IBs, etc.), but sDMA has it's own
 149  * packet format that is different from the PM4 format
 150  * used by the CP. sDMA supports copying data, writing
 151  * embedded data, solid fills, and a number of other
 152  * things.  It also has support for tiling/detiling of
 153  * buffers.
 154  */
 155
 156 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
 157 {
 158         switch (adev->asic_type) {
 159         case CHIP_FIJI:
 160                 amdgpu_program_register_sequence(adev,
 161                                                  fiji_mgcg_cgcg_init,
 162                                                  (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
 163                 amdgpu_program_register_sequence(adev,
 164                                                  golden_settings_fiji_a10,
 165                                                  (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
 166                 break;
 167         case CHIP_TONGA:
 168                 amdgpu_program_register_sequence(adev,
 169                                                  tonga_mgcg_cgcg_init,
 170                                                  (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
 171                 amdgpu_program_register_sequence(adev,
 172                                                  golden_settings_tonga_a11,
 173                                                  (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
 174                 break;
 175         case CHIP_CARRIZO:
 176                 amdgpu_program_register_sequence(adev,
 177                                                  cz_mgcg_cgcg_init,
 178                                                  (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
 179                 amdgpu_program_register_sequence(adev,
 180                                                  cz_golden_settings_a11,
 181                                                  (const u32)ARRAY_SIZE(cz_golden_settings_a11));
 182                 break;
 183         case CHIP_STONEY:
 184                 amdgpu_program_register_sequence(adev,
 185                                                  stoney_mgcg_cgcg_init,
 186                                                  (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
 187                 amdgpu_program_register_sequence(adev,
 188                                                  stoney_golden_settings_a11,
 189                                                  (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
 190                 break;
 191         default:
 192                 break;
 193         }
 194 }
 195
 196 /**
 197  * sdma_v3_0_init_microcode - load ucode images from disk
 198  *
 199  * @adev: amdgpu_device pointer
 200  *
 201  * Use the firmware interface to load the ucode images into
 202  * the driver (not loaded into hw).
 203  * Returns 0 on success, error on failure.
 204  */
 205 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
 206 {
 207         const char *chip_name;
 208         char fw_name[30];
 209         int err = 0, i;
 210         struct amdgpu_firmware_info *info = NULL;
 211         const struct common_firmware_header *header = NULL;
 212         const struct sdma_firmware_header_v1_0 *hdr;
 213
 214         DRM_DEBUG("\n");
 215
 216         switch (adev->asic_type) {
 217         case CHIP_TONGA:
 218                 chip_name = "tonga";
 219                 break;
 220         case CHIP_FIJI:
 221                 chip_name = "fiji";
 222                 break;
 223         case CHIP_CARRIZO:
 224                 chip_name = "carrizo";
 225                 break;
 226         case CHIP_STONEY:
 227                 chip_name = "stoney";
 228                 break;
 229         default: BUG();
 230         }
 231
 232         for (i = 0; i < adev->sdma.num_instances; i++) {
 233                 if (i == 0)
 234                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 235                 else
 236                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
 237                 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 238                 if (err)
 239                         goto out;
 240                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 241                 if (err)
 242                         goto out;
 243                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 244                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 245                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 246                 if (adev->sdma.instance[i].feature_version >= 20)
 247                         adev->sdma.instance[i].burst_nop = true;
 248
 249                 if (adev->firmware.smu_load) {
 250                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 251                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 252                         info->fw = adev->sdma.instance[i].fw;
 253                         header = (const struct common_firmware_header *)info->fw->data;
 254                         adev->firmware.fw_size +=
 255                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 256                 }
 257         }
 258 out:
 259         if (err) {
 260                 printk(KERN_ERR
 261                        "sdma_v3_0: Failed to load firmware \"%s\"\n",
 262                        fw_name);
 263                 for (i = 0; i < adev->sdma.num_instances; i++) {
 264                         release_firmware(adev->sdma.instance[i].fw);
 265                         adev->sdma.instance[i].fw = NULL;
 266                 }
 267         }
 268         return err;
 269 }
 270
 271 /**
 272  * sdma_v3_0_ring_get_rptr - get the current read pointer
 273  *
 274  * @ring: amdgpu ring pointer
 275  *
 276  * Get the current rptr from the hardware (VI+).
 277  */
 278 static uint32_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
 279 {
 280         u32 rptr;
 281
 282         /* XXX check if swapping is necessary on BE */
 283         rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2;
 284
 285         return rptr;
 286 }
 287
 288 /**
 289  * sdma_v3_0_ring_get_wptr - get the current write pointer
 290  *
 291  * @ring: amdgpu ring pointer
 292  *
 293  * Get the current wptr from the hardware (VI+).
 294  */
 295 static uint32_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
 296 {
 297         struct amdgpu_device *adev = ring->adev;
 298         u32 wptr;
 299
 300         if (ring->use_doorbell) {
 301                 /* XXX check if swapping is necessary on BE */
 302                 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
 303         } else {
 304                 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
 305
 306                 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
 307         }
 308
 309         return wptr;
 310 }
 311
 312 /**
 313  * sdma_v3_0_ring_set_wptr - commit the write pointer
 314  *
 315  * @ring: amdgpu ring pointer
 316  *
 317  * Write the wptr back to the hardware (VI+).
 318  */
 319 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
 320 {
 321         struct amdgpu_device *adev = ring->adev;
 322
 323         if (ring->use_doorbell) {
 324                 /* XXX check if swapping is necessary on BE */
 325                 adev->wb.wb[ring->wptr_offs] = ring->wptr << 2;
 326                 WDOORBELL32(ring->doorbell_index, ring->wptr << 2);
 327         } else {
 328                 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
 329
 330                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);
 331         }
 332 }
 333
 334 static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 335 {
 336         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 337         int i;
 338
 339         for (i = 0; i < count; i++)
 340                 if (sdma && sdma->burst_nop && (i == 0))
 341                         amdgpu_ring_write(ring, ring->nop |
 342                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 343                 else
 344                         amdgpu_ring_write(ring, ring->nop);
 345 }
 346
 347 /**
 348  * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine
 349  *
 350  * @ring: amdgpu ring pointer
 351  * @ib: IB object to schedule
 352  *
 353  * Schedule an IB in the DMA ring (VI).
 354  */
 355 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
 356                                    struct amdgpu_ib *ib)
 357 {
 358         u32 vmid = ib->vm_id & 0xf;
 359         u32 next_rptr = ring->wptr + 5;
 360
 361         while ((next_rptr & 7) != 2)
 362                 next_rptr++;
 363         next_rptr += 6;
 364
 365         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 366                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 367         amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc);
 368         amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
 369         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
 370         amdgpu_ring_write(ring, next_rptr);
 371
 372         /* IB packet must end on a 8 DW boundary */
 373         sdma_v3_0_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8);
 374
 375         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 376                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
 377         /* base must be 32 byte aligned */
 378         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 379         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 380         amdgpu_ring_write(ring, ib->length_dw);
 381         amdgpu_ring_write(ring, 0);
 382         amdgpu_ring_write(ring, 0);
 383
 384 }
 385
 386 /**
 387  * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 388  *
 389  * @ring: amdgpu ring pointer
 390  *
 391  * Emit an hdp flush packet on the requested DMA ring.
 392  */
 393 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 394 {
 395         u32 ref_and_mask = 0;
 396
 397         if (ring == &ring->adev->sdma.instance[0].ring)
 398                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
 399         else
 400                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
 401
 402         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 403                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 404                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 405         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
 406         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
 407         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 408         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 409         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 410                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 411 }
 412
 413 static void sdma_v3_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
 414 {
 415         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 416                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 417         amdgpu_ring_write(ring, mmHDP_DEBUG0);
 418         amdgpu_ring_write(ring, 1);
 419 }
 420
 421 /**
 422  * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring
 423  *
 424  * @ring: amdgpu ring pointer
 425  * @fence: amdgpu fence object
 426  *
 427  * Add a DMA fence packet to the ring to write
 428  * the fence seq number and DMA trap packet to generate
 429  * an interrupt if needed (VI).
 430  */
 431 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 432                                       unsigned flags)
 433 {
 434         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 435         /* write the fence */
 436         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 437         amdgpu_ring_write(ring, lower_32_bits(addr));
 438         amdgpu_ring_write(ring, upper_32_bits(addr));
 439         amdgpu_ring_write(ring, lower_32_bits(seq));
 440
 441         /* optionally write high bits as well */
 442         if (write64bit) {
 443                 addr += 4;
 444                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 445                 amdgpu_ring_write(ring, lower_32_bits(addr));
 446                 amdgpu_ring_write(ring, upper_32_bits(addr));
 447                 amdgpu_ring_write(ring, upper_32_bits(seq));
 448         }
 449
 450         /* generate an interrupt */
 451         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 452         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 453 }
 454
 455 unsigned init_cond_exec(struct amdgpu_ring *ring)
 456 {
 457         unsigned ret;
 458         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
 459         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
 460         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
 461         amdgpu_ring_write(ring, 1);
 462         ret = ring->wptr;/* this is the offset we need patch later */
 463         amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
 464         return ret;
 465 }
 466
 467 void patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
 468 {
 469         unsigned cur;
 470         BUG_ON(ring->ring[offset] != 0x55aa55aa);
 471
 472         cur = ring->wptr - 1;
 473         if (likely(cur > offset))
 474                 ring->ring[offset] = cur - offset;
 475         else
 476                 ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
 477 }
 478
 479
 480 /**
 481  * sdma_v3_0_gfx_stop - stop the gfx async dma engines
 482  *
 483  * @adev: amdgpu_device pointer
 484  *
 485  * Stop the gfx async dma ring buffers (VI).
 486  */
 487 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev)
 488 {
 489         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 490         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 491         u32 rb_cntl, ib_cntl;
 492         int i;
 493
 494         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 495             (adev->mman.buffer_funcs_ring == sdma1))
 496                 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
 497
 498         for (i = 0; i < adev->sdma.num_instances; i++) {
 499                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 500                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 501                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 502                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 503                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 504                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 505         }
 506         sdma0->ready = false;
 507         sdma1->ready = false;
 508 }
 509
 510 /**
 511  * sdma_v3_0_rlc_stop - stop the compute async dma engines
 512  *
 513  * @adev: amdgpu_device pointer
 514  *
 515  * Stop the compute async dma queues (VI).
 516  */
 517 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev)
 518 {
 519         /* XXX todo */
 520 }
 521
 522 /**
 523  * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch
 524  *
 525  * @adev: amdgpu_device pointer
 526  * @enable: enable/disable the DMA MEs context switch.
 527  *
 528  * Halt or unhalt the async dma engines context switch (VI).
 529  */
 530 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 531 {
 532         u32 f32_cntl;
 533         int i;
 534
 535         for (i = 0; i < adev->sdma.num_instances; i++) {
 536                 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
 537                 if (enable)
 538                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 539                                         AUTO_CTXSW_ENABLE, 1);
 540                 else
 541                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 542                                         AUTO_CTXSW_ENABLE, 0);
 543                 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
 544         }
 545 }
 546
 547 /**
 548  * sdma_v3_0_enable - stop the async dma engines
 549  *
 550  * @adev: amdgpu_device pointer
 551  * @enable: enable/disable the DMA MEs.
 552  *
 553  * Halt or unhalt the async dma engines (VI).
 554  */
 555 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable)
 556 {
 557         u32 f32_cntl;
 558         int i;
 559
 560         if (enable == false) {
 561                 sdma_v3_0_gfx_stop(adev);
 562                 sdma_v3_0_rlc_stop(adev);
 563         }
 564
 565         for (i = 0; i < adev->sdma.num_instances; i++) {
 566                 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
 567                 if (enable)
 568                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
 569                 else
 570                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
 571                 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
 572         }
 573 }
 574
 575 /**
 576  * sdma_v3_0_gfx_resume - setup and start the async dma engines
 577  *
 578  * @adev: amdgpu_device pointer
 579  *
 580  * Set up the gfx DMA ring buffers and enable them (VI).
 581  * Returns 0 for success, error for failure.
 582  */
 583 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
 584 {
 585         struct amdgpu_ring *ring;
 586         u32 rb_cntl, ib_cntl;
 587         u32 rb_bufsz;
 588         u32 wb_offset;
 589         u32 doorbell;
 590         int i, j, r;
 591
 592         for (i = 0; i < adev->sdma.num_instances; i++) {
 593                 ring = &adev->sdma.instance[i].ring;
 594                 wb_offset = (ring->rptr_offs * 4);
 595
 596                 mutex_lock(&adev->srbm_mutex);
 597                 for (j = 0; j < 16; j++) {
 598                         vi_srbm_select(adev, 0, 0, 0, j);
 599                         /* SDMA GFX */
 600                         WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
 601                         WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
 602                 }
 603                 vi_srbm_select(adev, 0, 0, 0, 0);
 604                 mutex_unlock(&adev->srbm_mutex);
 605
 606                 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
 607                        adev->gfx.config.gb_addr_config & 0x70);
 608
 609                 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 610
 611                 /* Set ring buffer size in dwords */
 612                 rb_bufsz = order_base_2(ring->ring_size / 4);
 613                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 614                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 615 #ifdef __BIG_ENDIAN
 616                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 617                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 618                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 619 #endif
 620                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 621
 622                 /* Initialize the ring buffer's read and write pointers */
 623                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
 624                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
 625
 626                 /* set the wb address whether it's enabled or not */
 627                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
 628                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 629                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
 630                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 631
 632                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 633
 634                 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 635                 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 636
 637                 ring->wptr = 0;
 638                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
 639
 640                 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]);
 641
 642                 if (ring->use_doorbell) {
 643                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL,
 644                                                  OFFSET, ring->doorbell_index);
 645                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 646                 } else {
 647                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 648                 }
 649                 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell);
 650
 651                 /* enable DMA RB */
 652                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 653                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 654
 655                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 656                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 657 #ifdef __BIG_ENDIAN
 658                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 659 #endif
 660                 /* enable DMA IBs */
 661                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 662
 663                 ring->ready = true;
 664
 665                 r = amdgpu_ring_test_ring(ring);
 666                 if (r) {
 667                         ring->ready = false;
 668                         return r;
 669                 }
 670
 671                 if (adev->mman.buffer_funcs_ring == ring)
 672                         amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
 673         }
 674
 675         return 0;
 676 }
 677
 678 /**
 679  * sdma_v3_0_rlc_resume - setup and start the async dma engines
 680  *
 681  * @adev: amdgpu_device pointer
 682  *
 683  * Set up the compute DMA queues and enable them (VI).
 684  * Returns 0 for success, error for failure.
 685  */
 686 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev)
 687 {
 688         /* XXX todo */
 689         return 0;
 690 }
 691
 692 /**
 693  * sdma_v3_0_load_microcode - load the sDMA ME ucode
 694  *
 695  * @adev: amdgpu_device pointer
 696  *
 697  * Loads the sDMA0/1 ucode.
 698  * Returns 0 for success, -EINVAL if the ucode is not available.
 699  */
 700 static int sdma_v3_0_load_microcode(struct amdgpu_device *adev)
 701 {
 702         const struct sdma_firmware_header_v1_0 *hdr;
 703         const __le32 *fw_data;
 704         u32 fw_size;
 705         int i, j;
 706
 707         /* halt the MEs */
 708         sdma_v3_0_enable(adev, false);
 709
 710         for (i = 0; i < adev->sdma.num_instances; i++) {
 711                 if (!adev->sdma.instance[i].fw)
 712                         return -EINVAL;
 713                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 714                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 715                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 716                 fw_data = (const __le32 *)
 717                         (adev->sdma.instance[i].fw->data +
 718                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 719                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
 720                 for (j = 0; j < fw_size; j++)
 721                         WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
 722                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
 723         }
 724
 725         return 0;
 726 }
 727
 728 /**
 729  * sdma_v3_0_start - setup and start the async dma engines
 730  *
 731  * @adev: amdgpu_device pointer
 732  *
 733  * Set up the DMA engines and enable them (VI).
 734  * Returns 0 for success, error for failure.
 735  */
 736 static int sdma_v3_0_start(struct amdgpu_device *adev)
 737 {
 738         int r, i;
 739
 740         if (!adev->pp_enabled) {
 741                 if (!adev->firmware.smu_load) {
 742                         r = sdma_v3_0_load_microcode(adev);
 743                         if (r)
 744                                 return r;
 745                 } else {
 746                         for (i = 0; i < adev->sdma.num_instances; i++) {
 747                                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
 748                                                                                  (i == 0) ?
 749                                                                                  AMDGPU_UCODE_ID_SDMA0 :
 750                                                                                  AMDGPU_UCODE_ID_SDMA1);
 751                                 if (r)
 752                                         return -EINVAL;
 753                         }
 754                 }
 755         }
 756
 757         /* unhalt the MEs */
 758         sdma_v3_0_enable(adev, true);
 759         /* enable sdma ring preemption */
 760         sdma_v3_0_ctx_switch_enable(adev, true);
 761
 762         /* start the gfx rings and rlc compute queues */
 763         r = sdma_v3_0_gfx_resume(adev);
 764         if (r)
 765                 return r;
 766         r = sdma_v3_0_rlc_resume(adev);
 767         if (r)
 768                 return r;
 769
 770         return 0;
 771 }
 772
 773 /**
 774  * sdma_v3_0_ring_test_ring - simple async dma engine test
 775  *
 776  * @ring: amdgpu_ring structure holding ring information
 777  *
 778  * Test the DMA engine by writing using it to write an
 779  * value to memory. (VI).
 780  * Returns 0 for success, error for failure.
 781  */
 782 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring)
 783 {
 784         struct amdgpu_device *adev = ring->adev;
 785         unsigned i;
 786         unsigned index;
 787         int r;
 788         u32 tmp;
 789         u64 gpu_addr;
 790
 791         r = amdgpu_wb_get(adev, &index);
 792         if (r) {
 793                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 794                 return r;
 795         }
 796
 797         gpu_addr = adev->wb.gpu_addr + (index * 4);
 798         tmp = 0xCAFEDEAD;
 799         adev->wb.wb[index] = cpu_to_le32(tmp);
 800
 801         r = amdgpu_ring_alloc(ring, 5);
 802         if (r) {
 803                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 804                 amdgpu_wb_free(adev, index);
 805                 return r;
 806         }
 807
 808         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 809                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 810         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 811         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 812         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
 813         amdgpu_ring_write(ring, 0xDEADBEEF);
 814         amdgpu_ring_commit(ring);
 815
 816         for (i = 0; i < adev->usec_timeout; i++) {
 817                 tmp = le32_to_cpu(adev->wb.wb[index]);
 818                 if (tmp == 0xDEADBEEF)
 819                         break;
 820                 DRM_UDELAY(1);
 821         }
 822
 823         if (i < adev->usec_timeout) {
 824                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
 825         } else {
 826                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 827                           ring->idx, tmp);
 828                 r = -EINVAL;
 829         }
 830         amdgpu_wb_free(adev, index);
 831
 832         return r;
 833 }
 834
 835 /**
 836  * sdma_v3_0_ring_test_ib - test an IB on the DMA engine
 837  *
 838  * @ring: amdgpu_ring structure holding ring information
 839  *
 840  * Test a simple IB in the DMA ring (VI).
 841  * Returns 0 on success, error on failure.
 842  */
 843 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring)
 844 {
 845         struct amdgpu_device *adev = ring->adev;
 846         struct amdgpu_ib ib;
 847         struct fence *f = NULL;
 848         unsigned i;
 849         unsigned index;
 850         int r;
 851         u32 tmp = 0;
 852         u64 gpu_addr;
 853
 854         r = amdgpu_wb_get(adev, &index);
 855         if (r) {
 856                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 857                 return r;
 858         }
 859
 860         gpu_addr = adev->wb.gpu_addr + (index * 4);
 861         tmp = 0xCAFEDEAD;
 862         adev->wb.wb[index] = cpu_to_le32(tmp);
 863         memset(&ib, 0, sizeof(ib));
 864         r = amdgpu_ib_get(adev, NULL, 256, &ib);
 865         if (r) {
 866                 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
 867                 goto err0;
 868         }
 869
 870         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 871                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 872         ib.ptr[1] = lower_32_bits(gpu_addr);
 873         ib.ptr[2] = upper_32_bits(gpu_addr);
 874         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
 875         ib.ptr[4] = 0xDEADBEEF;
 876         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 877         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 878         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 879         ib.length_dw = 8;
 880
 881         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 882         if (r)
 883                 goto err1;
 884
 885         r = fence_wait(f, false);
 886         if (r) {
 887                 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
 888                 goto err1;
 889         }
 890         for (i = 0; i < adev->usec_timeout; i++) {
 891                 tmp = le32_to_cpu(adev->wb.wb[index]);
 892                 if (tmp == 0xDEADBEEF)
 893                         break;
 894                 DRM_UDELAY(1);
 895         }
 896         if (i < adev->usec_timeout) {
 897                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
 898                          ring->idx, i);
 899                 goto err1;
 900         } else {
 901                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
 902                 r = -EINVAL;
 903         }
 904 err1:
 905         fence_put(f);
 906         amdgpu_ib_free(adev, &ib, NULL);
 907         fence_put(f);
 908 err0:
 909         amdgpu_wb_free(adev, index);
 910         return r;
 911 }
 912
 913 /**
 914  * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART
 915  *
 916  * @ib: indirect buffer to fill with commands
 917  * @pe: addr of the page entry
 918  * @src: src addr to copy from
 919  * @count: number of page entries to update
 920  *
 921  * Update PTEs by copying them from the GART using sDMA (CIK).
 922  */
 923 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib,
 924                                   uint64_t pe, uint64_t src,
 925                                   unsigned count)
 926 {
 927         while (count) {
 928                 unsigned bytes = count * 8;
 929                 if (bytes > 0x1FFFF8)
 930                         bytes = 0x1FFFF8;
 931
 932                 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
 933                         SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 934                 ib->ptr[ib->length_dw++] = bytes;
 935                 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 936                 ib->ptr[ib->length_dw++] = lower_32_bits(src);
 937                 ib->ptr[ib->length_dw++] = upper_32_bits(src);
 938                 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 939                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 940
 941                 pe += bytes;
 942                 src += bytes;
 943                 count -= bytes / 8;
 944         }
 945 }
 946
 947 /**
 948  * sdma_v3_0_vm_write_pte - update PTEs by writing them manually
 949  *
 950  * @ib: indirect buffer to fill with commands
 951  * @pe: addr of the page entry
 952  * @addr: dst addr to write into pe
 953  * @count: number of page entries to update
 954  * @incr: increase next addr by incr bytes
 955  * @flags: access flags
 956  *
 957  * Update PTEs by writing them manually using sDMA (CIK).
 958  */
 959 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib,
 960                                    const dma_addr_t *pages_addr, uint64_t pe,
 961                                    uint64_t addr, unsigned count,
 962                                    uint32_t incr, uint32_t flags)
 963 {
 964         uint64_t value;
 965         unsigned ndw;
 966
 967         while (count) {
 968                 ndw = count * 2;
 969                 if (ndw > 0xFFFFE)
 970                         ndw = 0xFFFFE;
 971
 972                 /* for non-physically contiguous pages (system) */
 973                 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 974                         SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 975                 ib->ptr[ib->length_dw++] = pe;
 976                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 977                 ib->ptr[ib->length_dw++] = ndw;
 978                 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
 979                         value = amdgpu_vm_map_gart(pages_addr, addr);
 980                         addr += incr;
 981                         value |= flags;
 982                         ib->ptr[ib->length_dw++] = value;
 983                         ib->ptr[ib->length_dw++] = upper_32_bits(value);
 984                 }
 985         }
 986 }
 987
 988 /**
 989  * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA
 990  *
 991  * @ib: indirect buffer to fill with commands
 992  * @pe: addr of the page entry
 993  * @addr: dst addr to write into pe
 994  * @count: number of page entries to update
 995  * @incr: increase next addr by incr bytes
 996  * @flags: access flags
 997  *
 998  * Update the page tables using sDMA (CIK).
 999  */
1000 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1001                                      uint64_t pe,
1002                                      uint64_t addr, unsigned count,
1003                                      uint32_t incr, uint32_t flags)
1004 {
1005         uint64_t value;
1006         unsigned ndw;
1007
1008         while (count) {
1009                 ndw = count;
1010                 if (ndw > 0x7FFFF)
1011                         ndw = 0x7FFFF;
1012
1013                 if (flags & AMDGPU_PTE_VALID)
1014                         value = addr;
1015                 else
1016                         value = 0;
1017
1018                 /* for physically contiguous pages (vram) */
1019                 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
1020                 ib->ptr[ib->length_dw++] = pe; /* dst addr */
1021                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1022                 ib->ptr[ib->length_dw++] = flags; /* mask */
1023                 ib->ptr[ib->length_dw++] = 0;
1024                 ib->ptr[ib->length_dw++] = value; /* value */
1025                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1026                 ib->ptr[ib->length_dw++] = incr; /* increment size */
1027                 ib->ptr[ib->length_dw++] = 0;
1028                 ib->ptr[ib->length_dw++] = ndw; /* number of entries */
1029
1030                 pe += ndw * 8;
1031                 addr += ndw * incr;
1032                 count -= ndw;
1033         }
1034 }
1035
1036 /**
1037  * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw
1038  *
1039  * @ib: indirect buffer to fill with padding
1040  *
1041  */
1042 static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1043 {
1044         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
1045         u32 pad_count;
1046         int i;
1047
1048         pad_count = (8 - (ib->length_dw & 0x7)) % 8;
1049         for (i = 0; i < pad_count; i++)
1050                 if (sdma && sdma->burst_nop && (i == 0))
1051                         ib->ptr[ib->length_dw++] =
1052                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1053                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1054                 else
1055                         ib->ptr[ib->length_dw++] =
1056                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1057 }
1058
1059 /**
1060  * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline
1061  *
1062  * @ring: amdgpu_ring pointer
1063  *
1064  * Make sure all previous operations are completed (CIK).
1065  */
1066 static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1067 {
1068         uint32_t seq = ring->fence_drv.sync_seq;
1069         uint64_t addr = ring->fence_drv.gpu_addr;
1070
1071         /* wait for idle */
1072         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1073                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1074                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1075                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1076         amdgpu_ring_write(ring, addr & 0xfffffffc);
1077         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1078         amdgpu_ring_write(ring, seq); /* reference */
1079         amdgpu_ring_write(ring, 0xfffffff); /* mask */
1080         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1081                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1082 }
1083
1084 /**
1085  * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA
1086  *
1087  * @ring: amdgpu_ring pointer
1088  * @vm: amdgpu_vm pointer
1089  *
1090  * Update the page table base and flush the VM TLB
1091  * using sDMA (VI).
1092  */
1093 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1094                                          unsigned vm_id, uint64_t pd_addr)
1095 {
1096         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1097                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1098         if (vm_id < 8) {
1099                 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
1100         } else {
1101                 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
1102         }
1103         amdgpu_ring_write(ring, pd_addr >> 12);
1104
1105         /* flush TLB */
1106         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1107                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1108         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
1109         amdgpu_ring_write(ring, 1 << vm_id);
1110
1111         /* wait for flush */
1112         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1113                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1114                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
1115         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1116         amdgpu_ring_write(ring, 0);
1117         amdgpu_ring_write(ring, 0); /* reference */
1118         amdgpu_ring_write(ring, 0); /* mask */
1119         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1120                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
1121 }
1122
1123 static int sdma_v3_0_early_init(void *handle)
1124 {
1125         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1126
1127         switch (adev->asic_type) {
1128         case CHIP_STONEY:
1129                 adev->sdma.num_instances = 1;
1130                 break;
1131         default:
1132                 adev->sdma.num_instances = SDMA_MAX_INSTANCE;
1133                 break;
1134         }
1135
1136         sdma_v3_0_set_ring_funcs(adev);
1137         sdma_v3_0_set_buffer_funcs(adev);
1138         sdma_v3_0_set_vm_pte_funcs(adev);
1139         sdma_v3_0_set_irq_funcs(adev);
1140
1141         return 0;
1142 }
1143
1144 static int sdma_v3_0_sw_init(void *handle)
1145 {
1146         struct amdgpu_ring *ring;
1147         int r, i;
1148         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1149
1150         /* SDMA trap event */
1151         r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
1152         if (r)
1153                 return r;
1154
1155         /* SDMA Privileged inst */
1156         r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
1157         if (r)
1158                 return r;
1159
1160         /* SDMA Privileged inst */
1161         r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
1162         if (r)
1163                 return r;
1164
1165         r = sdma_v3_0_init_microcode(adev);
1166         if (r) {
1167                 DRM_ERROR("Failed to load sdma firmware!\n");
1168                 return r;
1169         }
1170
1171         for (i = 0; i < adev->sdma.num_instances; i++) {
1172                 ring = &adev->sdma.instance[i].ring;
1173                 ring->ring_obj = NULL;
1174                 ring->use_doorbell = true;
1175                 ring->doorbell_index = (i == 0) ?
1176                         AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1;
1177
1178                 sprintf(ring->name, "sdma%d", i);
1179                 r = amdgpu_ring_init(adev, ring, 1024,
1180                                      SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
1181                                      &adev->sdma.trap_irq,
1182                                      (i == 0) ?
1183                                      AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1,
1184                                      AMDGPU_RING_TYPE_SDMA);
1185                 if (r)
1186                         return r;
1187         }
1188
1189         return r;
1190 }
1191
1192 static int sdma_v3_0_sw_fini(void *handle)
1193 {
1194         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1195         int i;
1196
1197         for (i = 0; i < adev->sdma.num_instances; i++)
1198                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1199
1200         return 0;
1201 }
1202
1203 static int sdma_v3_0_hw_init(void *handle)
1204 {
1205         int r;
1206         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1207
1208         sdma_v3_0_init_golden_registers(adev);
1209
1210         r = sdma_v3_0_start(adev);
1211         if (r)
1212                 return r;
1213
1214         return r;
1215 }
1216
1217 static int sdma_v3_0_hw_fini(void *handle)
1218 {
1219         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1220
1221         sdma_v3_0_ctx_switch_enable(adev, false);
1222         sdma_v3_0_enable(adev, false);
1223
1224         return 0;
1225 }
1226
1227 static int sdma_v3_0_suspend(void *handle)
1228 {
1229         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1230
1231         return sdma_v3_0_hw_fini(adev);
1232 }
1233
1234 static int sdma_v3_0_resume(void *handle)
1235 {
1236         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1237
1238         return sdma_v3_0_hw_init(adev);
1239 }
1240
1241 static bool sdma_v3_0_is_idle(void *handle)
1242 {
1243         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1244         u32 tmp = RREG32(mmSRBM_STATUS2);
1245
1246         if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1247                    SRBM_STATUS2__SDMA1_BUSY_MASK))
1248             return false;
1249
1250         return true;
1251 }
1252
1253 static int sdma_v3_0_wait_for_idle(void *handle)
1254 {
1255         unsigned i;
1256         u32 tmp;
1257         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1258
1259         for (i = 0; i < adev->usec_timeout; i++) {
1260                 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1261                                 SRBM_STATUS2__SDMA1_BUSY_MASK);
1262
1263                 if (!tmp)
1264                         return 0;
1265                 udelay(1);
1266         }
1267         return -ETIMEDOUT;
1268 }
1269
1270 static void sdma_v3_0_print_status(void *handle)
1271 {
1272         int i, j;
1273         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1274
1275         dev_info(adev->dev, "VI SDMA registers\n");
1276         dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
1277                  RREG32(mmSRBM_STATUS2));
1278         for (i = 0; i < adev->sdma.num_instances; i++) {
1279                 dev_info(adev->dev, "  SDMA%d_STATUS_REG=0x%08X\n",
1280                          i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
1281                 dev_info(adev->dev, "  SDMA%d_F32_CNTL=0x%08X\n",
1282                          i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));
1283                 dev_info(adev->dev, "  SDMA%d_CNTL=0x%08X\n",
1284                          i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));
1285                 dev_info(adev->dev, "  SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
1286                          i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));
1287                 dev_info(adev->dev, "  SDMA%d_GFX_IB_CNTL=0x%08X\n",
1288                          i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));
1289                 dev_info(adev->dev, "  SDMA%d_GFX_RB_CNTL=0x%08X\n",
1290                          i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));
1291                 dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR=0x%08X\n",
1292                          i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));
1293                 dev_info(adev->dev, "  SDMA%d_GFX_RB_WPTR=0x%08X\n",
1294                          i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));
1295                 dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
1296                          i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));
1297                 dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
1298                          i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));
1299                 dev_info(adev->dev, "  SDMA%d_GFX_RB_BASE=0x%08X\n",
1300                          i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
1301                 dev_info(adev->dev, "  SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
1302                          i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
1303                 dev_info(adev->dev, "  SDMA%d_GFX_DOORBELL=0x%08X\n",
1304                          i, RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]));
1305                 dev_info(adev->dev, "  SDMA%d_TILING_CONFIG=0x%08X\n",
1306                          i, RREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i]));
1307                 mutex_lock(&adev->srbm_mutex);
1308                 for (j = 0; j < 16; j++) {
1309                         vi_srbm_select(adev, 0, 0, 0, j);
1310                         dev_info(adev->dev, "  VM %d:\n", j);
1311                         dev_info(adev->dev, "  SDMA%d_GFX_VIRTUAL_ADDR=0x%08X\n",
1312                                  i, RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));
1313                         dev_info(adev->dev, "  SDMA%d_GFX_APE1_CNTL=0x%08X\n",
1314                                  i, RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));
1315                 }
1316                 vi_srbm_select(adev, 0, 0, 0, 0);
1317                 mutex_unlock(&adev->srbm_mutex);
1318         }
1319 }
1320
1321 static int sdma_v3_0_soft_reset(void *handle)
1322 {
1323         u32 srbm_soft_reset = 0;
1324         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1325         u32 tmp = RREG32(mmSRBM_STATUS2);
1326
1327         if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1328                 /* sdma0 */
1329                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1330                 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1331                 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1332                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1333         }
1334         if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1335                 /* sdma1 */
1336                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1337                 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1338                 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1339                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1340         }
1341
1342         if (srbm_soft_reset) {
1343                 sdma_v3_0_print_status((void *)adev);
1344
1345                 tmp = RREG32(mmSRBM_SOFT_RESET);
1346                 tmp |= srbm_soft_reset;
1347                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1348                 WREG32(mmSRBM_SOFT_RESET, tmp);
1349                 tmp = RREG32(mmSRBM_SOFT_RESET);
1350
1351                 udelay(50);
1352
1353                 tmp &= ~srbm_soft_reset;
1354                 WREG32(mmSRBM_SOFT_RESET, tmp);
1355                 tmp = RREG32(mmSRBM_SOFT_RESET);
1356
1357                 /* Wait a little for things to settle down */
1358                 udelay(50);
1359
1360                 sdma_v3_0_print_status((void *)adev);
1361         }
1362
1363         return 0;
1364 }
1365
1366 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev,
1367                                         struct amdgpu_irq_src *source,
1368                                         unsigned type,
1369                                         enum amdgpu_interrupt_state state)
1370 {
1371         u32 sdma_cntl;
1372
1373         switch (type) {
1374         case AMDGPU_SDMA_IRQ_TRAP0:
1375                 switch (state) {
1376                 case AMDGPU_IRQ_STATE_DISABLE:
1377                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1378                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1379                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1380                         break;
1381                 case AMDGPU_IRQ_STATE_ENABLE:
1382                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1383                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1384                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1385                         break;
1386                 default:
1387                         break;
1388                 }
1389                 break;
1390         case AMDGPU_SDMA_IRQ_TRAP1:
1391                 switch (state) {
1392                 case AMDGPU_IRQ_STATE_DISABLE:
1393                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1394                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1395                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1396                         break;
1397                 case AMDGPU_IRQ_STATE_ENABLE:
1398                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1399                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1400                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1401                         break;
1402                 default:
1403                         break;
1404                 }
1405                 break;
1406         default:
1407                 break;
1408         }
1409         return 0;
1410 }
1411
1412 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev,
1413                                       struct amdgpu_irq_src *source,
1414                                       struct amdgpu_iv_entry *entry)
1415 {
1416         u8 instance_id, queue_id;
1417
1418         instance_id = (entry->ring_id & 0x3) >> 0;
1419         queue_id = (entry->ring_id & 0xc) >> 2;
1420         DRM_DEBUG("IH: SDMA trap\n");
1421         switch (instance_id) {
1422         case 0:
1423                 switch (queue_id) {
1424                 case 0:
1425                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1426                         break;
1427                 case 1:
1428                         /* XXX compute */
1429                         break;
1430                 case 2:
1431                         /* XXX compute */
1432                         break;
1433                 }
1434                 break;
1435         case 1:
1436                 switch (queue_id) {
1437                 case 0:
1438                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1439                         break;
1440                 case 1:
1441                         /* XXX compute */
1442                         break;
1443                 case 2:
1444                         /* XXX compute */
1445                         break;
1446                 }
1447                 break;
1448         }
1449         return 0;
1450 }
1451
1452 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1453                                               struct amdgpu_irq_src *source,
1454                                               struct amdgpu_iv_entry *entry)
1455 {
1456         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1457         schedule_work(&adev->reset_work);
1458         return 0;
1459 }
1460
1461 static void sdma_v3_0_update_sdma_medium_grain_clock_gating(
1462                 struct amdgpu_device *adev,
1463                 bool enable)
1464 {
1465         uint32_t temp, data;
1466         int i;
1467
1468         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1469                 for (i = 0; i < adev->sdma.num_instances; i++) {
1470                         temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1471                         data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1472                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1473                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1474                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1475                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1476                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1477                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1478                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1479                         if (data != temp)
1480                                 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1481                 }
1482         } else {
1483                 for (i = 0; i < adev->sdma.num_instances; i++) {
1484                         temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1485                         data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1486                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1487                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1488                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1489                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1490                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1491                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1492                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK;
1493
1494                         if (data != temp)
1495                                 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1496                 }
1497         }
1498 }
1499
1500 static void sdma_v3_0_update_sdma_medium_grain_light_sleep(
1501                 struct amdgpu_device *adev,
1502                 bool enable)
1503 {
1504         uint32_t temp, data;
1505         int i;
1506
1507         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1508                 for (i = 0; i < adev->sdma.num_instances; i++) {
1509                         temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1510                         data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1511
1512                         if (temp != data)
1513                                 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1514                 }
1515         } else {
1516                 for (i = 0; i < adev->sdma.num_instances; i++) {
1517                         temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1518                         data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1519
1520                         if (temp != data)
1521                                 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1522                 }
1523         }
1524 }
1525
1526 static int sdma_v3_0_set_clockgating_state(void *handle,
1527                                           enum amd_clockgating_state state)
1528 {
1529         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1530
1531         switch (adev->asic_type) {
1532         case CHIP_FIJI:
1533         case CHIP_CARRIZO:
1534         case CHIP_STONEY:
1535                 sdma_v3_0_update_sdma_medium_grain_clock_gating(adev,
1536                                 state == AMD_CG_STATE_GATE ? true : false);
1537                 sdma_v3_0_update_sdma_medium_grain_light_sleep(adev,
1538                                 state == AMD_CG_STATE_GATE ? true : false);
1539                 break;
1540         default:
1541                 break;
1542         }
1543         return 0;
1544 }
1545
1546 static int sdma_v3_0_set_powergating_state(void *handle,
1547                                           enum amd_powergating_state state)
1548 {
1549         return 0;
1550 }
1551
1552 const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
1553         .early_init = sdma_v3_0_early_init,
1554         .late_init = NULL,
1555         .sw_init = sdma_v3_0_sw_init,
1556         .sw_fini = sdma_v3_0_sw_fini,
1557         .hw_init = sdma_v3_0_hw_init,
1558         .hw_fini = sdma_v3_0_hw_fini,
1559         .suspend = sdma_v3_0_suspend,
1560         .resume = sdma_v3_0_resume,
1561         .is_idle = sdma_v3_0_is_idle,
1562         .wait_for_idle = sdma_v3_0_wait_for_idle,
1563         .soft_reset = sdma_v3_0_soft_reset,
1564         .print_status = sdma_v3_0_print_status,
1565         .set_clockgating_state = sdma_v3_0_set_clockgating_state,
1566         .set_powergating_state = sdma_v3_0_set_powergating_state,
1567 };
1568
1569 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
1570         .get_rptr = sdma_v3_0_ring_get_rptr,
1571         .get_wptr = sdma_v3_0_ring_get_wptr,
1572         .set_wptr = sdma_v3_0_ring_set_wptr,
1573         .parse_cs = NULL,
1574         .emit_ib = sdma_v3_0_ring_emit_ib,
1575         .emit_fence = sdma_v3_0_ring_emit_fence,
1576         .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync,
1577         .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
1578         .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
1579         .emit_hdp_invalidate = sdma_v3_0_ring_emit_hdp_invalidate,
1580         .test_ring = sdma_v3_0_ring_test_ring,
1581         .test_ib = sdma_v3_0_ring_test_ib,
1582         .insert_nop = sdma_v3_0_ring_insert_nop,
1583         .pad_ib = sdma_v3_0_ring_pad_ib,
1584 };
1585
1586 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
1587 {
1588         int i;
1589
1590         for (i = 0; i < adev->sdma.num_instances; i++)
1591                 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs;
1592 }
1593
1594 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {
1595         .set = sdma_v3_0_set_trap_irq_state,
1596         .process = sdma_v3_0_process_trap_irq,
1597 };
1598
1599 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = {
1600         .process = sdma_v3_0_process_illegal_inst_irq,
1601 };
1602
1603 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev)
1604 {
1605         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1606         adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs;
1607         adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs;
1608 }
1609
1610 /**
1611  * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine
1612  *
1613  * @ring: amdgpu_ring structure holding ring information
1614  * @src_offset: src GPU address
1615  * @dst_offset: dst GPU address
1616  * @byte_count: number of bytes to xfer
1617  *
1618  * Copy GPU buffers using the DMA engine (VI).
1619  * Used by the amdgpu ttm implementation to move pages if
1620  * registered as the asic copy callback.
1621  */
1622 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib,
1623                                        uint64_t src_offset,
1624                                        uint64_t dst_offset,
1625                                        uint32_t byte_count)
1626 {
1627         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1628                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1629         ib->ptr[ib->length_dw++] = byte_count;
1630         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1631         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1632         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1633         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1634         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1635 }
1636
1637 /**
1638  * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine
1639  *
1640  * @ring: amdgpu_ring structure holding ring information
1641  * @src_data: value to write to buffer
1642  * @dst_offset: dst GPU address
1643  * @byte_count: number of bytes to xfer
1644  *
1645  * Fill GPU buffers using the DMA engine (VI).
1646  */
1647 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib,
1648                                        uint32_t src_data,
1649                                        uint64_t dst_offset,
1650                                        uint32_t byte_count)
1651 {
1652         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1653         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1654         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1655         ib->ptr[ib->length_dw++] = src_data;
1656         ib->ptr[ib->length_dw++] = byte_count;
1657 }
1658
1659 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = {
1660         .copy_max_bytes = 0x1fffff,
1661         .copy_num_dw = 7,
1662         .emit_copy_buffer = sdma_v3_0_emit_copy_buffer,
1663
1664         .fill_max_bytes = 0x1fffff,
1665         .fill_num_dw = 5,
1666         .emit_fill_buffer = sdma_v3_0_emit_fill_buffer,
1667 };
1668
1669 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev)
1670 {
1671         if (adev->mman.buffer_funcs == NULL) {
1672                 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs;
1673                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1674         }
1675 }
1676
1677 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
1678         .copy_pte = sdma_v3_0_vm_copy_pte,
1679         .write_pte = sdma_v3_0_vm_write_pte,
1680         .set_pte_pde = sdma_v3_0_vm_set_pte_pde,
1681 };
1682
1683 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1684 {
1685         unsigned i;
1686
1687         if (adev->vm_manager.vm_pte_funcs == NULL) {
1688                 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
1689                 for (i = 0; i < adev->sdma.num_instances; i++)
1690                         adev->vm_manager.vm_pte_rings[i] =
1691                                 &adev->sdma.instance[i].ring;
1692
1693                 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
1694         }
1695 }