drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29 #include "vi.h"
  30 #include "vid.h"
  31
  32 #include "oss/oss_3_0_d.h"
  33 #include "oss/oss_3_0_sh_mask.h"
  34
  35 #include "gmc/gmc_8_1_d.h"
  36 #include "gmc/gmc_8_1_sh_mask.h"
  37
  38 #include "gca/gfx_8_0_d.h"
  39 #include "gca/gfx_8_0_enum.h"
  40 #include "gca/gfx_8_0_sh_mask.h"
  41
  42 #include "bif/bif_5_0_d.h"
  43 #include "bif/bif_5_0_sh_mask.h"
  44
  45 #include "tonga_sdma_pkt_open.h"
  46
  47 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev);
  48 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev);
  49 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  50 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev);
  51
  52 MODULE_FIRMWARE("amdgpu/tonga_sdma.bin");
  53 MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin");
  54 MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin");
  55 MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin");
  56 MODULE_FIRMWARE("amdgpu/fiji_sdma.bin");
  57 MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin");
  58 MODULE_FIRMWARE("amdgpu/stoney_sdma.bin");
  59 MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin");
  60 MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin");
  61 MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin");
  62 MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin");
  63
  64
  65 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  66 {
  67         SDMA0_REGISTER_OFFSET,
  68         SDMA1_REGISTER_OFFSET
  69 };
  70
  71 static const u32 golden_settings_tonga_a11[] =
  72 {
  73         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  74         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
  75         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  76         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  77         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  78         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
  79         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
  80         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  81         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  82         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  83 };
  84
  85 static const u32 tonga_mgcg_cgcg_init[] =
  86 {
  87         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
  88         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
  89 };
  90
  91 static const u32 golden_settings_fiji_a10[] =
  92 {
  93         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  94         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  95         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  96         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  97         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
  98         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  99         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 100         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 101 };
 102
 103 static const u32 fiji_mgcg_cgcg_init[] =
 104 {
 105         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
 106         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
 107 };
 108
 109 static const u32 golden_settings_polaris11_a11[] =
 110 {
 111         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
 112         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
 113         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 114         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 115         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 116         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
 117         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
 118         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 119         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 120         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 121 };
 122
 123 static const u32 golden_settings_polaris10_a11[] =
 124 {
 125         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
 126         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
 127         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 128         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 129         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 130         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
 131         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
 132         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 133         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 134         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 135 };
 136
 137 static const u32 cz_golden_settings_a11[] =
 138 {
 139         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
 140         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
 141         mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
 142         mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
 143         mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
 144         mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
 145         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
 146         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
 147         mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100,
 148         mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800,
 149         mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100,
 150         mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100,
 151 };
 152
 153 static const u32 cz_mgcg_cgcg_init[] =
 154 {
 155         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
 156         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
 157 };
 158
 159 static const u32 stoney_golden_settings_a11[] =
 160 {
 161         mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
 162         mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
 163         mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
 164         mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
 165 };
 166
 167 static const u32 stoney_mgcg_cgcg_init[] =
 168 {
 169         mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100,
 170 };
 171
 172 /*
 173  * sDMA - System DMA
 174  * Starting with CIK, the GPU has new asynchronous
 175  * DMA engines.  These engines are used for compute
 176  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
 177  * and each one supports 1 ring buffer used for gfx
 178  * and 2 queues used for compute.
 179  *
 180  * The programming model is very similar to the CP
 181  * (ring buffer, IBs, etc.), but sDMA has it's own
 182  * packet format that is different from the PM4 format
 183  * used by the CP. sDMA supports copying data, writing
 184  * embedded data, solid fills, and a number of other
 185  * things.  It also has support for tiling/detiling of
 186  * buffers.
 187  */
 188
 189 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
 190 {
 191         switch (adev->asic_type) {
 192         case CHIP_FIJI:
 193                 amdgpu_program_register_sequence(adev,
 194                                                  fiji_mgcg_cgcg_init,
 195                                                  (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
 196                 amdgpu_program_register_sequence(adev,
 197                                                  golden_settings_fiji_a10,
 198                                                  (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
 199                 break;
 200         case CHIP_TONGA:
 201                 amdgpu_program_register_sequence(adev,
 202                                                  tonga_mgcg_cgcg_init,
 203                                                  (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
 204                 amdgpu_program_register_sequence(adev,
 205                                                  golden_settings_tonga_a11,
 206                                                  (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
 207                 break;
 208         case CHIP_POLARIS11:
 209                 amdgpu_program_register_sequence(adev,
 210                                                  golden_settings_polaris11_a11,
 211                                                  (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
 212                 break;
 213         case CHIP_POLARIS10:
 214                 amdgpu_program_register_sequence(adev,
 215                                                  golden_settings_polaris10_a11,
 216                                                  (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
 217                 break;
 218         case CHIP_CARRIZO:
 219                 amdgpu_program_register_sequence(adev,
 220                                                  cz_mgcg_cgcg_init,
 221                                                  (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
 222                 amdgpu_program_register_sequence(adev,
 223                                                  cz_golden_settings_a11,
 224                                                  (const u32)ARRAY_SIZE(cz_golden_settings_a11));
 225                 break;
 226         case CHIP_STONEY:
 227                 amdgpu_program_register_sequence(adev,
 228                                                  stoney_mgcg_cgcg_init,
 229                                                  (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
 230                 amdgpu_program_register_sequence(adev,
 231                                                  stoney_golden_settings_a11,
 232                                                  (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
 233                 break;
 234         default:
 235                 break;
 236         }
 237 }
 238
 239 static void sdma_v3_0_free_microcode(struct amdgpu_device *adev)
 240 {
 241         int i;
 242         for (i = 0; i < adev->sdma.num_instances; i++) {
 243                 release_firmware(adev->sdma.instance[i].fw);
 244                 adev->sdma.instance[i].fw = NULL;
 245         }
 246 }
 247
 248 /**
 249  * sdma_v3_0_init_microcode - load ucode images from disk
 250  *
 251  * @adev: amdgpu_device pointer
 252  *
 253  * Use the firmware interface to load the ucode images into
 254  * the driver (not loaded into hw).
 255  * Returns 0 on success, error on failure.
 256  */
 257 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
 258 {
 259         const char *chip_name;
 260         char fw_name[30];
 261         int err = 0, i;
 262         struct amdgpu_firmware_info *info = NULL;
 263         const struct common_firmware_header *header = NULL;
 264         const struct sdma_firmware_header_v1_0 *hdr;
 265
 266         DRM_DEBUG("\n");
 267
 268         switch (adev->asic_type) {
 269         case CHIP_TONGA:
 270                 chip_name = "tonga";
 271                 break;
 272         case CHIP_FIJI:
 273                 chip_name = "fiji";
 274                 break;
 275         case CHIP_POLARIS11:
 276                 chip_name = "polaris11";
 277                 break;
 278         case CHIP_POLARIS10:
 279                 chip_name = "polaris10";
 280                 break;
 281         case CHIP_CARRIZO:
 282                 chip_name = "carrizo";
 283                 break;
 284         case CHIP_STONEY:
 285                 chip_name = "stoney";
 286                 break;
 287         default: BUG();
 288         }
 289
 290         for (i = 0; i < adev->sdma.num_instances; i++) {
 291                 if (i == 0)
 292                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 293                 else
 294                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
 295                 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 296                 if (err)
 297                         goto out;
 298                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 299                 if (err)
 300                         goto out;
 301                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 302                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 303                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 304                 if (adev->sdma.instance[i].feature_version >= 20)
 305                         adev->sdma.instance[i].burst_nop = true;
 306
 307                 if (adev->firmware.smu_load) {
 308                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 309                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 310                         info->fw = adev->sdma.instance[i].fw;
 311                         header = (const struct common_firmware_header *)info->fw->data;
 312                         adev->firmware.fw_size +=
 313                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 314                 }
 315         }
 316 out:
 317         if (err) {
 318                 printk(KERN_ERR
 319                        "sdma_v3_0: Failed to load firmware \"%s\"\n",
 320                        fw_name);
 321                 for (i = 0; i < adev->sdma.num_instances; i++) {
 322                         release_firmware(adev->sdma.instance[i].fw);
 323                         adev->sdma.instance[i].fw = NULL;
 324                 }
 325         }
 326         return err;
 327 }
 328
 329 /**
 330  * sdma_v3_0_ring_get_rptr - get the current read pointer
 331  *
 332  * @ring: amdgpu ring pointer
 333  *
 334  * Get the current rptr from the hardware (VI+).
 335  */
 336 static uint32_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
 337 {
 338         /* XXX check if swapping is necessary on BE */
 339         return ring->adev->wb.wb[ring->rptr_offs] >> 2;
 340 }
 341
 342 /**
 343  * sdma_v3_0_ring_get_wptr - get the current write pointer
 344  *
 345  * @ring: amdgpu ring pointer
 346  *
 347  * Get the current wptr from the hardware (VI+).
 348  */
 349 static uint32_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
 350 {
 351         struct amdgpu_device *adev = ring->adev;
 352         u32 wptr;
 353
 354         if (ring->use_doorbell) {
 355                 /* XXX check if swapping is necessary on BE */
 356                 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
 357         } else {
 358                 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
 359
 360                 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
 361         }
 362
 363         return wptr;
 364 }
 365
 366 /**
 367  * sdma_v3_0_ring_set_wptr - commit the write pointer
 368  *
 369  * @ring: amdgpu ring pointer
 370  *
 371  * Write the wptr back to the hardware (VI+).
 372  */
 373 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
 374 {
 375         struct amdgpu_device *adev = ring->adev;
 376
 377         if (ring->use_doorbell) {
 378                 /* XXX check if swapping is necessary on BE */
 379                 adev->wb.wb[ring->wptr_offs] = ring->wptr << 2;
 380                 WDOORBELL32(ring->doorbell_index, ring->wptr << 2);
 381         } else {
 382                 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
 383
 384                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);
 385         }
 386 }
 387
 388 static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 389 {
 390         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 391         int i;
 392
 393         for (i = 0; i < count; i++)
 394                 if (sdma && sdma->burst_nop && (i == 0))
 395                         amdgpu_ring_write(ring, ring->nop |
 396                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 397                 else
 398                         amdgpu_ring_write(ring, ring->nop);
 399 }
 400
 401 /**
 402  * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine
 403  *
 404  * @ring: amdgpu ring pointer
 405  * @ib: IB object to schedule
 406  *
 407  * Schedule an IB in the DMA ring (VI).
 408  */
 409 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
 410                                    struct amdgpu_ib *ib,
 411                                    unsigned vm_id, bool ctx_switch)
 412 {
 413         u32 vmid = vm_id & 0xf;
 414
 415         /* IB packet must end on a 8 DW boundary */
 416         sdma_v3_0_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8);
 417
 418         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 419                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
 420         /* base must be 32 byte aligned */
 421         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 422         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 423         amdgpu_ring_write(ring, ib->length_dw);
 424         amdgpu_ring_write(ring, 0);
 425         amdgpu_ring_write(ring, 0);
 426
 427 }
 428
 429 /**
 430  * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 431  *
 432  * @ring: amdgpu ring pointer
 433  *
 434  * Emit an hdp flush packet on the requested DMA ring.
 435  */
 436 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 437 {
 438         u32 ref_and_mask = 0;
 439
 440         if (ring == &ring->adev->sdma.instance[0].ring)
 441                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
 442         else
 443                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
 444
 445         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 446                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 447                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 448         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
 449         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
 450         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 451         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 452         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 453                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 454 }
 455
 456 static void sdma_v3_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
 457 {
 458         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 459                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 460         amdgpu_ring_write(ring, mmHDP_DEBUG0);
 461         amdgpu_ring_write(ring, 1);
 462 }
 463
 464 /**
 465  * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring
 466  *
 467  * @ring: amdgpu ring pointer
 468  * @fence: amdgpu fence object
 469  *
 470  * Add a DMA fence packet to the ring to write
 471  * the fence seq number and DMA trap packet to generate
 472  * an interrupt if needed (VI).
 473  */
 474 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 475                                       unsigned flags)
 476 {
 477         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 478         /* write the fence */
 479         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 480         amdgpu_ring_write(ring, lower_32_bits(addr));
 481         amdgpu_ring_write(ring, upper_32_bits(addr));
 482         amdgpu_ring_write(ring, lower_32_bits(seq));
 483
 484         /* optionally write high bits as well */
 485         if (write64bit) {
 486                 addr += 4;
 487                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 488                 amdgpu_ring_write(ring, lower_32_bits(addr));
 489                 amdgpu_ring_write(ring, upper_32_bits(addr));
 490                 amdgpu_ring_write(ring, upper_32_bits(seq));
 491         }
 492
 493         /* generate an interrupt */
 494         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 495         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 496 }
 497
 498 unsigned init_cond_exec(struct amdgpu_ring *ring)
 499 {
 500         unsigned ret;
 501         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
 502         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
 503         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
 504         amdgpu_ring_write(ring, 1);
 505         ret = ring->wptr;/* this is the offset we need patch later */
 506         amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
 507         return ret;
 508 }
 509
 510 void patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
 511 {
 512         unsigned cur;
 513         BUG_ON(ring->ring[offset] != 0x55aa55aa);
 514
 515         cur = ring->wptr - 1;
 516         if (likely(cur > offset))
 517                 ring->ring[offset] = cur - offset;
 518         else
 519                 ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
 520 }
 521
 522
 523 /**
 524  * sdma_v3_0_gfx_stop - stop the gfx async dma engines
 525  *
 526  * @adev: amdgpu_device pointer
 527  *
 528  * Stop the gfx async dma ring buffers (VI).
 529  */
 530 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev)
 531 {
 532         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 533         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 534         u32 rb_cntl, ib_cntl;
 535         int i;
 536
 537         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 538             (adev->mman.buffer_funcs_ring == sdma1))
 539                 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
 540
 541         for (i = 0; i < adev->sdma.num_instances; i++) {
 542                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 543                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 544                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 545                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 546                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 547                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 548         }
 549         sdma0->ready = false;
 550         sdma1->ready = false;
 551 }
 552
 553 /**
 554  * sdma_v3_0_rlc_stop - stop the compute async dma engines
 555  *
 556  * @adev: amdgpu_device pointer
 557  *
 558  * Stop the compute async dma queues (VI).
 559  */
 560 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev)
 561 {
 562         /* XXX todo */
 563 }
 564
 565 /**
 566  * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch
 567  *
 568  * @adev: amdgpu_device pointer
 569  * @enable: enable/disable the DMA MEs context switch.
 570  *
 571  * Halt or unhalt the async dma engines context switch (VI).
 572  */
 573 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 574 {
 575         u32 f32_cntl;
 576         int i;
 577
 578         for (i = 0; i < adev->sdma.num_instances; i++) {
 579                 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
 580                 if (enable)
 581                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 582                                         AUTO_CTXSW_ENABLE, 1);
 583                 else
 584                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 585                                         AUTO_CTXSW_ENABLE, 0);
 586                 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
 587         }
 588 }
 589
 590 /**
 591  * sdma_v3_0_enable - stop the async dma engines
 592  *
 593  * @adev: amdgpu_device pointer
 594  * @enable: enable/disable the DMA MEs.
 595  *
 596  * Halt or unhalt the async dma engines (VI).
 597  */
 598 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable)
 599 {
 600         u32 f32_cntl;
 601         int i;
 602
 603         if (!enable) {
 604                 sdma_v3_0_gfx_stop(adev);
 605                 sdma_v3_0_rlc_stop(adev);
 606         }
 607
 608         for (i = 0; i < adev->sdma.num_instances; i++) {
 609                 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
 610                 if (enable)
 611                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
 612                 else
 613                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
 614                 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
 615         }
 616 }
 617
 618 /**
 619  * sdma_v3_0_gfx_resume - setup and start the async dma engines
 620  *
 621  * @adev: amdgpu_device pointer
 622  *
 623  * Set up the gfx DMA ring buffers and enable them (VI).
 624  * Returns 0 for success, error for failure.
 625  */
 626 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
 627 {
 628         struct amdgpu_ring *ring;
 629         u32 rb_cntl, ib_cntl;
 630         u32 rb_bufsz;
 631         u32 wb_offset;
 632         u32 doorbell;
 633         int i, j, r;
 634
 635         for (i = 0; i < adev->sdma.num_instances; i++) {
 636                 ring = &adev->sdma.instance[i].ring;
 637                 wb_offset = (ring->rptr_offs * 4);
 638
 639                 mutex_lock(&adev->srbm_mutex);
 640                 for (j = 0; j < 16; j++) {
 641                         vi_srbm_select(adev, 0, 0, 0, j);
 642                         /* SDMA GFX */
 643                         WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
 644                         WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
 645                 }
 646                 vi_srbm_select(adev, 0, 0, 0, 0);
 647                 mutex_unlock(&adev->srbm_mutex);
 648
 649                 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
 650                        adev->gfx.config.gb_addr_config & 0x70);
 651
 652                 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 653
 654                 /* Set ring buffer size in dwords */
 655                 rb_bufsz = order_base_2(ring->ring_size / 4);
 656                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 657                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 658 #ifdef __BIG_ENDIAN
 659                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 660                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 661                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 662 #endif
 663                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 664
 665                 /* Initialize the ring buffer's read and write pointers */
 666                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
 667                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
 668                 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
 669                 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
 670
 671                 /* set the wb address whether it's enabled or not */
 672                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
 673                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 674                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
 675                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 676
 677                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 678
 679                 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 680                 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 681
 682                 ring->wptr = 0;
 683                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
 684
 685                 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]);
 686
 687                 if (ring->use_doorbell) {
 688                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL,
 689                                                  OFFSET, ring->doorbell_index);
 690                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 691                 } else {
 692                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 693                 }
 694                 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell);
 695
 696                 /* enable DMA RB */
 697                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 698                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 699
 700                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 701                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 702 #ifdef __BIG_ENDIAN
 703                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 704 #endif
 705                 /* enable DMA IBs */
 706                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 707
 708                 ring->ready = true;
 709         }
 710
 711         /* unhalt the MEs */
 712         sdma_v3_0_enable(adev, true);
 713         /* enable sdma ring preemption */
 714         sdma_v3_0_ctx_switch_enable(adev, true);
 715
 716         for (i = 0; i < adev->sdma.num_instances; i++) {
 717                 ring = &adev->sdma.instance[i].ring;
 718                 r = amdgpu_ring_test_ring(ring);
 719                 if (r) {
 720                         ring->ready = false;
 721                         return r;
 722                 }
 723
 724                 if (adev->mman.buffer_funcs_ring == ring)
 725                         amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
 726         }
 727
 728         return 0;
 729 }
 730
 731 /**
 732  * sdma_v3_0_rlc_resume - setup and start the async dma engines
 733  *
 734  * @adev: amdgpu_device pointer
 735  *
 736  * Set up the compute DMA queues and enable them (VI).
 737  * Returns 0 for success, error for failure.
 738  */
 739 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev)
 740 {
 741         /* XXX todo */
 742         return 0;
 743 }
 744
 745 /**
 746  * sdma_v3_0_load_microcode - load the sDMA ME ucode
 747  *
 748  * @adev: amdgpu_device pointer
 749  *
 750  * Loads the sDMA0/1 ucode.
 751  * Returns 0 for success, -EINVAL if the ucode is not available.
 752  */
 753 static int sdma_v3_0_load_microcode(struct amdgpu_device *adev)
 754 {
 755         const struct sdma_firmware_header_v1_0 *hdr;
 756         const __le32 *fw_data;
 757         u32 fw_size;
 758         int i, j;
 759
 760         /* halt the MEs */
 761         sdma_v3_0_enable(adev, false);
 762
 763         for (i = 0; i < adev->sdma.num_instances; i++) {
 764                 if (!adev->sdma.instance[i].fw)
 765                         return -EINVAL;
 766                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 767                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 768                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 769                 fw_data = (const __le32 *)
 770                         (adev->sdma.instance[i].fw->data +
 771                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 772                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
 773                 for (j = 0; j < fw_size; j++)
 774                         WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
 775                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
 776         }
 777
 778         return 0;
 779 }
 780
 781 /**
 782  * sdma_v3_0_start - setup and start the async dma engines
 783  *
 784  * @adev: amdgpu_device pointer
 785  *
 786  * Set up the DMA engines and enable them (VI).
 787  * Returns 0 for success, error for failure.
 788  */
 789 static int sdma_v3_0_start(struct amdgpu_device *adev)
 790 {
 791         int r, i;
 792
 793         if (!adev->pp_enabled) {
 794                 if (!adev->firmware.smu_load) {
 795                         r = sdma_v3_0_load_microcode(adev);
 796                         if (r)
 797                                 return r;
 798                 } else {
 799                         for (i = 0; i < adev->sdma.num_instances; i++) {
 800                                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
 801                                                                                  (i == 0) ?
 802                                                                                  AMDGPU_UCODE_ID_SDMA0 :
 803                                                                                  AMDGPU_UCODE_ID_SDMA1);
 804                                 if (r)
 805                                         return -EINVAL;
 806                         }
 807                 }
 808         }
 809
 810         /* disble sdma engine before programing it */
 811         sdma_v3_0_ctx_switch_enable(adev, false);
 812         sdma_v3_0_enable(adev, false);
 813
 814         /* start the gfx rings and rlc compute queues */
 815         r = sdma_v3_0_gfx_resume(adev);
 816         if (r)
 817                 return r;
 818         r = sdma_v3_0_rlc_resume(adev);
 819         if (r)
 820                 return r;
 821
 822         return 0;
 823 }
 824
 825 /**
 826  * sdma_v3_0_ring_test_ring - simple async dma engine test
 827  *
 828  * @ring: amdgpu_ring structure holding ring information
 829  *
 830  * Test the DMA engine by writing using it to write an
 831  * value to memory. (VI).
 832  * Returns 0 for success, error for failure.
 833  */
 834 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring)
 835 {
 836         struct amdgpu_device *adev = ring->adev;
 837         unsigned i;
 838         unsigned index;
 839         int r;
 840         u32 tmp;
 841         u64 gpu_addr;
 842
 843         r = amdgpu_wb_get(adev, &index);
 844         if (r) {
 845                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 846                 return r;
 847         }
 848
 849         gpu_addr = adev->wb.gpu_addr + (index * 4);
 850         tmp = 0xCAFEDEAD;
 851         adev->wb.wb[index] = cpu_to_le32(tmp);
 852
 853         r = amdgpu_ring_alloc(ring, 5);
 854         if (r) {
 855                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 856                 amdgpu_wb_free(adev, index);
 857                 return r;
 858         }
 859
 860         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 861                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 862         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 863         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 864         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
 865         amdgpu_ring_write(ring, 0xDEADBEEF);
 866         amdgpu_ring_commit(ring);
 867
 868         for (i = 0; i < adev->usec_timeout; i++) {
 869                 tmp = le32_to_cpu(adev->wb.wb[index]);
 870                 if (tmp == 0xDEADBEEF)
 871                         break;
 872                 DRM_UDELAY(1);
 873         }
 874
 875         if (i < adev->usec_timeout) {
 876                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
 877         } else {
 878                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 879                           ring->idx, tmp);
 880                 r = -EINVAL;
 881         }
 882         amdgpu_wb_free(adev, index);
 883
 884         return r;
 885 }
 886
 887 /**
 888  * sdma_v3_0_ring_test_ib - test an IB on the DMA engine
 889  *
 890  * @ring: amdgpu_ring structure holding ring information
 891  *
 892  * Test a simple IB in the DMA ring (VI).
 893  * Returns 0 on success, error on failure.
 894  */
 895 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 896 {
 897         struct amdgpu_device *adev = ring->adev;
 898         struct amdgpu_ib ib;
 899         struct fence *f = NULL;
 900         unsigned index;
 901         u32 tmp = 0;
 902         u64 gpu_addr;
 903         long r;
 904
 905         r = amdgpu_wb_get(adev, &index);
 906         if (r) {
 907                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 908                 return r;
 909         }
 910
 911         gpu_addr = adev->wb.gpu_addr + (index * 4);
 912         tmp = 0xCAFEDEAD;
 913         adev->wb.wb[index] = cpu_to_le32(tmp);
 914         memset(&ib, 0, sizeof(ib));
 915         r = amdgpu_ib_get(adev, NULL, 256, &ib);
 916         if (r) {
 917                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 918                 goto err0;
 919         }
 920
 921         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 922                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 923         ib.ptr[1] = lower_32_bits(gpu_addr);
 924         ib.ptr[2] = upper_32_bits(gpu_addr);
 925         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
 926         ib.ptr[4] = 0xDEADBEEF;
 927         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 928         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 929         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 930         ib.length_dw = 8;
 931
 932         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
 933         if (r)
 934                 goto err1;
 935
 936         r = fence_wait_timeout(f, false, timeout);
 937         if (r == 0) {
 938                 DRM_ERROR("amdgpu: IB test timed out\n");
 939                 r = -ETIMEDOUT;
 940                 goto err1;
 941         } else if (r < 0) {
 942                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 943                 goto err1;
 944         }
 945         tmp = le32_to_cpu(adev->wb.wb[index]);
 946         if (tmp == 0xDEADBEEF) {
 947                 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
 948                 r = 0;
 949         } else {
 950                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
 951                 r = -EINVAL;
 952         }
 953 err1:
 954         amdgpu_ib_free(adev, &ib, NULL);
 955         fence_put(f);
 956 err0:
 957         amdgpu_wb_free(adev, index);
 958         return r;
 959 }
 960
 961 /**
 962  * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART
 963  *
 964  * @ib: indirect buffer to fill with commands
 965  * @pe: addr of the page entry
 966  * @src: src addr to copy from
 967  * @count: number of page entries to update
 968  *
 969  * Update PTEs by copying them from the GART using sDMA (CIK).
 970  */
 971 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib,
 972                                   uint64_t pe, uint64_t src,
 973                                   unsigned count)
 974 {
 975         unsigned bytes = count * 8;
 976
 977         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
 978                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 979         ib->ptr[ib->length_dw++] = bytes;
 980         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 981         ib->ptr[ib->length_dw++] = lower_32_bits(src);
 982         ib->ptr[ib->length_dw++] = upper_32_bits(src);
 983         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 984         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 985 }
 986
 987 /**
 988  * sdma_v3_0_vm_write_pte - update PTEs by writing them manually
 989  *
 990  * @ib: indirect buffer to fill with commands
 991  * @pe: addr of the page entry
 992  * @value: dst addr to write into pe
 993  * @count: number of page entries to update
 994  * @incr: increase next addr by incr bytes
 995  *
 996  * Update PTEs by writing them manually using sDMA (CIK).
 997  */
 998 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
 999                                    uint64_t value, unsigned count,
1000                                    uint32_t incr)
1001 {
1002         unsigned ndw = count * 2;
1003
1004         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1005                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1006         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1007         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1008         ib->ptr[ib->length_dw++] = ndw;
1009         for (; ndw > 0; ndw -= 2, --count, pe += 8) {
1010                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1011                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1012                 value += incr;
1013         }
1014 }
1015
1016 /**
1017  * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA
1018  *
1019  * @ib: indirect buffer to fill with commands
1020  * @pe: addr of the page entry
1021  * @addr: dst addr to write into pe
1022  * @count: number of page entries to update
1023  * @incr: increase next addr by incr bytes
1024  * @flags: access flags
1025  *
1026  * Update the page tables using sDMA (CIK).
1027  */
1028 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
1029                                      uint64_t addr, unsigned count,
1030                                      uint32_t incr, uint32_t flags)
1031 {
1032         /* for physically contiguous pages (vram) */
1033         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
1034         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1035         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1036         ib->ptr[ib->length_dw++] = flags; /* mask */
1037         ib->ptr[ib->length_dw++] = 0;
1038         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1039         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1040         ib->ptr[ib->length_dw++] = incr; /* increment size */
1041         ib->ptr[ib->length_dw++] = 0;
1042         ib->ptr[ib->length_dw++] = count; /* number of entries */
1043 }
1044
1045 /**
1046  * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw
1047  *
1048  * @ib: indirect buffer to fill with padding
1049  *
1050  */
1051 static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1052 {
1053         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
1054         u32 pad_count;
1055         int i;
1056
1057         pad_count = (8 - (ib->length_dw & 0x7)) % 8;
1058         for (i = 0; i < pad_count; i++)
1059                 if (sdma && sdma->burst_nop && (i == 0))
1060                         ib->ptr[ib->length_dw++] =
1061                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1062                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1063                 else
1064                         ib->ptr[ib->length_dw++] =
1065                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1066 }
1067
1068 /**
1069  * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline
1070  *
1071  * @ring: amdgpu_ring pointer
1072  *
1073  * Make sure all previous operations are completed (CIK).
1074  */
1075 static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1076 {
1077         uint32_t seq = ring->fence_drv.sync_seq;
1078         uint64_t addr = ring->fence_drv.gpu_addr;
1079
1080         /* wait for idle */
1081         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1082                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1083                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1084                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1085         amdgpu_ring_write(ring, addr & 0xfffffffc);
1086         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1087         amdgpu_ring_write(ring, seq); /* reference */
1088         amdgpu_ring_write(ring, 0xfffffff); /* mask */
1089         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1090                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1091 }
1092
1093 /**
1094  * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA
1095  *
1096  * @ring: amdgpu_ring pointer
1097  * @vm: amdgpu_vm pointer
1098  *
1099  * Update the page table base and flush the VM TLB
1100  * using sDMA (VI).
1101  */
1102 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1103                                          unsigned vm_id, uint64_t pd_addr)
1104 {
1105         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1106                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1107         if (vm_id < 8) {
1108                 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
1109         } else {
1110                 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
1111         }
1112         amdgpu_ring_write(ring, pd_addr >> 12);
1113
1114         /* flush TLB */
1115         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1116                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1117         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
1118         amdgpu_ring_write(ring, 1 << vm_id);
1119
1120         /* wait for flush */
1121         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1122                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1123                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
1124         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1125         amdgpu_ring_write(ring, 0);
1126         amdgpu_ring_write(ring, 0); /* reference */
1127         amdgpu_ring_write(ring, 0); /* mask */
1128         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1129                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
1130 }
1131
1132 static int sdma_v3_0_early_init(void *handle)
1133 {
1134         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1135
1136         switch (adev->asic_type) {
1137         case CHIP_STONEY:
1138                 adev->sdma.num_instances = 1;
1139                 break;
1140         default:
1141                 adev->sdma.num_instances = SDMA_MAX_INSTANCE;
1142                 break;
1143         }
1144
1145         sdma_v3_0_set_ring_funcs(adev);
1146         sdma_v3_0_set_buffer_funcs(adev);
1147         sdma_v3_0_set_vm_pte_funcs(adev);
1148         sdma_v3_0_set_irq_funcs(adev);
1149
1150         return 0;
1151 }
1152
1153 static int sdma_v3_0_sw_init(void *handle)
1154 {
1155         struct amdgpu_ring *ring;
1156         int r, i;
1157         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1158
1159         /* SDMA trap event */
1160         r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
1161         if (r)
1162                 return r;
1163
1164         /* SDMA Privileged inst */
1165         r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
1166         if (r)
1167                 return r;
1168
1169         /* SDMA Privileged inst */
1170         r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
1171         if (r)
1172                 return r;
1173
1174         r = sdma_v3_0_init_microcode(adev);
1175         if (r) {
1176                 DRM_ERROR("Failed to load sdma firmware!\n");
1177                 return r;
1178         }
1179
1180         for (i = 0; i < adev->sdma.num_instances; i++) {
1181                 ring = &adev->sdma.instance[i].ring;
1182                 ring->ring_obj = NULL;
1183                 ring->use_doorbell = true;
1184                 ring->doorbell_index = (i == 0) ?
1185                         AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1;
1186
1187                 sprintf(ring->name, "sdma%d", i);
1188                 r = amdgpu_ring_init(adev, ring, 1024,
1189                                      SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
1190                                      &adev->sdma.trap_irq,
1191                                      (i == 0) ?
1192                                      AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1,
1193                                      AMDGPU_RING_TYPE_SDMA);
1194                 if (r)
1195                         return r;
1196         }
1197
1198         return r;
1199 }
1200
1201 static int sdma_v3_0_sw_fini(void *handle)
1202 {
1203         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1204         int i;
1205
1206         for (i = 0; i < adev->sdma.num_instances; i++)
1207                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1208
1209         sdma_v3_0_free_microcode(adev);
1210         return 0;
1211 }
1212
1213 static int sdma_v3_0_hw_init(void *handle)
1214 {
1215         int r;
1216         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1217
1218         sdma_v3_0_init_golden_registers(adev);
1219
1220         r = sdma_v3_0_start(adev);
1221         if (r)
1222                 return r;
1223
1224         return r;
1225 }
1226
1227 static int sdma_v3_0_hw_fini(void *handle)
1228 {
1229         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1230
1231         sdma_v3_0_ctx_switch_enable(adev, false);
1232         sdma_v3_0_enable(adev, false);
1233
1234         return 0;
1235 }
1236
1237 static int sdma_v3_0_suspend(void *handle)
1238 {
1239         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1240
1241         return sdma_v3_0_hw_fini(adev);
1242 }
1243
1244 static int sdma_v3_0_resume(void *handle)
1245 {
1246         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1247
1248         return sdma_v3_0_hw_init(adev);
1249 }
1250
1251 static bool sdma_v3_0_is_idle(void *handle)
1252 {
1253         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1254         u32 tmp = RREG32(mmSRBM_STATUS2);
1255
1256         if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1257                    SRBM_STATUS2__SDMA1_BUSY_MASK))
1258             return false;
1259
1260         return true;
1261 }
1262
1263 static int sdma_v3_0_wait_for_idle(void *handle)
1264 {
1265         unsigned i;
1266         u32 tmp;
1267         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1268
1269         for (i = 0; i < adev->usec_timeout; i++) {
1270                 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1271                                 SRBM_STATUS2__SDMA1_BUSY_MASK);
1272
1273                 if (!tmp)
1274                         return 0;
1275                 udelay(1);
1276         }
1277         return -ETIMEDOUT;
1278 }
1279
1280 static int sdma_v3_0_check_soft_reset(void *handle)
1281 {
1282         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1283         u32 srbm_soft_reset = 0;
1284         u32 tmp = RREG32(mmSRBM_STATUS2);
1285
1286         if ((tmp & SRBM_STATUS2__SDMA_BUSY_MASK) ||
1287             (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)) {
1288                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1289                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1290         }
1291
1292         if (srbm_soft_reset) {
1293                 adev->ip_block_status[AMD_IP_BLOCK_TYPE_SDMA].hang = true;
1294                 adev->sdma.srbm_soft_reset = srbm_soft_reset;
1295         } else {
1296                 adev->ip_block_status[AMD_IP_BLOCK_TYPE_SDMA].hang = false;
1297                 adev->sdma.srbm_soft_reset = 0;
1298         }
1299
1300         return 0;
1301 }
1302
1303 static int sdma_v3_0_pre_soft_reset(void *handle)
1304 {
1305         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1306         u32 srbm_soft_reset = 0;
1307
1308         if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_SDMA].hang)
1309                 return 0;
1310
1311         srbm_soft_reset = adev->sdma.srbm_soft_reset;
1312
1313         if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
1314             REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
1315                 sdma_v3_0_ctx_switch_enable(adev, false);
1316                 sdma_v3_0_enable(adev, false);
1317         }
1318
1319         return 0;
1320 }
1321
1322 static int sdma_v3_0_post_soft_reset(void *handle)
1323 {
1324         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1325         u32 srbm_soft_reset = 0;
1326
1327         if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_SDMA].hang)
1328                 return 0;
1329
1330         srbm_soft_reset = adev->sdma.srbm_soft_reset;
1331
1332         if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
1333             REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
1334                 sdma_v3_0_gfx_resume(adev);
1335                 sdma_v3_0_rlc_resume(adev);
1336         }
1337
1338         return 0;
1339 }
1340
1341 static int sdma_v3_0_soft_reset(void *handle)
1342 {
1343         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1344         u32 srbm_soft_reset = 0;
1345         u32 tmp;
1346
1347         if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_SDMA].hang)
1348                 return 0;
1349
1350         srbm_soft_reset = adev->sdma.srbm_soft_reset;
1351
1352         if (srbm_soft_reset) {
1353                 tmp = RREG32(mmSRBM_SOFT_RESET);
1354                 tmp |= srbm_soft_reset;
1355                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1356                 WREG32(mmSRBM_SOFT_RESET, tmp);
1357                 tmp = RREG32(mmSRBM_SOFT_RESET);
1358
1359                 udelay(50);
1360
1361                 tmp &= ~srbm_soft_reset;
1362                 WREG32(mmSRBM_SOFT_RESET, tmp);
1363                 tmp = RREG32(mmSRBM_SOFT_RESET);
1364
1365                 /* Wait a little for things to settle down */
1366                 udelay(50);
1367         }
1368
1369         return 0;
1370 }
1371
1372 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev,
1373                                         struct amdgpu_irq_src *source,
1374                                         unsigned type,
1375                                         enum amdgpu_interrupt_state state)
1376 {
1377         u32 sdma_cntl;
1378
1379         switch (type) {
1380         case AMDGPU_SDMA_IRQ_TRAP0:
1381                 switch (state) {
1382                 case AMDGPU_IRQ_STATE_DISABLE:
1383                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1384                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1385                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1386                         break;
1387                 case AMDGPU_IRQ_STATE_ENABLE:
1388                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1389                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1390                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1391                         break;
1392                 default:
1393                         break;
1394                 }
1395                 break;
1396         case AMDGPU_SDMA_IRQ_TRAP1:
1397                 switch (state) {
1398                 case AMDGPU_IRQ_STATE_DISABLE:
1399                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1400                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1401                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1402                         break;
1403                 case AMDGPU_IRQ_STATE_ENABLE:
1404                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1405                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1406                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1407                         break;
1408                 default:
1409                         break;
1410                 }
1411                 break;
1412         default:
1413                 break;
1414         }
1415         return 0;
1416 }
1417
1418 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev,
1419                                       struct amdgpu_irq_src *source,
1420                                       struct amdgpu_iv_entry *entry)
1421 {
1422         u8 instance_id, queue_id;
1423
1424         instance_id = (entry->ring_id & 0x3) >> 0;
1425         queue_id = (entry->ring_id & 0xc) >> 2;
1426         DRM_DEBUG("IH: SDMA trap\n");
1427         switch (instance_id) {
1428         case 0:
1429                 switch (queue_id) {
1430                 case 0:
1431                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1432                         break;
1433                 case 1:
1434                         /* XXX compute */
1435                         break;
1436                 case 2:
1437                         /* XXX compute */
1438                         break;
1439                 }
1440                 break;
1441         case 1:
1442                 switch (queue_id) {
1443                 case 0:
1444                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1445                         break;
1446                 case 1:
1447                         /* XXX compute */
1448                         break;
1449                 case 2:
1450                         /* XXX compute */
1451                         break;
1452                 }
1453                 break;
1454         }
1455         return 0;
1456 }
1457
1458 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1459                                               struct amdgpu_irq_src *source,
1460                                               struct amdgpu_iv_entry *entry)
1461 {
1462         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1463         schedule_work(&adev->reset_work);
1464         return 0;
1465 }
1466
1467 static void sdma_v3_0_update_sdma_medium_grain_clock_gating(
1468                 struct amdgpu_device *adev,
1469                 bool enable)
1470 {
1471         uint32_t temp, data;
1472         int i;
1473
1474         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1475                 for (i = 0; i < adev->sdma.num_instances; i++) {
1476                         temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1477                         data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1478                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1479                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1480                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1481                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1482                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1483                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1484                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1485                         if (data != temp)
1486                                 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1487                 }
1488         } else {
1489                 for (i = 0; i < adev->sdma.num_instances; i++) {
1490                         temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1491                         data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1492                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1493                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1494                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1495                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1496                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1497                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1498                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK;
1499
1500                         if (data != temp)
1501                                 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1502                 }
1503         }
1504 }
1505
1506 static void sdma_v3_0_update_sdma_medium_grain_light_sleep(
1507                 struct amdgpu_device *adev,
1508                 bool enable)
1509 {
1510         uint32_t temp, data;
1511         int i;
1512
1513         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1514                 for (i = 0; i < adev->sdma.num_instances; i++) {
1515                         temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1516                         data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1517
1518                         if (temp != data)
1519                                 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1520                 }
1521         } else {
1522                 for (i = 0; i < adev->sdma.num_instances; i++) {
1523                         temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1524                         data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1525
1526                         if (temp != data)
1527                                 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1528                 }
1529         }
1530 }
1531
1532 static int sdma_v3_0_set_clockgating_state(void *handle,
1533                                           enum amd_clockgating_state state)
1534 {
1535         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1536
1537         switch (adev->asic_type) {
1538         case CHIP_FIJI:
1539         case CHIP_CARRIZO:
1540         case CHIP_STONEY:
1541                 sdma_v3_0_update_sdma_medium_grain_clock_gating(adev,
1542                                 state == AMD_CG_STATE_GATE ? true : false);
1543                 sdma_v3_0_update_sdma_medium_grain_light_sleep(adev,
1544                                 state == AMD_CG_STATE_GATE ? true : false);
1545                 break;
1546         default:
1547                 break;
1548         }
1549         return 0;
1550 }
1551
1552 static int sdma_v3_0_set_powergating_state(void *handle,
1553                                           enum amd_powergating_state state)
1554 {
1555         return 0;
1556 }
1557
1558 const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
1559         .name = "sdma_v3_0",
1560         .early_init = sdma_v3_0_early_init,
1561         .late_init = NULL,
1562         .sw_init = sdma_v3_0_sw_init,
1563         .sw_fini = sdma_v3_0_sw_fini,
1564         .hw_init = sdma_v3_0_hw_init,
1565         .hw_fini = sdma_v3_0_hw_fini,
1566         .suspend = sdma_v3_0_suspend,
1567         .resume = sdma_v3_0_resume,
1568         .is_idle = sdma_v3_0_is_idle,
1569         .wait_for_idle = sdma_v3_0_wait_for_idle,
1570         .check_soft_reset = sdma_v3_0_check_soft_reset,
1571         .pre_soft_reset = sdma_v3_0_pre_soft_reset,
1572         .post_soft_reset = sdma_v3_0_post_soft_reset,
1573         .soft_reset = sdma_v3_0_soft_reset,
1574         .set_clockgating_state = sdma_v3_0_set_clockgating_state,
1575         .set_powergating_state = sdma_v3_0_set_powergating_state,
1576 };
1577
1578 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
1579         .get_rptr = sdma_v3_0_ring_get_rptr,
1580         .get_wptr = sdma_v3_0_ring_get_wptr,
1581         .set_wptr = sdma_v3_0_ring_set_wptr,
1582         .parse_cs = NULL,
1583         .emit_ib = sdma_v3_0_ring_emit_ib,
1584         .emit_fence = sdma_v3_0_ring_emit_fence,
1585         .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync,
1586         .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
1587         .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
1588         .emit_hdp_invalidate = sdma_v3_0_ring_emit_hdp_invalidate,
1589         .test_ring = sdma_v3_0_ring_test_ring,
1590         .test_ib = sdma_v3_0_ring_test_ib,
1591         .insert_nop = sdma_v3_0_ring_insert_nop,
1592         .pad_ib = sdma_v3_0_ring_pad_ib,
1593 };
1594
1595 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
1596 {
1597         int i;
1598
1599         for (i = 0; i < adev->sdma.num_instances; i++)
1600                 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs;
1601 }
1602
1603 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {
1604         .set = sdma_v3_0_set_trap_irq_state,
1605         .process = sdma_v3_0_process_trap_irq,
1606 };
1607
1608 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = {
1609         .process = sdma_v3_0_process_illegal_inst_irq,
1610 };
1611
1612 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev)
1613 {
1614         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1615         adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs;
1616         adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs;
1617 }
1618
1619 /**
1620  * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine
1621  *
1622  * @ring: amdgpu_ring structure holding ring information
1623  * @src_offset: src GPU address
1624  * @dst_offset: dst GPU address
1625  * @byte_count: number of bytes to xfer
1626  *
1627  * Copy GPU buffers using the DMA engine (VI).
1628  * Used by the amdgpu ttm implementation to move pages if
1629  * registered as the asic copy callback.
1630  */
1631 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib,
1632                                        uint64_t src_offset,
1633                                        uint64_t dst_offset,
1634                                        uint32_t byte_count)
1635 {
1636         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1637                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1638         ib->ptr[ib->length_dw++] = byte_count;
1639         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1640         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1641         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1642         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1643         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1644 }
1645
1646 /**
1647  * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine
1648  *
1649  * @ring: amdgpu_ring structure holding ring information
1650  * @src_data: value to write to buffer
1651  * @dst_offset: dst GPU address
1652  * @byte_count: number of bytes to xfer
1653  *
1654  * Fill GPU buffers using the DMA engine (VI).
1655  */
1656 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib,
1657                                        uint32_t src_data,
1658                                        uint64_t dst_offset,
1659                                        uint32_t byte_count)
1660 {
1661         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1662         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1663         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1664         ib->ptr[ib->length_dw++] = src_data;
1665         ib->ptr[ib->length_dw++] = byte_count;
1666 }
1667
1668 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = {
1669         .copy_max_bytes = 0x1fffff,
1670         .copy_num_dw = 7,
1671         .emit_copy_buffer = sdma_v3_0_emit_copy_buffer,
1672
1673         .fill_max_bytes = 0x1fffff,
1674         .fill_num_dw = 5,
1675         .emit_fill_buffer = sdma_v3_0_emit_fill_buffer,
1676 };
1677
1678 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev)
1679 {
1680         if (adev->mman.buffer_funcs == NULL) {
1681                 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs;
1682                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1683         }
1684 }
1685
1686 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
1687         .copy_pte = sdma_v3_0_vm_copy_pte,
1688         .write_pte = sdma_v3_0_vm_write_pte,
1689         .set_pte_pde = sdma_v3_0_vm_set_pte_pde,
1690 };
1691
1692 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1693 {
1694         unsigned i;
1695
1696         if (adev->vm_manager.vm_pte_funcs == NULL) {
1697                 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
1698                 for (i = 0; i < adev->sdma.num_instances; i++)
1699                         adev->vm_manager.vm_pte_rings[i] =
1700                                 &adev->sdma.instance[i].ring;
1701
1702                 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
1703         }
1704 }