drivers/gpu/drm/amd/amdgpu/si.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/slab.h>
  26 #include <linux/module.h>
  27 #include "drmP.h"
  28 #include "amdgpu.h"
  29 #include "amdgpu_atombios.h"
  30 #include "amdgpu_ih.h"
  31 #include "amdgpu_uvd.h"
  32 #include "amdgpu_vce.h"
  33 #include "atom.h"
  34 #include "amdgpu_powerplay.h"
  35 #include "si/sid.h"
  36 #include "si_ih.h"
  37 #include "gfx_v6_0.h"
  38 #include "gmc_v6_0.h"
  39 #include "si_dma.h"
  40 #include "dce_v6_0.h"
  41 #include "si.h"
  42
  43 static const u32 tahiti_golden_registers[] =
  44 {
  45         0x2684, 0x00010000, 0x00018208,
  46         0x260c, 0xffffffff, 0x00000000,
  47         0x260d, 0xf00fffff, 0x00000400,
  48         0x260e, 0x0002021c, 0x00020200,
  49         0x031e, 0x00000080, 0x00000000,
  50         0x340c, 0x000300c0, 0x00800040,
  51         0x360c, 0x000300c0, 0x00800040,
  52         0x16ec, 0x000000f0, 0x00000070,
  53         0x16f0, 0x00200000, 0x50100000,
  54         0x1c0c, 0x31000311, 0x00000011,
  55         0x09df, 0x00000003, 0x000007ff,
  56         0x0903, 0x000007ff, 0x00000000,
  57         0x2285, 0xf000001f, 0x00000007,
  58         0x22c9, 0xffffffff, 0x00ffffff,
  59         0x22c4, 0x0000ff0f, 0x00000000,
  60         0xa293, 0x07ffffff, 0x4e000000,
  61         0xa0d4, 0x3f3f3fff, 0x2a00126a,
  62         0x000c, 0x000000ff, 0x0040,
  63         0x000d, 0x00000040, 0x00004040,
  64         0x2440, 0x07ffffff, 0x03000000,
  65         0x23a2, 0x01ff1f3f, 0x00000000,
  66         0x23a1, 0x01ff1f3f, 0x00000000,
  67         0x2418, 0x0000007f, 0x00000020,
  68         0x2542, 0x00010000, 0x00010000,
  69         0x2b05, 0x00000200, 0x000002fb,
  70         0x2b04, 0xffffffff, 0x0000543b,
  71         0x2b03, 0xffffffff, 0xa9210876,
  72         0x2234, 0xffffffff, 0x000fff40,
  73         0x2235, 0x0000001f, 0x00000010,
  74         0x0504, 0x20000000, 0x20fffed8,
  75         0x0570, 0x000c0fc0, 0x000c0400
  76 };
  77
  78 static const u32 tahiti_golden_registers2[] =
  79 {
  80         0x0319, 0x00000001, 0x00000001
  81 };
  82
  83 static const u32 tahiti_golden_rlc_registers[] =
  84 {
  85         0x3109, 0xffffffff, 0x00601005,
  86         0x311f, 0xffffffff, 0x10104040,
  87         0x3122, 0xffffffff, 0x0100000a,
  88         0x30c5, 0xffffffff, 0x00000800,
  89         0x30c3, 0xffffffff, 0x800000f4,
  90         0x3d2a, 0xffffffff, 0x00000000
  91 };
  92
  93 static const u32 pitcairn_golden_registers[] =
  94 {
  95         0x2684, 0x00010000, 0x00018208,
  96         0x260c, 0xffffffff, 0x00000000,
  97         0x260d, 0xf00fffff, 0x00000400,
  98         0x260e, 0x0002021c, 0x00020200,
  99         0x031e, 0x00000080, 0x00000000,
 100         0x340c, 0x000300c0, 0x00800040,
 101         0x360c, 0x000300c0, 0x00800040,
 102         0x16ec, 0x000000f0, 0x00000070,
 103         0x16f0, 0x00200000, 0x50100000,
 104         0x1c0c, 0x31000311, 0x00000011,
 105         0x0ab9, 0x00073ffe, 0x000022a2,
 106         0x0903, 0x000007ff, 0x00000000,
 107         0x2285, 0xf000001f, 0x00000007,
 108         0x22c9, 0xffffffff, 0x00ffffff,
 109         0x22c4, 0x0000ff0f, 0x00000000,
 110         0xa293, 0x07ffffff, 0x4e000000,
 111         0xa0d4, 0x3f3f3fff, 0x2a00126a,
 112         0x000c, 0x000000ff, 0x0040,
 113         0x000d, 0x00000040, 0x00004040,
 114         0x2440, 0x07ffffff, 0x03000000,
 115         0x2418, 0x0000007f, 0x00000020,
 116         0x2542, 0x00010000, 0x00010000,
 117         0x2b05, 0x000003ff, 0x000000f7,
 118         0x2b04, 0xffffffff, 0x00000000,
 119         0x2b03, 0xffffffff, 0x32761054,
 120         0x2235, 0x0000001f, 0x00000010,
 121         0x0570, 0x000c0fc0, 0x000c0400
 122 };
 123
 124 static const u32 pitcairn_golden_rlc_registers[] =
 125 {
 126         0x3109, 0xffffffff, 0x00601004,
 127         0x311f, 0xffffffff, 0x10102020,
 128         0x3122, 0xffffffff, 0x01000020,
 129         0x30c5, 0xffffffff, 0x00000800,
 130         0x30c3, 0xffffffff, 0x800000a4
 131 };
 132
 133 static const u32 verde_pg_init[] =
 134 {
 135         0xd4f, 0xffffffff, 0x40000,
 136         0xd4e, 0xffffffff, 0x200010ff,
 137         0xd4f, 0xffffffff, 0x0,
 138         0xd4f, 0xffffffff, 0x0,
 139         0xd4f, 0xffffffff, 0x0,
 140         0xd4f, 0xffffffff, 0x0,
 141         0xd4f, 0xffffffff, 0x0,
 142         0xd4f, 0xffffffff, 0x7007,
 143         0xd4e, 0xffffffff, 0x300010ff,
 144         0xd4f, 0xffffffff, 0x0,
 145         0xd4f, 0xffffffff, 0x0,
 146         0xd4f, 0xffffffff, 0x0,
 147         0xd4f, 0xffffffff, 0x0,
 148         0xd4f, 0xffffffff, 0x0,
 149         0xd4f, 0xffffffff, 0x400000,
 150         0xd4e, 0xffffffff, 0x100010ff,
 151         0xd4f, 0xffffffff, 0x0,
 152         0xd4f, 0xffffffff, 0x0,
 153         0xd4f, 0xffffffff, 0x0,
 154         0xd4f, 0xffffffff, 0x0,
 155         0xd4f, 0xffffffff, 0x0,
 156         0xd4f, 0xffffffff, 0x120200,
 157         0xd4e, 0xffffffff, 0x500010ff,
 158         0xd4f, 0xffffffff, 0x0,
 159         0xd4f, 0xffffffff, 0x0,
 160         0xd4f, 0xffffffff, 0x0,
 161         0xd4f, 0xffffffff, 0x0,
 162         0xd4f, 0xffffffff, 0x0,
 163         0xd4f, 0xffffffff, 0x1e1e16,
 164         0xd4e, 0xffffffff, 0x600010ff,
 165         0xd4f, 0xffffffff, 0x0,
 166         0xd4f, 0xffffffff, 0x0,
 167         0xd4f, 0xffffffff, 0x0,
 168         0xd4f, 0xffffffff, 0x0,
 169         0xd4f, 0xffffffff, 0x0,
 170         0xd4f, 0xffffffff, 0x171f1e,
 171         0xd4e, 0xffffffff, 0x700010ff,
 172         0xd4f, 0xffffffff, 0x0,
 173         0xd4f, 0xffffffff, 0x0,
 174         0xd4f, 0xffffffff, 0x0,
 175         0xd4f, 0xffffffff, 0x0,
 176         0xd4f, 0xffffffff, 0x0,
 177         0xd4f, 0xffffffff, 0x0,
 178         0xd4e, 0xffffffff, 0x9ff,
 179         0xd40, 0xffffffff, 0x0,
 180         0xd41, 0xffffffff, 0x10000800,
 181         0xd41, 0xffffffff, 0xf,
 182         0xd41, 0xffffffff, 0xf,
 183         0xd40, 0xffffffff, 0x4,
 184         0xd41, 0xffffffff, 0x1000051e,
 185         0xd41, 0xffffffff, 0xffff,
 186         0xd41, 0xffffffff, 0xffff,
 187         0xd40, 0xffffffff, 0x8,
 188         0xd41, 0xffffffff, 0x80500,
 189         0xd40, 0xffffffff, 0x12,
 190         0xd41, 0xffffffff, 0x9050c,
 191         0xd40, 0xffffffff, 0x1d,
 192         0xd41, 0xffffffff, 0xb052c,
 193         0xd40, 0xffffffff, 0x2a,
 194         0xd41, 0xffffffff, 0x1053e,
 195         0xd40, 0xffffffff, 0x2d,
 196         0xd41, 0xffffffff, 0x10546,
 197         0xd40, 0xffffffff, 0x30,
 198         0xd41, 0xffffffff, 0xa054e,
 199         0xd40, 0xffffffff, 0x3c,
 200         0xd41, 0xffffffff, 0x1055f,
 201         0xd40, 0xffffffff, 0x3f,
 202         0xd41, 0xffffffff, 0x10567,
 203         0xd40, 0xffffffff, 0x42,
 204         0xd41, 0xffffffff, 0x1056f,
 205         0xd40, 0xffffffff, 0x45,
 206         0xd41, 0xffffffff, 0x10572,
 207         0xd40, 0xffffffff, 0x48,
 208         0xd41, 0xffffffff, 0x20575,
 209         0xd40, 0xffffffff, 0x4c,
 210         0xd41, 0xffffffff, 0x190801,
 211         0xd40, 0xffffffff, 0x67,
 212         0xd41, 0xffffffff, 0x1082a,
 213         0xd40, 0xffffffff, 0x6a,
 214         0xd41, 0xffffffff, 0x1b082d,
 215         0xd40, 0xffffffff, 0x87,
 216         0xd41, 0xffffffff, 0x310851,
 217         0xd40, 0xffffffff, 0xba,
 218         0xd41, 0xffffffff, 0x891,
 219         0xd40, 0xffffffff, 0xbc,
 220         0xd41, 0xffffffff, 0x893,
 221         0xd40, 0xffffffff, 0xbe,
 222         0xd41, 0xffffffff, 0x20895,
 223         0xd40, 0xffffffff, 0xc2,
 224         0xd41, 0xffffffff, 0x20899,
 225         0xd40, 0xffffffff, 0xc6,
 226         0xd41, 0xffffffff, 0x2089d,
 227         0xd40, 0xffffffff, 0xca,
 228         0xd41, 0xffffffff, 0x8a1,
 229         0xd40, 0xffffffff, 0xcc,
 230         0xd41, 0xffffffff, 0x8a3,
 231         0xd40, 0xffffffff, 0xce,
 232         0xd41, 0xffffffff, 0x308a5,
 233         0xd40, 0xffffffff, 0xd3,
 234         0xd41, 0xffffffff, 0x6d08cd,
 235         0xd40, 0xffffffff, 0x142,
 236         0xd41, 0xffffffff, 0x2000095a,
 237         0xd41, 0xffffffff, 0x1,
 238         0xd40, 0xffffffff, 0x144,
 239         0xd41, 0xffffffff, 0x301f095b,
 240         0xd40, 0xffffffff, 0x165,
 241         0xd41, 0xffffffff, 0xc094d,
 242         0xd40, 0xffffffff, 0x173,
 243         0xd41, 0xffffffff, 0xf096d,
 244         0xd40, 0xffffffff, 0x184,
 245         0xd41, 0xffffffff, 0x15097f,
 246         0xd40, 0xffffffff, 0x19b,
 247         0xd41, 0xffffffff, 0xc0998,
 248         0xd40, 0xffffffff, 0x1a9,
 249         0xd41, 0xffffffff, 0x409a7,
 250         0xd40, 0xffffffff, 0x1af,
 251         0xd41, 0xffffffff, 0xcdc,
 252         0xd40, 0xffffffff, 0x1b1,
 253         0xd41, 0xffffffff, 0x800,
 254         0xd42, 0xffffffff, 0x6c9b2000,
 255         0xd44, 0xfc00, 0x2000,
 256         0xd51, 0xffffffff, 0xfc0,
 257         0xa35, 0x00000100, 0x100
 258 };
 259
 260 static const u32 verde_golden_rlc_registers[] =
 261 {
 262         0x3109, 0xffffffff, 0x033f1005,
 263         0x311f, 0xffffffff, 0x10808020,
 264         0x3122, 0xffffffff, 0x00800008,
 265         0x30c5, 0xffffffff, 0x00001000,
 266         0x30c3, 0xffffffff, 0x80010014
 267 };
 268
 269 static const u32 verde_golden_registers[] =
 270 {
 271         0x2684, 0x00010000, 0x00018208,
 272         0x260c, 0xffffffff, 0x00000000,
 273         0x260d, 0xf00fffff, 0x00000400,
 274         0x260e, 0x0002021c, 0x00020200,
 275         0x031e, 0x00000080, 0x00000000,
 276         0x340c, 0x000300c0, 0x00800040,
 277         0x340c, 0x000300c0, 0x00800040,
 278         0x360c, 0x000300c0, 0x00800040,
 279         0x360c, 0x000300c0, 0x00800040,
 280         0x16ec, 0x000000f0, 0x00000070,
 281         0x16f0, 0x00200000, 0x50100000,
 282
 283         0x1c0c, 0x31000311, 0x00000011,
 284         0x0ab9, 0x00073ffe, 0x000022a2,
 285         0x0ab9, 0x00073ffe, 0x000022a2,
 286         0x0ab9, 0x00073ffe, 0x000022a2,
 287         0x0903, 0x000007ff, 0x00000000,
 288         0x0903, 0x000007ff, 0x00000000,
 289         0x0903, 0x000007ff, 0x00000000,
 290         0x2285, 0xf000001f, 0x00000007,
 291         0x2285, 0xf000001f, 0x00000007,
 292         0x2285, 0xf000001f, 0x00000007,
 293         0x2285, 0xffffffff, 0x00ffffff,
 294         0x22c4, 0x0000ff0f, 0x00000000,
 295
 296         0xa293, 0x07ffffff, 0x4e000000,
 297         0xa0d4, 0x3f3f3fff, 0x0000124a,
 298         0xa0d4, 0x3f3f3fff, 0x0000124a,
 299         0xa0d4, 0x3f3f3fff, 0x0000124a,
 300         0x000c, 0x000000ff, 0x0040,
 301         0x000d, 0x00000040, 0x00004040,
 302         0x2440, 0x07ffffff, 0x03000000,
 303         0x2440, 0x07ffffff, 0x03000000,
 304         0x23a2, 0x01ff1f3f, 0x00000000,
 305         0x23a3, 0x01ff1f3f, 0x00000000,
 306         0x23a2, 0x01ff1f3f, 0x00000000,
 307         0x23a1, 0x01ff1f3f, 0x00000000,
 308         0x23a1, 0x01ff1f3f, 0x00000000,
 309
 310         0x23a1, 0x01ff1f3f, 0x00000000,
 311         0x2418, 0x0000007f, 0x00000020,
 312         0x2542, 0x00010000, 0x00010000,
 313         0x2b01, 0x000003ff, 0x00000003,
 314         0x2b05, 0x000003ff, 0x00000003,
 315         0x2b05, 0x000003ff, 0x00000003,
 316         0x2b04, 0xffffffff, 0x00000000,
 317         0x2b04, 0xffffffff, 0x00000000,
 318         0x2b04, 0xffffffff, 0x00000000,
 319         0x2b03, 0xffffffff, 0x00001032,
 320         0x2b03, 0xffffffff, 0x00001032,
 321         0x2b03, 0xffffffff, 0x00001032,
 322         0x2235, 0x0000001f, 0x00000010,
 323         0x2235, 0x0000001f, 0x00000010,
 324         0x2235, 0x0000001f, 0x00000010,
 325         0x0570, 0x000c0fc0, 0x000c0400
 326 };
 327
 328 static const u32 oland_golden_registers[] =
 329 {
 330         0x2684, 0x00010000, 0x00018208,
 331         0x260c, 0xffffffff, 0x00000000,
 332         0x260d, 0xf00fffff, 0x00000400,
 333         0x260e, 0x0002021c, 0x00020200,
 334         0x031e, 0x00000080, 0x00000000,
 335         0x340c, 0x000300c0, 0x00800040,
 336         0x360c, 0x000300c0, 0x00800040,
 337         0x16ec, 0x000000f0, 0x00000070,
 338         0x16f9, 0x00200000, 0x50100000,
 339         0x1c0c, 0x31000311, 0x00000011,
 340         0x0ab9, 0x00073ffe, 0x000022a2,
 341         0x0903, 0x000007ff, 0x00000000,
 342         0x2285, 0xf000001f, 0x00000007,
 343         0x22c9, 0xffffffff, 0x00ffffff,
 344         0x22c4, 0x0000ff0f, 0x00000000,
 345         0xa293, 0x07ffffff, 0x4e000000,
 346         0xa0d4, 0x3f3f3fff, 0x00000082,
 347         0x000c, 0x000000ff, 0x0040,
 348         0x000d, 0x00000040, 0x00004040,
 349         0x2440, 0x07ffffff, 0x03000000,
 350         0x2418, 0x0000007f, 0x00000020,
 351         0x2542, 0x00010000, 0x00010000,
 352         0x2b05, 0x000003ff, 0x000000f3,
 353         0x2b04, 0xffffffff, 0x00000000,
 354         0x2b03, 0xffffffff, 0x00003210,
 355         0x2235, 0x0000001f, 0x00000010,
 356         0x0570, 0x000c0fc0, 0x000c0400
 357 };
 358
 359 static const u32 oland_golden_rlc_registers[] =
 360 {
 361         0x3109, 0xffffffff, 0x00601005,
 362         0x311f, 0xffffffff, 0x10104040,
 363         0x3122, 0xffffffff, 0x0100000a,
 364         0x30c5, 0xffffffff, 0x00000800,
 365         0x30c3, 0xffffffff, 0x800000f4
 366 };
 367
 368 static const u32 hainan_golden_registers[] =
 369 {
 370         0x2684, 0x00010000, 0x00018208,
 371         0x260c, 0xffffffff, 0x00000000,
 372         0x260d, 0xf00fffff, 0x00000400,
 373         0x260e, 0x0002021c, 0x00020200,
 374         0x4595, 0xff000fff, 0x00000100,
 375         0x340c, 0x000300c0, 0x00800040,
 376         0x3630, 0xff000fff, 0x00000100,
 377         0x360c, 0x000300c0, 0x00800040,
 378         0x0ab9, 0x00073ffe, 0x000022a2,
 379         0x0903, 0x000007ff, 0x00000000,
 380         0x2285, 0xf000001f, 0x00000007,
 381         0x22c9, 0xffffffff, 0x00ffffff,
 382         0x22c4, 0x0000ff0f, 0x00000000,
 383         0xa393, 0x07ffffff, 0x4e000000,
 384         0xa0d4, 0x3f3f3fff, 0x00000000,
 385         0x000c, 0x000000ff, 0x0040,
 386         0x000d, 0x00000040, 0x00004040,
 387         0x2440, 0x03e00000, 0x03600000,
 388         0x2418, 0x0000007f, 0x00000020,
 389         0x2542, 0x00010000, 0x00010000,
 390         0x2b05, 0x000003ff, 0x000000f1,
 391         0x2b04, 0xffffffff, 0x00000000,
 392         0x2b03, 0xffffffff, 0x00003210,
 393         0x2235, 0x0000001f, 0x00000010,
 394         0x0570, 0x000c0fc0, 0x000c0400
 395 };
 396
 397 static const u32 hainan_golden_registers2[] =
 398 {
 399         0x263e, 0xffffffff, 0x02010001
 400 };
 401
 402 static const u32 tahiti_mgcg_cgcg_init[] =
 403 {
 404         0x3100, 0xffffffff, 0xfffffffc,
 405         0x200b, 0xffffffff, 0xe0000000,
 406         0x2698, 0xffffffff, 0x00000100,
 407         0x24a9, 0xffffffff, 0x00000100,
 408         0x3059, 0xffffffff, 0x00000100,
 409         0x25dd, 0xffffffff, 0x00000100,
 410         0x2261, 0xffffffff, 0x06000100,
 411         0x2286, 0xffffffff, 0x00000100,
 412         0x24a8, 0xffffffff, 0x00000100,
 413         0x30e0, 0xffffffff, 0x00000100,
 414         0x22ca, 0xffffffff, 0x00000100,
 415         0x2451, 0xffffffff, 0x00000100,
 416         0x2362, 0xffffffff, 0x00000100,
 417         0x2363, 0xffffffff, 0x00000100,
 418         0x240c, 0xffffffff, 0x00000100,
 419         0x240d, 0xffffffff, 0x00000100,
 420         0x240e, 0xffffffff, 0x00000100,
 421         0x240f, 0xffffffff, 0x00000100,
 422         0x2b60, 0xffffffff, 0x00000100,
 423         0x2b15, 0xffffffff, 0x00000100,
 424         0x225f, 0xffffffff, 0x06000100,
 425         0x261a, 0xffffffff, 0x00000100,
 426         0x2544, 0xffffffff, 0x00000100,
 427         0x2bc1, 0xffffffff, 0x00000100,
 428         0x2b81, 0xffffffff, 0x00000100,
 429         0x2527, 0xffffffff, 0x00000100,
 430         0x200b, 0xffffffff, 0xe0000000,
 431         0x2458, 0xffffffff, 0x00010000,
 432         0x2459, 0xffffffff, 0x00030002,
 433         0x245a, 0xffffffff, 0x00040007,
 434         0x245b, 0xffffffff, 0x00060005,
 435         0x245c, 0xffffffff, 0x00090008,
 436         0x245d, 0xffffffff, 0x00020001,
 437         0x245e, 0xffffffff, 0x00040003,
 438         0x245f, 0xffffffff, 0x00000007,
 439         0x2460, 0xffffffff, 0x00060005,
 440         0x2461, 0xffffffff, 0x00090008,
 441         0x2462, 0xffffffff, 0x00030002,
 442         0x2463, 0xffffffff, 0x00050004,
 443         0x2464, 0xffffffff, 0x00000008,
 444         0x2465, 0xffffffff, 0x00070006,
 445         0x2466, 0xffffffff, 0x000a0009,
 446         0x2467, 0xffffffff, 0x00040003,
 447         0x2468, 0xffffffff, 0x00060005,
 448         0x2469, 0xffffffff, 0x00000009,
 449         0x246a, 0xffffffff, 0x00080007,
 450         0x246b, 0xffffffff, 0x000b000a,
 451         0x246c, 0xffffffff, 0x00050004,
 452         0x246d, 0xffffffff, 0x00070006,
 453         0x246e, 0xffffffff, 0x0008000b,
 454         0x246f, 0xffffffff, 0x000a0009,
 455         0x2470, 0xffffffff, 0x000d000c,
 456         0x2471, 0xffffffff, 0x00060005,
 457         0x2472, 0xffffffff, 0x00080007,
 458         0x2473, 0xffffffff, 0x0000000b,
 459         0x2474, 0xffffffff, 0x000a0009,
 460         0x2475, 0xffffffff, 0x000d000c,
 461         0x2476, 0xffffffff, 0x00070006,
 462         0x2477, 0xffffffff, 0x00090008,
 463         0x2478, 0xffffffff, 0x0000000c,
 464         0x2479, 0xffffffff, 0x000b000a,
 465         0x247a, 0xffffffff, 0x000e000d,
 466         0x247b, 0xffffffff, 0x00080007,
 467         0x247c, 0xffffffff, 0x000a0009,
 468         0x247d, 0xffffffff, 0x0000000d,
 469         0x247e, 0xffffffff, 0x000c000b,
 470         0x247f, 0xffffffff, 0x000f000e,
 471         0x2480, 0xffffffff, 0x00090008,
 472         0x2481, 0xffffffff, 0x000b000a,
 473         0x2482, 0xffffffff, 0x000c000f,
 474         0x2483, 0xffffffff, 0x000e000d,
 475         0x2484, 0xffffffff, 0x00110010,
 476         0x2485, 0xffffffff, 0x000a0009,
 477         0x2486, 0xffffffff, 0x000c000b,
 478         0x2487, 0xffffffff, 0x0000000f,
 479         0x2488, 0xffffffff, 0x000e000d,
 480         0x2489, 0xffffffff, 0x00110010,
 481         0x248a, 0xffffffff, 0x000b000a,
 482         0x248b, 0xffffffff, 0x000d000c,
 483         0x248c, 0xffffffff, 0x00000010,
 484         0x248d, 0xffffffff, 0x000f000e,
 485         0x248e, 0xffffffff, 0x00120011,
 486         0x248f, 0xffffffff, 0x000c000b,
 487         0x2490, 0xffffffff, 0x000e000d,
 488         0x2491, 0xffffffff, 0x00000011,
 489         0x2492, 0xffffffff, 0x0010000f,
 490         0x2493, 0xffffffff, 0x00130012,
 491         0x2494, 0xffffffff, 0x000d000c,
 492         0x2495, 0xffffffff, 0x000f000e,
 493         0x2496, 0xffffffff, 0x00100013,
 494         0x2497, 0xffffffff, 0x00120011,
 495         0x2498, 0xffffffff, 0x00150014,
 496         0x2499, 0xffffffff, 0x000e000d,
 497         0x249a, 0xffffffff, 0x0010000f,
 498         0x249b, 0xffffffff, 0x00000013,
 499         0x249c, 0xffffffff, 0x00120011,
 500         0x249d, 0xffffffff, 0x00150014,
 501         0x249e, 0xffffffff, 0x000f000e,
 502         0x249f, 0xffffffff, 0x00110010,
 503         0x24a0, 0xffffffff, 0x00000014,
 504         0x24a1, 0xffffffff, 0x00130012,
 505         0x24a2, 0xffffffff, 0x00160015,
 506         0x24a3, 0xffffffff, 0x0010000f,
 507         0x24a4, 0xffffffff, 0x00120011,
 508         0x24a5, 0xffffffff, 0x00000015,
 509         0x24a6, 0xffffffff, 0x00140013,
 510         0x24a7, 0xffffffff, 0x00170016,
 511         0x2454, 0xffffffff, 0x96940200,
 512         0x21c2, 0xffffffff, 0x00900100,
 513         0x311e, 0xffffffff, 0x00000080,
 514         0x3101, 0xffffffff, 0x0020003f,
 515         0xc, 0xffffffff, 0x0000001c,
 516         0xd, 0x000f0000, 0x000f0000,
 517         0x583, 0xffffffff, 0x00000100,
 518         0x409, 0xffffffff, 0x00000100,
 519         0x40b, 0x00000101, 0x00000000,
 520         0x82a, 0xffffffff, 0x00000104,
 521         0x993, 0x000c0000, 0x000c0000,
 522         0x992, 0x000c0000, 0x000c0000,
 523         0x1579, 0xff000fff, 0x00000100,
 524         0x157a, 0x00000001, 0x00000001,
 525         0xbd4, 0x00000001, 0x00000001,
 526         0xc33, 0xc0000fff, 0x00000104,
 527         0x3079, 0x00000001, 0x00000001,
 528         0x3430, 0xfffffff0, 0x00000100,
 529         0x3630, 0xfffffff0, 0x00000100
 530 };
 531 static const u32 pitcairn_mgcg_cgcg_init[] =
 532 {
 533         0x3100, 0xffffffff, 0xfffffffc,
 534         0x200b, 0xffffffff, 0xe0000000,
 535         0x2698, 0xffffffff, 0x00000100,
 536         0x24a9, 0xffffffff, 0x00000100,
 537         0x3059, 0xffffffff, 0x00000100,
 538         0x25dd, 0xffffffff, 0x00000100,
 539         0x2261, 0xffffffff, 0x06000100,
 540         0x2286, 0xffffffff, 0x00000100,
 541         0x24a8, 0xffffffff, 0x00000100,
 542         0x30e0, 0xffffffff, 0x00000100,
 543         0x22ca, 0xffffffff, 0x00000100,
 544         0x2451, 0xffffffff, 0x00000100,
 545         0x2362, 0xffffffff, 0x00000100,
 546         0x2363, 0xffffffff, 0x00000100,
 547         0x240c, 0xffffffff, 0x00000100,
 548         0x240d, 0xffffffff, 0x00000100,
 549         0x240e, 0xffffffff, 0x00000100,
 550         0x240f, 0xffffffff, 0x00000100,
 551         0x2b60, 0xffffffff, 0x00000100,
 552         0x2b15, 0xffffffff, 0x00000100,
 553         0x225f, 0xffffffff, 0x06000100,
 554         0x261a, 0xffffffff, 0x00000100,
 555         0x2544, 0xffffffff, 0x00000100,
 556         0x2bc1, 0xffffffff, 0x00000100,
 557         0x2b81, 0xffffffff, 0x00000100,
 558         0x2527, 0xffffffff, 0x00000100,
 559         0x200b, 0xffffffff, 0xe0000000,
 560         0x2458, 0xffffffff, 0x00010000,
 561         0x2459, 0xffffffff, 0x00030002,
 562         0x245a, 0xffffffff, 0x00040007,
 563         0x245b, 0xffffffff, 0x00060005,
 564         0x245c, 0xffffffff, 0x00090008,
 565         0x245d, 0xffffffff, 0x00020001,
 566         0x245e, 0xffffffff, 0x00040003,
 567         0x245f, 0xffffffff, 0x00000007,
 568         0x2460, 0xffffffff, 0x00060005,
 569         0x2461, 0xffffffff, 0x00090008,
 570         0x2462, 0xffffffff, 0x00030002,
 571         0x2463, 0xffffffff, 0x00050004,
 572         0x2464, 0xffffffff, 0x00000008,
 573         0x2465, 0xffffffff, 0x00070006,
 574         0x2466, 0xffffffff, 0x000a0009,
 575         0x2467, 0xffffffff, 0x00040003,
 576         0x2468, 0xffffffff, 0x00060005,
 577         0x2469, 0xffffffff, 0x00000009,
 578         0x246a, 0xffffffff, 0x00080007,
 579         0x246b, 0xffffffff, 0x000b000a,
 580         0x246c, 0xffffffff, 0x00050004,
 581         0x246d, 0xffffffff, 0x00070006,
 582         0x246e, 0xffffffff, 0x0008000b,
 583         0x246f, 0xffffffff, 0x000a0009,
 584         0x2470, 0xffffffff, 0x000d000c,
 585         0x2480, 0xffffffff, 0x00090008,
 586         0x2481, 0xffffffff, 0x000b000a,
 587         0x2482, 0xffffffff, 0x000c000f,
 588         0x2483, 0xffffffff, 0x000e000d,
 589         0x2484, 0xffffffff, 0x00110010,
 590         0x2485, 0xffffffff, 0x000a0009,
 591         0x2486, 0xffffffff, 0x000c000b,
 592         0x2487, 0xffffffff, 0x0000000f,
 593         0x2488, 0xffffffff, 0x000e000d,
 594         0x2489, 0xffffffff, 0x00110010,
 595         0x248a, 0xffffffff, 0x000b000a,
 596         0x248b, 0xffffffff, 0x000d000c,
 597         0x248c, 0xffffffff, 0x00000010,
 598         0x248d, 0xffffffff, 0x000f000e,
 599         0x248e, 0xffffffff, 0x00120011,
 600         0x248f, 0xffffffff, 0x000c000b,
 601         0x2490, 0xffffffff, 0x000e000d,
 602         0x2491, 0xffffffff, 0x00000011,
 603         0x2492, 0xffffffff, 0x0010000f,
 604         0x2493, 0xffffffff, 0x00130012,
 605         0x2494, 0xffffffff, 0x000d000c,
 606         0x2495, 0xffffffff, 0x000f000e,
 607         0x2496, 0xffffffff, 0x00100013,
 608         0x2497, 0xffffffff, 0x00120011,
 609         0x2498, 0xffffffff, 0x00150014,
 610         0x2454, 0xffffffff, 0x96940200,
 611         0x21c2, 0xffffffff, 0x00900100,
 612         0x311e, 0xffffffff, 0x00000080,
 613         0x3101, 0xffffffff, 0x0020003f,
 614         0xc, 0xffffffff, 0x0000001c,
 615         0xd, 0x000f0000, 0x000f0000,
 616         0x583, 0xffffffff, 0x00000100,
 617         0x409, 0xffffffff, 0x00000100,
 618         0x40b, 0x00000101, 0x00000000,
 619         0x82a, 0xffffffff, 0x00000104,
 620         0x1579, 0xff000fff, 0x00000100,
 621         0x157a, 0x00000001, 0x00000001,
 622         0xbd4, 0x00000001, 0x00000001,
 623         0xc33, 0xc0000fff, 0x00000104,
 624         0x3079, 0x00000001, 0x00000001,
 625         0x3430, 0xfffffff0, 0x00000100,
 626         0x3630, 0xfffffff0, 0x00000100
 627 };
 628 static const u32 verde_mgcg_cgcg_init[] =
 629 {
 630         0x3100, 0xffffffff, 0xfffffffc,
 631         0x200b, 0xffffffff, 0xe0000000,
 632         0x2698, 0xffffffff, 0x00000100,
 633         0x24a9, 0xffffffff, 0x00000100,
 634         0x3059, 0xffffffff, 0x00000100,
 635         0x25dd, 0xffffffff, 0x00000100,
 636         0x2261, 0xffffffff, 0x06000100,
 637         0x2286, 0xffffffff, 0x00000100,
 638         0x24a8, 0xffffffff, 0x00000100,
 639         0x30e0, 0xffffffff, 0x00000100,
 640         0x22ca, 0xffffffff, 0x00000100,
 641         0x2451, 0xffffffff, 0x00000100,
 642         0x2362, 0xffffffff, 0x00000100,
 643         0x2363, 0xffffffff, 0x00000100,
 644         0x240c, 0xffffffff, 0x00000100,
 645         0x240d, 0xffffffff, 0x00000100,
 646         0x240e, 0xffffffff, 0x00000100,
 647         0x240f, 0xffffffff, 0x00000100,
 648         0x2b60, 0xffffffff, 0x00000100,
 649         0x2b15, 0xffffffff, 0x00000100,
 650         0x225f, 0xffffffff, 0x06000100,
 651         0x261a, 0xffffffff, 0x00000100,
 652         0x2544, 0xffffffff, 0x00000100,
 653         0x2bc1, 0xffffffff, 0x00000100,
 654         0x2b81, 0xffffffff, 0x00000100,
 655         0x2527, 0xffffffff, 0x00000100,
 656         0x200b, 0xffffffff, 0xe0000000,
 657         0x2458, 0xffffffff, 0x00010000,
 658         0x2459, 0xffffffff, 0x00030002,
 659         0x245a, 0xffffffff, 0x00040007,
 660         0x245b, 0xffffffff, 0x00060005,
 661         0x245c, 0xffffffff, 0x00090008,
 662         0x245d, 0xffffffff, 0x00020001,
 663         0x245e, 0xffffffff, 0x00040003,
 664         0x245f, 0xffffffff, 0x00000007,
 665         0x2460, 0xffffffff, 0x00060005,
 666         0x2461, 0xffffffff, 0x00090008,
 667         0x2462, 0xffffffff, 0x00030002,
 668         0x2463, 0xffffffff, 0x00050004,
 669         0x2464, 0xffffffff, 0x00000008,
 670         0x2465, 0xffffffff, 0x00070006,
 671         0x2466, 0xffffffff, 0x000a0009,
 672         0x2467, 0xffffffff, 0x00040003,
 673         0x2468, 0xffffffff, 0x00060005,
 674         0x2469, 0xffffffff, 0x00000009,
 675         0x246a, 0xffffffff, 0x00080007,
 676         0x246b, 0xffffffff, 0x000b000a,
 677         0x246c, 0xffffffff, 0x00050004,
 678         0x246d, 0xffffffff, 0x00070006,
 679         0x246e, 0xffffffff, 0x0008000b,
 680         0x246f, 0xffffffff, 0x000a0009,
 681         0x2470, 0xffffffff, 0x000d000c,
 682         0x2480, 0xffffffff, 0x00090008,
 683         0x2481, 0xffffffff, 0x000b000a,
 684         0x2482, 0xffffffff, 0x000c000f,
 685         0x2483, 0xffffffff, 0x000e000d,
 686         0x2484, 0xffffffff, 0x00110010,
 687         0x2485, 0xffffffff, 0x000a0009,
 688         0x2486, 0xffffffff, 0x000c000b,
 689         0x2487, 0xffffffff, 0x0000000f,
 690         0x2488, 0xffffffff, 0x000e000d,
 691         0x2489, 0xffffffff, 0x00110010,
 692         0x248a, 0xffffffff, 0x000b000a,
 693         0x248b, 0xffffffff, 0x000d000c,
 694         0x248c, 0xffffffff, 0x00000010,
 695         0x248d, 0xffffffff, 0x000f000e,
 696         0x248e, 0xffffffff, 0x00120011,
 697         0x248f, 0xffffffff, 0x000c000b,
 698         0x2490, 0xffffffff, 0x000e000d,
 699         0x2491, 0xffffffff, 0x00000011,
 700         0x2492, 0xffffffff, 0x0010000f,
 701         0x2493, 0xffffffff, 0x00130012,
 702         0x2494, 0xffffffff, 0x000d000c,
 703         0x2495, 0xffffffff, 0x000f000e,
 704         0x2496, 0xffffffff, 0x00100013,
 705         0x2497, 0xffffffff, 0x00120011,
 706         0x2498, 0xffffffff, 0x00150014,
 707         0x2454, 0xffffffff, 0x96940200,
 708         0x21c2, 0xffffffff, 0x00900100,
 709         0x311e, 0xffffffff, 0x00000080,
 710         0x3101, 0xffffffff, 0x0020003f,
 711         0xc, 0xffffffff, 0x0000001c,
 712         0xd, 0x000f0000, 0x000f0000,
 713         0x583, 0xffffffff, 0x00000100,
 714         0x409, 0xffffffff, 0x00000100,
 715         0x40b, 0x00000101, 0x00000000,
 716         0x82a, 0xffffffff, 0x00000104,
 717         0x993, 0x000c0000, 0x000c0000,
 718         0x992, 0x000c0000, 0x000c0000,
 719         0x1579, 0xff000fff, 0x00000100,
 720         0x157a, 0x00000001, 0x00000001,
 721         0xbd4, 0x00000001, 0x00000001,
 722         0xc33, 0xc0000fff, 0x00000104,
 723         0x3079, 0x00000001, 0x00000001,
 724         0x3430, 0xfffffff0, 0x00000100,
 725         0x3630, 0xfffffff0, 0x00000100
 726 };
 727 static const u32 oland_mgcg_cgcg_init[] =
 728 {
 729         0x3100, 0xffffffff, 0xfffffffc,
 730         0x200b, 0xffffffff, 0xe0000000,
 731         0x2698, 0xffffffff, 0x00000100,
 732         0x24a9, 0xffffffff, 0x00000100,
 733         0x3059, 0xffffffff, 0x00000100,
 734         0x25dd, 0xffffffff, 0x00000100,
 735         0x2261, 0xffffffff, 0x06000100,
 736         0x2286, 0xffffffff, 0x00000100,
 737         0x24a8, 0xffffffff, 0x00000100,
 738         0x30e0, 0xffffffff, 0x00000100,
 739         0x22ca, 0xffffffff, 0x00000100,
 740         0x2451, 0xffffffff, 0x00000100,
 741         0x2362, 0xffffffff, 0x00000100,
 742         0x2363, 0xffffffff, 0x00000100,
 743         0x240c, 0xffffffff, 0x00000100,
 744         0x240d, 0xffffffff, 0x00000100,
 745         0x240e, 0xffffffff, 0x00000100,
 746         0x240f, 0xffffffff, 0x00000100,
 747         0x2b60, 0xffffffff, 0x00000100,
 748         0x2b15, 0xffffffff, 0x00000100,
 749         0x225f, 0xffffffff, 0x06000100,
 750         0x261a, 0xffffffff, 0x00000100,
 751         0x2544, 0xffffffff, 0x00000100,
 752         0x2bc1, 0xffffffff, 0x00000100,
 753         0x2b81, 0xffffffff, 0x00000100,
 754         0x2527, 0xffffffff, 0x00000100,
 755         0x200b, 0xffffffff, 0xe0000000,
 756         0x2458, 0xffffffff, 0x00010000,
 757         0x2459, 0xffffffff, 0x00030002,
 758         0x245a, 0xffffffff, 0x00040007,
 759         0x245b, 0xffffffff, 0x00060005,
 760         0x245c, 0xffffffff, 0x00090008,
 761         0x245d, 0xffffffff, 0x00020001,
 762         0x245e, 0xffffffff, 0x00040003,
 763         0x245f, 0xffffffff, 0x00000007,
 764         0x2460, 0xffffffff, 0x00060005,
 765         0x2461, 0xffffffff, 0x00090008,
 766         0x2462, 0xffffffff, 0x00030002,
 767         0x2463, 0xffffffff, 0x00050004,
 768         0x2464, 0xffffffff, 0x00000008,
 769         0x2465, 0xffffffff, 0x00070006,
 770         0x2466, 0xffffffff, 0x000a0009,
 771         0x2467, 0xffffffff, 0x00040003,
 772         0x2468, 0xffffffff, 0x00060005,
 773         0x2469, 0xffffffff, 0x00000009,
 774         0x246a, 0xffffffff, 0x00080007,
 775         0x246b, 0xffffffff, 0x000b000a,
 776         0x246c, 0xffffffff, 0x00050004,
 777         0x246d, 0xffffffff, 0x00070006,
 778         0x246e, 0xffffffff, 0x0008000b,
 779         0x246f, 0xffffffff, 0x000a0009,
 780         0x2470, 0xffffffff, 0x000d000c,
 781         0x2471, 0xffffffff, 0x00060005,
 782         0x2472, 0xffffffff, 0x00080007,
 783         0x2473, 0xffffffff, 0x0000000b,
 784         0x2474, 0xffffffff, 0x000a0009,
 785         0x2475, 0xffffffff, 0x000d000c,
 786         0x2454, 0xffffffff, 0x96940200,
 787         0x21c2, 0xffffffff, 0x00900100,
 788         0x311e, 0xffffffff, 0x00000080,
 789         0x3101, 0xffffffff, 0x0020003f,
 790         0xc, 0xffffffff, 0x0000001c,
 791         0xd, 0x000f0000, 0x000f0000,
 792         0x583, 0xffffffff, 0x00000100,
 793         0x409, 0xffffffff, 0x00000100,
 794         0x40b, 0x00000101, 0x00000000,
 795         0x82a, 0xffffffff, 0x00000104,
 796         0x993, 0x000c0000, 0x000c0000,
 797         0x992, 0x000c0000, 0x000c0000,
 798         0x1579, 0xff000fff, 0x00000100,
 799         0x157a, 0x00000001, 0x00000001,
 800         0xbd4, 0x00000001, 0x00000001,
 801         0xc33, 0xc0000fff, 0x00000104,
 802         0x3079, 0x00000001, 0x00000001,
 803         0x3430, 0xfffffff0, 0x00000100,
 804         0x3630, 0xfffffff0, 0x00000100
 805 };
 806 static const u32 hainan_mgcg_cgcg_init[] =
 807 {
 808         0x3100, 0xffffffff, 0xfffffffc,
 809         0x200b, 0xffffffff, 0xe0000000,
 810         0x2698, 0xffffffff, 0x00000100,
 811         0x24a9, 0xffffffff, 0x00000100,
 812         0x3059, 0xffffffff, 0x00000100,
 813         0x25dd, 0xffffffff, 0x00000100,
 814         0x2261, 0xffffffff, 0x06000100,
 815         0x2286, 0xffffffff, 0x00000100,
 816         0x24a8, 0xffffffff, 0x00000100,
 817         0x30e0, 0xffffffff, 0x00000100,
 818         0x22ca, 0xffffffff, 0x00000100,
 819         0x2451, 0xffffffff, 0x00000100,
 820         0x2362, 0xffffffff, 0x00000100,
 821         0x2363, 0xffffffff, 0x00000100,
 822         0x240c, 0xffffffff, 0x00000100,
 823         0x240d, 0xffffffff, 0x00000100,
 824         0x240e, 0xffffffff, 0x00000100,
 825         0x240f, 0xffffffff, 0x00000100,
 826         0x2b60, 0xffffffff, 0x00000100,
 827         0x2b15, 0xffffffff, 0x00000100,
 828         0x225f, 0xffffffff, 0x06000100,
 829         0x261a, 0xffffffff, 0x00000100,
 830         0x2544, 0xffffffff, 0x00000100,
 831         0x2bc1, 0xffffffff, 0x00000100,
 832         0x2b81, 0xffffffff, 0x00000100,
 833         0x2527, 0xffffffff, 0x00000100,
 834         0x200b, 0xffffffff, 0xe0000000,
 835         0x2458, 0xffffffff, 0x00010000,
 836         0x2459, 0xffffffff, 0x00030002,
 837         0x245a, 0xffffffff, 0x00040007,
 838         0x245b, 0xffffffff, 0x00060005,
 839         0x245c, 0xffffffff, 0x00090008,
 840         0x245d, 0xffffffff, 0x00020001,
 841         0x245e, 0xffffffff, 0x00040003,
 842         0x245f, 0xffffffff, 0x00000007,
 843         0x2460, 0xffffffff, 0x00060005,
 844         0x2461, 0xffffffff, 0x00090008,
 845         0x2462, 0xffffffff, 0x00030002,
 846         0x2463, 0xffffffff, 0x00050004,
 847         0x2464, 0xffffffff, 0x00000008,
 848         0x2465, 0xffffffff, 0x00070006,
 849         0x2466, 0xffffffff, 0x000a0009,
 850         0x2467, 0xffffffff, 0x00040003,
 851         0x2468, 0xffffffff, 0x00060005,
 852         0x2469, 0xffffffff, 0x00000009,
 853         0x246a, 0xffffffff, 0x00080007,
 854         0x246b, 0xffffffff, 0x000b000a,
 855         0x246c, 0xffffffff, 0x00050004,
 856         0x246d, 0xffffffff, 0x00070006,
 857         0x246e, 0xffffffff, 0x0008000b,
 858         0x246f, 0xffffffff, 0x000a0009,
 859         0x2470, 0xffffffff, 0x000d000c,
 860         0x2471, 0xffffffff, 0x00060005,
 861         0x2472, 0xffffffff, 0x00080007,
 862         0x2473, 0xffffffff, 0x0000000b,
 863         0x2474, 0xffffffff, 0x000a0009,
 864         0x2475, 0xffffffff, 0x000d000c,
 865         0x2454, 0xffffffff, 0x96940200,
 866         0x21c2, 0xffffffff, 0x00900100,
 867         0x311e, 0xffffffff, 0x00000080,
 868         0x3101, 0xffffffff, 0x0020003f,
 869         0xc, 0xffffffff, 0x0000001c,
 870         0xd, 0x000f0000, 0x000f0000,
 871         0x583, 0xffffffff, 0x00000100,
 872         0x409, 0xffffffff, 0x00000100,
 873         0x82a, 0xffffffff, 0x00000104,
 874         0x993, 0x000c0000, 0x000c0000,
 875         0x992, 0x000c0000, 0x000c0000,
 876         0xbd4, 0x00000001, 0x00000001,
 877         0xc33, 0xc0000fff, 0x00000104,
 878         0x3079, 0x00000001, 0x00000001,
 879         0x3430, 0xfffffff0, 0x00000100,
 880         0x3630, 0xfffffff0, 0x00000100
 881 };
 882
 883 static u32 si_pcie_rreg(struct amdgpu_device *adev, u32 reg)
 884 {
 885         unsigned long flags;
 886         u32 r;
 887
 888         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 889         WREG32(AMDGPU_PCIE_INDEX, reg);
 890         (void)RREG32(AMDGPU_PCIE_INDEX);
 891         r = RREG32(AMDGPU_PCIE_DATA);
 892         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 893         return r;
 894 }
 895
 896 static void si_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 897 {
 898         unsigned long flags;
 899
 900         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 901         WREG32(AMDGPU_PCIE_INDEX, reg);
 902         (void)RREG32(AMDGPU_PCIE_INDEX);
 903         WREG32(AMDGPU_PCIE_DATA, v);
 904         (void)RREG32(AMDGPU_PCIE_DATA);
 905         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 906 }
 907
 908 u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg)
 909 {
 910         unsigned long flags;
 911         u32 r;
 912
 913         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 914         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
 915         (void)RREG32(PCIE_PORT_INDEX);
 916         r = RREG32(PCIE_PORT_DATA);
 917         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 918         return r;
 919 }
 920
 921 void si_pciep_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 922 {
 923         unsigned long flags;
 924
 925         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 926         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
 927         (void)RREG32(PCIE_PORT_INDEX);
 928         WREG32(PCIE_PORT_DATA, (v));
 929         (void)RREG32(PCIE_PORT_DATA);
 930         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 931 }
 932
 933 static u32 si_smc_rreg(struct amdgpu_device *adev, u32 reg)
 934 {
 935         unsigned long flags;
 936         u32 r;
 937
 938         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 939         WREG32(SMC_IND_INDEX_0, (reg));
 940         r = RREG32(SMC_IND_DATA_0);
 941         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 942         return r;
 943 }
 944
 945 static void si_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 946 {
 947         unsigned long flags;
 948
 949         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 950         WREG32(SMC_IND_INDEX_0, (reg));
 951         WREG32(SMC_IND_DATA_0, (v));
 952         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 953 }
 954
 955 static struct amdgpu_allowed_register_entry si_allowed_read_registers[] = {
 956         {GRBM_STATUS, false},
 957         {GB_ADDR_CONFIG, false},
 958         {MC_ARB_RAMCFG, false},
 959         {GB_TILE_MODE0, false},
 960         {GB_TILE_MODE1, false},
 961         {GB_TILE_MODE2, false},
 962         {GB_TILE_MODE3, false},
 963         {GB_TILE_MODE4, false},
 964         {GB_TILE_MODE5, false},
 965         {GB_TILE_MODE6, false},
 966         {GB_TILE_MODE7, false},
 967         {GB_TILE_MODE8, false},
 968         {GB_TILE_MODE9, false},
 969         {GB_TILE_MODE10, false},
 970         {GB_TILE_MODE11, false},
 971         {GB_TILE_MODE12, false},
 972         {GB_TILE_MODE13, false},
 973         {GB_TILE_MODE14, false},
 974         {GB_TILE_MODE15, false},
 975         {GB_TILE_MODE16, false},
 976         {GB_TILE_MODE17, false},
 977         {GB_TILE_MODE18, false},
 978         {GB_TILE_MODE19, false},
 979         {GB_TILE_MODE20, false},
 980         {GB_TILE_MODE21, false},
 981         {GB_TILE_MODE22, false},
 982         {GB_TILE_MODE23, false},
 983         {GB_TILE_MODE24, false},
 984         {GB_TILE_MODE25, false},
 985         {GB_TILE_MODE26, false},
 986         {GB_TILE_MODE27, false},
 987         {GB_TILE_MODE28, false},
 988         {GB_TILE_MODE29, false},
 989         {GB_TILE_MODE30, false},
 990         {GB_TILE_MODE31, false},
 991         {CC_RB_BACKEND_DISABLE, false, true},
 992         {GC_USER_RB_BACKEND_DISABLE, false, true},
 993         {PA_SC_RASTER_CONFIG, false, true},
 994 };
 995
 996 static uint32_t si_read_indexed_register(struct amdgpu_device *adev,
 997                                           u32 se_num, u32 sh_num,
 998                                           u32 reg_offset)
 999 {
1000         uint32_t val;
1001
1002         mutex_lock(&adev->grbm_idx_mutex);
1003         if (se_num != 0xffffffff || sh_num != 0xffffffff)
1004                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
1005
1006         val = RREG32(reg_offset);
1007
1008         if (se_num != 0xffffffff || sh_num != 0xffffffff)
1009                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1010         mutex_unlock(&adev->grbm_idx_mutex);
1011         return val;
1012 }
1013
1014 static int si_read_register(struct amdgpu_device *adev, u32 se_num,
1015                              u32 sh_num, u32 reg_offset, u32 *value)
1016 {
1017         uint32_t i;
1018
1019         *value = 0;
1020         for (i = 0; i < ARRAY_SIZE(si_allowed_read_registers); i++) {
1021                 if (reg_offset != si_allowed_read_registers[i].reg_offset)
1022                         continue;
1023
1024                 if (!si_allowed_read_registers[i].untouched)
1025                         *value = si_allowed_read_registers[i].grbm_indexed ?
1026                                  si_read_indexed_register(adev, se_num,
1027                                                            sh_num, reg_offset) :
1028                                  RREG32(reg_offset);
1029                 return 0;
1030         }
1031         return -EINVAL;
1032 }
1033
1034 static bool si_read_disabled_bios(struct amdgpu_device *adev)
1035 {
1036         u32 bus_cntl;
1037         u32 d1vga_control = 0;
1038         u32 d2vga_control = 0;
1039         u32 vga_render_control = 0;
1040         u32 rom_cntl;
1041         bool r;
1042
1043         bus_cntl = RREG32(R600_BUS_CNTL);
1044         if (adev->mode_info.num_crtc) {
1045                 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
1046                 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
1047                 vga_render_control = RREG32(VGA_RENDER_CONTROL);
1048         }
1049         rom_cntl = RREG32(R600_ROM_CNTL);
1050
1051         /* enable the rom */
1052         WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
1053         if (adev->mode_info.num_crtc) {
1054                 /* Disable VGA mode */
1055                 WREG32(AVIVO_D1VGA_CONTROL,
1056                        (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
1057                                           AVIVO_DVGA_CONTROL_TIMING_SELECT)));
1058                 WREG32(AVIVO_D2VGA_CONTROL,
1059                        (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
1060                                           AVIVO_DVGA_CONTROL_TIMING_SELECT)));
1061                 WREG32(VGA_RENDER_CONTROL,
1062                        (vga_render_control & C_000300_VGA_VSTATUS_CNTL));
1063         }
1064         WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
1065
1066         r = amdgpu_read_bios(adev);
1067
1068         /* restore regs */
1069         WREG32(R600_BUS_CNTL, bus_cntl);
1070         if (adev->mode_info.num_crtc) {
1071                 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
1072                 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
1073                 WREG32(VGA_RENDER_CONTROL, vga_render_control);
1074         }
1075         WREG32(R600_ROM_CNTL, rom_cntl);
1076         return r;
1077 }
1078
1079 //xxx: not implemented
1080 static int si_asic_reset(struct amdgpu_device *adev)
1081 {
1082         return 0;
1083 }
1084
1085 static void si_vga_set_state(struct amdgpu_device *adev, bool state)
1086 {
1087         uint32_t temp;
1088
1089         temp = RREG32(CONFIG_CNTL);
1090         if (state == false) {
1091                 temp &= ~(1<<0);
1092                 temp |= (1<<1);
1093         } else {
1094                 temp &= ~(1<<1);
1095         }
1096         WREG32(CONFIG_CNTL, temp);
1097 }
1098
1099 static u32 si_get_xclk(struct amdgpu_device *adev)
1100 {
1101         u32 reference_clock = adev->clock.spll.reference_freq;
1102         u32 tmp;
1103
1104         tmp = RREG32(CG_CLKPIN_CNTL_2);
1105         if (tmp & MUX_TCLK_TO_XCLK)
1106                 return TCLK;
1107
1108         tmp = RREG32(CG_CLKPIN_CNTL);
1109         if (tmp & XTALIN_DIVIDE)
1110                 return reference_clock / 4;
1111
1112         return reference_clock;
1113 }
1114
1115 //xxx:not implemented
1116 static int si_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
1117 {
1118         return 0;
1119 }
1120
1121 static void si_detect_hw_virtualization(struct amdgpu_device *adev)
1122 {
1123         if (is_virtual_machine()) /* passthrough mode */
1124                 adev->virtualization.virtual_caps |= AMDGPU_PASSTHROUGH_MODE;
1125 }
1126
1127 static const struct amdgpu_asic_funcs si_asic_funcs =
1128 {
1129         .read_disabled_bios = &si_read_disabled_bios,
1130         .detect_hw_virtualization = si_detect_hw_virtualization,
1131         .read_register = &si_read_register,
1132         .reset = &si_asic_reset,
1133         .set_vga_state = &si_vga_set_state,
1134         .get_xclk = &si_get_xclk,
1135         .set_uvd_clocks = &si_set_uvd_clocks,
1136         .set_vce_clocks = NULL,
1137 };
1138
1139 static uint32_t si_get_rev_id(struct amdgpu_device *adev)
1140 {
1141         return (RREG32(CC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK)
1142                 >> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT;
1143 }
1144
1145 static int si_common_early_init(void *handle)
1146 {
1147         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1148
1149         adev->smc_rreg = &si_smc_rreg;
1150         adev->smc_wreg = &si_smc_wreg;
1151         adev->pcie_rreg = &si_pcie_rreg;
1152         adev->pcie_wreg = &si_pcie_wreg;
1153         adev->pciep_rreg = &si_pciep_rreg;
1154         adev->pciep_wreg = &si_pciep_wreg;
1155         adev->uvd_ctx_rreg = NULL;
1156         adev->uvd_ctx_wreg = NULL;
1157         adev->didt_rreg = NULL;
1158         adev->didt_wreg = NULL;
1159
1160         adev->asic_funcs = &si_asic_funcs;
1161
1162         adev->rev_id = si_get_rev_id(adev);
1163         adev->external_rev_id = 0xFF;
1164         switch (adev->asic_type) {
1165         case CHIP_TAHITI:
1166                 adev->cg_flags =
1167                         AMD_CG_SUPPORT_GFX_MGCG |
1168                         AMD_CG_SUPPORT_GFX_MGLS |
1169                         /*AMD_CG_SUPPORT_GFX_CGCG |*/
1170                         AMD_CG_SUPPORT_GFX_CGLS |
1171                         AMD_CG_SUPPORT_GFX_CGTS |
1172                         AMD_CG_SUPPORT_GFX_CP_LS |
1173                         AMD_CG_SUPPORT_MC_MGCG |
1174                         AMD_CG_SUPPORT_SDMA_MGCG |
1175                         AMD_CG_SUPPORT_BIF_LS |
1176                         AMD_CG_SUPPORT_VCE_MGCG |
1177                         AMD_CG_SUPPORT_UVD_MGCG |
1178                         AMD_CG_SUPPORT_HDP_LS |
1179                         AMD_CG_SUPPORT_HDP_MGCG;
1180                         adev->pg_flags = 0;
1181                 break;
1182         case CHIP_PITCAIRN:
1183                 adev->cg_flags =
1184                         AMD_CG_SUPPORT_GFX_MGCG |
1185                         AMD_CG_SUPPORT_GFX_MGLS |
1186                         /*AMD_CG_SUPPORT_GFX_CGCG |*/
1187                         AMD_CG_SUPPORT_GFX_CGLS |
1188                         AMD_CG_SUPPORT_GFX_CGTS |
1189                         AMD_CG_SUPPORT_GFX_CP_LS |
1190                         AMD_CG_SUPPORT_GFX_RLC_LS |
1191                         AMD_CG_SUPPORT_MC_LS |
1192                         AMD_CG_SUPPORT_MC_MGCG |
1193                         AMD_CG_SUPPORT_SDMA_MGCG |
1194                         AMD_CG_SUPPORT_BIF_LS |
1195                         AMD_CG_SUPPORT_VCE_MGCG |
1196                         AMD_CG_SUPPORT_UVD_MGCG |
1197                         AMD_CG_SUPPORT_HDP_LS |
1198                         AMD_CG_SUPPORT_HDP_MGCG;
1199                 adev->pg_flags = 0;
1200                 break;
1201
1202         case CHIP_VERDE:
1203                 adev->cg_flags =
1204                         AMD_CG_SUPPORT_GFX_MGCG |
1205                         AMD_CG_SUPPORT_GFX_MGLS |
1206                         AMD_CG_SUPPORT_GFX_CGLS |
1207                         AMD_CG_SUPPORT_GFX_CGTS |
1208                         AMD_CG_SUPPORT_GFX_CGTS_LS |
1209                         AMD_CG_SUPPORT_GFX_CP_LS |
1210                         AMD_CG_SUPPORT_MC_LS |
1211                         AMD_CG_SUPPORT_MC_MGCG |
1212                         AMD_CG_SUPPORT_SDMA_MGCG |
1213                         AMD_CG_SUPPORT_SDMA_LS |
1214                         AMD_CG_SUPPORT_BIF_LS |
1215                         AMD_CG_SUPPORT_VCE_MGCG |
1216                         AMD_CG_SUPPORT_UVD_MGCG |
1217                         AMD_CG_SUPPORT_HDP_LS |
1218                         AMD_CG_SUPPORT_HDP_MGCG;
1219                 adev->pg_flags = 0;
1220                 //???
1221                 adev->external_rev_id = adev->rev_id + 0x14;
1222                 break;
1223         case CHIP_OLAND:
1224                 adev->cg_flags =
1225                         AMD_CG_SUPPORT_GFX_MGCG |
1226                         AMD_CG_SUPPORT_GFX_MGLS |
1227                         /*AMD_CG_SUPPORT_GFX_CGCG |*/
1228                         AMD_CG_SUPPORT_GFX_CGLS |
1229                         AMD_CG_SUPPORT_GFX_CGTS |
1230                         AMD_CG_SUPPORT_GFX_CP_LS |
1231                         AMD_CG_SUPPORT_GFX_RLC_LS |
1232                         AMD_CG_SUPPORT_MC_LS |
1233                         AMD_CG_SUPPORT_MC_MGCG |
1234                         AMD_CG_SUPPORT_SDMA_MGCG |
1235                         AMD_CG_SUPPORT_BIF_LS |
1236                         AMD_CG_SUPPORT_UVD_MGCG |
1237                         AMD_CG_SUPPORT_HDP_LS |
1238                         AMD_CG_SUPPORT_HDP_MGCG;
1239                 adev->pg_flags = 0;
1240                 break;
1241         case CHIP_HAINAN:
1242                 adev->cg_flags =
1243                         AMD_CG_SUPPORT_GFX_MGCG |
1244                         AMD_CG_SUPPORT_GFX_MGLS |
1245                         /*AMD_CG_SUPPORT_GFX_CGCG |*/
1246                         AMD_CG_SUPPORT_GFX_CGLS |
1247                         AMD_CG_SUPPORT_GFX_CGTS |
1248                         AMD_CG_SUPPORT_GFX_CP_LS |
1249                         AMD_CG_SUPPORT_GFX_RLC_LS |
1250                         AMD_CG_SUPPORT_MC_LS |
1251                         AMD_CG_SUPPORT_MC_MGCG |
1252                         AMD_CG_SUPPORT_SDMA_MGCG |
1253                         AMD_CG_SUPPORT_BIF_LS |
1254                         AMD_CG_SUPPORT_HDP_LS |
1255                         AMD_CG_SUPPORT_HDP_MGCG;
1256                 adev->pg_flags = 0;
1257                 break;
1258
1259         default:
1260                 return -EINVAL;
1261         }
1262
1263         return 0;
1264 }
1265
1266 static int si_common_sw_init(void *handle)
1267 {
1268         return 0;
1269 }
1270
1271 static int si_common_sw_fini(void *handle)
1272 {
1273         return 0;
1274 }
1275
1276
1277 static void si_init_golden_registers(struct amdgpu_device *adev)
1278 {
1279         switch (adev->asic_type) {
1280         case CHIP_TAHITI:
1281                 amdgpu_program_register_sequence(adev,
1282                                                  tahiti_golden_registers,
1283                                                  (const u32)ARRAY_SIZE(tahiti_golden_registers));
1284                 amdgpu_program_register_sequence(adev,
1285                                                  tahiti_golden_rlc_registers,
1286                                                  (const u32)ARRAY_SIZE(tahiti_golden_rlc_registers));
1287                 amdgpu_program_register_sequence(adev,
1288                                                  tahiti_mgcg_cgcg_init,
1289                                                  (const u32)ARRAY_SIZE(tahiti_mgcg_cgcg_init));
1290                 amdgpu_program_register_sequence(adev,
1291                                                  tahiti_golden_registers2,
1292                                                  (const u32)ARRAY_SIZE(tahiti_golden_registers2));
1293                 break;
1294         case CHIP_PITCAIRN:
1295                 amdgpu_program_register_sequence(adev,
1296                                                  pitcairn_golden_registers,
1297                                                  (const u32)ARRAY_SIZE(pitcairn_golden_registers));
1298                 amdgpu_program_register_sequence(adev,
1299                                                  pitcairn_golden_rlc_registers,
1300                                                  (const u32)ARRAY_SIZE(pitcairn_golden_rlc_registers));
1301                 amdgpu_program_register_sequence(adev,
1302                                                  pitcairn_mgcg_cgcg_init,
1303                                                  (const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
1304         case CHIP_VERDE:
1305                 amdgpu_program_register_sequence(adev,
1306                                                  verde_golden_registers,
1307                                                  (const u32)ARRAY_SIZE(verde_golden_registers));
1308                 amdgpu_program_register_sequence(adev,
1309                                                  verde_golden_rlc_registers,
1310                                                  (const u32)ARRAY_SIZE(verde_golden_rlc_registers));
1311                 amdgpu_program_register_sequence(adev,
1312                                                  verde_mgcg_cgcg_init,
1313                                                  (const u32)ARRAY_SIZE(verde_mgcg_cgcg_init));
1314                 amdgpu_program_register_sequence(adev,
1315                                                  verde_pg_init,
1316                                                  (const u32)ARRAY_SIZE(verde_pg_init));
1317                 break;
1318         case CHIP_OLAND:
1319                 amdgpu_program_register_sequence(adev,
1320                                                  oland_golden_registers,
1321                                                  (const u32)ARRAY_SIZE(oland_golden_registers));
1322                 amdgpu_program_register_sequence(adev,
1323                                                  oland_golden_rlc_registers,
1324                                                  (const u32)ARRAY_SIZE(oland_golden_rlc_registers));
1325                 amdgpu_program_register_sequence(adev,
1326                                                  oland_mgcg_cgcg_init,
1327                                                  (const u32)ARRAY_SIZE(oland_mgcg_cgcg_init));
1328         case CHIP_HAINAN:
1329                 amdgpu_program_register_sequence(adev,
1330                                                  hainan_golden_registers,
1331                                                  (const u32)ARRAY_SIZE(hainan_golden_registers));
1332                 amdgpu_program_register_sequence(adev,
1333                                                  hainan_golden_registers2,
1334                                                  (const u32)ARRAY_SIZE(hainan_golden_registers2));
1335                 amdgpu_program_register_sequence(adev,
1336                                                  hainan_mgcg_cgcg_init,
1337                                                  (const u32)ARRAY_SIZE(hainan_mgcg_cgcg_init));
1338                 break;
1339
1340
1341         default:
1342                 BUG();
1343         }
1344 }
1345
1346 static void si_pcie_gen3_enable(struct amdgpu_device *adev)
1347 {
1348         struct pci_dev *root = adev->pdev->bus->self;
1349         int bridge_pos, gpu_pos;
1350         u32 speed_cntl, mask, current_data_rate;
1351         int ret, i;
1352         u16 tmp16;
1353
1354         if (pci_is_root_bus(adev->pdev->bus))
1355                 return;
1356
1357         if (amdgpu_pcie_gen2 == 0)
1358                 return;
1359
1360         if (adev->flags & AMD_IS_APU)
1361                 return;
1362
1363         ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
1364         if (ret != 0)
1365                 return;
1366
1367         if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80)))
1368                 return;
1369
1370         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1371         current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >>
1372                 LC_CURRENT_DATA_RATE_SHIFT;
1373         if (mask & DRM_PCIE_SPEED_80) {
1374                 if (current_data_rate == 2) {
1375                         DRM_INFO("PCIE gen 3 link speeds already enabled\n");
1376                         return;
1377                 }
1378                 DRM_INFO("enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n");
1379         } else if (mask & DRM_PCIE_SPEED_50) {
1380                 if (current_data_rate == 1) {
1381                         DRM_INFO("PCIE gen 2 link speeds already enabled\n");
1382                         return;
1383                 }
1384                 DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n");
1385         }
1386
1387         bridge_pos = pci_pcie_cap(root);
1388         if (!bridge_pos)
1389                 return;
1390
1391         gpu_pos = pci_pcie_cap(adev->pdev);
1392         if (!gpu_pos)
1393                 return;
1394
1395         if (mask & DRM_PCIE_SPEED_80) {
1396                 if (current_data_rate != 2) {
1397                         u16 bridge_cfg, gpu_cfg;
1398                         u16 bridge_cfg2, gpu_cfg2;
1399                         u32 max_lw, current_lw, tmp;
1400
1401                         pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
1402                         pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
1403
1404                         tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
1405                         pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
1406
1407                         tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
1408                         pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
1409
1410                         tmp = RREG32_PCIE(PCIE_LC_STATUS1);
1411                         max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
1412                         current_lw = (tmp & LC_OPERATING_LINK_WIDTH_MASK) >> LC_OPERATING_LINK_WIDTH_SHIFT;
1413
1414                         if (current_lw < max_lw) {
1415                                 tmp = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
1416                                 if (tmp & LC_RENEGOTIATION_SUPPORT) {
1417                                         tmp &= ~(LC_LINK_WIDTH_MASK | LC_UPCONFIGURE_DIS);
1418                                         tmp |= (max_lw << LC_LINK_WIDTH_SHIFT);
1419                                         tmp |= LC_UPCONFIGURE_SUPPORT | LC_RENEGOTIATE_EN | LC_RECONFIG_NOW;
1420                                         WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, tmp);
1421                                 }
1422                         }
1423
1424                         for (i = 0; i < 10; i++) {
1425                                 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16);
1426                                 if (tmp16 & PCI_EXP_DEVSTA_TRPND)
1427                                         break;
1428
1429                                 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
1430                                 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
1431
1432                                 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2);
1433                                 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2);
1434
1435                                 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
1436                                 tmp |= LC_SET_QUIESCE;
1437                                 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
1438
1439                                 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
1440                                 tmp |= LC_REDO_EQ;
1441                                 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
1442
1443                                 mdelay(100);
1444
1445                                 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16);
1446                                 tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
1447                                 tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
1448                                 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
1449
1450                                 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16);
1451                                 tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
1452                                 tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
1453                                 pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
1454
1455                                 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
1456                                 tmp16 &= ~((1 << 4) | (7 << 9));
1457                                 tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
1458                                 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
1459
1460                                 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
1461                                 tmp16 &= ~((1 << 4) | (7 << 9));
1462                                 tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
1463                                 pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
1464
1465                                 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
1466                                 tmp &= ~LC_SET_QUIESCE;
1467                                 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
1468                         }
1469                 }
1470         }
1471
1472         speed_cntl |= LC_FORCE_EN_SW_SPEED_CHANGE | LC_FORCE_DIS_HW_SPEED_CHANGE;
1473         speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE;
1474         WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
1475
1476         pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
1477         tmp16 &= ~0xf;
1478         if (mask & DRM_PCIE_SPEED_80)
1479                 tmp16 |= 3;
1480         else if (mask & DRM_PCIE_SPEED_50)
1481                 tmp16 |= 2;
1482         else
1483                 tmp16 |= 1;
1484         pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
1485
1486         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1487         speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;
1488         WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
1489
1490         for (i = 0; i < adev->usec_timeout; i++) {
1491                 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1492                 if ((speed_cntl & LC_INITIATE_LINK_SPEED_CHANGE) == 0)
1493                         break;
1494                 udelay(1);
1495         }
1496 }
1497
1498 static inline u32 si_pif_phy0_rreg(struct amdgpu_device *adev, u32 reg)
1499 {
1500         unsigned long flags;
1501         u32 r;
1502
1503         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1504         WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
1505         r = RREG32(EVERGREEN_PIF_PHY0_DATA);
1506         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1507         return r;
1508 }
1509
1510 static inline void si_pif_phy0_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
1511 {
1512         unsigned long flags;
1513
1514         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1515         WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
1516         WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
1517         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1518 }
1519
1520 static inline u32 si_pif_phy1_rreg(struct amdgpu_device *adev, u32 reg)
1521 {
1522         unsigned long flags;
1523         u32 r;
1524
1525         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1526         WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
1527         r = RREG32(EVERGREEN_PIF_PHY1_DATA);
1528         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1529         return r;
1530 }
1531
1532 static inline void si_pif_phy1_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
1533 {
1534         unsigned long flags;
1535
1536         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1537         WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
1538         WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
1539         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1540 }
1541 static void si_program_aspm(struct amdgpu_device *adev)
1542 {
1543         u32 data, orig;
1544         bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false;
1545         bool disable_clkreq = false;
1546
1547         if (amdgpu_aspm == 0)
1548                 return;
1549
1550         if (adev->flags & AMD_IS_APU)
1551                 return;
1552         orig = data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
1553         data &= ~LC_XMIT_N_FTS_MASK;
1554         data |= LC_XMIT_N_FTS(0x24) | LC_XMIT_N_FTS_OVERRIDE_EN;
1555         if (orig != data)
1556                 WREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL, data);
1557
1558         orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL3);
1559         data |= LC_GO_TO_RECOVERY;
1560         if (orig != data)
1561                 WREG32_PCIE_PORT(PCIE_LC_CNTL3, data);
1562
1563         orig = data = RREG32_PCIE(PCIE_P_CNTL);
1564         data |= P_IGNORE_EDB_ERR;
1565         if (orig != data)
1566                 WREG32_PCIE(PCIE_P_CNTL, data);
1567
1568         orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
1569         data &= ~(LC_L0S_INACTIVITY_MASK | LC_L1_INACTIVITY_MASK);
1570         data |= LC_PMI_TO_L1_DIS;
1571         if (!disable_l0s)
1572                 data |= LC_L0S_INACTIVITY(7);
1573
1574         if (!disable_l1) {
1575                 data |= LC_L1_INACTIVITY(7);
1576                 data &= ~LC_PMI_TO_L1_DIS;
1577                 if (orig != data)
1578                         WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
1579
1580                 if (!disable_plloff_in_l1) {
1581                         bool clk_req_support;
1582
1583                         orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0);
1584                         data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
1585                         data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
1586                         if (orig != data)
1587                                 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_0, data);
1588
1589                         orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_1);
1590                         data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
1591                         data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
1592                         if (orig != data)
1593                                 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_1, data);
1594
1595                         orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_0);
1596                         data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
1597                         data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
1598                         if (orig != data)
1599                                 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_0, data);
1600
1601                         orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_1);
1602                         data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
1603                         data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
1604                         if (orig != data)
1605                                 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data);
1606
1607                         if ((adev->family != CHIP_OLAND) && (adev->family != CHIP_HAINAN)) {
1608                                 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0);
1609                                 data &= ~PLL_RAMP_UP_TIME_0_MASK;
1610                                 if (orig != data)
1611                                         si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_0, data);
1612
1613                                 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_1);
1614                                 data &= ~PLL_RAMP_UP_TIME_1_MASK;
1615                                 if (orig != data)
1616                                         si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_1, data);
1617
1618                                 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_2);
1619                                 data &= ~PLL_RAMP_UP_TIME_2_MASK;
1620                                 if (orig != data)
1621                                         si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_2, data);
1622
1623                                 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_3);
1624                                 data &= ~PLL_RAMP_UP_TIME_3_MASK;
1625                                 if (orig != data)
1626                                         si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_3, data);
1627
1628                                 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_0);
1629                                 data &= ~PLL_RAMP_UP_TIME_0_MASK;
1630                                 if (orig != data)
1631                                         si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_0, data);
1632
1633                                 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_1);
1634                                 data &= ~PLL_RAMP_UP_TIME_1_MASK;
1635                                 if (orig != data)
1636                                         si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data);
1637
1638                                 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_2);
1639                                 data &= ~PLL_RAMP_UP_TIME_2_MASK;
1640                                 if (orig != data)
1641                                         si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_2, data);
1642
1643                                 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_3);
1644                                 data &= ~PLL_RAMP_UP_TIME_3_MASK;
1645                                 if (orig != data)
1646                                         si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_3, data);
1647                         }
1648                         orig = data = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
1649                         data &= ~LC_DYN_LANES_PWR_STATE_MASK;
1650                         data |= LC_DYN_LANES_PWR_STATE(3);
1651                         if (orig != data)
1652                                 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, data);
1653
1654                         orig = data = si_pif_phy0_rreg(adev,PB0_PIF_CNTL);
1655                         data &= ~LS2_EXIT_TIME_MASK;
1656                         if ((adev->family == CHIP_OLAND) || (adev->family == CHIP_HAINAN))
1657                                 data |= LS2_EXIT_TIME(5);
1658                         if (orig != data)
1659                                 si_pif_phy0_wreg(adev,PB0_PIF_CNTL, data);
1660
1661                         orig = data = si_pif_phy1_rreg(adev,PB1_PIF_CNTL);
1662                         data &= ~LS2_EXIT_TIME_MASK;
1663                         if ((adev->family == CHIP_OLAND) || (adev->family == CHIP_HAINAN))
1664                                 data |= LS2_EXIT_TIME(5);
1665                         if (orig != data)
1666                                 si_pif_phy1_wreg(adev,PB1_PIF_CNTL, data);
1667
1668                         if (!disable_clkreq &&
1669                             !pci_is_root_bus(adev->pdev->bus)) {
1670                                 struct pci_dev *root = adev->pdev->bus->self;
1671                                 u32 lnkcap;
1672
1673                                 clk_req_support = false;
1674                                 pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap);
1675                                 if (lnkcap & PCI_EXP_LNKCAP_CLKPM)
1676                                         clk_req_support = true;
1677                         } else {
1678                                 clk_req_support = false;
1679                         }
1680
1681                         if (clk_req_support) {
1682                                 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL2);
1683                                 data |= LC_ALLOW_PDWN_IN_L1 | LC_ALLOW_PDWN_IN_L23;
1684                                 if (orig != data)
1685                                         WREG32_PCIE_PORT(PCIE_LC_CNTL2, data);
1686
1687                                 orig = data = RREG32(THM_CLK_CNTL);
1688                                 data &= ~(CMON_CLK_SEL_MASK | TMON_CLK_SEL_MASK);
1689                                 data |= CMON_CLK_SEL(1) | TMON_CLK_SEL(1);
1690                                 if (orig != data)
1691                                         WREG32(THM_CLK_CNTL, data);
1692
1693                                 orig = data = RREG32(MISC_CLK_CNTL);
1694                                 data &= ~(DEEP_SLEEP_CLK_SEL_MASK | ZCLK_SEL_MASK);
1695                                 data |= DEEP_SLEEP_CLK_SEL(1) | ZCLK_SEL(1);
1696                                 if (orig != data)
1697                                         WREG32(MISC_CLK_CNTL, data);
1698
1699                                 orig = data = RREG32(CG_CLKPIN_CNTL);
1700                                 data &= ~BCLK_AS_XCLK;
1701                                 if (orig != data)
1702                                         WREG32(CG_CLKPIN_CNTL, data);
1703
1704                                 orig = data = RREG32(CG_CLKPIN_CNTL_2);
1705                                 data &= ~FORCE_BIF_REFCLK_EN;
1706                                 if (orig != data)
1707                                         WREG32(CG_CLKPIN_CNTL_2, data);
1708
1709                                 orig = data = RREG32(MPLL_BYPASSCLK_SEL);
1710                                 data &= ~MPLL_CLKOUT_SEL_MASK;
1711                                 data |= MPLL_CLKOUT_SEL(4);
1712                                 if (orig != data)
1713                                         WREG32(MPLL_BYPASSCLK_SEL, data);
1714
1715                                 orig = data = RREG32(SPLL_CNTL_MODE);
1716                                 data &= ~SPLL_REFCLK_SEL_MASK;
1717                                 if (orig != data)
1718                                         WREG32(SPLL_CNTL_MODE, data);
1719                         }
1720                 }
1721         } else {
1722                 if (orig != data)
1723                         WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
1724         }
1725
1726         orig = data = RREG32_PCIE(PCIE_CNTL2);
1727         data |= SLV_MEM_LS_EN | MST_MEM_LS_EN | REPLAY_MEM_LS_EN;
1728         if (orig != data)
1729                 WREG32_PCIE(PCIE_CNTL2, data);
1730
1731         if (!disable_l0s) {
1732                 data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
1733                 if((data & LC_N_FTS_MASK) == LC_N_FTS_MASK) {
1734                         data = RREG32_PCIE(PCIE_LC_STATUS1);
1735                         if ((data & LC_REVERSE_XMIT) && (data & LC_REVERSE_RCVR)) {
1736                                 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
1737                                 data &= ~LC_L0S_INACTIVITY_MASK;
1738                                 if (orig != data)
1739                                         WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
1740                         }
1741                 }
1742         }
1743 }
1744
1745 static void si_fix_pci_max_read_req_size(struct amdgpu_device *adev)
1746 {
1747         int readrq;
1748         u16 v;
1749
1750         readrq = pcie_get_readrq(adev->pdev);
1751         v = ffs(readrq) - 8;
1752         if ((v == 0) || (v == 6) || (v == 7))
1753                 pcie_set_readrq(adev->pdev, 512);
1754 }
1755
1756 static int si_common_hw_init(void *handle)
1757 {
1758         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1759
1760         si_fix_pci_max_read_req_size(adev);
1761         si_init_golden_registers(adev);
1762         si_pcie_gen3_enable(adev);
1763         si_program_aspm(adev);
1764
1765         return 0;
1766 }
1767
1768 static int si_common_hw_fini(void *handle)
1769 {
1770         return 0;
1771 }
1772
1773 static int si_common_suspend(void *handle)
1774 {
1775         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1776
1777         return si_common_hw_fini(adev);
1778 }
1779
1780 static int si_common_resume(void *handle)
1781 {
1782         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1783
1784         return si_common_hw_init(adev);
1785 }
1786
1787 static bool si_common_is_idle(void *handle)
1788 {
1789         return true;
1790 }
1791
1792 static int si_common_wait_for_idle(void *handle)
1793 {
1794         return 0;
1795 }
1796
1797 static int si_common_soft_reset(void *handle)
1798 {
1799         return 0;
1800 }
1801
1802 static int si_common_set_clockgating_state(void *handle,
1803                                             enum amd_clockgating_state state)
1804 {
1805         return 0;
1806 }
1807
1808 static int si_common_set_powergating_state(void *handle,
1809                                             enum amd_powergating_state state)
1810 {
1811         return 0;
1812 }
1813
1814 const struct amd_ip_funcs si_common_ip_funcs = {
1815         .name = "si_common",
1816         .early_init = si_common_early_init,
1817         .late_init = NULL,
1818         .sw_init = si_common_sw_init,
1819         .sw_fini = si_common_sw_fini,
1820         .hw_init = si_common_hw_init,
1821         .hw_fini = si_common_hw_fini,
1822         .suspend = si_common_suspend,
1823         .resume = si_common_resume,
1824         .is_idle = si_common_is_idle,
1825         .wait_for_idle = si_common_wait_for_idle,
1826         .soft_reset = si_common_soft_reset,
1827         .set_clockgating_state = si_common_set_clockgating_state,
1828         .set_powergating_state = si_common_set_powergating_state,
1829 };
1830
1831 static const struct amdgpu_ip_block_version verde_ip_blocks[] =
1832 {
1833         {
1834                 .type = AMD_IP_BLOCK_TYPE_COMMON,
1835                 .major = 1,
1836                 .minor = 0,
1837                 .rev = 0,
1838                 .funcs = &si_common_ip_funcs,
1839         },
1840         {
1841                 .type = AMD_IP_BLOCK_TYPE_GMC,
1842                 .major = 6,
1843                 .minor = 0,
1844                 .rev = 0,
1845                 .funcs = &gmc_v6_0_ip_funcs,
1846         },
1847         {
1848                 .type = AMD_IP_BLOCK_TYPE_IH,
1849                 .major = 1,
1850                 .minor = 0,
1851                 .rev = 0,
1852                 .funcs = &si_ih_ip_funcs,
1853         },
1854         {
1855                 .type = AMD_IP_BLOCK_TYPE_SMC,
1856                 .major = 6,
1857                 .minor = 0,
1858                 .rev = 0,
1859                 .funcs = &amdgpu_pp_ip_funcs,
1860         },
1861         {
1862                 .type = AMD_IP_BLOCK_TYPE_DCE,
1863                 .major = 6,
1864                 .minor = 0,
1865                 .rev = 0,
1866                 .funcs = &dce_v6_0_ip_funcs,
1867         },
1868         {
1869                 .type = AMD_IP_BLOCK_TYPE_GFX,
1870                 .major = 6,
1871                 .minor = 0,
1872                 .rev = 0,
1873                 .funcs = &gfx_v6_0_ip_funcs,
1874         },
1875         {
1876                 .type = AMD_IP_BLOCK_TYPE_SDMA,
1877                 .major = 1,
1878                 .minor = 0,
1879                 .rev = 0,
1880                 .funcs = &si_dma_ip_funcs,
1881         },
1882 /*      {
1883                 .type = AMD_IP_BLOCK_TYPE_UVD,
1884                 .major = 3,
1885                 .minor = 1,
1886                 .rev = 0,
1887                 .funcs = &si_null_ip_funcs,
1888         },
1889         {
1890                 .type = AMD_IP_BLOCK_TYPE_VCE,
1891                 .major = 1,
1892                 .minor = 0,
1893                 .rev = 0,
1894                 .funcs = &si_null_ip_funcs,
1895         },
1896         */
1897 };
1898
1899
1900 static const struct amdgpu_ip_block_version hainan_ip_blocks[] =
1901 {
1902         {
1903                 .type = AMD_IP_BLOCK_TYPE_COMMON,
1904                 .major = 1,
1905                 .minor = 0,
1906                 .rev = 0,
1907                 .funcs = &si_common_ip_funcs,
1908         },
1909         {
1910                 .type = AMD_IP_BLOCK_TYPE_GMC,
1911                 .major = 6,
1912                 .minor = 0,
1913                 .rev = 0,
1914                 .funcs = &gmc_v6_0_ip_funcs,
1915         },
1916         {
1917                 .type = AMD_IP_BLOCK_TYPE_IH,
1918                 .major = 1,
1919                 .minor = 0,
1920                 .rev = 0,
1921                 .funcs = &si_ih_ip_funcs,
1922         },
1923         {
1924                 .type = AMD_IP_BLOCK_TYPE_SMC,
1925                 .major = 6,
1926                 .minor = 0,
1927                 .rev = 0,
1928                 .funcs = &amdgpu_pp_ip_funcs,
1929         },
1930         {
1931                 .type = AMD_IP_BLOCK_TYPE_GFX,
1932                 .major = 6,
1933                 .minor = 0,
1934                 .rev = 0,
1935                 .funcs = &gfx_v6_0_ip_funcs,
1936         },
1937         {
1938                 .type = AMD_IP_BLOCK_TYPE_SDMA,
1939                 .major = 1,
1940                 .minor = 0,
1941                 .rev = 0,
1942                 .funcs = &si_dma_ip_funcs,
1943         },
1944 };
1945
1946 int si_set_ip_blocks(struct amdgpu_device *adev)
1947 {
1948         switch (adev->asic_type) {
1949         case CHIP_VERDE:
1950         case CHIP_TAHITI:
1951         case CHIP_PITCAIRN:
1952         case CHIP_OLAND:
1953                 adev->ip_blocks = verde_ip_blocks;
1954                 adev->num_ip_blocks = ARRAY_SIZE(verde_ip_blocks);
1955                 break;
1956         case CHIP_HAINAN:
1957                 adev->ip_blocks = hainan_ip_blocks;
1958                 adev->num_ip_blocks = ARRAY_SIZE(hainan_ip_blocks);
1959                 break;
1960         default:
1961                 BUG();
1962         }
1963         return 0;
1964 }
1965