2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 #include "amd_shared.h"
32 * enum cgs_gpu_mem_type - GPU memory types
34 enum cgs_gpu_mem_type {
35 CGS_GPU_MEM_TYPE__VISIBLE_FB,
36 CGS_GPU_MEM_TYPE__INVISIBLE_FB,
37 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
38 CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB,
39 CGS_GPU_MEM_TYPE__GART_CACHEABLE,
40 CGS_GPU_MEM_TYPE__GART_WRITECOMBINE
44 * enum cgs_ind_reg - Indirect register spaces
53 CGS_IND_REG__AUDIO_ENDPT
57 * enum cgs_clock - Clocks controlled by the SMU
71 * enum cgs_engine - Engines that can be statically power-gated
85 * enum cgs_voltage_planes - Voltage planes for external camera HW
87 enum cgs_voltage_planes {
88 CGS_VOLTAGE_PLANE__SENSOR0,
89 CGS_VOLTAGE_PLANE__SENSOR1,
94 * enum cgs_ucode_id - Firmware types for different IPs
105 CGS_UCODE_ID_CP_MEC_JT1,
106 CGS_UCODE_ID_CP_MEC_JT2,
107 CGS_UCODE_ID_GMCON_RENG,
109 CGS_UCODE_ID_MAXIMUM,
112 enum cgs_system_info_id {
113 CGS_SYSTEM_INFO_ADAPTER_BDF_ID = 1,
114 CGS_SYSTEM_INFO_PCIE_GEN_INFO,
115 CGS_SYSTEM_INFO_PCIE_MLW,
116 CGS_SYSTEM_INFO_PCIE_DEV,
117 CGS_SYSTEM_INFO_PCIE_REV,
118 CGS_SYSTEM_INFO_CG_FLAGS,
119 CGS_SYSTEM_INFO_PG_FLAGS,
120 CGS_SYSTEM_INFO_GFX_CU_INFO,
121 CGS_SYSTEM_INFO_GFX_SE_INFO,
122 CGS_SYSTEM_INFO_ID_MAXIMUM,
125 struct cgs_system_info {
127 enum cgs_system_info_id info_id;
132 uint64_t padding[13];
136 * enum cgs_resource_type - GPU resource type
138 enum cgs_resource_type {
139 CGS_RESOURCE_TYPE_MMIO = 0,
140 CGS_RESOURCE_TYPE_FB,
141 CGS_RESOURCE_TYPE_IO,
142 CGS_RESOURCE_TYPE_DOORBELL,
143 CGS_RESOURCE_TYPE_ROM,
147 * struct cgs_clock_limits - Clock limits
149 * Clocks are specified in 10KHz units.
151 struct cgs_clock_limits {
152 unsigned min; /**< Minimum supported frequency */
153 unsigned max; /**< Maxumim supported frequency */
154 unsigned sustainable; /**< Thermally sustainable frequency */
158 * struct cgs_firmware_info - Firmware information
160 struct cgs_firmware_info {
162 uint16_t feature_version;
166 /* only for smc firmware */
167 uint32_t ucode_start_address;
172 struct cgs_mode_info {
173 uint32_t refresh_rate;
175 uint32_t vblank_time_us;
178 struct cgs_display_info {
179 uint32_t display_count;
180 uint32_t active_display_mask;
181 struct cgs_mode_info *mode_info;
184 typedef unsigned long cgs_handle_t;
186 #define CGS_ACPI_METHOD_ATCS 0x53435441
187 #define CGS_ACPI_METHOD_ATIF 0x46495441
188 #define CGS_ACPI_METHOD_ATPX 0x58505441
189 #define CGS_ACPI_FIELD_METHOD_NAME 0x00000001
190 #define CGS_ACPI_FIELD_INPUT_ARGUMENT_COUNT 0x00000002
191 #define CGS_ACPI_MAX_BUFFER_SIZE 256
192 #define CGS_ACPI_TYPE_ANY 0x00
193 #define CGS_ACPI_TYPE_INTEGER 0x01
194 #define CGS_ACPI_TYPE_STRING 0x02
195 #define CGS_ACPI_TYPE_BUFFER 0x03
196 #define CGS_ACPI_TYPE_PACKAGE 0x04
198 struct cgs_acpi_method_argument {
200 uint32_t data_length;
207 struct cgs_acpi_method_info {
210 uint32_t input_count;
212 struct cgs_acpi_method_argument *pinput_argument;
213 uint32_t output_count;
214 struct cgs_acpi_method_argument *poutput_argument;
219 * cgs_gpu_mem_info() - Return information about memory heaps
220 * @cgs_device: opaque device handle
222 * @mc_start: Start MC address of the heap (output)
223 * @mc_size: MC address space size (output)
224 * @mem_size: maximum amount of memory available for allocation (output)
226 * This function returns information about memory heaps. The type
227 * parameter is used to select the memory heap. The mc_start and
228 * mc_size for GART heaps may be bigger than the memory available for
231 * mc_start and mc_size are undefined for non-contiguous FB memory
232 * types, since buffers allocated with these types may or may not be
235 * Return: 0 on success, -errno otherwise
237 typedef int (*cgs_gpu_mem_info_t)(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type,
238 uint64_t *mc_start, uint64_t *mc_size,
242 * cgs_gmap_kmem() - map kernel memory to GART aperture
243 * @cgs_device: opaque device handle
244 * @kmem: pointer to kernel memory
246 * @min_offset: minimum offset from start of GART aperture
247 * @max_offset: maximum offset from start of GART aperture
248 * @kmem_handle: kernel memory handle (output)
249 * @mcaddr: MC address (output)
251 * Return: 0 on success, -errno otherwise
253 typedef int (*cgs_gmap_kmem_t)(struct cgs_device *cgs_device, void *kmem, uint64_t size,
254 uint64_t min_offset, uint64_t max_offset,
255 cgs_handle_t *kmem_handle, uint64_t *mcaddr);
258 * cgs_gunmap_kmem() - unmap kernel memory
259 * @cgs_device: opaque device handle
260 * @kmem_handle: kernel memory handle returned by gmap_kmem
262 * Return: 0 on success, -errno otherwise
264 typedef int (*cgs_gunmap_kmem_t)(struct cgs_device *cgs_device, cgs_handle_t kmem_handle);
267 * cgs_alloc_gpu_mem() - Allocate GPU memory
268 * @cgs_device: opaque device handle
270 * @size: size in bytes
271 * @align: alignment in bytes
272 * @min_offset: minimum offset from start of heap
273 * @max_offset: maximum offset from start of heap
274 * @handle: memory handle (output)
276 * The memory types CGS_GPU_MEM_TYPE_*_CONTIG_FB force contiguous
277 * memory allocation. This guarantees that the MC address returned by
278 * cgs_gmap_gpu_mem is not mapped through the GART. The non-contiguous
279 * FB memory types may be GART mapped depending on memory
280 * fragmentation and memory allocator policies.
282 * If min/max_offset are non-0, the allocation will be forced to
283 * reside between these offsets in its respective memory heap. The
284 * base address that the offset relates to, depends on the memory
287 * - CGS_GPU_MEM_TYPE__*_CONTIG_FB: FB MC base address
288 * - CGS_GPU_MEM_TYPE__GART_*: GART aperture base address
289 * - others: undefined, don't use with max_offset
291 * Return: 0 on success, -errno otherwise
293 typedef int (*cgs_alloc_gpu_mem_t)(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type,
294 uint64_t size, uint64_t align,
295 uint64_t min_offset, uint64_t max_offset,
296 cgs_handle_t *handle);
299 * cgs_free_gpu_mem() - Free GPU memory
300 * @cgs_device: opaque device handle
301 * @handle: memory handle returned by alloc or import
303 * Return: 0 on success, -errno otherwise
305 typedef int (*cgs_free_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle);
308 * cgs_gmap_gpu_mem() - GPU-map GPU memory
309 * @cgs_device: opaque device handle
310 * @handle: memory handle returned by alloc or import
311 * @mcaddr: MC address (output)
313 * Ensures that a buffer is GPU accessible and returns its MC address.
315 * Return: 0 on success, -errno otherwise
317 typedef int (*cgs_gmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle,
321 * cgs_gunmap_gpu_mem() - GPU-unmap GPU memory
322 * @cgs_device: opaque device handle
323 * @handle: memory handle returned by alloc or import
325 * Allows the buffer to be migrated while it's not used by the GPU.
327 * Return: 0 on success, -errno otherwise
329 typedef int (*cgs_gunmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle);
332 * cgs_kmap_gpu_mem() - Kernel-map GPU memory
334 * @cgs_device: opaque device handle
335 * @handle: memory handle returned by alloc or import
336 * @map: Kernel virtual address the memory was mapped to (output)
338 * Return: 0 on success, -errno otherwise
340 typedef int (*cgs_kmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle,
344 * cgs_kunmap_gpu_mem() - Kernel-unmap GPU memory
345 * @cgs_device: opaque device handle
346 * @handle: memory handle returned by alloc or import
348 * Return: 0 on success, -errno otherwise
350 typedef int (*cgs_kunmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle);
353 * cgs_read_register() - Read an MMIO register
354 * @cgs_device: opaque device handle
355 * @offset: register offset
357 * Return: register value
359 typedef uint32_t (*cgs_read_register_t)(struct cgs_device *cgs_device, unsigned offset);
362 * cgs_write_register() - Write an MMIO register
363 * @cgs_device: opaque device handle
364 * @offset: register offset
365 * @value: register value
367 typedef void (*cgs_write_register_t)(struct cgs_device *cgs_device, unsigned offset,
371 * cgs_read_ind_register() - Read an indirect register
372 * @cgs_device: opaque device handle
373 * @offset: register offset
375 * Return: register value
377 typedef uint32_t (*cgs_read_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space,
381 * cgs_write_ind_register() - Write an indirect register
382 * @cgs_device: opaque device handle
383 * @offset: register offset
384 * @value: register value
386 typedef void (*cgs_write_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space,
387 unsigned index, uint32_t value);
390 * cgs_read_pci_config_byte() - Read byte from PCI configuration space
391 * @cgs_device: opaque device handle
396 typedef uint8_t (*cgs_read_pci_config_byte_t)(struct cgs_device *cgs_device, unsigned addr);
399 * cgs_read_pci_config_word() - Read word from PCI configuration space
400 * @cgs_device: opaque device handle
401 * @addr: address, must be word-aligned
405 typedef uint16_t (*cgs_read_pci_config_word_t)(struct cgs_device *cgs_device, unsigned addr);
408 * cgs_read_pci_config_dword() - Read dword from PCI configuration space
409 * @cgs_device: opaque device handle
410 * @addr: address, must be dword-aligned
414 typedef uint32_t (*cgs_read_pci_config_dword_t)(struct cgs_device *cgs_device,
418 * cgs_write_pci_config_byte() - Write byte to PCI configuration space
419 * @cgs_device: opaque device handle
421 * @value: value to write
423 typedef void (*cgs_write_pci_config_byte_t)(struct cgs_device *cgs_device, unsigned addr,
427 * cgs_write_pci_config_word() - Write byte to PCI configuration space
428 * @cgs_device: opaque device handle
429 * @addr: address, must be word-aligned
430 * @value: value to write
432 typedef void (*cgs_write_pci_config_word_t)(struct cgs_device *cgs_device, unsigned addr,
436 * cgs_write_pci_config_dword() - Write byte to PCI configuration space
437 * @cgs_device: opaque device handle
438 * @addr: address, must be dword-aligned
439 * @value: value to write
441 typedef void (*cgs_write_pci_config_dword_t)(struct cgs_device *cgs_device, unsigned addr,
446 * cgs_get_pci_resource() - provide access to a device resource (PCI BAR)
447 * @cgs_device: opaque device handle
448 * @resource_type: Type of Resource (MMIO, IO, ROM, FB, DOORBELL)
449 * @size: size of the region
450 * @offset: offset from the start of the region
451 * @resource_base: base address (not including offset) returned
453 * Return: 0 on success, -errno otherwise
455 typedef int (*cgs_get_pci_resource_t)(struct cgs_device *cgs_device,
456 enum cgs_resource_type resource_type,
459 uint64_t *resource_base);
462 * cgs_atom_get_data_table() - Get a pointer to an ATOM BIOS data table
463 * @cgs_device: opaque device handle
464 * @table: data table index
465 * @size: size of the table (output, may be NULL)
466 * @frev: table format revision (output, may be NULL)
467 * @crev: table content revision (output, may be NULL)
469 * Return: Pointer to start of the table, or NULL on failure
471 typedef const void *(*cgs_atom_get_data_table_t)(
472 struct cgs_device *cgs_device, unsigned table,
473 uint16_t *size, uint8_t *frev, uint8_t *crev);
476 * cgs_atom_get_cmd_table_revs() - Get ATOM BIOS command table revisions
477 * @cgs_device: opaque device handle
478 * @table: data table index
479 * @frev: table format revision (output, may be NULL)
480 * @crev: table content revision (output, may be NULL)
482 * Return: 0 on success, -errno otherwise
484 typedef int (*cgs_atom_get_cmd_table_revs_t)(struct cgs_device *cgs_device, unsigned table,
485 uint8_t *frev, uint8_t *crev);
488 * cgs_atom_exec_cmd_table() - Execute an ATOM BIOS command table
489 * @cgs_device: opaque device handle
490 * @table: command table index
493 * Return: 0 on success, -errno otherwise
495 typedef int (*cgs_atom_exec_cmd_table_t)(struct cgs_device *cgs_device,
496 unsigned table, void *args);
499 * cgs_create_pm_request() - Create a power management request
500 * @cgs_device: opaque device handle
501 * @request: handle of created PM request (output)
503 * Return: 0 on success, -errno otherwise
505 typedef int (*cgs_create_pm_request_t)(struct cgs_device *cgs_device, cgs_handle_t *request);
508 * cgs_destroy_pm_request() - Destroy a power management request
509 * @cgs_device: opaque device handle
510 * @request: handle of created PM request
512 * Return: 0 on success, -errno otherwise
514 typedef int (*cgs_destroy_pm_request_t)(struct cgs_device *cgs_device, cgs_handle_t request);
517 * cgs_set_pm_request() - Activate or deactiveate a PM request
518 * @cgs_device: opaque device handle
519 * @request: PM request handle
520 * @active: 0 = deactivate, non-0 = activate
522 * While a PM request is active, its minimum clock requests are taken
523 * into account as the requested engines are powered up. When the
524 * request is inactive, the engines may be powered down and clocks may
525 * be lower, depending on other PM requests by other driver
528 * Return: 0 on success, -errno otherwise
530 typedef int (*cgs_set_pm_request_t)(struct cgs_device *cgs_device, cgs_handle_t request,
534 * cgs_pm_request_clock() - Request a minimum frequency for a specific clock
535 * @cgs_device: opaque device handle
536 * @request: PM request handle
537 * @clock: which clock?
538 * @freq: requested min. frequency in 10KHz units (0 to clear request)
540 * Return: 0 on success, -errno otherwise
542 typedef int (*cgs_pm_request_clock_t)(struct cgs_device *cgs_device, cgs_handle_t request,
543 enum cgs_clock clock, unsigned freq);
546 * cgs_pm_request_engine() - Request an engine to be powered up
547 * @cgs_device: opaque device handle
548 * @request: PM request handle
549 * @engine: which engine?
550 * @powered: 0 = powered down, non-0 = powered up
552 * Return: 0 on success, -errno otherwise
554 typedef int (*cgs_pm_request_engine_t)(struct cgs_device *cgs_device, cgs_handle_t request,
555 enum cgs_engine engine, int powered);
558 * cgs_pm_query_clock_limits() - Query clock frequency limits
559 * @cgs_device: opaque device handle
560 * @clock: which clock?
561 * @limits: clock limits
563 * Return: 0 on success, -errno otherwise
565 typedef int (*cgs_pm_query_clock_limits_t)(struct cgs_device *cgs_device,
566 enum cgs_clock clock,
567 struct cgs_clock_limits *limits);
570 * cgs_set_camera_voltages() - Apply specific voltages to PMIC voltage planes
571 * @cgs_device: opaque device handle
572 * @mask: bitmask of voltages to change (1<<CGS_VOLTAGE_PLANE__xyz|...)
573 * @voltages: pointer to array of voltage values in 1mV units
575 * Return: 0 on success, -errno otherwise
577 typedef int (*cgs_set_camera_voltages_t)(struct cgs_device *cgs_device, uint32_t mask,
578 const uint32_t *voltages);
580 * cgs_get_firmware_info - Get the firmware information from core driver
581 * @cgs_device: opaque device handle
582 * @type: the firmware type
583 * @info: returend firmware information
585 * Return: 0 on success, -errno otherwise
587 typedef int (*cgs_get_firmware_info)(struct cgs_device *cgs_device,
588 enum cgs_ucode_id type,
589 struct cgs_firmware_info *info);
591 typedef int (*cgs_rel_firmware)(struct cgs_device *cgs_device,
592 enum cgs_ucode_id type);
594 typedef int(*cgs_set_powergating_state)(struct cgs_device *cgs_device,
595 enum amd_ip_block_type block_type,
596 enum amd_powergating_state state);
598 typedef int(*cgs_set_clockgating_state)(struct cgs_device *cgs_device,
599 enum amd_ip_block_type block_type,
600 enum amd_clockgating_state state);
602 typedef int(*cgs_get_active_displays_info)(
603 struct cgs_device *cgs_device,
604 struct cgs_display_info *info);
606 typedef int (*cgs_notify_dpm_enabled)(struct cgs_device *cgs_device, bool enabled);
608 typedef int (*cgs_call_acpi_method)(struct cgs_device *cgs_device,
609 uint32_t acpi_method,
610 uint32_t acpi_function,
611 void *pinput, void *poutput,
612 uint32_t output_count,
614 uint32_t output_size);
616 typedef int (*cgs_query_system_info)(struct cgs_device *cgs_device,
617 struct cgs_system_info *sys_info);
620 /* memory management calls (similar to KFD interface) */
621 cgs_gpu_mem_info_t gpu_mem_info;
622 cgs_gmap_kmem_t gmap_kmem;
623 cgs_gunmap_kmem_t gunmap_kmem;
624 cgs_alloc_gpu_mem_t alloc_gpu_mem;
625 cgs_free_gpu_mem_t free_gpu_mem;
626 cgs_gmap_gpu_mem_t gmap_gpu_mem;
627 cgs_gunmap_gpu_mem_t gunmap_gpu_mem;
628 cgs_kmap_gpu_mem_t kmap_gpu_mem;
629 cgs_kunmap_gpu_mem_t kunmap_gpu_mem;
631 cgs_read_register_t read_register;
632 cgs_write_register_t write_register;
633 cgs_read_ind_register_t read_ind_register;
634 cgs_write_ind_register_t write_ind_register;
635 /* PCI configuration space access */
636 cgs_read_pci_config_byte_t read_pci_config_byte;
637 cgs_read_pci_config_word_t read_pci_config_word;
638 cgs_read_pci_config_dword_t read_pci_config_dword;
639 cgs_write_pci_config_byte_t write_pci_config_byte;
640 cgs_write_pci_config_word_t write_pci_config_word;
641 cgs_write_pci_config_dword_t write_pci_config_dword;
643 cgs_get_pci_resource_t get_pci_resource;
645 cgs_atom_get_data_table_t atom_get_data_table;
646 cgs_atom_get_cmd_table_revs_t atom_get_cmd_table_revs;
647 cgs_atom_exec_cmd_table_t atom_exec_cmd_table;
648 /* Power management */
649 cgs_create_pm_request_t create_pm_request;
650 cgs_destroy_pm_request_t destroy_pm_request;
651 cgs_set_pm_request_t set_pm_request;
652 cgs_pm_request_clock_t pm_request_clock;
653 cgs_pm_request_engine_t pm_request_engine;
654 cgs_pm_query_clock_limits_t pm_query_clock_limits;
655 cgs_set_camera_voltages_t set_camera_voltages;
657 cgs_get_firmware_info get_firmware_info;
658 cgs_rel_firmware rel_firmware;
660 cgs_set_powergating_state set_powergating_state;
661 cgs_set_clockgating_state set_clockgating_state;
662 /* display manager */
663 cgs_get_active_displays_info get_active_displays_info;
664 /* notify dpm enabled */
665 cgs_notify_dpm_enabled notify_dpm_enabled;
667 cgs_call_acpi_method call_acpi_method;
668 /* get system info */
669 cgs_query_system_info query_system_info;
672 struct cgs_os_ops; /* To be define in OS-specific CGS header */
676 const struct cgs_ops *ops;
677 const struct cgs_os_ops *os_ops;
678 /* to be embedded at the start of driver private structure */
681 /* Convenience macros that make CGS indirect function calls look like
682 * normal function calls */
683 #define CGS_CALL(func,dev,...) \
684 (((struct cgs_device *)dev)->ops->func(dev, ##__VA_ARGS__))
685 #define CGS_OS_CALL(func,dev,...) \
686 (((struct cgs_device *)dev)->os_ops->func(dev, ##__VA_ARGS__))
688 #define cgs_gpu_mem_info(dev,type,mc_start,mc_size,mem_size) \
689 CGS_CALL(gpu_mem_info,dev,type,mc_start,mc_size,mem_size)
690 #define cgs_gmap_kmem(dev,kmem,size,min_off,max_off,kmem_handle,mcaddr) \
691 CGS_CALL(gmap_kmem,dev,kmem,size,min_off,max_off,kmem_handle,mcaddr)
692 #define cgs_gunmap_kmem(dev,kmem_handle) \
693 CGS_CALL(gunmap_kmem,dev,keme_handle)
694 #define cgs_alloc_gpu_mem(dev,type,size,align,min_off,max_off,handle) \
695 CGS_CALL(alloc_gpu_mem,dev,type,size,align,min_off,max_off,handle)
696 #define cgs_free_gpu_mem(dev,handle) \
697 CGS_CALL(free_gpu_mem,dev,handle)
698 #define cgs_gmap_gpu_mem(dev,handle,mcaddr) \
699 CGS_CALL(gmap_gpu_mem,dev,handle,mcaddr)
700 #define cgs_gunmap_gpu_mem(dev,handle) \
701 CGS_CALL(gunmap_gpu_mem,dev,handle)
702 #define cgs_kmap_gpu_mem(dev,handle,map) \
703 CGS_CALL(kmap_gpu_mem,dev,handle,map)
704 #define cgs_kunmap_gpu_mem(dev,handle) \
705 CGS_CALL(kunmap_gpu_mem,dev,handle)
707 #define cgs_read_register(dev,offset) \
708 CGS_CALL(read_register,dev,offset)
709 #define cgs_write_register(dev,offset,value) \
710 CGS_CALL(write_register,dev,offset,value)
711 #define cgs_read_ind_register(dev,space,index) \
712 CGS_CALL(read_ind_register,dev,space,index)
713 #define cgs_write_ind_register(dev,space,index,value) \
714 CGS_CALL(write_ind_register,dev,space,index,value)
716 #define cgs_read_pci_config_byte(dev,addr) \
717 CGS_CALL(read_pci_config_byte,dev,addr)
718 #define cgs_read_pci_config_word(dev,addr) \
719 CGS_CALL(read_pci_config_word,dev,addr)
720 #define cgs_read_pci_config_dword(dev,addr) \
721 CGS_CALL(read_pci_config_dword,dev,addr)
722 #define cgs_write_pci_config_byte(dev,addr,value) \
723 CGS_CALL(write_pci_config_byte,dev,addr,value)
724 #define cgs_write_pci_config_word(dev,addr,value) \
725 CGS_CALL(write_pci_config_word,dev,addr,value)
726 #define cgs_write_pci_config_dword(dev,addr,value) \
727 CGS_CALL(write_pci_config_dword,dev,addr,value)
729 #define cgs_atom_get_data_table(dev,table,size,frev,crev) \
730 CGS_CALL(atom_get_data_table,dev,table,size,frev,crev)
731 #define cgs_atom_get_cmd_table_revs(dev,table,frev,crev) \
732 CGS_CALL(atom_get_cmd_table_revs,dev,table,frev,crev)
733 #define cgs_atom_exec_cmd_table(dev,table,args) \
734 CGS_CALL(atom_exec_cmd_table,dev,table,args)
736 #define cgs_create_pm_request(dev,request) \
737 CGS_CALL(create_pm_request,dev,request)
738 #define cgs_destroy_pm_request(dev,request) \
739 CGS_CALL(destroy_pm_request,dev,request)
740 #define cgs_set_pm_request(dev,request,active) \
741 CGS_CALL(set_pm_request,dev,request,active)
742 #define cgs_pm_request_clock(dev,request,clock,freq) \
743 CGS_CALL(pm_request_clock,dev,request,clock,freq)
744 #define cgs_pm_request_engine(dev,request,engine,powered) \
745 CGS_CALL(pm_request_engine,dev,request,engine,powered)
746 #define cgs_pm_query_clock_limits(dev,clock,limits) \
747 CGS_CALL(pm_query_clock_limits,dev,clock,limits)
748 #define cgs_set_camera_voltages(dev,mask,voltages) \
749 CGS_CALL(set_camera_voltages,dev,mask,voltages)
750 #define cgs_get_firmware_info(dev, type, info) \
751 CGS_CALL(get_firmware_info, dev, type, info)
752 #define cgs_rel_firmware(dev, type) \
753 CGS_CALL(rel_firmware, dev, type)
754 #define cgs_set_powergating_state(dev, block_type, state) \
755 CGS_CALL(set_powergating_state, dev, block_type, state)
756 #define cgs_set_clockgating_state(dev, block_type, state) \
757 CGS_CALL(set_clockgating_state, dev, block_type, state)
758 #define cgs_notify_dpm_enabled(dev, enabled) \
759 CGS_CALL(notify_dpm_enabled, dev, enabled)
761 #define cgs_get_active_displays_info(dev, info) \
762 CGS_CALL(get_active_displays_info, dev, info)
764 #define cgs_call_acpi_method(dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size) \
765 CGS_CALL(call_acpi_method, dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size)
766 #define cgs_query_system_info(dev, sys_info) \
767 CGS_CALL(query_system_info, dev, sys_info)
768 #define cgs_get_pci_resource(cgs_device, resource_type, size, offset, \
770 CGS_CALL(get_pci_resource, cgs_device, resource_type, size, offset, \
773 #endif /* _CGS_COMMON_H */