drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui <ray.huang@amd.com>
  23  *
  24  */
  25 #include <linux/module.h>
  26 #include <linux/slab.h>
  27 #include <linux/fb.h>
  28 #include "linux/delay.h"
  29 #include "pp_acpi.h"
  30 #include "hwmgr.h"
  31 #include <atombios.h>
  32 #include "iceland_hwmgr.h"
  33 #include "pptable.h"
  34 #include "processpptables.h"
  35 #include "pp_debug.h"
  36 #include "ppsmc.h"
  37 #include "cgs_common.h"
  38 #include "pppcielanes.h"
  39 #include "iceland_dyn_defaults.h"
  40 #include "smumgr.h"
  41 #include "iceland_smumgr.h"
  42 #include "iceland_clockpowergating.h"
  43 #include "iceland_thermal.h"
  44 #include "iceland_powertune.h"
  45
  46 #include "gmc/gmc_8_1_d.h"
  47 #include "gmc/gmc_8_1_sh_mask.h"
  48
  49 #include "bif/bif_5_0_d.h"
  50 #include "bif/bif_5_0_sh_mask.h"
  51
  52 #include "smu/smu_7_1_1_d.h"
  53 #include "smu/smu_7_1_1_sh_mask.h"
  54
  55 #include "cgs_linux.h"
  56 #include "eventmgr.h"
  57 #include "amd_pcie_helpers.h"
  58
  59 #define MC_CG_ARB_FREQ_F0           0x0a
  60 #define MC_CG_ARB_FREQ_F1           0x0b
  61 #define MC_CG_ARB_FREQ_F2           0x0c
  62 #define MC_CG_ARB_FREQ_F3           0x0d
  63
  64 #define MC_CG_SEQ_DRAMCONF_S0       0x05
  65 #define MC_CG_SEQ_DRAMCONF_S1       0x06
  66 #define MC_CG_SEQ_YCLK_SUSPEND      0x04
  67 #define MC_CG_SEQ_YCLK_RESUME       0x0a
  68
  69 #define PCIE_BUS_CLK                10000
  70 #define TCLK                        (PCIE_BUS_CLK / 10)
  71
  72 #define SMC_RAM_END                 0x40000
  73 #define SMC_CG_IND_START            0xc0030000
  74 #define SMC_CG_IND_END              0xc0040000  /* First byte after SMC_CG_IND*/
  75
  76 #define VOLTAGE_SCALE               4
  77 #define VOLTAGE_VID_OFFSET_SCALE1   625
  78 #define VOLTAGE_VID_OFFSET_SCALE2   100
  79
  80 const uint32_t iceland_magic = (uint32_t)(PHM_VIslands_Magic);
  81
  82 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
  83 #define MC_SEQ_MISC0_GDDR5_MASK  0xf0000000
  84 #define MC_SEQ_MISC0_GDDR5_VALUE 5
  85
  86 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
  87 enum DPM_EVENT_SRC {
  88     DPM_EVENT_SRC_ANALOG = 0,               /* Internal analog trip point */
  89     DPM_EVENT_SRC_EXTERNAL = 1,             /* External (GPIO 17) signal */
  90     DPM_EVENT_SRC_DIGITAL = 2,              /* Internal digital trip point (DIG_THERM_DPM) */
  91     DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,   /* Internal analog or external */
  92     DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4   /* Internal digital or external */
  93 };
  94
  95 static int iceland_read_clock_registers(struct pp_hwmgr *hwmgr)
  96 {
  97         iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
  98
  99         data->clock_registers.vCG_SPLL_FUNC_CNTL         =
 100                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL);
 101         data->clock_registers.vCG_SPLL_FUNC_CNTL_2       =
 102                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2);
 103         data->clock_registers.vCG_SPLL_FUNC_CNTL_3       =
 104                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_3);
 105         data->clock_registers.vCG_SPLL_FUNC_CNTL_4       =
 106                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4);
 107         data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM   =
 108                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM);
 109         data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2 =
 110                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM_2);
 111         data->clock_registers.vDLL_CNTL                  =
 112                 cgs_read_register(hwmgr->device, mmDLL_CNTL);
 113         data->clock_registers.vMCLK_PWRMGT_CNTL          =
 114                 cgs_read_register(hwmgr->device, mmMCLK_PWRMGT_CNTL);
 115         data->clock_registers.vMPLL_AD_FUNC_CNTL         =
 116                 cgs_read_register(hwmgr->device, mmMPLL_AD_FUNC_CNTL);
 117         data->clock_registers.vMPLL_DQ_FUNC_CNTL         =
 118                 cgs_read_register(hwmgr->device, mmMPLL_DQ_FUNC_CNTL);
 119         data->clock_registers.vMPLL_FUNC_CNTL            =
 120                 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL);
 121         data->clock_registers.vMPLL_FUNC_CNTL_1          =
 122                 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_1);
 123         data->clock_registers.vMPLL_FUNC_CNTL_2          =
 124                 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_2);
 125         data->clock_registers.vMPLL_SS1                  =
 126                 cgs_read_register(hwmgr->device, mmMPLL_SS1);
 127         data->clock_registers.vMPLL_SS2                  =
 128                 cgs_read_register(hwmgr->device, mmMPLL_SS2);
 129
 130         return 0;
 131 }
 132
 133 /**
 134  * Find out if memory is GDDR5.
 135  *
 136  * @param    hwmgr  the address of the powerplay hardware manager.
 137  * @return   always 0
 138  */
 139 int iceland_get_memory_type(struct pp_hwmgr *hwmgr)
 140 {
 141         iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
 142         uint32_t temp;
 143
 144         temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
 145
 146         data->is_memory_GDDR5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
 147                         ((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
 148                          MC_SEQ_MISC0_GDDR5_SHIFT));
 149
 150         return 0;
 151 }
 152
 153 int iceland_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
 154 {
 155         /* iceland does not have MM hardware blocks */
 156         return 0;
 157 }
 158
 159 /**
 160  * Enables Dynamic Power Management by SMC
 161  *
 162  * @param    hwmgr  the address of the powerplay hardware manager.
 163  * @return   always 0
 164  */
 165 int iceland_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
 166 {
 167         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, STATIC_PM_EN, 1);
 168
 169         return 0;
 170 }
 171
 172 /**
 173  * Find the MC microcode version and store it in the HwMgr struct
 174  *
 175  * @param    hwmgr  the address of the powerplay hardware manager.
 176  * @return   always 0
 177  */
 178 int iceland_get_mc_microcode_version(struct pp_hwmgr *hwmgr)
 179 {
 180         cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
 181
 182         hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
 183
 184         return 0;
 185 }
 186
 187 static int iceland_init_sclk_threshold(struct pp_hwmgr *hwmgr)
 188 {
 189         iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
 190
 191         data->low_sclk_interrupt_threshold = 0;
 192
 193         return 0;
 194 }
 195
 196
 197 static int iceland_setup_asic_task(struct pp_hwmgr *hwmgr)
 198 {
 199         int tmp_result, result = 0;
 200
 201         tmp_result = iceland_read_clock_registers(hwmgr);
 202         PP_ASSERT_WITH_CODE((0 == tmp_result),
 203                 "Failed to read clock registers!", result = tmp_result);
 204
 205         tmp_result = iceland_get_memory_type(hwmgr);
 206         PP_ASSERT_WITH_CODE((0 == tmp_result),
 207                 "Failed to get memory type!", result = tmp_result);
 208
 209         tmp_result = iceland_enable_acpi_power_management(hwmgr);
 210         PP_ASSERT_WITH_CODE((0 == tmp_result),
 211                 "Failed to enable ACPI power management!", result = tmp_result);
 212
 213         tmp_result = iceland_get_mc_microcode_version(hwmgr);
 214         PP_ASSERT_WITH_CODE((0 == tmp_result),
 215                 "Failed to get MC microcode version!", result = tmp_result);
 216
 217         tmp_result = iceland_init_sclk_threshold(hwmgr);
 218         PP_ASSERT_WITH_CODE((0 == tmp_result),
 219                 "Failed to init sclk threshold!", result = tmp_result);
 220
 221         return result;
 222 }
 223
 224 static bool cf_iceland_voltage_control(struct pp_hwmgr *hwmgr)
 225 {
 226         struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend);
 227
 228         return ICELAND_VOLTAGE_CONTROL_NONE != data->voltage_control;
 229 }
 230
 231 /*
 232  * -------------- Voltage Tables ----------------------
 233  * If the voltage table would be bigger than what will fit into the
 234  * state table on the SMC keep only the higher entries.
 235  */
 236
 237 static void iceland_trim_voltage_table_to_fit_state_table(
 238                 struct pp_hwmgr *hwmgr,
 239                 uint32_t max_voltage_steps,
 240                 pp_atomctrl_voltage_table *voltage_table)
 241 {
 242         unsigned int i, diff;
 243
 244         if (voltage_table->count <= max_voltage_steps) {
 245                 return;
 246         }
 247
 248         diff = voltage_table->count - max_voltage_steps;
 249
 250         for (i = 0; i < max_voltage_steps; i++) {
 251                 voltage_table->entries[i] = voltage_table->entries[i + diff];
 252         }
 253
 254         voltage_table->count = max_voltage_steps;
 255
 256         return;
 257 }
 258
 259 /**
 260  * Enable voltage control
 261  *
 262  * @param    hwmgr  the address of the powerplay hardware manager.
 263  * @return   always 0
 264  */
 265 int iceland_enable_voltage_control(struct pp_hwmgr *hwmgr)
 266 {
 267         /* enable voltage control */
 268         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
 269
 270         return 0;
 271 }
 272
 273 static int iceland_get_svi2_voltage_table(struct pp_hwmgr *hwmgr,
 274                 struct phm_clock_voltage_dependency_table *voltage_dependency_table,
 275                 pp_atomctrl_voltage_table *voltage_table)
 276 {
 277         uint32_t i;
 278
 279         PP_ASSERT_WITH_CODE((NULL != voltage_table),
 280                         "Voltage Dependency Table empty.", return -EINVAL;);
 281
 282         voltage_table->mask_low = 0;
 283         voltage_table->phase_delay = 0;
 284         voltage_table->count = voltage_dependency_table->count;
 285
 286         for (i = 0; i < voltage_dependency_table->count; i++) {
 287                 voltage_table->entries[i].value =
 288                         voltage_dependency_table->entries[i].v;
 289                 voltage_table->entries[i].smio_low = 0;
 290         }
 291
 292         return 0;
 293 }
 294
 295 /**
 296  * Create Voltage Tables.
 297  *
 298  * @param    hwmgr  the address of the powerplay hardware manager.
 299  * @return   always 0
 300  */
 301 int iceland_construct_voltage_tables(struct pp_hwmgr *hwmgr)
 302 {
 303         iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
 304         int result;
 305
 306         /* GPIO voltage */
 307         if (ICELAND_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control) {
 308                 result = atomctrl_get_voltage_table_v3(hwmgr,
 309                                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT,
 310                                         &data->vddc_voltage_table);
 311                 PP_ASSERT_WITH_CODE((0 == result),
 312                         "Failed to retrieve VDDC table.", return result;);
 313         } else if (ICELAND_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
 314                 /* SVI2 VDDC voltage */
 315                 result = iceland_get_svi2_voltage_table(hwmgr,
 316                                         hwmgr->dyn_state.vddc_dependency_on_mclk,
 317                                         &data->vddc_voltage_table);
 318                 PP_ASSERT_WITH_CODE((0 == result),
 319                         "Failed to retrieve SVI2 VDDC table from dependancy table.", return result;);
 320         }
 321
 322         PP_ASSERT_WITH_CODE(
 323                         (data->vddc_voltage_table.count <= (SMU71_MAX_LEVELS_VDDC)),
 324                         "Too many voltage values for VDDC. Trimming to fit state table.",
 325                         iceland_trim_voltage_table_to_fit_state_table(hwmgr,
 326                         SMU71_MAX_LEVELS_VDDC, &(data->vddc_voltage_table));
 327                         );
 328
 329         /* GPIO */
 330         if (ICELAND_VOLTAGE_CONTROL_BY_GPIO == data->vdd_ci_control) {
 331                 result = atomctrl_get_voltage_table_v3(hwmgr,
 332                                         VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT, &(data->vddci_voltage_table));
 333                 PP_ASSERT_WITH_CODE((0 == result),
 334                         "Failed to retrieve VDDCI table.", return result;);
 335         }
 336
 337         /* SVI2 VDDCI voltage */
 338         if (ICELAND_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_ci_control) {
 339                 result = iceland_get_svi2_voltage_table(hwmgr,
 340                                         hwmgr->dyn_state.vddci_dependency_on_mclk,
 341                                         &data->vddci_voltage_table);
 342                 PP_ASSERT_WITH_CODE((0 == result),
 343                         "Failed to retrieve SVI2 VDDCI table from dependancy table.", return result;);
 344         }
 345
 346         PP_ASSERT_WITH_CODE(
 347                         (data->vddci_voltage_table.count <= (SMU71_MAX_LEVELS_VDDCI)),
 348                         "Too many voltage values for VDDCI. Trimming to fit state table.",
 349                         iceland_trim_voltage_table_to_fit_state_table(hwmgr,
 350                         SMU71_MAX_LEVELS_VDDCI, &(data->vddci_voltage_table));
 351                         );
 352
 353
 354         /* GPIO */
 355         if (ICELAND_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
 356                 result = atomctrl_get_voltage_table_v3(hwmgr,
 357                                         VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT, &(data->mvdd_voltage_table));
 358                 PP_ASSERT_WITH_CODE((0 == result),
 359                         "Failed to retrieve table.", return result;);
 360         }
 361
 362         /* SVI2 voltage control */
 363         if (ICELAND_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
 364                 result = iceland_get_svi2_voltage_table(hwmgr,
 365                                         hwmgr->dyn_state.mvdd_dependency_on_mclk,
 366                                         &data->mvdd_voltage_table);
 367                 PP_ASSERT_WITH_CODE((0 == result),
 368                         "Failed to retrieve SVI2 MVDD table from dependancy table.", return result;);
 369         }
 370
 371         PP_ASSERT_WITH_CODE(
 372                         (data->mvdd_voltage_table.count <= (SMU71_MAX_LEVELS_MVDD)),
 373                         "Too many voltage values for MVDD. Trimming to fit state table.",
 374                         iceland_trim_voltage_table_to_fit_state_table(hwmgr,
 375                         SMU71_MAX_LEVELS_MVDD, &(data->mvdd_voltage_table));
 376                         );
 377
 378         return 0;
 379 }
 380
 381 /*---------------------------MC----------------------------*/
 382
 383 uint8_t iceland_get_memory_module_index(struct pp_hwmgr *hwmgr)
 384 {
 385         return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));
 386 }
 387
 388 bool iceland_check_s0_mc_reg_index(uint16_t inReg, uint16_t *outReg)
 389 {
 390         bool result = true;
 391
 392         switch (inReg) {
 393         case  mmMC_SEQ_RAS_TIMING:
 394                 *outReg = mmMC_SEQ_RAS_TIMING_LP;
 395                 break;
 396
 397         case  mmMC_SEQ_DLL_STBY:
 398                 *outReg = mmMC_SEQ_DLL_STBY_LP;
 399                 break;
 400
 401         case  mmMC_SEQ_G5PDX_CMD0:
 402                 *outReg = mmMC_SEQ_G5PDX_CMD0_LP;
 403                 break;
 404
 405         case  mmMC_SEQ_G5PDX_CMD1:
 406                 *outReg = mmMC_SEQ_G5PDX_CMD1_LP;
 407                 break;
 408
 409         case  mmMC_SEQ_G5PDX_CTRL:
 410                 *outReg = mmMC_SEQ_G5PDX_CTRL_LP;
 411                 break;
 412
 413         case mmMC_SEQ_CAS_TIMING:
 414                 *outReg = mmMC_SEQ_CAS_TIMING_LP;
 415                 break;
 416
 417         case mmMC_SEQ_MISC_TIMING:
 418                 *outReg = mmMC_SEQ_MISC_TIMING_LP;
 419                 break;
 420
 421         case mmMC_SEQ_MISC_TIMING2:
 422                 *outReg = mmMC_SEQ_MISC_TIMING2_LP;
 423                 break;
 424
 425         case mmMC_SEQ_PMG_DVS_CMD:
 426                 *outReg = mmMC_SEQ_PMG_DVS_CMD_LP;
 427                 break;
 428
 429         case mmMC_SEQ_PMG_DVS_CTL:
 430                 *outReg = mmMC_SEQ_PMG_DVS_CTL_LP;
 431                 break;
 432
 433         case mmMC_SEQ_RD_CTL_D0:
 434                 *outReg = mmMC_SEQ_RD_CTL_D0_LP;
 435                 break;
 436
 437         case mmMC_SEQ_RD_CTL_D1:
 438                 *outReg = mmMC_SEQ_RD_CTL_D1_LP;
 439                 break;
 440
 441         case mmMC_SEQ_WR_CTL_D0:
 442                 *outReg = mmMC_SEQ_WR_CTL_D0_LP;
 443                 break;
 444
 445         case mmMC_SEQ_WR_CTL_D1:
 446                 *outReg = mmMC_SEQ_WR_CTL_D1_LP;
 447                 break;
 448
 449         case mmMC_PMG_CMD_EMRS:
 450                 *outReg = mmMC_SEQ_PMG_CMD_EMRS_LP;
 451                 break;
 452
 453         case mmMC_PMG_CMD_MRS:
 454                 *outReg = mmMC_SEQ_PMG_CMD_MRS_LP;
 455                 break;
 456
 457         case mmMC_PMG_CMD_MRS1:
 458                 *outReg = mmMC_SEQ_PMG_CMD_MRS1_LP;
 459                 break;
 460
 461         case mmMC_SEQ_PMG_TIMING:
 462                 *outReg = mmMC_SEQ_PMG_TIMING_LP;
 463                 break;
 464
 465         case mmMC_PMG_CMD_MRS2:
 466                 *outReg = mmMC_SEQ_PMG_CMD_MRS2_LP;
 467                 break;
 468
 469         case mmMC_SEQ_WR_CTL_2:
 470                 *outReg = mmMC_SEQ_WR_CTL_2_LP;
 471                 break;
 472
 473         default:
 474                 result = false;
 475                 break;
 476         }
 477
 478         return result;
 479 }
 480
 481 int iceland_set_s0_mc_reg_index(phw_iceland_mc_reg_table *table)
 482 {
 483         uint32_t i;
 484         uint16_t address;
 485
 486         for (i = 0; i < table->last; i++) {
 487                 table->mc_reg_address[i].s0 =
 488                         iceland_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address)
 489                         ? address : table->mc_reg_address[i].s1;
 490         }
 491         return 0;
 492 }
 493
 494 int iceland_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table, phw_iceland_mc_reg_table *ni_table)
 495 {
 496         uint8_t i, j;
 497
 498         PP_ASSERT_WITH_CODE((table->last <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
 499                 "Invalid VramInfo table.", return -1);
 500         PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES),
 501                 "Invalid VramInfo table.", return -1);
 502
 503         for (i = 0; i < table->last; i++) {
 504                 ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
 505         }
 506         ni_table->last = table->last;
 507
 508         for (i = 0; i < table->num_entries; i++) {
 509                 ni_table->mc_reg_table_entry[i].mclk_max =
 510                         table->mc_reg_table_entry[i].mclk_max;
 511                 for (j = 0; j < table->last; j++) {
 512                         ni_table->mc_reg_table_entry[i].mc_data[j] =
 513                                 table->mc_reg_table_entry[i].mc_data[j];
 514                 }
 515         }
 516
 517         ni_table->num_entries = table->num_entries;
 518
 519         return 0;
 520 }
 521
 522 /**
 523  * VBIOS omits some information to reduce size, we need to recover them here.
 524  * 1.   when we see mmMC_SEQ_MISC1, bit[31:16] EMRS1, need to be write to  mmMC_PMG_CMD_EMRS /_LP[15:0].
 525  *      Bit[15:0] MRS, need to be update mmMC_PMG_CMD_MRS/_LP[15:0]
 526  * 2.   when we see mmMC_SEQ_RESERVE_M, bit[15:0] EMRS2, need to be write to mmMC_PMG_CMD_MRS1/_LP[15:0].
 527  * 3.   need to set these data for each clock range
 528  *
 529  * @param    hwmgr the address of the powerplay hardware manager.
 530  * @param    table the address of MCRegTable
 531  * @return   always 0
 532  */
 533 static int iceland_set_mc_special_registers(struct pp_hwmgr *hwmgr, phw_iceland_mc_reg_table *table)
 534 {
 535         uint8_t i, j, k;
 536         uint32_t temp_reg;
 537         const iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend);
 538
 539         for (i = 0, j = table->last; i < table->last; i++) {
 540                 PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
 541                         "Invalid VramInfo table.", return -1);
 542                 switch (table->mc_reg_address[i].s1) {
 543                 /*
 544                  * mmMC_SEQ_MISC1, bit[31:16] EMRS1, need to be write
 545                  * to mmMC_PMG_CMD_EMRS/_LP[15:0]. Bit[15:0] MRS, need
 546                  * to be update mmMC_PMG_CMD_MRS/_LP[15:0]
 547                  */
 548                 case mmMC_SEQ_MISC1:
 549                         temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS);
 550                         table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
 551                         table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP;
 552                         for (k = 0; k < table->num_entries; k++) {
 553                                 table->mc_reg_table_entry[k].mc_data[j] =
 554                                         ((temp_reg & 0xffff0000)) |
 555                                         ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
 556                         }
 557                         j++;
 558                         PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
 559                                 "Invalid VramInfo table.", return -1);
 560
 561                         temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS);
 562                         table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
 563                         table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
 564                         for (k = 0; k < table->num_entries; k++) {
 565                                 table->mc_reg_table_entry[k].mc_data[j] =
 566                                         (temp_reg & 0xffff0000) |
 567                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
 568
 569                                 if (!data->is_memory_GDDR5) {
 570                                         table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
 571                                 }
 572                         }
 573                         j++;
 574                         PP_ASSERT_WITH_CODE((j <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
 575                                 "Invalid VramInfo table.", return -1);
 576
 577                         if (!data->is_memory_GDDR5) {
 578                                 table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
 579                                 table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
 580                                 for (k = 0; k < table->num_entries; k++) {
 581                                         table->mc_reg_table_entry[k].mc_data[j] =
 582                                                 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
 583                                 }
 584                                 j++;
 585                                 PP_ASSERT_WITH_CODE((j <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
 586                                         "Invalid VramInfo table.", return -1);
 587                         }
 588
 589                         break;
 590
 591                 case mmMC_SEQ_RESERVE_M:
 592                         temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1);
 593                         table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1;
 594                         table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP;
 595                         for (k = 0; k < table->num_entries; k++) {
 596                                 table->mc_reg_table_entry[k].mc_data[j] =
 597                                         (temp_reg & 0xffff0000) |
 598                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
 599                         }
 600                         j++;
 601                         PP_ASSERT_WITH_CODE((j <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
 602                                 "Invalid VramInfo table.", return -1);
 603                         break;
 604
 605                 default:
 606                         break;
 607                 }
 608
 609         }
 610
 611         table->last = j;
 612
 613         return 0;
 614 }
 615
 616
 617 static int iceland_set_valid_flag(phw_iceland_mc_reg_table *table)
 618 {
 619         uint8_t i, j;
 620         for (i = 0; i < table->last; i++) {
 621                 for (j = 1; j < table->num_entries; j++) {
 622                         if (table->mc_reg_table_entry[j-1].mc_data[i] !=
 623                                 table->mc_reg_table_entry[j].mc_data[i]) {
 624                                 table->validflag |= (1<<i);
 625                                 break;
 626                         }
 627                 }
 628         }
 629
 630         return 0;
 631 }
 632
 633 static int iceland_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
 634 {
 635         int result;
 636         iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
 637         pp_atomctrl_mc_reg_table *table;
 638         phw_iceland_mc_reg_table *ni_table = &data->iceland_mc_reg_table;
 639         uint8_t module_index = iceland_get_memory_module_index(hwmgr);
 640
 641         table = kzalloc(sizeof(pp_atomctrl_mc_reg_table), GFP_KERNEL);
 642
 643         if (NULL == table)
 644                 return -ENOMEM;
 645
 646         /* Program additional LP registers that are no longer programmed by VBIOS */
 647         cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
 648         cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
 649         cgs_write_register(hwmgr->device, mmMC_SEQ_DLL_STBY_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_DLL_STBY));
 650         cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0));
 651         cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1));
 652         cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL));
 653         cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD));
 654         cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL));
 655         cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING));
 656         cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
 657         cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_EMRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS));
 658         cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS));
 659         cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS1_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1));
 660         cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0));
 661         cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
 662         cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
 663         cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
 664         cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
 665         cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2));
 666         cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2));
 667
 668         memset(table, 0x00, sizeof(pp_atomctrl_mc_reg_table));
 669
 670         result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table);
 671
 672         if (0 == result)
 673                 result = iceland_copy_vbios_smc_reg_table(table, ni_table);
 674
 675         if (0 == result) {
 676                 iceland_set_s0_mc_reg_index(ni_table);
 677                 result = iceland_set_mc_special_registers(hwmgr, ni_table);
 678         }
 679
 680         if (0 == result)
 681                 iceland_set_valid_flag(ni_table);
 682
 683         kfree(table);
 684         return result;
 685 }
 686
 687 /**
 688  * Programs static screed detection parameters
 689  *
 690  * @param   hwmgr  the address of the powerplay hardware manager.
 691  * @return   always 0
 692  */
 693 int iceland_program_static_screen_threshold_parameters(struct pp_hwmgr *hwmgr)
 694 {
 695         iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
 696
 697         /* Set static screen threshold unit*/
 698         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
 699                 CGS_IND_REG__SMC, CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
 700                 data->static_screen_threshold_unit);
 701         /* Set static screen threshold*/
 702         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
 703                 CGS_IND_REG__SMC, CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
 704                 data->static_screen_threshold);
 705
 706         return 0;
 707 }
 708
 709 /**
 710  * Setup display gap for glitch free memory clock switching.
 711  *
 712  * @param    hwmgr  the address of the powerplay hardware manager.
 713  * @return   always 0
 714  */
 715 int iceland_enable_display_gap(struct pp_hwmgr *hwmgr)
 716 {
 717         uint32_t display_gap = cgs_read_ind_register(hwmgr->device,
 718                                                         CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
 719
 720         display_gap = PHM_SET_FIELD(display_gap,
 721                                         CG_DISPLAY_GAP_CNTL, DISP_GAP, DISPLAY_GAP_IGNORE);
 722
 723         display_gap = PHM_SET_FIELD(display_gap,
 724                                         CG_DISPLAY_GAP_CNTL, DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
 725
 726         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 727                 ixCG_DISPLAY_GAP_CNTL, display_gap);
 728
 729         return 0;
 730 }
 731
 732 /**
 733  * Programs activity state transition voting clients
 734  *
 735  * @param    hwmgr  the address of the powerplay hardware manager.
 736  * @return   always 0
 737  */
 738 int iceland_program_voting_clients(struct pp_hwmgr *hwmgr)
 739 {
 740         iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
 741
 742         /* Clear reset for voting clients before enabling DPM */
 743         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 744                 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
 745         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 746                 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
 747
 748         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 749                 ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
 750         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 751                 ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
 752         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 753                 ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
 754         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 755                 ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
 756         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 757                 ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
 758         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 759                 ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
 760         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 761                 ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
 762         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 763                 ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
 764
 765         return 0;
 766 }
 767
 768 static int iceland_upload_firmware(struct pp_hwmgr *hwmgr)
 769 {
 770         int ret = 0;
 771
 772         if (!iceland_is_smc_ram_running(hwmgr->smumgr))
 773                 ret = iceland_smu_upload_firmware_image(hwmgr->smumgr);
 774
 775         return ret;
 776 }
 777
 778 /**
 779  * Get the location of various tables inside the FW image.
 780  *
 781  * @param    hwmgr  the address of the powerplay hardware manager.
 782  * @return   always 0
 783  */
 784 int iceland_process_firmware_header(struct pp_hwmgr *hwmgr)
 785 {
 786         iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
 787
 788         uint32_t tmp;
 789         int result;
 790         bool error = 0;
 791
 792         result = iceland_read_smc_sram_dword(hwmgr->smumgr,
 793                                 SMU71_FIRMWARE_HEADER_LOCATION +
 794                                 offsetof(SMU71_Firmware_Header, DpmTable),
 795                                 &tmp, data->sram_end);
 796
 797         if (0 == result) {
 798                 data->dpm_table_start = tmp;
 799         }
 800
 801         error |= (0 != result);
 802
 803         result = iceland_read_smc_sram_dword(hwmgr->smumgr,
 804                                 SMU71_FIRMWARE_HEADER_LOCATION +
 805                                 offsetof(SMU71_Firmware_Header, SoftRegisters),
 806                                 &tmp, data->sram_end);
 807
 808         if (0 == result) {
 809                 data->soft_regs_start = tmp;
 810         }
 811
 812         error |= (0 != result);
 813
 814
 815         result = iceland_read_smc_sram_dword(hwmgr->smumgr,
 816                                 SMU71_FIRMWARE_HEADER_LOCATION +
 817                                 offsetof(SMU71_Firmware_Header, mcRegisterTable),
 818                                 &tmp, data->sram_end);
 819
 820         if (0 == result) {
 821                 data->mc_reg_table_start = tmp;
 822         }
 823
 824         result = iceland_read_smc_sram_dword(hwmgr->smumgr,
 825                                 SMU71_FIRMWARE_HEADER_LOCATION +
 826                                 offsetof(SMU71_Firmware_Header, FanTable),
 827                                 &tmp, data->sram_end);
 828
 829         if (0 == result) {
 830                 data->fan_table_start = tmp;
 831         }
 832
 833         error |= (0 != result);
 834
 835         result = iceland_read_smc_sram_dword(hwmgr->smumgr,
 836                                 SMU71_FIRMWARE_HEADER_LOCATION +
 837                                 offsetof(SMU71_Firmware_Header, mcArbDramTimingTable),
 838                                 &tmp, data->sram_end);
 839
 840         if (0 == result) {
 841                 data->arb_table_start = tmp;
 842         }
 843
 844         error |= (0 != result);
 845
 846
 847         result = iceland_read_smc_sram_dword(hwmgr->smumgr,
 848                                 SMU71_FIRMWARE_HEADER_LOCATION +
 849                                 offsetof(SMU71_Firmware_Header, Version),
 850                                 &tmp, data->sram_end);
 851
 852         if (0 == result) {
 853                 hwmgr->microcode_version_info.SMC = tmp;
 854         }
 855
 856         error |= (0 != result);
 857
 858         result = iceland_read_smc_sram_dword(hwmgr->smumgr,
 859                                 SMU71_FIRMWARE_HEADER_LOCATION +
 860                                 offsetof(SMU71_Firmware_Header, UlvSettings),
 861                                 &tmp, data->sram_end);
 862
 863         if (0 == result) {
 864                 data->ulv_settings_start = tmp;
 865         }
 866
 867         error |= (0 != result);
 868
 869         return error ? 1 : 0;
 870 }
 871
 872 /*
 873 * Copy one arb setting to another and then switch the active set.
 874 * arbFreqSrc and arbFreqDest is one of the MC_CG_ARB_FREQ_Fx constants.
 875 */
 876 int iceland_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
 877                 uint32_t arbFreqSrc, uint32_t arbFreqDest)
 878 {
 879         uint32_t mc_arb_dram_timing;
 880         uint32_t mc_arb_dram_timing2;
 881         uint32_t burst_time;
 882         uint32_t mc_cg_config;
 883
 884         switch (arbFreqSrc) {
 885         case MC_CG_ARB_FREQ_F0:
 886                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
 887                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
 888                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
 889                 break;
 890
 891         case MC_CG_ARB_FREQ_F1:
 892                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
 893                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
 894                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
 895                 break;
 896
 897         default:
 898                 return -1;
 899         }
 900
 901         switch (arbFreqDest) {
 902         case MC_CG_ARB_FREQ_F0:
 903                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
 904                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
 905                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
 906                 break;
 907
 908         case MC_CG_ARB_FREQ_F1:
 909                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
 910                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
 911                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
 912                 break;
 913
 914         default:
 915                 return -1;
 916         }
 917
 918         mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
 919         mc_cg_config |= 0x0000000F;
 920         cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
 921         PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arbFreqDest);
 922
 923         return 0;
 924 }
 925
 926 /**
 927  * Initial switch from ARB F0->F1
 928  *
 929  * @param    hwmgr  the address of the powerplay hardware manager.
 930  * @return   always 0
 931  * This function is to be called from the SetPowerState table.
 932  */
 933 int iceland_initial_switch_from_arb_f0_to_f1(struct pp_hwmgr *hwmgr)
 934 {
 935         return iceland_copy_and_switch_arb_sets(hwmgr, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
 936 }
 937
 938 /* ---------------------------------------- ULV related functions ----------------------------------------------------*/
 939
 940
 941 static int iceland_reset_single_dpm_table(
 942         struct pp_hwmgr *hwmgr,
 943         struct iceland_single_dpm_table *dpm_table,
 944         uint32_t count)
 945 {
 946         uint32_t i;
 947         if (!(count <= MAX_REGULAR_DPM_NUMBER))
 948                 printk(KERN_ERR "[ powerplay ] Fatal error, can not set up single DPM \
 949                         table entries to exceed max number! \n");
 950
 951         dpm_table->count = count;
 952         for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++) {
 953                 dpm_table->dpm_levels[i].enabled = 0;
 954         }
 955
 956         return 0;
 957 }
 958
 959 static void iceland_setup_pcie_table_entry(
 960         struct iceland_single_dpm_table *dpm_table,
 961         uint32_t index, uint32_t pcie_gen,
 962         uint32_t pcie_lanes)
 963 {
 964         dpm_table->dpm_levels[index].value = pcie_gen;
 965         dpm_table->dpm_levels[index].param1 = pcie_lanes;
 966         dpm_table->dpm_levels[index].enabled = 1;
 967 }
 968
 969 /*
 970  * Set up the PCIe DPM table as follows:
 971  *
 972  * A  = Performance State, Max, Gen Speed
 973  * C  = Performance State, Min, Gen Speed
 974  * 1  = Performance State, Max, Lane #
 975  * 3  = Performance State, Min, Lane #
 976  *
 977  * B  = Power Saving State, Max, Gen Speed
 978  * D  = Power Saving State, Min, Gen Speed
 979  * 2  = Power Saving State, Max, Lane #
 980  * 4  = Power Saving State, Min, Lane #
 981  *
 982  *
 983  * DPM Index   Gen Speed   Lane #
 984  * 5           A           1
 985  * 4           B           2
 986  * 3           C           1
 987  * 2           D           2
 988  * 1           C           3
 989  * 0           D           4
 990  *
 991  */
 992 static int iceland_setup_default_pcie_tables(struct pp_hwmgr *hwmgr)
 993 {
 994         iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
 995
 996         PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
 997                                 data->use_pcie_power_saving_levels),
 998                         "No pcie performance levels!", return -EINVAL);
 999
1000         if (data->use_pcie_performance_levels && !data->use_pcie_power_saving_levels) {
1001                 data->pcie_gen_power_saving = data->pcie_gen_performance;
1002                 data->pcie_lane_power_saving = data->pcie_lane_performance;
1003         } else if (!data->use_pcie_performance_levels && data->use_pcie_power_saving_levels) {
1004                 data->pcie_gen_performance = data->pcie_gen_power_saving;
1005                 data->pcie_lane_performance = data->pcie_lane_power_saving;
1006         }
1007
1008         iceland_reset_single_dpm_table(hwmgr, &data->dpm_table.pcie_speed_table, SMU71_MAX_LEVELS_LINK);
1009
1010         /* Hardcode Pcie Table */
1011         iceland_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
1012                 get_pcie_gen_support(data->pcie_gen_cap, PP_Min_PCIEGen),
1013                 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
1014         iceland_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
1015                 get_pcie_gen_support(data->pcie_gen_cap, PP_Min_PCIEGen),
1016                 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
1017         iceland_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
1018                 get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen),
1019                 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
1020         iceland_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
1021                 get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen),
1022                 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
1023         iceland_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
1024                 get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen),
1025                 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
1026         iceland_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
1027                 get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen),
1028                 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
1029         data->dpm_table.pcie_speed_table.count = 6;
1030
1031         return 0;
1032
1033 }
1034
1035
1036 /*
1037  * This function is to initalize all DPM state tables for SMU7 based on the dependency table.
1038  * Dynamic state patching function will then trim these state tables to the allowed range based
1039  * on the power policy or external client requests, such as UVD request, etc.
1040  */
1041 static int iceland_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
1042 {
1043         iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
1044         uint32_t i;
1045
1046         struct phm_clock_voltage_dependency_table *allowed_vdd_sclk_table =
1047                 hwmgr->dyn_state.vddc_dependency_on_sclk;
1048         struct phm_clock_voltage_dependency_table *allowed_vdd_mclk_table =
1049                 hwmgr->dyn_state.vddc_dependency_on_mclk;
1050         struct phm_cac_leakage_table *std_voltage_table =
1051                 hwmgr->dyn_state.cac_leakage_table;
1052
1053         PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL,
1054                 "SCLK dependency table is missing. This table is mandatory", return -1);
1055         PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table->count >= 1,
1056                 "SCLK dependency table has to have is missing. This table is mandatory", return -1);
1057
1058         PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
1059                 "MCLK dependency table is missing. This table is mandatory", return -1);
1060         PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table->count >= 1,
1061                 "VMCLK dependency table has to have is missing. This table is mandatory", return -1);
1062
1063         /* clear the state table to reset everything to default */
1064         memset(&(data->dpm_table), 0x00, sizeof(data->dpm_table));
1065         iceland_reset_single_dpm_table(hwmgr, &data->dpm_table.sclk_table, SMU71_MAX_LEVELS_GRAPHICS);
1066         iceland_reset_single_dpm_table(hwmgr, &data->dpm_table.mclk_table, SMU71_MAX_LEVELS_MEMORY);
1067         iceland_reset_single_dpm_table(hwmgr, &data->dpm_table.vddc_table, SMU71_MAX_LEVELS_VDDC);
1068         iceland_reset_single_dpm_table(hwmgr, &data->dpm_table.vdd_ci_table, SMU71_MAX_LEVELS_VDDCI);
1069         iceland_reset_single_dpm_table(hwmgr, &data->dpm_table.mvdd_table, SMU71_MAX_LEVELS_MVDD);
1070
1071         PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL,
1072                 "SCLK dependency table is missing. This table is mandatory", return -1);
1073         /* Initialize Sclk DPM table based on allow Sclk values*/
1074         data->dpm_table.sclk_table.count = 0;
1075
1076         for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
1077                 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value !=
1078                                 allowed_vdd_sclk_table->entries[i].clk) {
1079                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
1080                                 allowed_vdd_sclk_table->entries[i].clk;
1081                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = 1; /*(i==0) ? 1 : 0; to do */
1082                         data->dpm_table.sclk_table.count++;
1083                 }
1084         }
1085
1086         PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
1087                 "MCLK dependency table is missing. This table is mandatory", return -1);
1088         /* Initialize Mclk DPM table based on allow Mclk values */
1089         data->dpm_table.mclk_table.count = 0;
1090         for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
1091                 if (i == 0 || data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count-1].value !=
1092                         allowed_vdd_mclk_table->entries[i].clk) {
1093                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
1094                                 allowed_vdd_mclk_table->entries[i].clk;
1095                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = 1; /*(i==0) ? 1 : 0; */
1096                         data->dpm_table.mclk_table.count++;
1097                 }
1098         }
1099
1100         /* Initialize Vddc DPM table based on allow Vddc values.  And populate corresponding std values. */
1101         for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
1102                 data->dpm_table.vddc_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
1103                 data->dpm_table.vddc_table.dpm_levels[i].param1 = std_voltage_table->entries[i].Leakage;
1104                 /* param1 is for corresponding std voltage */
1105                 data->dpm_table.vddc_table.dpm_levels[i].enabled = 1;
1106         }
1107
1108         data->dpm_table.vddc_table.count = allowed_vdd_sclk_table->count;
1109         allowed_vdd_mclk_table = hwmgr->dyn_state.vddci_dependency_on_mclk;
1110
1111         if (NULL != allowed_vdd_mclk_table) {
1112                 /* Initialize Vddci DPM table based on allow Mclk values */
1113                 for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
1114                         data->dpm_table.vdd_ci_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
1115                         data->dpm_table.vdd_ci_table.dpm_levels[i].enabled = 1;
1116                 }
1117                 data->dpm_table.vdd_ci_table.count = allowed_vdd_mclk_table->count;
1118         }
1119
1120         allowed_vdd_mclk_table = hwmgr->dyn_state.mvdd_dependency_on_mclk;
1121
1122         if (NULL != allowed_vdd_mclk_table) {
1123                 /*
1124                  * Initialize MVDD DPM table based on allow Mclk
1125                  * values
1126                  */
1127                 for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
1128                         data->dpm_table.mvdd_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
1129                         data->dpm_table.mvdd_table.dpm_levels[i].enabled = 1;
1130                 }
1131                 data->dpm_table.mvdd_table.count = allowed_vdd_mclk_table->count;
1132         }
1133
1134         /* setup PCIE gen speed levels*/
1135         iceland_setup_default_pcie_tables(hwmgr);
1136
1137         /* save a copy of the default DPM table*/
1138         memcpy(&(data->golden_dpm_table), &(data->dpm_table), sizeof(struct iceland_dpm_table));
1139
1140         return 0;
1141 }
1142
1143 /**
1144  * @brief PhwIceland_GetVoltageOrder
1145  *  Returns index of requested voltage record in lookup(table)
1146  * @param hwmgr - pointer to hardware manager
1147  * @param lookutab - lookup list to search in
1148  * @param voltage - voltage to look for
1149  * @return 0 on success
1150  */
1151 uint8_t iceland_get_voltage_index(phm_ppt_v1_voltage_lookup_table *look_up_table,
1152                 uint16_t voltage)
1153 {
1154         uint8_t count = (uint8_t) (look_up_table->count);
1155         uint8_t i;
1156
1157         PP_ASSERT_WITH_CODE((NULL != look_up_table), "Lookup Table empty.", return 0;);
1158         PP_ASSERT_WITH_CODE((0 != count), "Lookup Table empty.", return 0;);
1159
1160         for (i = 0; i < count; i++) {
1161                 /* find first voltage equal or bigger than requested */
1162                 if (look_up_table->entries[i].us_vdd >= voltage)
1163                         return i;
1164         }
1165
1166         /* voltage is bigger than max voltage in the table */
1167         return i-1;
1168 }
1169
1170
1171 static int iceland_get_std_voltage_value_sidd(struct pp_hwmgr *hwmgr,
1172                 pp_atomctrl_voltage_table_entry *tab, uint16_t *hi,
1173                 uint16_t *lo)
1174 {
1175         uint16_t v_index;
1176         bool vol_found = false;
1177         *hi = tab->value * VOLTAGE_SCALE;
1178         *lo = tab->value * VOLTAGE_SCALE;
1179
1180         /* SCLK/VDDC Dependency Table has to exist. */
1181         PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.vddc_dependency_on_sclk,
1182                             "The SCLK/VDDC Dependency Table does not exist.\n",
1183                             return -EINVAL);
1184
1185         if (NULL == hwmgr->dyn_state.cac_leakage_table) {
1186                 pr_warning("CAC Leakage Table does not exist, using vddc.\n");
1187                 return 0;
1188         }
1189
1190         /*
1191          * Since voltage in the sclk/vddc dependency table is not
1192          * necessarily in ascending order because of ELB voltage
1193          * patching, loop through entire list to find exact voltage.
1194          */
1195         for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) {
1196                 if (tab->value == hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) {
1197                         vol_found = true;
1198                         if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) {
1199                                 *lo = hwmgr->dyn_state.cac_leakage_table->entries[v_index].Vddc * VOLTAGE_SCALE;
1200                                 *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[v_index].Leakage * VOLTAGE_SCALE);
1201                         } else {
1202                                 pr_warning("Index from SCLK/VDDC Dependency Table exceeds the CAC Leakage Table index, using maximum index from CAC table.\n");
1203                                 *lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Vddc * VOLTAGE_SCALE;
1204                                 *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Leakage * VOLTAGE_SCALE);
1205                         }
1206                         break;
1207                 }
1208         }
1209
1210         /*
1211          * If voltage is not found in the first pass, loop again to
1212          * find the best match, equal or higher value.
1213          */
1214         if (!vol_found) {
1215                 for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) {
1216                         if (tab->value <= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) {
1217                                 vol_found = true;
1218                                 if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) {
1219                                         *lo = hwmgr->dyn_state.cac_leakage_table->entries[v_index].Vddc * VOLTAGE_SCALE;
1220                                         *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[v_index].Leakage) * VOLTAGE_SCALE;
1221                                 } else {
1222                                         pr_warning("Index from SCLK/VDDC Dependency Table exceeds the CAC Leakage Table index in second look up, using maximum index from CAC table.");
1223                                         *lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Vddc * VOLTAGE_SCALE;
1224                                         *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Leakage * VOLTAGE_SCALE);
1225                                 }
1226                                 break;
1227                         }
1228                 }
1229
1230                 if (!vol_found)
1231                         pr_warning("Unable to get std_vddc from SCLK/VDDC Dependency Table, using vddc.\n");
1232         }
1233
1234         return 0;
1235 }
1236
1237 static int iceland_populate_smc_voltage_table(struct pp_hwmgr *hwmgr,
1238                 pp_atomctrl_voltage_table_entry *tab,
1239                 SMU71_Discrete_VoltageLevel *smc_voltage_tab) {
1240         int result;
1241
1242
1243         result = iceland_get_std_voltage_value_sidd(hwmgr, tab,
1244                         &smc_voltage_tab->StdVoltageHiSidd,
1245                         &smc_voltage_tab->StdVoltageLoSidd);
1246         if (0 != result) {
1247                 smc_voltage_tab->StdVoltageHiSidd = tab->value * VOLTAGE_SCALE;
1248                 smc_voltage_tab->StdVoltageLoSidd = tab->value * VOLTAGE_SCALE;
1249         }
1250
1251         smc_voltage_tab->Voltage = PP_HOST_TO_SMC_US(tab->value * VOLTAGE_SCALE);
1252         CONVERT_FROM_HOST_TO_SMC_US(smc_voltage_tab->StdVoltageHiSidd);
1253         CONVERT_FROM_HOST_TO_SMC_US(smc_voltage_tab->StdVoltageHiSidd);
1254
1255         return 0;
1256 }
1257
1258 /**
1259  * Vddc table preparation for SMC.
1260  *
1261  * @param    hwmgr      the address of the hardware manager
1262  * @param    table     the SMC DPM table structure to be populated
1263  * @return   always 0
1264  */
1265 static int iceland_populate_smc_vddc_table(struct pp_hwmgr *hwmgr,
1266                         SMU71_Discrete_DpmTable *table)
1267 {
1268         unsigned int count;
1269         int result;
1270
1271         iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
1272
1273         table->VddcLevelCount = data->vddc_voltage_table.count;
1274         for (count = 0; count < table->VddcLevelCount; count++) {
1275                 result = iceland_populate_smc_voltage_table(hwmgr,
1276                                 &data->vddc_voltage_table.entries[count],
1277                                 &table->VddcLevel[count]);
1278                 PP_ASSERT_WITH_CODE(0 == result, "do not populate SMC VDDC voltage table", return -EINVAL);
1279
1280                 /* GPIO voltage control */
1281                 if (ICELAND_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control)
1282                         table->VddcLevel[count].Smio |= data->vddc_voltage_table.entries[count].smio_low;
1283                 else if (ICELAND_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control)
1284                         table->VddcLevel[count].Smio = 0;
1285         }
1286
1287         CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount);
1288
1289         return 0;
1290 }
1291
1292 /**
1293  * Vddci table preparation for SMC.
1294  *
1295  * @param    *hwmgr The address of the hardware manager.
1296  * @param    *table The SMC DPM table structure to be populated.
1297  * @return   0
1298  */
1299 static int iceland_populate_smc_vdd_ci_table(struct pp_hwmgr *hwmgr,
1300                         SMU71_Discrete_DpmTable *table)
1301 {
1302         int result;
1303         uint32_t count;
1304         iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
1305
1306         table->VddciLevelCount = data->vddci_voltage_table.count;
1307         for (count = 0; count < table->VddciLevelCount; count++) {
1308                 result = iceland_populate_smc_voltage_table(hwmgr,
1309                                 &data->vddci_voltage_table.entries[count],
1310                                 &table->VddciLevel[count]);
1311                 PP_ASSERT_WITH_CODE(0 == result, "do not populate SMC VDDCI voltage table", return -EINVAL);
1312
1313                 /* GPIO voltage control */
1314                 if (ICELAND_VOLTAGE_CONTROL_BY_GPIO == data->vdd_ci_control)
1315                         table->VddciLevel[count].Smio |= data->vddci_voltage_table.entries[count].smio_low;
1316                 else
1317                         table->VddciLevel[count].Smio = 0;
1318         }
1319
1320         CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount);
1321
1322         return 0;
1323 }
1324
1325 /**
1326  * Mvdd table preparation for SMC.
1327  *
1328  * @param    *hwmgr The address of the hardware manager.
1329  * @param    *table The SMC DPM table structure to be populated.
1330  * @return   0
1331  */
1332 static int iceland_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
1333                         SMU71_Discrete_DpmTable *table)
1334 {
1335         int result;
1336         uint32_t count;
1337         iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
1338
1339         table->MvddLevelCount = data->mvdd_voltage_table.count;
1340         for (count = 0; count < table->MvddLevelCount; count++) {
1341                 result = iceland_populate_smc_voltage_table(hwmgr,
1342                                 &data->mvdd_voltage_table.entries[count],
1343                                 &table->MvddLevel[count]);
1344                 PP_ASSERT_WITH_CODE(0 == result, "do not populate SMC VDDCI voltage table", return -EINVAL);
1345
1346                 /* GPIO voltage control */
1347                 if (ICELAND_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control)
1348                         table->MvddLevel[count].Smio |= data->mvdd_voltage_table.entries[count].smio_low;
1349                 else
1350                         table->MvddLevel[count].Smio = 0;
1351         }
1352
1353         CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount);
1354
1355         return 0;
1356 }
1357
1358 /**
1359  * Convert a voltage value in mv unit to VID number required by SMU firmware
1360  */
1361 static uint8_t convert_to_vid(uint16_t vddc)
1362 {
1363         return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
1364 }
1365
1366 int iceland_populate_bapm_vddc_vid_sidd(struct pp_hwmgr *hwmgr)
1367 {
1368         int i;
1369         struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend);
1370         uint8_t * hi_vid = data->power_tune_table.BapmVddCVidHiSidd;
1371         uint8_t * lo_vid = data->power_tune_table.BapmVddCVidLoSidd;
1372
1373         PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.cac_leakage_table,
1374                             "The CAC Leakage table does not exist!", return -EINVAL);
1375         PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count <= 8,
1376                             "There should never be more than 8 entries for BapmVddcVid!!!", return -EINVAL);
1377         PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_on_sclk->count,
1378                             "CACLeakageTable->count and VddcDependencyOnSCLk->count not equal", return -EINVAL);
1379
1380         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_EVV)) {
1381                 for (i = 0; (uint32_t) i < hwmgr->dyn_state.cac_leakage_table->count; i++) {
1382                         lo_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc1);
1383                         hi_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc2);
1384                 }
1385         } else {
1386                 PP_ASSERT_WITH_CODE(false, "Iceland should always support EVV", return -EINVAL);
1387         }
1388
1389         return 0;
1390 }
1391
1392 int iceland_populate_vddc_vid(struct pp_hwmgr *hwmgr)
1393 {
1394         int i;
1395         struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend);
1396         uint8_t *vid = data->power_tune_table.VddCVid;
1397
1398         PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 8,
1399                 "There should never be more than 8 entries for VddcVid!!!",
1400                 return -EINVAL);
1401
1402         for (i = 0; i < (int)data->vddc_voltage_table.count; i++) {
1403                 vid[i] = convert_to_vid(data->vddc_voltage_table.entries[i].value);
1404         }
1405
1406         return 0;
1407 }
1408
1409 /**
1410  * Preparation of voltage tables for SMC.
1411  *
1412  * @param    hwmgr      the address of the hardware manager
1413  * @param    table     the SMC DPM table structure to be populated
1414  * @return   always 0
1415  */
1416
1417 int iceland_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
1418         SMU71_Discrete_DpmTable *table)
1419 {
1420         int result;
1421
1422         result = iceland_populate_smc_vddc_table(hwmgr, table);
1423         PP_ASSERT_WITH_CODE(0 == result,
1424                         "can not populate VDDC voltage table to SMC", return -1);
1425
1426         result = iceland_populate_smc_vdd_ci_table(hwmgr, table);
1427         PP_ASSERT_WITH_CODE(0 == result,
1428                         "can not populate VDDCI voltage table to SMC", return -1);
1429
1430         result = iceland_populate_smc_mvdd_table(hwmgr, table);
1431         PP_ASSERT_WITH_CODE(0 == result,
1432                         "can not populate MVDD voltage table to SMC", return -1);
1433
1434         return 0;
1435 }
1436
1437
1438 /**
1439  * Re-generate the DPM level mask value
1440  * @param    hwmgr      the address of the hardware manager
1441  */
1442 static uint32_t iceland_get_dpm_level_enable_mask_value(
1443                         struct iceland_single_dpm_table * dpm_table)
1444 {
1445         uint32_t i;
1446         uint32_t mask_value = 0;
1447
1448         for (i = dpm_table->count; i > 0; i--) {
1449                 mask_value = mask_value << 1;
1450
1451                 if (dpm_table->dpm_levels[i-1].enabled)
1452                         mask_value |= 0x1;
1453                 else
1454                         mask_value &= 0xFFFFFFFE;
1455         }
1456         return mask_value;
1457 }
1458
1459 int iceland_populate_memory_timing_parameters(
1460                 struct pp_hwmgr *hwmgr,
1461                 uint32_t engine_clock,
1462                 uint32_t memory_clock,
1463                 struct SMU71_Discrete_MCArbDramTimingTableEntry *arb_regs
1464                 )
1465 {
1466         uint32_t dramTiming;
1467         uint32_t dramTiming2;
1468         uint32_t burstTime;
1469         int result;
1470
1471         result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1472                                 engine_clock, memory_clock);
1473
1474         PP_ASSERT_WITH_CODE(result == 0,
1475                 "Error calling VBIOS to set DRAM_TIMING.", return result);
1476
1477         dramTiming  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1478         dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1479         burstTime = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1480
1481         arb_regs->McArbDramTiming  = PP_HOST_TO_SMC_UL(dramTiming);
1482         arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2);
1483         arb_regs->McArbBurstTime = (uint8_t)burstTime;
1484
1485         return 0;
1486 }
1487
1488 /**
1489  * Setup parameters for the MC ARB.
1490  *
1491  * @param    hwmgr  the address of the powerplay hardware manager.
1492  * @return   always 0
1493  * This function is to be called from the SetPowerState table.
1494  */
1495 int iceland_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1496 {
1497         iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
1498         int result = 0;
1499         SMU71_Discrete_MCArbDramTimingTable  arb_regs;
1500         uint32_t i, j;
1501
1502         memset(&arb_regs, 0x00, sizeof(SMU71_Discrete_MCArbDramTimingTable));
1503
1504         for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1505                 for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
1506                         result = iceland_populate_memory_timing_parameters
1507                                 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value,
1508                                  data->dpm_table.mclk_table.dpm_levels[j].value,
1509                                  &arb_regs.entries[i][j]);
1510
1511                         if (0 != result) {
1512                                 break;
1513                         }
1514                 }
1515         }
1516
1517         if (0 == result) {
1518                 result = iceland_copy_bytes_to_smc(
1519                                 hwmgr->smumgr,
1520                                 data->arb_table_start,
1521                                 (uint8_t *)&arb_regs,
1522                                 sizeof(SMU71_Discrete_MCArbDramTimingTable),
1523                                 data->sram_end
1524                                 );
1525         }
1526
1527         return result;
1528 }
1529
1530 static int iceland_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU71_Discrete_DpmTable *table)
1531 {
1532         iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
1533         struct iceland_dpm_table *dpm_table = &data->dpm_table;
1534         uint32_t i;
1535
1536         /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */
1537         for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
1538                 table->LinkLevel[i].PcieGenSpeed  =
1539                         (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
1540                 table->LinkLevel[i].PcieLaneCount =
1541                         (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
1542                 table->LinkLevel[i].EnabledForActivity =
1543                         1;
1544                 table->LinkLevel[i].SPC =
1545                         (uint8_t)(data->pcie_spc_cap & 0xff);
1546                 table->LinkLevel[i].DownThreshold =
1547                         PP_HOST_TO_SMC_UL(5);
1548                 table->LinkLevel[i].UpThreshold =
1549                         PP_HOST_TO_SMC_UL(30);
1550         }
1551
1552         data->smc_state_table.LinkLevelCount =
1553                 (uint8_t)dpm_table->pcie_speed_table.count;
1554         data->dpm_level_enable_mask.pcie_dpm_enable_mask =
1555                 iceland_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
1556
1557         return 0;
1558 }
1559
1560 static int iceland_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1561                                         SMU71_Discrete_DpmTable *table)
1562 {
1563         return 0;
1564 }
1565
1566 uint8_t iceland_get_voltage_id(pp_atomctrl_voltage_table *voltage_table,
1567                 uint32_t voltage)
1568 {
1569         uint8_t count = (uint8_t) (voltage_table->count);
1570         uint8_t i = 0;
1571
1572         PP_ASSERT_WITH_CODE((NULL != voltage_table),
1573                 "Voltage Table empty.", return 0;);
1574         PP_ASSERT_WITH_CODE((0 != count),
1575                 "Voltage Table empty.", return 0;);
1576
1577         for (i = 0; i < count; i++) {
1578                 /* find first voltage bigger than requested */
1579                 if (voltage_table->entries[i].value >= voltage)
1580                         return i;
1581         }
1582
1583         /* voltage is bigger than max voltage in the table */
1584         return i - 1;
1585 }
1586
1587 static int iceland_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1588                                           SMU71_Discrete_DpmTable *table)
1589 {
1590         return 0;
1591 }
1592
1593 static int iceland_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
1594                                           SMU71_Discrete_DpmTable *table)
1595 {
1596         return 0;
1597 }
1598
1599 static int iceland_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
1600                                            SMU71_Discrete_DpmTable *table)
1601 {
1602         return 0;
1603 }
1604
1605
1606 static int iceland_populate_smc_svi2_config(struct pp_hwmgr *hwmgr,
1607                                             SMU71_Discrete_DpmTable *tab)
1608 {
1609         iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
1610
1611         if(ICELAND_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control)
1612                 tab->SVI2Enable |= VDDC_ON_SVI2;
1613
1614         if(ICELAND_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_ci_control)
1615                 tab->SVI2Enable |= VDDCI_ON_SVI2;
1616         else
1617                 tab->MergedVddci = 1;
1618
1619         if(ICELAND_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control)
1620                 tab->SVI2Enable |= MVDD_ON_SVI2;
1621
1622         PP_ASSERT_WITH_CODE( tab->SVI2Enable != (VDDC_ON_SVI2 | VDDCI_ON_SVI2 | MVDD_ON_SVI2) &&
1623                 (tab->SVI2Enable & VDDC_ON_SVI2), "SVI2 domain configuration is incorrect!", return -EINVAL);
1624
1625         return 0;
1626 }
1627
1628 static int iceland_get_dependecy_volt_by_clk(struct pp_hwmgr *hwmgr,
1629         struct phm_clock_voltage_dependency_table *allowed_clock_voltage_table,
1630         uint32_t clock, uint32_t *vol)
1631 {
1632         uint32_t i = 0;
1633
1634         /* clock - voltage dependency table is empty table */
1635         if (allowed_clock_voltage_table->count == 0)
1636                 return -EINVAL;
1637
1638         for (i = 0; i < allowed_clock_voltage_table->count; i++) {
1639                 /* find first sclk bigger than request */
1640                 if (allowed_clock_voltage_table->entries[i].clk >= clock) {
1641                         *vol = allowed_clock_voltage_table->entries[i].v;
1642                         return 0;
1643                 }
1644         }
1645
1646         /* sclk is bigger than max sclk in the dependence table */
1647         *vol = allowed_clock_voltage_table->entries[i - 1].v;
1648
1649         return 0;
1650 }
1651
1652 static uint8_t iceland_get_mclk_frequency_ratio(uint32_t memory_clock,
1653                 bool strobe_mode)
1654 {
1655         uint8_t mc_para_index;
1656
1657         if (strobe_mode) {
1658                 if (memory_clock < 12500) {
1659                         mc_para_index = 0x00;
1660                 } else if (memory_clock > 47500) {
1661                         mc_para_index = 0x0f;
1662                 } else {
1663                         mc_para_index = (uint8_t)((memory_clock - 10000) / 2500);
1664                 }
1665         } else {
1666                 if (memory_clock < 65000) {
1667                         mc_para_index = 0x00;
1668                 } else if (memory_clock > 135000) {
1669                         mc_para_index = 0x0f;
1670                 } else {
1671                         mc_para_index = (uint8_t)((memory_clock - 60000) / 5000);
1672                 }
1673         }
1674
1675         return mc_para_index;
1676 }
1677
1678 static uint8_t iceland_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock)
1679 {
1680         uint8_t mc_para_index;
1681
1682         if (memory_clock < 10000) {
1683                 mc_para_index = 0;
1684         } else if (memory_clock >= 80000) {
1685                 mc_para_index = 0x0f;
1686         } else {
1687                 mc_para_index = (uint8_t)((memory_clock - 10000) / 5000 + 1);
1688         }
1689
1690         return mc_para_index;
1691 }
1692
1693 static int iceland_populate_phase_value_based_on_sclk(struct pp_hwmgr *hwmgr, const struct phm_phase_shedding_limits_table *pl,
1694                                         uint32_t sclk, uint32_t *p_shed)
1695 {
1696         unsigned int i;
1697
1698         /* use the minimum phase shedding */
1699         *p_shed = 1;
1700
1701         /*
1702          * PPGen ensures the phase shedding limits table is sorted
1703          * from lowest voltage/sclk/mclk to highest voltage/sclk/mclk.
1704          * VBIOS ensures the phase shedding masks table is sorted from
1705          * least phases enabled (phase shedding on) to most phases
1706          * enabled (phase shedding off).
1707          */
1708         for (i = 0; i < pl->count; i++) {
1709             if (sclk < pl->entries[i].Sclk) {
1710                 /* Enable phase shedding */
1711                 *p_shed = i;
1712                 break;
1713             }
1714         }
1715
1716         return 0;
1717 }
1718
1719 static int iceland_populate_phase_value_based_on_mclk(struct pp_hwmgr *hwmgr, const struct phm_phase_shedding_limits_table *pl,
1720                                         uint32_t memory_clock, uint32_t *p_shed)
1721 {
1722         unsigned int i;
1723
1724         /* use the minimum phase shedding */
1725         *p_shed = 1;
1726
1727         /*
1728          * PPGen ensures the phase shedding limits table is sorted
1729          * from lowest voltage/sclk/mclk to highest voltage/sclk/mclk.
1730          * VBIOS ensures the phase shedding masks table is sorted from
1731          * least phases enabled (phase shedding on) to most phases
1732          * enabled (phase shedding off).
1733          */
1734         for (i = 0; i < pl->count; i++) {
1735             if (memory_clock < pl->entries[i].Mclk) {
1736                 /* Enable phase shedding */
1737                 *p_shed = i;
1738                 break;
1739             }
1740         }
1741
1742         return 0;
1743 }
1744
1745 /**
1746  * Populates the SMC MCLK structure using the provided memory clock
1747  *
1748  * @param    hwmgr      the address of the hardware manager
1749  * @param    memory_clock the memory clock to use to populate the structure
1750  * @param    sclk        the SMC SCLK structure to be populated
1751  */
1752 static int iceland_calculate_mclk_params(
1753                 struct pp_hwmgr *hwmgr,
1754                 uint32_t memory_clock,
1755                 SMU71_Discrete_MemoryLevel *mclk,
1756                 bool strobe_mode,
1757                 bool dllStateOn
1758                 )
1759 {
1760         const iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
1761         uint32_t  dll_cntl = data->clock_registers.vDLL_CNTL;
1762         uint32_t  mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;
1763         uint32_t  mpll_ad_func_cntl = data->clock_registers.vMPLL_AD_FUNC_CNTL;
1764         uint32_t  mpll_dq_func_cntl = data->clock_registers.vMPLL_DQ_FUNC_CNTL;
1765         uint32_t  mpll_func_cntl = data->clock_registers.vMPLL_FUNC_CNTL;
1766         uint32_t  mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1;
1767         uint32_t  mpll_func_cntl_2 = data->clock_registers.vMPLL_FUNC_CNTL_2;
1768         uint32_t  mpll_ss1 = data->clock_registers.vMPLL_SS1;
1769         uint32_t  mpll_ss2 = data->clock_registers.vMPLL_SS2;
1770
1771         pp_atomctrl_memory_clock_param mpll_param;
1772         int result;
1773
1774         result = atomctrl_get_memory_pll_dividers_si(hwmgr,
1775                                 memory_clock, &mpll_param, strobe_mode);
1776         PP_ASSERT_WITH_CODE(0 == result,
1777                 "Error retrieving Memory Clock Parameters from VBIOS.", return result);
1778
1779         /* MPLL_FUNC_CNTL setup*/
1780         mpll_func_cntl = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL, mpll_param.bw_ctrl);
1781
1782         /* MPLL_FUNC_CNTL_1 setup*/
1783         mpll_func_cntl_1  = PHM_SET_FIELD(mpll_func_cntl_1,
1784                                                         MPLL_FUNC_CNTL_1, CLKF, mpll_param.mpll_fb_divider.cl_kf);
1785         mpll_func_cntl_1  = PHM_SET_FIELD(mpll_func_cntl_1,
1786                                                         MPLL_FUNC_CNTL_1, CLKFRAC, mpll_param.mpll_fb_divider.clk_frac);
1787         mpll_func_cntl_1  = PHM_SET_FIELD(mpll_func_cntl_1,
1788                                                         MPLL_FUNC_CNTL_1, VCO_MODE, mpll_param.vco_mode);
1789
1790         /* MPLL_AD_FUNC_CNTL setup*/
1791         mpll_ad_func_cntl = PHM_SET_FIELD(mpll_ad_func_cntl,
1792                                                         MPLL_AD_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
1793
1794         if (data->is_memory_GDDR5) {
1795                 /* MPLL_DQ_FUNC_CNTL setup*/
1796                 mpll_dq_func_cntl  = PHM_SET_FIELD(mpll_dq_func_cntl,
1797                                                                 MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel);
1798                 mpll_dq_func_cntl  = PHM_SET_FIELD(mpll_dq_func_cntl,
1799                                                                 MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
1800         }
1801
1802         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1803                         PHM_PlatformCaps_MemorySpreadSpectrumSupport)) {
1804                 /*
1805                  ************************************
1806                  Fref = Reference Frequency
1807                  NF = Feedback divider ratio
1808                  NR = Reference divider ratio
1809                  Fnom = Nominal VCO output frequency = Fref * NF / NR
1810                  Fs = Spreading Rate
1811                  D = Percentage down-spread / 2
1812                  Fint = Reference input frequency to PFD = Fref / NR
1813                  NS = Spreading rate divider ratio = int(Fint / (2 * Fs))
1814                  CLKS = NS - 1 = ISS_STEP_NUM[11:0]
1815                  NV = D * Fs / Fnom * 4 * ((Fnom/Fref * NR) ^ 2)
1816                  CLKV = 65536 * NV = ISS_STEP_SIZE[25:0]
1817                  *************************************
1818                  */
1819                 pp_atomctrl_internal_ss_info ss_info;
1820                 uint32_t freq_nom;
1821                 uint32_t tmp;
1822                 uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr);
1823
1824                 /* for GDDR5 for all modes and DDR3 */
1825                 if (1 == mpll_param.qdr)
1826                         freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider);
1827                 else
1828                         freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider);
1829
1830                 /* tmp = (freq_nom / reference_clock * reference_divider) ^ 2  Note: S.I. reference_divider = 1*/
1831                 tmp = (freq_nom / reference_clock);
1832                 tmp = tmp * tmp;
1833
1834                 if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr, freq_nom, &ss_info)) {
1835                         /* ss_info.speed_spectrum_percentage -- in unit of 0.01% */
1836                         /* ss.Info.speed_spectrum_rate -- in unit of khz */
1837                         /* CLKS = reference_clock / (2 * speed_spectrum_rate * reference_divider) * 10 */
1838                         /*     = reference_clock * 5 / speed_spectrum_rate */
1839                         uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate;
1840
1841                         /* CLKV = 65536 * speed_spectrum_percentage / 2 * spreadSpecrumRate / freq_nom * 4 / 100000 * ((freq_nom / reference_clock) ^ 2) */
1842                         /*     = 131 * speed_spectrum_percentage * speed_spectrum_rate / 100 * ((freq_nom / reference_clock) ^ 2) / freq_nom */
1843                         uint32_t clkv =
1844                                 (uint32_t)((((131 * ss_info.speed_spectrum_percentage *
1845                                                         ss_info.speed_spectrum_rate) / 100) * tmp) / freq_nom);
1846
1847                         mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv);
1848                         mpll_ss2 = PHM_SET_FIELD(mpll_ss2, MPLL_SS2, CLKS, clks);
1849                 }
1850         }
1851
1852         /* MCLK_PWRMGT_CNTL setup */
1853         mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1854                 MCLK_PWRMGT_CNTL, DLL_SPEED, mpll_param.dll_speed);
1855         mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1856                 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, dllStateOn);
1857         mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1858                 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, dllStateOn);
1859
1860
1861         /* Save the result data to outpupt memory level structure */
1862         mclk->MclkFrequency   = memory_clock;
1863         mclk->MpllFuncCntl    = mpll_func_cntl;
1864         mclk->MpllFuncCntl_1  = mpll_func_cntl_1;
1865         mclk->MpllFuncCntl_2  = mpll_func_cntl_2;
1866         mclk->MpllAdFuncCntl  = mpll_ad_func_cntl;
1867         mclk->MpllDqFuncCntl  = mpll_dq_func_cntl;
1868         mclk->MclkPwrmgtCntl  = mclk_pwrmgt_cntl;
1869         mclk->DllCntl         = dll_cntl;
1870         mclk->MpllSs1         = mpll_ss1;
1871         mclk->MpllSs2         = mpll_ss2;
1872
1873         return 0;
1874 }
1875
1876 static int iceland_populate_single_memory_level(
1877                 struct pp_hwmgr *hwmgr,
1878                 uint32_t memory_clock,
1879                 SMU71_Discrete_MemoryLevel *memory_level
1880                 )
1881 {
1882         iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
1883         int result = 0;
1884         bool dllStateOn;
1885         struct cgs_display_info info = {0};
1886
1887
1888         if (NULL != hwmgr->dyn_state.vddc_dependency_on_mclk) {
1889                 result = iceland_get_dependecy_volt_by_clk(hwmgr,
1890                         hwmgr->dyn_state.vddc_dependency_on_mclk, memory_clock, &memory_level->MinVddc);
1891                 PP_ASSERT_WITH_CODE((0 == result),
1892                         "can not find MinVddc voltage value from memory VDDC voltage dependency table", return result);
1893         }
1894
1895         if (data->vdd_ci_control == ICELAND_VOLTAGE_CONTROL_NONE) {
1896                 memory_level->MinVddci = memory_level->MinVddc;
1897         } else if (NULL != hwmgr->dyn_state.vddci_dependency_on_mclk) {
1898                 result = iceland_get_dependecy_volt_by_clk(hwmgr,
1899                                 hwmgr->dyn_state.vddci_dependency_on_mclk,
1900                                 memory_clock,
1901                                 &memory_level->MinVddci);
1902                 PP_ASSERT_WITH_CODE((0 == result),
1903                         "can not find MinVddci voltage value from memory VDDCI voltage dependency table", return result);
1904         }
1905
1906         if (NULL != hwmgr->dyn_state.mvdd_dependency_on_mclk) {
1907                 result = iceland_get_dependecy_volt_by_clk(hwmgr,
1908                         hwmgr->dyn_state.mvdd_dependency_on_mclk, memory_clock, &memory_level->MinMvdd);
1909                 PP_ASSERT_WITH_CODE((0 == result),
1910                         "can not find MinMVDD voltage value from memory MVDD voltage dependency table", return result);
1911         }
1912
1913         memory_level->MinVddcPhases = 1;
1914
1915         if (data->vddc_phase_shed_control) {
1916                 iceland_populate_phase_value_based_on_mclk(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table,
1917                                 memory_clock, &memory_level->MinVddcPhases);
1918         }
1919
1920         memory_level->EnabledForThrottle = 1;
1921         memory_level->EnabledForActivity = 1;
1922         memory_level->UpHyst = 0;
1923         memory_level->DownHyst = 100;
1924         memory_level->VoltageDownHyst = 0;
1925
1926         /* Indicates maximum activity level for this performance level.*/
1927         memory_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
1928         memory_level->StutterEnable = 0;
1929         memory_level->StrobeEnable = 0;
1930         memory_level->EdcReadEnable = 0;
1931         memory_level->EdcWriteEnable = 0;
1932         memory_level->RttEnable = 0;
1933
1934         /* default set to low watermark. Highest level will be set to high later.*/
1935         memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1936
1937         cgs_get_active_displays_info(hwmgr->device, &info);
1938         data->display_timing.num_existing_displays = info.display_count;
1939
1940         //if ((data->mclk_stutter_mode_threshold != 0) &&
1941         //    (memory_clock <= data->mclk_stutter_mode_threshold) &&
1942         //    (data->is_uvd_enabled == 0)
1943         //    && (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE) & 0x1)
1944         //    && (data->display_timing.num_existing_displays <= 2)
1945         //    && (data->display_timing.num_existing_displays != 0))
1946         //      memory_level->StutterEnable = 1;
1947
1948         /* decide strobe mode*/
1949         memory_level->StrobeEnable = (data->mclk_strobe_mode_threshold != 0) &&
1950                 (memory_clock <= data->mclk_strobe_mode_threshold);
1951
1952         /* decide EDC mode and memory clock ratio*/
1953         if (data->is_memory_GDDR5) {
1954                 memory_level->StrobeRatio = iceland_get_mclk_frequency_ratio(memory_clock,
1955                                         memory_level->StrobeEnable);
1956
1957                 if ((data->mclk_edc_enable_threshold != 0) &&
1958                                 (memory_clock > data->mclk_edc_enable_threshold)) {
1959                         memory_level->EdcReadEnable = 1;
1960                 }
1961
1962                 if ((data->mclk_edc_wr_enable_threshold != 0) &&
1963                                 (memory_clock > data->mclk_edc_wr_enable_threshold)) {
1964                         memory_level->EdcWriteEnable = 1;
1965                 }
1966
1967                 if (memory_level->StrobeEnable) {
1968                         if (iceland_get_mclk_frequency_ratio(memory_clock, 1) >=
1969                                         ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf)) {
1970                                 dllStateOn = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
1971                         } else {
1972                                 dllStateOn = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0;
1973                         }
1974
1975                 } else {
1976                         dllStateOn = data->dll_defaule_on;
1977                 }
1978         } else {
1979                 memory_level->StrobeRatio =
1980                         iceland_get_ddr3_mclk_frequency_ratio(memory_clock);
1981                 dllStateOn = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
1982         }
1983
1984         result = iceland_calculate_mclk_params(hwmgr,
1985                 memory_clock, memory_level, memory_level->StrobeEnable, dllStateOn);
1986
1987         if (0 == result) {
1988                 memory_level->MinVddc = PP_HOST_TO_SMC_UL(memory_level->MinVddc * VOLTAGE_SCALE);
1989                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MinVddcPhases);
1990                 memory_level->MinVddci = PP_HOST_TO_SMC_UL(memory_level->MinVddci * VOLTAGE_SCALE);
1991                 memory_level->MinMvdd = PP_HOST_TO_SMC_UL(memory_level->MinMvdd * VOLTAGE_SCALE);
1992                 /* MCLK frequency in units of 10KHz*/
1993                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkFrequency);
1994                 /* Indicates maximum activity level for this performance level.*/
1995                 CONVERT_FROM_HOST_TO_SMC_US(memory_level->ActivityLevel);
1996                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl);
1997                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_1);
1998                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_2);
1999                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllAdFuncCntl);
2000                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllDqFuncCntl);
2001                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkPwrmgtCntl);
2002                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->DllCntl);
2003                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs1);
2004                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs2);
2005         }
2006
2007         return result;
2008 }
2009
2010 /**
2011  * Populates the SMC MVDD structure using the provided memory clock.
2012  *
2013  * @param    hwmgr      the address of the hardware manager
2014  * @param    mclk        the MCLK value to be used in the decision if MVDD should be high or low.
2015  * @param    voltage     the SMC VOLTAGE structure to be populated
2016  */
2017 int iceland_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk, SMU71_Discrete_VoltageLevel *voltage)
2018 {
2019         const iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
2020         uint32_t i = 0;
2021
2022         if (ICELAND_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
2023                 /* find mvdd value which clock is more than request */
2024                 for (i = 0; i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count; i++) {
2025                         if (mclk <= hwmgr->dyn_state.mvdd_dependency_on_mclk->entries[i].clk) {
2026                                 /* Always round to higher voltage. */
2027                                 voltage->Voltage = data->mvdd_voltage_table.entries[i].value;
2028                                 break;
2029                         }
2030                 }
2031
2032                 PP_ASSERT_WITH_CODE(i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count,
2033                         "MVDD Voltage is outside the supported range.", return -1);
2034
2035         } else {
2036                 return -1;
2037         }
2038
2039         return 0;
2040 }
2041
2042
2043 static int iceland_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
2044         SMU71_Discrete_DpmTable *table)
2045 {
2046         int result = 0;
2047         const iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
2048         pp_atomctrl_clock_dividers_vi dividers;
2049         SMU71_Discrete_VoltageLevel voltage_level;
2050         uint32_t spll_func_cntl    = data->clock_registers.vCG_SPLL_FUNC_CNTL;
2051         uint32_t spll_func_cntl_2  = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
2052         uint32_t dll_cntl          = data->clock_registers.vDLL_CNTL;
2053         uint32_t mclk_pwrmgt_cntl  = data->clock_registers.vMCLK_PWRMGT_CNTL;
2054
2055         /* The ACPI state should not do DPM on DC (or ever).*/
2056         table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
2057
2058         if (data->acpi_vddc)
2059                 table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->acpi_vddc * VOLTAGE_SCALE);
2060         else
2061                 table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->min_vddc_in_pp_table * VOLTAGE_SCALE);
2062
2063         table->ACPILevel.MinVddcPhases = (data->vddc_phase_shed_control) ? 0 : 1;
2064
2065         /* assign zero for now*/
2066         table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr);
2067
2068         /* get the engine clock dividers for this clock value*/
2069         result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
2070                 table->ACPILevel.SclkFrequency,  &dividers);
2071
2072         PP_ASSERT_WITH_CODE(result == 0,
2073                 "Error retrieving Engine Clock dividers from VBIOS.", return result);
2074
2075         /* divider ID for required SCLK*/
2076         table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
2077         table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2078         table->ACPILevel.DeepSleepDivId = 0;
2079
2080         spll_func_cntl      = PHM_SET_FIELD(spll_func_cntl,
2081                                                         CG_SPLL_FUNC_CNTL,   SPLL_PWRON,     0);
2082         spll_func_cntl      = PHM_SET_FIELD(spll_func_cntl,
2083                                                         CG_SPLL_FUNC_CNTL,   SPLL_RESET,     1);
2084         spll_func_cntl_2    = PHM_SET_FIELD(spll_func_cntl_2,
2085                                                         CG_SPLL_FUNC_CNTL_2, SCLK_MUX_SEL,   4);
2086
2087         table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
2088         table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
2089         table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
2090         table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
2091         table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
2092         table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
2093         table->ACPILevel.CcPwrDynRm = 0;
2094         table->ACPILevel.CcPwrDynRm1 = 0;
2095
2096
2097         /* For various features to be enabled/disabled while this level is active.*/
2098         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
2099         /* SCLK frequency in units of 10KHz*/
2100         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
2101         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
2102         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
2103         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
2104         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
2105         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
2106         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
2107         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
2108         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
2109
2110         table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
2111         table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
2112
2113         /*  CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);*/
2114
2115         if (0 == iceland_populate_mvdd_value(hwmgr, 0, &voltage_level))
2116                 table->MemoryACPILevel.MinMvdd =
2117                         PP_HOST_TO_SMC_UL(voltage_level.Voltage * VOLTAGE_SCALE);
2118         else
2119                 table->MemoryACPILevel.MinMvdd = 0;
2120
2121         /* Force reset on DLL*/
2122         mclk_pwrmgt_cntl    = PHM_SET_FIELD(mclk_pwrmgt_cntl,
2123                 MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1);
2124         mclk_pwrmgt_cntl    = PHM_SET_FIELD(mclk_pwrmgt_cntl,
2125                 MCLK_PWRMGT_CNTL, MRDCK1_RESET, 0x1);
2126
2127         /* Disable DLL in ACPIState*/
2128         mclk_pwrmgt_cntl    = PHM_SET_FIELD(mclk_pwrmgt_cntl,
2129                 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, 0);
2130         mclk_pwrmgt_cntl    = PHM_SET_FIELD(mclk_pwrmgt_cntl,
2131                 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, 0);
2132
2133         /* Enable DLL bypass signal*/
2134         dll_cntl            = PHM_SET_FIELD(dll_cntl,
2135                 DLL_CNTL, MRDCK0_BYPASS, 0);
2136         dll_cntl            = PHM_SET_FIELD(dll_cntl,
2137                 DLL_CNTL, MRDCK1_BYPASS, 0);
2138
2139         table->MemoryACPILevel.DllCntl            =
2140                 PP_HOST_TO_SMC_UL(dll_cntl);
2141         table->MemoryACPILevel.MclkPwrmgtCntl     =
2142                 PP_HOST_TO_SMC_UL(mclk_pwrmgt_cntl);
2143         table->MemoryACPILevel.MpllAdFuncCntl     =
2144                 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_AD_FUNC_CNTL);
2145         table->MemoryACPILevel.MpllDqFuncCntl     =
2146                 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_DQ_FUNC_CNTL);
2147         table->MemoryACPILevel.MpllFuncCntl       =
2148                 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL);
2149         table->MemoryACPILevel.MpllFuncCntl_1     =
2150                 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_1);
2151         table->MemoryACPILevel.MpllFuncCntl_2     =
2152                 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_2);
2153         table->MemoryACPILevel.MpllSs1            =
2154                 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS1);
2155         table->MemoryACPILevel.MpllSs2            =
2156                 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2);
2157
2158         table->MemoryACPILevel.EnabledForThrottle = 0;
2159         table->MemoryACPILevel.EnabledForActivity = 0;
2160         table->MemoryACPILevel.UpHyst = 0;
2161         table->MemoryACPILevel.DownHyst = 100;
2162         table->MemoryACPILevel.VoltageDownHyst = 0;
2163         /* Indicates maximum activity level for this performance level.*/
2164         table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
2165
2166         table->MemoryACPILevel.StutterEnable = 0;
2167         table->MemoryACPILevel.StrobeEnable = 0;
2168         table->MemoryACPILevel.EdcReadEnable = 0;
2169         table->MemoryACPILevel.EdcWriteEnable = 0;
2170         table->MemoryACPILevel.RttEnable = 0;
2171
2172         return result;
2173 }
2174
2175 static int iceland_find_boot_level(struct iceland_single_dpm_table *table, uint32_t value, uint32_t *boot_level)
2176 {
2177         int result = 0;
2178         uint32_t i;
2179
2180         for (i = 0; i < table->count; i++) {
2181                 if (value == table->dpm_levels[i].value) {
2182                         *boot_level = i;
2183                         result = 0;
2184                 }
2185         }
2186         return result;
2187 }
2188
2189 /**
2190  * Calculates the SCLK dividers using the provided engine clock
2191  *
2192  * @param    hwmgr      the address of the hardware manager
2193  * @param    engine_clock the engine clock to use to populate the structure
2194  * @param    sclk        the SMC SCLK structure to be populated
2195  */
2196 int iceland_calculate_sclk_params(struct pp_hwmgr *hwmgr,
2197                 uint32_t engine_clock, SMU71_Discrete_GraphicsLevel *sclk)
2198 {
2199         const iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
2200         pp_atomctrl_clock_dividers_vi dividers;
2201         uint32_t spll_func_cntl            = data->clock_registers.vCG_SPLL_FUNC_CNTL;
2202         uint32_t spll_func_cntl_3          = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
2203         uint32_t spll_func_cntl_4          = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
2204         uint32_t cg_spll_spread_spectrum   = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
2205         uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
2206         uint32_t    reference_clock;
2207         uint32_t reference_divider;
2208         uint32_t fbdiv;
2209         int result;
2210
2211         /* get the engine clock dividers for this clock value*/
2212         result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock,  &dividers);
2213
2214         PP_ASSERT_WITH_CODE(result == 0,
2215                 "Error retrieving Engine Clock dividers from VBIOS.", return result);
2216
2217         /* To get FBDIV we need to multiply this by 16384 and divide it by Fref.*/
2218         reference_clock = atomctrl_get_reference_clock(hwmgr);
2219
2220         reference_divider = 1 + dividers.uc_pll_ref_div;
2221
2222         /* low 14 bits is fraction and high 12 bits is divider*/
2223         fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
2224
2225         /* SPLL_FUNC_CNTL setup*/
2226         spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
2227                 CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div);
2228         spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
2229                 CG_SPLL_FUNC_CNTL, SPLL_PDIV_A,  dividers.uc_pll_post_div);
2230
2231         /* SPLL_FUNC_CNTL_3 setup*/
2232         spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
2233                 CG_SPLL_FUNC_CNTL_3, SPLL_FB_DIV, fbdiv);
2234
2235         /* set to use fractional accumulation*/
2236         spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
2237                 CG_SPLL_FUNC_CNTL_3, SPLL_DITHEN, 1);
2238
2239         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2240                         PHM_PlatformCaps_EngineSpreadSpectrumSupport)) {
2241                 pp_atomctrl_internal_ss_info ss_info;
2242
2243                 uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div;
2244                 if (0 == atomctrl_get_engine_clock_spread_spectrum(hwmgr, vcoFreq, &ss_info)) {
2245                         /*
2246                         * ss_info.speed_spectrum_percentage -- in unit of 0.01%
2247                         * ss_info.speed_spectrum_rate -- in unit of khz
2248                         */
2249                         /* clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2 */
2250                         uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate);
2251
2252                         /* clkv = 2 * D * fbdiv / NS */
2253                         uint32_t clkV = 4 * ss_info.speed_spectrum_percentage * fbdiv / (clkS * 10000);
2254
2255                         cg_spll_spread_spectrum =
2256                                 PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, CLKS, clkS);
2257                         cg_spll_spread_spectrum =
2258                                 PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, SSEN, 1);
2259                         cg_spll_spread_spectrum_2 =
2260                                 PHM_SET_FIELD(cg_spll_spread_spectrum_2, CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clkV);
2261                 }
2262         }
2263
2264         sclk->SclkFrequency        = engine_clock;
2265         sclk->CgSpllFuncCntl3      = spll_func_cntl_3;
2266         sclk->CgSpllFuncCntl4      = spll_func_cntl_4;
2267         sclk->SpllSpreadSpectrum   = cg_spll_spread_spectrum;
2268         sclk->SpllSpreadSpectrum2  = cg_spll_spread_spectrum_2;
2269         sclk->SclkDid              = (uint8_t)dividers.pll_post_divider;
2270
2271         return 0;
2272 }
2273
2274 static uint8_t iceland_get_sleep_divider_id_from_clock(struct pp_hwmgr *hwmgr,
2275                 uint32_t engine_clock, uint32_t min_engine_clock_in_sr)
2276 {
2277         uint32_t i, temp;
2278         uint32_t min = (min_engine_clock_in_sr > ICELAND_MINIMUM_ENGINE_CLOCK) ?
2279                         min_engine_clock_in_sr : ICELAND_MINIMUM_ENGINE_CLOCK;
2280
2281         PP_ASSERT_WITH_CODE((engine_clock >= min),
2282                         "Engine clock can't satisfy stutter requirement!", return 0);
2283
2284         for (i = ICELAND_MAX_DEEPSLEEP_DIVIDER_ID;; i--) {
2285                 temp = engine_clock / (1 << i);
2286
2287                 if(temp >= min || i == 0)
2288                         break;
2289         }
2290         return (uint8_t)i;
2291 }
2292
2293 /**
2294  * Populates single SMC SCLK structure using the provided engine clock
2295  *
2296  * @param    hwmgr      the address of the hardware manager
2297  * @param    engine_clock the engine clock to use to populate the structure
2298  * @param    sclk        the SMC SCLK structure to be populated
2299  */
2300 static int iceland_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
2301                 uint32_t engine_clock, uint16_t sclk_activity_level_threshold,
2302                 SMU71_Discrete_GraphicsLevel *graphic_level)
2303 {
2304         int result;
2305         uint32_t threshold;
2306         iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
2307
2308         result = iceland_calculate_sclk_params(hwmgr, engine_clock, graphic_level);
2309
2310
2311         /* populate graphics levels*/
2312         result = iceland_get_dependecy_volt_by_clk(hwmgr,
2313                         hwmgr->dyn_state.vddc_dependency_on_sclk, engine_clock, &graphic_level->MinVddc);
2314         PP_ASSERT_WITH_CODE((0 == result),
2315                 "can not find VDDC voltage value for VDDC engine clock dependency table", return result);
2316
2317         /* SCLK frequency in units of 10KHz*/
2318         graphic_level->SclkFrequency = engine_clock;
2319
2320         /*
2321          * Minimum VDDC phases required to support this level, it
2322          * should get from dependence table.
2323          */
2324         graphic_level->MinVddcPhases = 1;
2325
2326         if (data->vddc_phase_shed_control) {
2327                 iceland_populate_phase_value_based_on_sclk(hwmgr,
2328                                 hwmgr->dyn_state.vddc_phase_shed_limits_table,
2329                                 engine_clock,
2330                                 &graphic_level->MinVddcPhases);
2331         }
2332
2333         /* Indicates maximum activity level for this performance level. 50% for now*/
2334         graphic_level->ActivityLevel = sclk_activity_level_threshold;
2335
2336         graphic_level->CcPwrDynRm = 0;
2337         graphic_level->CcPwrDynRm1 = 0;
2338         /* this level can be used if activity is high enough.*/
2339         graphic_level->EnabledForActivity = 1;
2340         /* this level can be used for throttling.*/
2341         graphic_level->EnabledForThrottle = 1;
2342         graphic_level->UpHyst = 0;
2343         graphic_level->DownHyst = 100;
2344         graphic_level->VoltageDownHyst = 0;
2345         graphic_level->PowerThrottle = 0;
2346
2347         threshold = engine_clock * data->fast_watermark_threshold / 100;
2348
2349         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2350                         PHM_PlatformCaps_SclkDeepSleep)) {
2351                 graphic_level->DeepSleepDivId =
2352                                 iceland_get_sleep_divider_id_from_clock(hwmgr, engine_clock,
2353                                                 data->display_timing.min_clock_insr);
2354         }
2355
2356         /* Default to slow, highest DPM level will be set to PPSMC_DISPLAY_WATERMARK_LOW later.*/
2357         graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2358
2359         if (0 == result) {
2360                 graphic_level->MinVddc = PP_HOST_TO_SMC_UL(graphic_level->MinVddc * VOLTAGE_SCALE);
2361                 /* CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVoltage);*/
2362                 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVddcPhases);
2363                 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SclkFrequency);
2364                 CONVERT_FROM_HOST_TO_SMC_US(graphic_level->ActivityLevel);
2365                 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl3);
2366                 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl4);
2367                 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum);
2368                 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum2);
2369                 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm);
2370                 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm1);
2371         }
2372
2373         return result;
2374 }
2375
2376 /**
2377  * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
2378  *
2379  * @param    hwmgr      the address of the hardware manager
2380  */
2381 static int iceland_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
2382 {
2383         iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
2384         struct iceland_dpm_table *dpm_table = &data->dpm_table;
2385         int result = 0;
2386         uint32_t level_array_adress = data->dpm_table_start +
2387                 offsetof(SMU71_Discrete_DpmTable, GraphicsLevel);
2388
2389         uint32_t level_array_size = sizeof(SMU71_Discrete_GraphicsLevel) * SMU71_MAX_LEVELS_GRAPHICS;
2390         SMU71_Discrete_GraphicsLevel *levels = data->smc_state_table.GraphicsLevel;
2391         uint32_t i;
2392         uint8_t highest_pcie_level_enabled = 0, lowest_pcie_level_enabled = 0, mid_pcie_level_enabled = 0, count = 0;
2393         memset(levels, 0x00, level_array_size);
2394
2395         for (i = 0; i < dpm_table->sclk_table.count; i++) {
2396                 result = iceland_populate_single_graphic_level(hwmgr,
2397                                         dpm_table->sclk_table.dpm_levels[i].value,
2398                                         (uint16_t)data->activity_target[i],
2399                                         &(data->smc_state_table.GraphicsLevel[i]));
2400                 if (0 != result)
2401                         return result;
2402
2403                 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
2404                 if (i > 1)
2405                         data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
2406         }
2407
2408         /* set highest level watermark to high */
2409         if (dpm_table->sclk_table.count > 1)
2410                 data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark =
2411                         PPSMC_DISPLAY_WATERMARK_HIGH;
2412
2413         data->smc_state_table.GraphicsDpmLevelCount =
2414                 (uint8_t)dpm_table->sclk_table.count;
2415         data->dpm_level_enable_mask.sclk_dpm_enable_mask =
2416                 iceland_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
2417
2418         while ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
2419                                 (1 << (highest_pcie_level_enabled + 1))) != 0) {
2420                 highest_pcie_level_enabled++;
2421         }
2422
2423         while ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
2424                (1 << lowest_pcie_level_enabled)) == 0) {
2425                 lowest_pcie_level_enabled++;
2426         }
2427
2428         while ((count < highest_pcie_level_enabled) &&
2429                         ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
2430                                 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0)) {
2431                 count++;
2432         }
2433
2434         mid_pcie_level_enabled = (lowest_pcie_level_enabled+1+count) < highest_pcie_level_enabled ?
2435                 (lowest_pcie_level_enabled + 1 + count) : highest_pcie_level_enabled;
2436
2437         /* set pcieDpmLevel to highest_pcie_level_enabled*/
2438         for (i = 2; i < dpm_table->sclk_table.count; i++) {
2439                 data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled;
2440         }
2441
2442         /* set pcieDpmLevel to lowest_pcie_level_enabled*/
2443         data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled;
2444
2445         /* set pcieDpmLevel to mid_pcie_level_enabled*/
2446         data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled;
2447
2448         /* level count will send to smc once at init smc table and never change*/
2449         result = iceland_copy_bytes_to_smc(hwmgr->smumgr, level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size, data->sram_end);
2450
2451         if (0 != result)
2452                 return result;
2453
2454         return 0;
2455 }
2456
2457 /**
2458  * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
2459  *
2460  * @param    hwmgr      the address of the hardware manager
2461  */
2462
2463 static int iceland_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
2464 {
2465         iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
2466         struct iceland_dpm_table *dpm_table = &data->dpm_table;
2467         int result;
2468         /* populate MCLK dpm table to SMU7 */
2469         uint32_t level_array_adress = data->dpm_table_start + offsetof(SMU71_Discrete_DpmTable, MemoryLevel);
2470         uint32_t level_array_size = sizeof(SMU71_Discrete_MemoryLevel) * SMU71_MAX_LEVELS_MEMORY;
2471         SMU71_Discrete_MemoryLevel *levels = data->smc_state_table.MemoryLevel;
2472         uint32_t i;
2473
2474         memset(levels, 0x00, level_array_size);
2475
2476         for (i = 0; i < dpm_table->mclk_table.count; i++) {
2477                 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
2478                         "can not populate memory level as memory clock is zero", return -1);
2479                 result = iceland_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value,
2480                         &(data->smc_state_table.MemoryLevel[i]));
2481                 if (0 != result) {
2482                         return result;
2483                 }
2484         }
2485
2486         /* Only enable level 0 for now.*/
2487         data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
2488
2489         /*
2490         * in order to prevent MC activity from stutter mode to push DPM up.
2491         * the UVD change complements this by putting the MCLK in a higher state
2492         * by default such that we are not effected by up threshold or and MCLK DPM latency.
2493         */
2494         data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F;
2495         CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.MemoryLevel[0].ActivityLevel);
2496
2497         data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count;
2498         data->dpm_level_enable_mask.mclk_dpm_enable_mask = iceland_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
2499         /* set highest level watermark to high*/
2500         data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
2501
2502         /* level count will send to smc once at init smc table and never change*/
2503         result = iceland_copy_bytes_to_smc(hwmgr->smumgr,
2504                 level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size, data->sram_end);
2505
2506         if (0 != result) {
2507                 return result;
2508         }
2509
2510         return 0;
2511 }
2512
2513 struct ICELAND_DLL_SPEED_SETTING
2514 {
2515         uint16_t        Min;           /* Minimum Data Rate*/
2516         uint16_t        Max;           /* Maximum Data Rate*/
2517         uint32_t        dll_speed;     /* The desired DLL_SPEED setting*/
2518 };
2519
2520 static int iceland_populate_ulv_level(struct pp_hwmgr *hwmgr, SMU71_Discrete_Ulv *pstate)
2521 {
2522         int result = 0;
2523         iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
2524         uint32_t voltage_response_time, ulv_voltage;
2525
2526         pstate->CcPwrDynRm = 0;
2527         pstate->CcPwrDynRm1 = 0;
2528
2529         //backbiasResponseTime is use for ULV state voltage value.
2530         result = pp_tables_get_response_times(hwmgr, &voltage_response_time, &ulv_voltage);
2531         PP_ASSERT_WITH_CODE((0 == result), "can not get ULV voltage value", return result;);
2532
2533         if(!ulv_voltage) {
2534                 data->ulv.ulv_supported = false;
2535                 return 0;
2536         }
2537
2538         if (ICELAND_VOLTAGE_CONTROL_BY_SVID2 != data->voltage_control) {
2539                 /* use minimum voltage if ulv voltage in pptable is bigger than minimum voltage */
2540                 if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v) {
2541                         pstate->VddcOffset = 0;
2542                 }
2543                 else {
2544                         /* used in SMIO Mode. not implemented for now. this is backup only for CI. */
2545                         pstate->VddcOffset = (uint16_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage);
2546                 }
2547         } else {
2548                 /* use minimum voltage if ulv voltage in pptable is bigger than minimum voltage */
2549                 if(ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v) {
2550                         pstate->VddcOffsetVid = 0;
2551                 } else {
2552                         /* used in SVI2 Mode */
2553                         pstate->VddcOffsetVid = (uint8_t)((hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage) * VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
2554                 }
2555         }
2556
2557         /* used in SVI2 Mode to shed phase */
2558         pstate->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
2559
2560         if (0 == result) {
2561                 CONVERT_FROM_HOST_TO_SMC_UL(pstate->CcPwrDynRm);
2562                 CONVERT_FROM_HOST_TO_SMC_UL(pstate->CcPwrDynRm1);
2563                 CONVERT_FROM_HOST_TO_SMC_US(pstate->VddcOffset);
2564         }
2565
2566         return result;
2567 }
2568
2569 static int iceland_populate_ulv_state(struct pp_hwmgr *hwmgr, SMU71_Discrete_Ulv *ulv)
2570 {
2571         return iceland_populate_ulv_level(hwmgr, ulv);
2572 }
2573
2574 static int iceland_populate_smc_initial_state(struct pp_hwmgr *hwmgr)
2575 {
2576         iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
2577         uint8_t count, level;
2578
2579         count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->count);
2580
2581         for (level = 0; level < count; level++) {
2582                 if (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[level].clk
2583                          >= data->vbios_boot_state.sclk_bootup_value) {
2584                         data->smc_state_table.GraphicsBootLevel = level;
2585                         break;
2586                 }
2587         }
2588
2589         count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_mclk->count);
2590
2591         for (level = 0; level < count; level++) {
2592                 if (hwmgr->dyn_state.vddc_dependency_on_mclk->entries[level].clk
2593                         >= data->vbios_boot_state.mclk_bootup_value) {
2594                         data->smc_state_table.MemoryBootLevel = level;
2595                         break;
2596                 }
2597         }
2598
2599         return 0;
2600 }
2601
2602 /**
2603  * Initializes the SMC table and uploads it
2604  *
2605  * @param    hwmgr  the address of the powerplay hardware manager.
2606  * @param    pInput  the pointer to input data (PowerState)
2607  * @return   always 0
2608  */
2609 int iceland_init_smc_table(struct pp_hwmgr *hwmgr)
2610 {
2611         int result;
2612         iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
2613         SMU71_Discrete_DpmTable  *table = &(data->smc_state_table);
2614         const struct phw_iceland_ulv_parm *ulv = &(data->ulv);
2615
2616         result = iceland_setup_default_dpm_tables(hwmgr);
2617         PP_ASSERT_WITH_CODE(0 == result,
2618                 "Failed to setup default DPM tables!", return result;);
2619         memset(&(data->smc_state_table), 0x00, sizeof(data->smc_state_table));
2620
2621         if (ICELAND_VOLTAGE_CONTROL_NONE != data->voltage_control) {
2622                 iceland_populate_smc_voltage_tables(hwmgr, table);
2623         }
2624
2625         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2626                         PHM_PlatformCaps_AutomaticDCTransition)) {
2627                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
2628         }
2629
2630         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2631                         PHM_PlatformCaps_StepVddc)) {
2632                 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
2633         }
2634
2635         if (data->is_memory_GDDR5) {
2636                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
2637         }
2638
2639         if (ulv->ulv_supported) {
2640                 result = iceland_populate_ulv_state(hwmgr, &data->ulv_setting);
2641                 PP_ASSERT_WITH_CODE(0 == result,
2642                         "Failed to initialize ULV state!", return result;);
2643
2644                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2645                         ixCG_ULV_PARAMETER, ulv->ch_ulv_parameter);
2646         }
2647
2648         result = iceland_populate_smc_link_level(hwmgr, table);
2649         PP_ASSERT_WITH_CODE(0 == result,
2650                 "Failed to initialize Link Level!", return result;);
2651
2652         result = iceland_populate_all_graphic_levels(hwmgr);
2653         PP_ASSERT_WITH_CODE(0 == result,
2654                 "Failed to initialize Graphics Level!", return result;);
2655
2656         result = iceland_populate_all_memory_levels(hwmgr);
2657         PP_ASSERT_WITH_CODE(0 == result,
2658                 "Failed to initialize Memory Level!", return result;);
2659
2660         result = iceland_populate_smc_acpi_level(hwmgr, table);
2661         PP_ASSERT_WITH_CODE(0 == result,
2662                 "Failed to initialize ACPI Level!", return result;);
2663
2664         result = iceland_populate_smc_vce_level(hwmgr, table);
2665         PP_ASSERT_WITH_CODE(0 == result,
2666                 "Failed to initialize VCE Level!", return result;);
2667
2668         result = iceland_populate_smc_acp_level(hwmgr, table);
2669         PP_ASSERT_WITH_CODE(0 == result,
2670                 "Failed to initialize ACP Level!", return result;);
2671
2672         result = iceland_populate_smc_samu_level(hwmgr, table);
2673         PP_ASSERT_WITH_CODE(0 == result,
2674                 "Failed to initialize SAMU Level!", return result;);
2675
2676         /*
2677          * Since only the initial state is completely set up at this
2678          * point (the other states are just copies of the boot state)
2679          * we only need to populate the  ARB settings for the initial
2680          * state.
2681          */
2682         result = iceland_program_memory_timing_parameters(hwmgr);
2683         PP_ASSERT_WITH_CODE(0 == result,
2684                 "Failed to Write ARB settings for the initial state.", return result;);
2685
2686         result = iceland_populate_smc_uvd_level(hwmgr, table);
2687         PP_ASSERT_WITH_CODE(0 == result,
2688                 "Failed to initialize UVD Level!", return result;);
2689
2690         table->GraphicsBootLevel = 0;
2691         table->MemoryBootLevel = 0;
2692
2693         /* find boot level from dpm table */
2694         result = iceland_find_boot_level(&(data->dpm_table.sclk_table),
2695                         data->vbios_boot_state.sclk_bootup_value,
2696                         (uint32_t *)&(data->smc_state_table.GraphicsBootLevel));
2697
2698         if (result)
2699                 pr_warning("VBIOS did not find boot engine clock value in dependency table.\n");
2700
2701         result = iceland_find_boot_level(&(data->dpm_table.mclk_table),
2702                                 data->vbios_boot_state.mclk_bootup_value,
2703                                 (uint32_t *)&(data->smc_state_table.MemoryBootLevel));
2704
2705         if (result)
2706                 pr_warning("VBIOS did not find boot memory clock value in dependency table.\n");
2707
2708         table->BootVddc = data->vbios_boot_state.vddc_bootup_value;
2709         if (ICELAND_VOLTAGE_CONTROL_NONE == data->vdd_ci_control) {
2710                 table->BootVddci = table->BootVddc;
2711         }
2712         else {
2713                 table->BootVddci = data->vbios_boot_state.vddci_bootup_value;
2714         }
2715         table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value;
2716
2717         result = iceland_populate_smc_initial_state(hwmgr);
2718         PP_ASSERT_WITH_CODE(0 == result, "Failed to initialize Boot State!", return result);
2719
2720         result = iceland_populate_bapm_parameters_in_dpm_table(hwmgr);
2721         PP_ASSERT_WITH_CODE(0 == result, "Failed to populate BAPM Parameters!", return result);
2722
2723         table->GraphicsVoltageChangeEnable  = 1;
2724         table->GraphicsThermThrottleEnable  = 1;
2725         table->GraphicsInterval = 1;
2726         table->VoltageInterval  = 1;
2727         table->ThermalInterval  = 1;
2728         table->TemperatureLimitHigh =
2729                 (data->thermal_temp_setting.temperature_high *
2730                  ICELAND_Q88_FORMAT_CONVERSION_UNIT) / PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2731         table->TemperatureLimitLow =
2732                 (data->thermal_temp_setting.temperature_low *
2733                 ICELAND_Q88_FORMAT_CONVERSION_UNIT) / PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2734         table->MemoryVoltageChangeEnable  = 1;
2735         table->MemoryInterval  = 1;
2736         table->VoltageResponseTime  = 0;
2737         table->PhaseResponseTime  = 0;
2738         table->MemoryThermThrottleEnable  = 1;
2739         table->PCIeBootLinkLevel = 0;
2740         table->PCIeGenInterval = 1;
2741
2742         result = iceland_populate_smc_svi2_config(hwmgr, table);
2743         PP_ASSERT_WITH_CODE(0 == result,
2744                 "Failed to populate SVI2 setting!", return result);
2745
2746         table->ThermGpio  = 17;
2747         table->SclkStepSize = 0x4000;
2748
2749         CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2750         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcVid);
2751         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcPhase);
2752         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddciVid);
2753         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskMvddVid);
2754         CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
2755         CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2756         CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2757         CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2758         CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2759
2760         table->BootVddc = PP_HOST_TO_SMC_US(table->BootVddc * VOLTAGE_SCALE);
2761         table->BootVddci = PP_HOST_TO_SMC_US(table->BootVddci * VOLTAGE_SCALE);
2762         table->BootMVdd = PP_HOST_TO_SMC_US(table->BootMVdd * VOLTAGE_SCALE);
2763
2764         /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2765         result = iceland_copy_bytes_to_smc(hwmgr->smumgr, data->dpm_table_start +
2766                                 offsetof(SMU71_Discrete_DpmTable, SystemFlags),
2767                                 (uint8_t *)&(table->SystemFlags),
2768                                 sizeof(SMU71_Discrete_DpmTable) - 3 * sizeof(SMU71_PIDController),
2769                                 data->sram_end);
2770
2771         PP_ASSERT_WITH_CODE(0 == result,
2772                 "Failed to upload dpm data to SMC memory!", return result);
2773
2774         /* Upload all ulv setting to SMC memory.(dpm level, dpm level count etc) */
2775         result = iceland_copy_bytes_to_smc(hwmgr->smumgr,
2776                         data->ulv_settings_start,
2777                         (uint8_t *)&(data->ulv_setting),
2778                         sizeof(SMU71_Discrete_Ulv),
2779                         data->sram_end);
2780
2781 #if 0
2782         /* Notify SMC to follow new GPIO scheme */
2783         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2784                         PHM_PlatformCaps_AutomaticDCTransition)) {
2785                 if (0 == iceland_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_UseNewGPIOScheme))
2786                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2787                                 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
2788         }
2789 #endif
2790
2791         return result;
2792 }
2793
2794 int iceland_populate_mc_reg_address(struct pp_hwmgr *hwmgr, SMU71_Discrete_MCRegisters *mc_reg_table)
2795 {
2796         const struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend);
2797
2798         uint32_t i, j;
2799
2800         for (i = 0, j = 0; j < data->iceland_mc_reg_table.last; j++) {
2801                 if (data->iceland_mc_reg_table.validflag & 1<<j) {
2802                         PP_ASSERT_WITH_CODE(i < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE,
2803                                 "Index of mc_reg_table->address[] array out of boundary", return -1);
2804                         mc_reg_table->address[i].s0 =
2805                                 PP_HOST_TO_SMC_US(data->iceland_mc_reg_table.mc_reg_address[j].s0);
2806                         mc_reg_table->address[i].s1 =
2807                                 PP_HOST_TO_SMC_US(data->iceland_mc_reg_table.mc_reg_address[j].s1);
2808                         i++;
2809                 }
2810         }
2811
2812         mc_reg_table->last = (uint8_t)i;
2813
2814         return 0;
2815 }
2816
2817 /* convert register values from driver to SMC format */
2818 void iceland_convert_mc_registers(
2819         const phw_iceland_mc_reg_entry * pEntry,
2820         SMU71_Discrete_MCRegisterSet *pData,
2821         uint32_t numEntries, uint32_t validflag)
2822 {
2823         uint32_t i, j;
2824
2825         for (i = 0, j = 0; j < numEntries; j++) {
2826                 if (validflag & 1<<j) {
2827                         pData->value[i] = PP_HOST_TO_SMC_UL(pEntry->mc_data[j]);
2828                         i++;
2829                 }
2830         }
2831 }
2832
2833 /* find the entry in the memory range table, then populate the value to SMC's iceland_mc_reg_table */
2834 int iceland_convert_mc_reg_table_entry_to_smc(
2835                 struct pp_hwmgr *hwmgr,
2836                 const uint32_t memory_clock,
2837                 SMU71_Discrete_MCRegisterSet *mc_reg_table_data
2838                 )
2839 {
2840         const iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend);
2841         uint32_t i = 0;
2842
2843         for (i = 0; i < data->iceland_mc_reg_table.num_entries; i++) {
2844                 if (memory_clock <=
2845                         data->iceland_mc_reg_table.mc_reg_table_entry[i].mclk_max) {
2846                         break;
2847                 }
2848         }
2849
2850         if ((i == data->iceland_mc_reg_table.num_entries) && (i > 0))
2851                 --i;
2852
2853         iceland_convert_mc_registers(&data->iceland_mc_reg_table.mc_reg_table_entry[i],
2854                 mc_reg_table_data, data->iceland_mc_reg_table.last, data->iceland_mc_reg_table.validflag);
2855
2856         return 0;
2857 }
2858
2859 int iceland_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
2860                 SMU71_Discrete_MCRegisters *mc_reg_table)
2861 {
2862         int result = 0;
2863         iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend);
2864         int res;
2865         uint32_t i;
2866
2867         for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
2868                 res = iceland_convert_mc_reg_table_entry_to_smc(
2869                                 hwmgr,
2870                                 data->dpm_table.mclk_table.dpm_levels[i].value,
2871                                 &mc_reg_table->data[i]
2872                                 );
2873
2874                 if (0 != res)
2875                         result = res;
2876         }
2877
2878         return result;
2879 }
2880
2881 int iceland_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
2882 {
2883         int result;
2884         struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend);
2885
2886         memset(&data->mc_reg_table, 0x00, sizeof(SMU71_Discrete_MCRegisters));
2887         result = iceland_populate_mc_reg_address(hwmgr, &(data->mc_reg_table));
2888         PP_ASSERT_WITH_CODE(0 == result,
2889                 "Failed to initialize MCRegTable for the MC register addresses!", return result;);
2890
2891         result = iceland_convert_mc_reg_table_to_smc(hwmgr, &data->mc_reg_table);
2892         PP_ASSERT_WITH_CODE(0 == result,
2893                 "Failed to initialize MCRegTable for driver state!", return result;);
2894
2895         return iceland_copy_bytes_to_smc(hwmgr->smumgr, data->mc_reg_table_start,
2896                         (uint8_t *)&data->mc_reg_table, sizeof(SMU71_Discrete_MCRegisters), data->sram_end);
2897 }
2898
2899 int iceland_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
2900 {
2901         PPSMC_Msg msg = has_display? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
2902
2903         return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ?  0 : -1;
2904 }
2905
2906 int iceland_enable_sclk_control(struct pp_hwmgr *hwmgr)
2907 {
2908         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, 0);
2909
2910         return 0;
2911 }
2912
2913 int iceland_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
2914 {
2915         iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
2916
2917         /* enable SCLK dpm */
2918         if (0 == data->sclk_dpm_key_disabled) {
2919                 PP_ASSERT_WITH_CODE(
2920                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2921                                                    PPSMC_MSG_DPM_Enable)),
2922                                 "Failed to enable SCLK DPM during DPM Start Function!",
2923                                 return -1);
2924         }
2925
2926         /* enable MCLK dpm */
2927         if (0 == data->mclk_dpm_key_disabled) {
2928                 PP_ASSERT_WITH_CODE(
2929                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2930                                              PPSMC_MSG_MCLKDPM_Enable)),
2931                                 "Failed to enable MCLK DPM during DPM Start Function!",
2932                                 return -1);
2933
2934                 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
2935
2936                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2937                         ixLCAC_MC0_CNTL, 0x05);/* CH0,1 read */
2938                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2939                         ixLCAC_MC1_CNTL, 0x05);/* CH2,3 read */
2940                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2941                         ixLCAC_CPL_CNTL, 0x100005);/*Read */
2942
2943                 udelay(10);
2944
2945                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2946                         ixLCAC_MC0_CNTL, 0x400005);/* CH0,1 write */
2947                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2948                         ixLCAC_MC1_CNTL, 0x400005);/* CH2,3 write */
2949                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2950                         ixLCAC_CPL_CNTL, 0x500005);/* write */
2951
2952         }
2953
2954         return 0;
2955 }
2956
2957 int iceland_start_dpm(struct pp_hwmgr *hwmgr)
2958 {
2959         iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
2960
2961         /* enable general power management */
2962         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, 1);
2963         /* enable sclk deep sleep */
2964         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, DYNAMIC_PM_EN, 1);
2965
2966         /* prepare for PCIE DPM */
2967         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SOFT_REGISTERS_TABLE_12, VoltageChangeTimeout, 0x1000);
2968
2969         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, SWRST_COMMAND_1, RESETLC, 0x0);
2970
2971         PP_ASSERT_WITH_CODE(
2972                         (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2973                                         PPSMC_MSG_Voltage_Cntl_Enable)),
2974                         "Failed to enable voltage DPM during DPM Start Function!",
2975                         return -1);
2976
2977         if (0 != iceland_enable_sclk_mclk_dpm(hwmgr)) {
2978                 PP_ASSERT_WITH_CODE(0, "Failed to enable Sclk DPM and Mclk DPM!", return -1);
2979         }
2980
2981         /* enable PCIE dpm */
2982         if (0 == data->pcie_dpm_key_disabled) {
2983                 PP_ASSERT_WITH_CODE(
2984                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2985                                                 PPSMC_MSG_PCIeDPM_Enable)),
2986                                 "Failed to enable pcie DPM during DPM Start Function!",
2987                                 return -1
2988                                 );
2989         }
2990
2991         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2992                             PHM_PlatformCaps_Falcon_QuickTransition)) {
2993                 smum_send_msg_to_smc(hwmgr->smumgr,
2994                                      PPSMC_MSG_EnableACDCGPIOInterrupt);
2995         }
2996
2997         return 0;
2998 }
2999
3000 static void iceland_set_dpm_event_sources(struct pp_hwmgr *hwmgr,
3001                 uint32_t sources)
3002 {
3003         bool protection;
3004         enum DPM_EVENT_SRC src;
3005
3006         switch (sources) {
3007         default:
3008                 printk(KERN_ERR "Unknown throttling event sources.");
3009                 /* fall through */
3010         case 0:
3011                 protection = false;
3012                 /* src is unused */
3013                 break;
3014         case (1 << PHM_AutoThrottleSource_Thermal):
3015                 protection = true;
3016                 src = DPM_EVENT_SRC_DIGITAL;
3017                 break;
3018         case (1 << PHM_AutoThrottleSource_External):
3019                 protection = true;
3020                 src = DPM_EVENT_SRC_EXTERNAL;
3021                 break;
3022         case (1 << PHM_AutoThrottleSource_External) |
3023                         (1 << PHM_AutoThrottleSource_Thermal):
3024                 protection = true;
3025                 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
3026                 break;
3027         }
3028         /* Order matters - don't enable thermal protection for the wrong source. */
3029         if (protection) {
3030                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
3031                                 DPM_EVENT_SRC, src);
3032                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
3033                                 THERMAL_PROTECTION_DIS,
3034                                 !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3035                                                 PHM_PlatformCaps_ThermalController));
3036         } else
3037                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
3038                                 THERMAL_PROTECTION_DIS, 1);
3039 }
3040
3041 static int iceland_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
3042                 PHM_AutoThrottleSource source)
3043 {
3044         struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend);
3045
3046         if (!(data->active_auto_throttle_sources & (1 << source))) {
3047                 data->active_auto_throttle_sources |= 1 << source;
3048                 iceland_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
3049         }
3050         return 0;
3051 }
3052
3053 static int iceland_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
3054 {
3055         return iceland_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
3056 }
3057
3058 static int iceland_tf_start_smc(struct pp_hwmgr *hwmgr)
3059 {
3060         int ret = 0;
3061
3062         if (!iceland_is_smc_ram_running(hwmgr->smumgr))
3063                 ret = iceland_smu_start_smc(hwmgr->smumgr);
3064
3065         return ret;
3066 }
3067
3068 /**
3069 * Programs the Deep Sleep registers
3070 *
3071 * @param    pHwMgr  the address of the powerplay hardware manager.
3072 * @param    pInput the pointer to input data (PhwEvergreen_DisplayConfiguration)
3073 * @param    pOutput the pointer to output data (unused)
3074 * @param    pStorage the pointer to temporary storage (unused)
3075 * @param    Result the last failure code (unused)
3076 * @return   always 0
3077 */
3078 static int iceland_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
3079 {
3080         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3081                             PHM_PlatformCaps_SclkDeepSleep)) {
3082                 if (smum_send_msg_to_smc(hwmgr->smumgr,
3083                                          PPSMC_MSG_MASTER_DeepSleep_ON) != 0)
3084                         PP_ASSERT_WITH_CODE(false,
3085                                             "Attempt to enable Master Deep Sleep switch failed!",
3086                                             return -EINVAL);
3087         } else {
3088                 if (smum_send_msg_to_smc(hwmgr->smumgr,
3089                                          PPSMC_MSG_MASTER_DeepSleep_OFF) != 0)
3090                         PP_ASSERT_WITH_CODE(false,
3091                                             "Attempt to disable Master Deep Sleep switch failed!",
3092                                             return -EINVAL);
3093         }
3094
3095         return 0;
3096 }
3097
3098 static int iceland_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
3099 {
3100         int tmp_result, result = 0;
3101
3102         if (cf_iceland_voltage_control(hwmgr)) {
3103                 tmp_result = iceland_enable_voltage_control(hwmgr);
3104                 PP_ASSERT_WITH_CODE((0 == tmp_result),
3105                         "Failed to enable voltage control!", return tmp_result);
3106
3107                 tmp_result = iceland_construct_voltage_tables(hwmgr);
3108                 PP_ASSERT_WITH_CODE((0 == tmp_result),
3109                         "Failed to contruct voltage tables!", return tmp_result);
3110         }
3111
3112         tmp_result = iceland_initialize_mc_reg_table(hwmgr);
3113         PP_ASSERT_WITH_CODE((0 == tmp_result),
3114                 "Failed to initialize MC reg table!", return tmp_result);
3115
3116         tmp_result = iceland_program_static_screen_threshold_parameters(hwmgr);
3117         PP_ASSERT_WITH_CODE((0 == tmp_result),
3118                 "Failed to program static screen threshold parameters!", return tmp_result);
3119
3120         tmp_result = iceland_enable_display_gap(hwmgr);
3121         PP_ASSERT_WITH_CODE((0 == tmp_result),
3122                 "Failed to enable display gap!", return tmp_result);
3123
3124         tmp_result = iceland_program_voting_clients(hwmgr);
3125         PP_ASSERT_WITH_CODE((0 == tmp_result),
3126                 "Failed to program voting clients!", return tmp_result);
3127
3128         tmp_result = iceland_upload_firmware(hwmgr);
3129         PP_ASSERT_WITH_CODE((0 == tmp_result),
3130                 "Failed to upload firmware header!", return tmp_result);
3131
3132         tmp_result = iceland_process_firmware_header(hwmgr);
3133         PP_ASSERT_WITH_CODE((0 == tmp_result),
3134                 "Failed to process firmware header!", return tmp_result);
3135
3136         tmp_result = iceland_initial_switch_from_arb_f0_to_f1(hwmgr);
3137         PP_ASSERT_WITH_CODE((0 == tmp_result),
3138                 "Failed to initialize switch from ArbF0 to F1!", return tmp_result);
3139
3140         tmp_result = iceland_init_smc_table(hwmgr);
3141         PP_ASSERT_WITH_CODE((0 == tmp_result),
3142                 "Failed to initialize SMC table!", return tmp_result);
3143
3144         tmp_result = iceland_populate_initial_mc_reg_table(hwmgr);
3145         PP_ASSERT_WITH_CODE((0 == tmp_result),
3146                 "Failed to populate initialize MC Reg table!", return tmp_result);
3147
3148         tmp_result = iceland_populate_pm_fuses(hwmgr);
3149         PP_ASSERT_WITH_CODE((0 == tmp_result),
3150                 "Failed to populate PM fuses!", return tmp_result);
3151
3152         /* start SMC */
3153         tmp_result = iceland_tf_start_smc(hwmgr);
3154         PP_ASSERT_WITH_CODE((0 == tmp_result),
3155                 "Failed to start SMC!", return tmp_result);
3156
3157         /* enable SCLK control */
3158         tmp_result = iceland_enable_sclk_control(hwmgr);
3159         PP_ASSERT_WITH_CODE((0 == tmp_result),
3160                 "Failed to enable SCLK control!", return tmp_result);
3161
3162         tmp_result = iceland_enable_deep_sleep_master_switch(hwmgr);
3163         PP_ASSERT_WITH_CODE((tmp_result == 0),
3164                 "Failed to enable deep sleep!", return tmp_result);
3165
3166         /* enable DPM */
3167         tmp_result = iceland_start_dpm(hwmgr);
3168         PP_ASSERT_WITH_CODE((0 == tmp_result),
3169                 "Failed to start DPM!", return tmp_result);
3170
3171         tmp_result = iceland_enable_smc_cac(hwmgr);
3172         PP_ASSERT_WITH_CODE((0 == tmp_result),
3173                 "Failed to enable SMC CAC!", return tmp_result);
3174
3175         tmp_result = iceland_enable_power_containment(hwmgr);
3176         PP_ASSERT_WITH_CODE((0 == tmp_result),
3177                 "Failed to enable power containment!", return tmp_result);
3178
3179         tmp_result = iceland_power_control_set_level(hwmgr);
3180         PP_ASSERT_WITH_CODE((0 == tmp_result),
3181                 "Failed to power control set level!", result = tmp_result);
3182
3183         tmp_result = iceland_enable_thermal_auto_throttle(hwmgr);
3184         PP_ASSERT_WITH_CODE((0 == tmp_result),
3185                         "Failed to enable thermal auto throttle!", result = tmp_result);
3186
3187         return result;
3188 }
3189
3190 static int iceland_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
3191 {
3192         return phm_hwmgr_backend_fini(hwmgr);
3193 }
3194
3195 static void iceland_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
3196 {
3197         iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend);
3198         struct phw_iceland_ulv_parm *ulv;
3199
3200         ulv = &data->ulv;
3201         ulv->ch_ulv_parameter = PPICELAND_CGULVPARAMETER_DFLT;
3202         data->voting_rights_clients0 = PPICELAND_VOTINGRIGHTSCLIENTS_DFLT0;
3203         data->voting_rights_clients1 = PPICELAND_VOTINGRIGHTSCLIENTS_DFLT1;
3204         data->voting_rights_clients2 = PPICELAND_VOTINGRIGHTSCLIENTS_DFLT2;
3205         data->voting_rights_clients3 = PPICELAND_VOTINGRIGHTSCLIENTS_DFLT3;
3206         data->voting_rights_clients4 = PPICELAND_VOTINGRIGHTSCLIENTS_DFLT4;
3207         data->voting_rights_clients5 = PPICELAND_VOTINGRIGHTSCLIENTS_DFLT5;
3208         data->voting_rights_clients6 = PPICELAND_VOTINGRIGHTSCLIENTS_DFLT6;
3209         data->voting_rights_clients7 = PPICELAND_VOTINGRIGHTSCLIENTS_DFLT7;
3210
3211         data->static_screen_threshold_unit = PPICELAND_STATICSCREENTHRESHOLDUNIT_DFLT;
3212         data->static_screen_threshold = PPICELAND_STATICSCREENTHRESHOLD_DFLT;
3213
3214         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3215                       PHM_PlatformCaps_ABM);
3216         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3217                     PHM_PlatformCaps_NonABMSupportInPPLib);
3218
3219         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3220                     PHM_PlatformCaps_DynamicACTiming);
3221
3222         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3223                       PHM_PlatformCaps_DisableMemoryTransition);
3224
3225         iceland_initialize_power_tune_defaults(hwmgr);
3226
3227         data->mclk_strobe_mode_threshold = 40000;
3228         data->mclk_stutter_mode_threshold = 30000;
3229         data->mclk_edc_enable_threshold = 40000;
3230         data->mclk_edc_wr_enable_threshold = 40000;
3231
3232         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3233                       PHM_PlatformCaps_DisableMCLS);
3234
3235         data->pcie_gen_performance.max = PP_PCIEGen1;
3236         data->pcie_gen_performance.min = PP_PCIEGen3;
3237         data->pcie_gen_power_saving.max = PP_PCIEGen1;
3238         data->pcie_gen_power_saving.min = PP_PCIEGen3;
3239
3240         data->pcie_lane_performance.max = 0;
3241         data->pcie_lane_performance.min = 16;
3242         data->pcie_lane_power_saving.max = 0;
3243         data->pcie_lane_power_saving.min = 16;
3244
3245         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3246                       PHM_PlatformCaps_SclkThrottleLowNotification);
3247 }
3248
3249 static int iceland_get_evv_voltage(struct pp_hwmgr *hwmgr)
3250 {
3251         iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
3252         uint16_t    virtual_voltage_id;
3253         uint16_t    vddc = 0;
3254         uint16_t    i;
3255
3256         /* the count indicates actual number of entries */
3257         data->vddc_leakage.count = 0;
3258         data->vddci_leakage.count = 0;
3259
3260         if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_EVV)) {
3261                 pr_err("Iceland should always support EVV\n");
3262                 return -EINVAL;
3263         }
3264
3265         /* retrieve voltage for leakage ID (0xff01 + i) */
3266         for (i = 0; i < ICELAND_MAX_LEAKAGE_COUNT; i++) {
3267                 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
3268
3269                 PP_ASSERT_WITH_CODE((0 == atomctrl_get_voltage_evv(hwmgr, virtual_voltage_id, &vddc)),
3270                                     "Error retrieving EVV voltage value!\n", continue);
3271
3272                 if (vddc >= 2000)
3273                         pr_warning("Invalid VDDC value!\n");
3274
3275                 if (vddc != 0 && vddc != virtual_voltage_id) {
3276                         data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = vddc;
3277                         data->vddc_leakage.leakage_id[data->vddc_leakage.count] = virtual_voltage_id;
3278                         data->vddc_leakage.count++;
3279                 }
3280         }
3281
3282         return 0;
3283 }
3284
3285 static void iceland_patch_with_vddc_leakage(struct pp_hwmgr *hwmgr,
3286                                             uint32_t *vddc)
3287 {
3288         iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend);
3289         uint32_t leakage_index;
3290         struct phw_iceland_leakage_voltage *leakage_table = &data->vddc_leakage;
3291
3292         /* search for leakage voltage ID 0xff01 ~ 0xff08 */
3293         for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
3294                 /*
3295                  * If this voltage matches a leakage voltage ID, patch
3296                  * with actual leakage voltage.
3297                  */
3298                 if (leakage_table->leakage_id[leakage_index] == *vddc) {
3299                         /*
3300                          * Need to make sure vddc is less than 2v or
3301                          * else, it could burn the ASIC.
3302                          */
3303                         if (leakage_table->actual_voltage[leakage_index] >= 2000)
3304                                 pr_warning("Invalid VDDC value!\n");
3305                         *vddc = leakage_table->actual_voltage[leakage_index];
3306                         /* we found leakage voltage */
3307                         break;
3308                 }
3309         }
3310
3311         if (*vddc >= ATOM_VIRTUAL_VOLTAGE_ID0)
3312                 pr_warning("Voltage value looks like a Leakage ID but it's not patched\n");
3313 }
3314
3315 static void iceland_patch_with_vddci_leakage(struct pp_hwmgr *hwmgr,
3316                                              uint32_t *vddci)
3317 {
3318         iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend);
3319         uint32_t leakage_index;
3320         struct phw_iceland_leakage_voltage *leakage_table = &data->vddci_leakage;
3321
3322         /* search for leakage voltage ID 0xff01 ~ 0xff08 */
3323         for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
3324                 /*
3325                  * If this voltage matches a leakage voltage ID, patch
3326                  * with actual leakage voltage.
3327                  */
3328                 if (leakage_table->leakage_id[leakage_index] == *vddci) {
3329                         *vddci = leakage_table->actual_voltage[leakage_index];
3330                         /* we found leakage voltage */
3331                         break;
3332                 }
3333         }
3334
3335         if (*vddci >= ATOM_VIRTUAL_VOLTAGE_ID0)
3336                 pr_warning("Voltage value looks like a Leakage ID but it's not patched\n");
3337 }
3338
3339 static int iceland_patch_vddc(struct pp_hwmgr *hwmgr,
3340                               struct phm_clock_voltage_dependency_table *tab)
3341 {
3342         uint16_t i;
3343
3344         if (tab)
3345                 for (i = 0; i < tab->count; i++)
3346                         iceland_patch_with_vddc_leakage(hwmgr, &tab->entries[i].v);
3347
3348         return 0;
3349 }
3350
3351 static int iceland_patch_vddci(struct pp_hwmgr *hwmgr,
3352                                struct phm_clock_voltage_dependency_table *tab)
3353 {
3354         uint16_t i;
3355
3356         if (tab)
3357                 for (i = 0; i < tab->count; i++)
3358                         iceland_patch_with_vddci_leakage(hwmgr, &tab->entries[i].v);
3359
3360         return 0;
3361 }
3362
3363 static int iceland_patch_vce_vddc(struct pp_hwmgr *hwmgr,
3364                                   struct phm_vce_clock_voltage_dependency_table *tab)
3365 {
3366         uint16_t i;
3367
3368         if (tab)
3369                 for (i = 0; i < tab->count; i++)
3370                         iceland_patch_with_vddc_leakage(hwmgr, &tab->entries[i].v);
3371
3372         return 0;
3373 }
3374
3375
3376 static int iceland_patch_uvd_vddc(struct pp_hwmgr *hwmgr,
3377                                   struct phm_uvd_clock_voltage_dependency_table *tab)
3378 {
3379         uint16_t i;
3380
3381         if (tab)
3382                 for (i = 0; i < tab->count; i++)
3383                         iceland_patch_with_vddc_leakage(hwmgr, &tab->entries[i].v);
3384
3385         return 0;
3386 }
3387
3388 static int iceland_patch_vddc_shed_limit(struct pp_hwmgr *hwmgr,
3389                                          struct phm_phase_shedding_limits_table *tab)
3390 {
3391         uint16_t i;
3392
3393         if (tab)
3394                 for (i = 0; i < tab->count; i++)
3395                         iceland_patch_with_vddc_leakage(hwmgr, &tab->entries[i].Voltage);
3396
3397         return 0;
3398 }
3399
3400 static int iceland_patch_samu_vddc(struct pp_hwmgr *hwmgr,
3401                                    struct phm_samu_clock_voltage_dependency_table *tab)
3402 {
3403         uint16_t i;
3404
3405         if (tab)
3406                 for (i = 0; i < tab->count; i++)
3407                         iceland_patch_with_vddc_leakage(hwmgr, &tab->entries[i].v);
3408
3409         return 0;
3410 }
3411
3412 static int iceland_patch_acp_vddc(struct pp_hwmgr *hwmgr,
3413                                   struct phm_acp_clock_voltage_dependency_table *tab)
3414 {
3415         uint16_t i;
3416
3417         if (tab)
3418                 for (i = 0; i < tab->count; i++)
3419                         iceland_patch_with_vddc_leakage(hwmgr, &tab->entries[i].v);
3420
3421         return 0;
3422 }
3423
3424 static int iceland_patch_limits_vddc(struct pp_hwmgr *hwmgr,
3425                                      struct phm_clock_and_voltage_limits *tab)
3426 {
3427         if (tab) {
3428                 iceland_patch_with_vddc_leakage(hwmgr, (uint32_t *)&tab->vddc);
3429                 iceland_patch_with_vddci_leakage(hwmgr, (uint32_t *)&tab->vddci);
3430         }
3431
3432         return 0;
3433 }
3434
3435 static int iceland_patch_cac_vddc(struct pp_hwmgr *hwmgr, struct phm_cac_leakage_table *tab)
3436 {
3437         uint32_t i;
3438         uint32_t vddc;
3439
3440         if (tab) {
3441                 for (i = 0; i < tab->count; i++) {
3442                         vddc = (uint32_t)(tab->entries[i].Vddc);
3443                         iceland_patch_with_vddc_leakage(hwmgr, &vddc);
3444                         tab->entries[i].Vddc = (uint16_t)vddc;
3445                 }
3446         }
3447
3448         return 0;
3449 }
3450
3451 static int iceland_patch_dependency_tables_with_leakage(struct pp_hwmgr *hwmgr)
3452 {
3453         int tmp;
3454
3455         tmp = iceland_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_sclk);
3456         if(tmp)
3457                 return -EINVAL;
3458
3459         tmp = iceland_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_mclk);
3460         if(tmp)
3461                 return -EINVAL;
3462
3463         tmp = iceland_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
3464         if(tmp)
3465                 return -EINVAL;
3466
3467         tmp = iceland_patch_vddci(hwmgr, hwmgr->dyn_state.vddci_dependency_on_mclk);
3468         if(tmp)
3469                 return -EINVAL;
3470
3471         tmp = iceland_patch_vce_vddc(hwmgr, hwmgr->dyn_state.vce_clock_voltage_dependency_table);
3472         if(tmp)
3473                 return -EINVAL;
3474
3475         tmp = iceland_patch_uvd_vddc(hwmgr, hwmgr->dyn_state.uvd_clock_voltage_dependency_table);
3476         if(tmp)
3477                 return -EINVAL;
3478
3479         tmp = iceland_patch_samu_vddc(hwmgr, hwmgr->dyn_state.samu_clock_voltage_dependency_table);
3480         if(tmp)
3481                 return -EINVAL;
3482
3483         tmp = iceland_patch_acp_vddc(hwmgr, hwmgr->dyn_state.acp_clock_voltage_dependency_table);
3484         if(tmp)
3485                 return -EINVAL;
3486
3487         tmp = iceland_patch_vddc_shed_limit(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table);
3488         if(tmp)
3489                 return -EINVAL;
3490
3491         tmp = iceland_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_ac);
3492         if(tmp)
3493                 return -EINVAL;
3494
3495         tmp = iceland_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_dc);
3496         if(tmp)
3497                 return -EINVAL;
3498
3499         tmp = iceland_patch_cac_vddc(hwmgr, hwmgr->dyn_state.cac_leakage_table);
3500         if(tmp)
3501                 return -EINVAL;
3502
3503         return 0;
3504 }
3505
3506 static int iceland_set_private_var_based_on_pptale(struct pp_hwmgr *hwmgr)
3507 {
3508         iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
3509
3510         struct phm_clock_voltage_dependency_table *allowed_sclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_sclk;
3511         struct phm_clock_voltage_dependency_table *allowed_mclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_mclk;
3512         struct phm_clock_voltage_dependency_table *allowed_mclk_vddci_table = hwmgr->dyn_state.vddci_dependency_on_mclk;
3513
3514         PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table != NULL,
3515                 "VDDC dependency on SCLK table is missing. This table is mandatory\n", return -EINVAL);
3516         PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table->count >= 1,
3517                 "VDDC dependency on SCLK table has to have is missing. This table is mandatory\n", return -EINVAL);
3518
3519         PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table != NULL,
3520                 "VDDC dependency on MCLK table is missing. This table is mandatory\n", return -EINVAL);
3521         PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table->count >= 1,
3522                 "VDD dependency on MCLK table has to have is missing. This table is mandatory\n", return -EINVAL);
3523
3524         data->min_vddc_in_pp_table = (uint16_t)allowed_sclk_vddc_table->entries[0].v;
3525         data->max_vddc_in_pp_table = (uint16_t)allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
3526
3527         hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
3528                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
3529         hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
3530                 allowed_mclk_vddc_table->entries[allowed_mclk_vddc_table->count - 1].clk;
3531         hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
3532                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
3533
3534         if (allowed_mclk_vddci_table != NULL && allowed_mclk_vddci_table->count >= 1) {
3535                 data->min_vddci_in_pp_table = (uint16_t)allowed_mclk_vddci_table->entries[0].v;
3536                 data->max_vddci_in_pp_table = (uint16_t)allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
3537         }
3538
3539         if (hwmgr->dyn_state.vddci_dependency_on_mclk != NULL && hwmgr->dyn_state.vddci_dependency_on_mclk->count > 1)
3540                 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = hwmgr->dyn_state.vddci_dependency_on_mclk->entries[hwmgr->dyn_state.vddci_dependency_on_mclk->count - 1].v;
3541
3542         return 0;
3543 }
3544
3545 static int iceland_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr)
3546 {
3547         uint32_t table_size;
3548         struct phm_clock_voltage_dependency_table *table_clk_vlt;
3549
3550         hwmgr->dyn_state.mclk_sclk_ratio = 4;
3551         hwmgr->dyn_state.sclk_mclk_delta = 15000;      /* 150 MHz */
3552         hwmgr->dyn_state.vddc_vddci_delta = 200;       /* 200mV */
3553
3554         /* initialize vddc_dep_on_dal_pwrl table */
3555         table_size = sizeof(uint32_t) + 4 * sizeof(struct phm_clock_voltage_dependency_record);
3556         table_clk_vlt = (struct phm_clock_voltage_dependency_table *)kzalloc(table_size, GFP_KERNEL);
3557
3558         if (NULL == table_clk_vlt) {
3559                 pr_err("[ powerplay ] Can not allocate space for vddc_dep_on_dal_pwrl! \n");
3560                 return -ENOMEM;
3561         } else {
3562                 table_clk_vlt->count = 4;
3563                 table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_ULTRALOW;
3564                 table_clk_vlt->entries[0].v = 0;
3565                 table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_LOW;
3566                 table_clk_vlt->entries[1].v = 720;
3567                 table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_NOMINAL;
3568                 table_clk_vlt->entries[2].v = 810;
3569                 table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_PERFORMANCE;
3570                 table_clk_vlt->entries[3].v = 900;
3571                 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
3572         }
3573
3574         return 0;
3575 }
3576
3577 /**
3578  * Initializes the Volcanic Islands Hardware Manager
3579  *
3580  * @param   hwmgr the address of the powerplay hardware manager.
3581  * @return   1 if success; otherwise appropriate error code.
3582  */
3583 static int iceland_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
3584 {
3585         int result = 0;
3586         SMU71_Discrete_DpmTable *table = NULL;
3587         iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend);
3588         pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
3589         bool stay_in_boot;
3590         struct phw_iceland_ulv_parm *ulv;
3591         struct cgs_system_info sys_info = {0};
3592
3593         PP_ASSERT_WITH_CODE((NULL != hwmgr),
3594                 "Invalid Parameter!", return -EINVAL;);
3595
3596         data->dll_defaule_on = 0;
3597         data->sram_end = SMC_RAM_END;
3598
3599         data->activity_target[0] = PPICELAND_TARGETACTIVITY_DFLT;
3600         data->activity_target[1] = PPICELAND_TARGETACTIVITY_DFLT;
3601         data->activity_target[2] = PPICELAND_TARGETACTIVITY_DFLT;
3602         data->activity_target[3] = PPICELAND_TARGETACTIVITY_DFLT;
3603         data->activity_target[4] = PPICELAND_TARGETACTIVITY_DFLT;
3604         data->activity_target[5] = PPICELAND_TARGETACTIVITY_DFLT;
3605         data->activity_target[6] = PPICELAND_TARGETACTIVITY_DFLT;
3606         data->activity_target[7] = PPICELAND_TARGETACTIVITY_DFLT;
3607
3608         data->mclk_activity_target = PPICELAND_MCLK_TARGETACTIVITY_DFLT;
3609
3610         data->sclk_dpm_key_disabled = 0;
3611         data->mclk_dpm_key_disabled = 0;
3612         data->pcie_dpm_key_disabled = 0;
3613         data->pcc_monitor_enabled = 0;
3614
3615         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3616                     PHM_PlatformCaps_UnTabledHardwareInterface);
3617
3618         data->gpio_debug = 0;
3619         data->engine_clock_data = 0;
3620         data->memory_clock_data = 0;
3621
3622         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3623                       PHM_PlatformCaps_SclkDeepSleepAboveLow);
3624
3625         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3626                     PHM_PlatformCaps_DynamicPatchPowerState);
3627
3628         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3629                     PHM_PlatformCaps_TablelessHardwareInterface);
3630
3631         /* Initializes DPM default values. */
3632         iceland_initialize_dpm_defaults(hwmgr);
3633
3634         /* Enable Platform EVV support. */
3635         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3636                     PHM_PlatformCaps_EVV);
3637
3638         /* Get leakage voltage based on leakage ID. */
3639         result = iceland_get_evv_voltage(hwmgr);
3640         if (result)
3641                 goto failed;
3642
3643         /**
3644          * Patch our voltage dependency table with actual leakage
3645          * voltage. We need to perform leakage translation before it's
3646          * used by other functions such as
3647          * iceland_set_hwmgr_variables_based_on_pptable.
3648          */
3649         result = iceland_patch_dependency_tables_with_leakage(hwmgr);
3650         if (result)
3651                 goto failed;
3652
3653         /* Parse pptable data read from VBIOS. */
3654         result = iceland_set_private_var_based_on_pptale(hwmgr);
3655         if (result)
3656                 goto failed;
3657
3658         /* ULV support */
3659         ulv = &(data->ulv);
3660         ulv->ulv_supported = 1;
3661
3662         /* Initalize Dynamic State Adjustment Rule Settings*/
3663         result = iceland_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
3664         if (result) {
3665                 pr_err("[ powerplay ] iceland_initializa_dynamic_state_adjustment_rule_settings failed!\n");
3666                 goto failed;
3667         }
3668
3669         data->voltage_control = ICELAND_VOLTAGE_CONTROL_NONE;
3670         data->vdd_ci_control = ICELAND_VOLTAGE_CONTROL_NONE;
3671         data->mvdd_control = ICELAND_VOLTAGE_CONTROL_NONE;
3672
3673         /*
3674          * Hardcode thermal temperature settings for now, these will
3675          * be overwritten if a custom policy exists.
3676          */
3677         data->thermal_temp_setting.temperature_low = 99500;
3678         data->thermal_temp_setting.temperature_high = 100000;
3679         data->thermal_temp_setting.temperature_shutdown = 104000;
3680         data->uvd_enabled = false;
3681
3682         table = &data->smc_state_table;
3683
3684         if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID,
3685                                        &gpio_pin_assignment)) {
3686                 table->VRHotGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
3687                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3688                             PHM_PlatformCaps_RegulatorHot);
3689         } else {
3690                 table->VRHotGpio = ICELAND_UNUSED_GPIO_PIN;
3691                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3692                               PHM_PlatformCaps_RegulatorHot);
3693         }
3694
3695         if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
3696                                        &gpio_pin_assignment)) {
3697                 table->AcDcGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
3698                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3699                             PHM_PlatformCaps_AutomaticDCTransition);
3700         } else {
3701                 table->AcDcGpio = ICELAND_UNUSED_GPIO_PIN;
3702                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3703                               PHM_PlatformCaps_AutomaticDCTransition);
3704         }
3705
3706         /*
3707          * If ucGPIO_ID=VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak.
3708          * Current Control feature is enabled and we should program
3709          * PCC HW register
3710          */
3711         if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID,
3712                                        &gpio_pin_assignment)) {
3713                 uint32_t temp_reg = cgs_read_ind_register(hwmgr->device,
3714                                                           CGS_IND_REG__SMC,
3715                                                           ixCNB_PWRMGT_CNTL);
3716
3717                 switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
3718                 case 0:
3719                         temp_reg = PHM_SET_FIELD(temp_reg,
3720                                 CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
3721                         break;
3722                 case 1:
3723                         temp_reg = PHM_SET_FIELD(temp_reg,
3724                                 CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
3725                         break;
3726                 case 2:
3727                         temp_reg = PHM_SET_FIELD(temp_reg,
3728                                 CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
3729                         break;
3730                 case 3:
3731                         temp_reg = PHM_SET_FIELD(temp_reg,
3732                                 CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
3733                         break;
3734                 case 4:
3735                         temp_reg = PHM_SET_FIELD(temp_reg,
3736                                 CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
3737                         break;
3738                 default:
3739                         pr_warning("[ powerplay ] Failed to setup PCC HW register! Wrong GPIO assigned for VDDC_PCC_GPIO_PINID!\n");
3740                         break;
3741                 }
3742                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3743                                        ixCNB_PWRMGT_CNTL, temp_reg);
3744         }
3745
3746         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3747                     PHM_PlatformCaps_EnableSMU7ThermalManagement);
3748         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3749                     PHM_PlatformCaps_SMU7);
3750
3751         if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3752                                                      VOLTAGE_TYPE_VDDC,
3753                                                      VOLTAGE_OBJ_GPIO_LUT))
3754                 data->voltage_control = ICELAND_VOLTAGE_CONTROL_BY_GPIO;
3755         else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3756                                                           VOLTAGE_TYPE_VDDC,
3757                                                           VOLTAGE_OBJ_SVID2))
3758                 data->voltage_control = ICELAND_VOLTAGE_CONTROL_BY_SVID2;
3759
3760         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3761                             PHM_PlatformCaps_ControlVDDCI)) {
3762                 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3763                                                              VOLTAGE_TYPE_VDDCI,
3764                                                              VOLTAGE_OBJ_GPIO_LUT))
3765                         data->vdd_ci_control = ICELAND_VOLTAGE_CONTROL_BY_GPIO;
3766                 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3767                                                                   VOLTAGE_TYPE_VDDCI,
3768                                                                   VOLTAGE_OBJ_SVID2))
3769                         data->vdd_ci_control = ICELAND_VOLTAGE_CONTROL_BY_SVID2;
3770         }
3771
3772         if (data->vdd_ci_control == ICELAND_VOLTAGE_CONTROL_NONE)
3773                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3774                               PHM_PlatformCaps_ControlVDDCI);
3775
3776         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3777                             PHM_PlatformCaps_EnableMVDDControl)) {
3778                 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3779                                                              VOLTAGE_TYPE_MVDDC,
3780                                                              VOLTAGE_OBJ_GPIO_LUT))
3781                         data->mvdd_control = ICELAND_VOLTAGE_CONTROL_BY_GPIO;
3782                 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3783                                                                   VOLTAGE_TYPE_MVDDC,
3784                                                                   VOLTAGE_OBJ_SVID2))
3785                         data->mvdd_control = ICELAND_VOLTAGE_CONTROL_BY_SVID2;
3786         }
3787
3788         if (data->mvdd_control == ICELAND_VOLTAGE_CONTROL_NONE)
3789                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3790                               PHM_PlatformCaps_EnableMVDDControl);
3791
3792         data->vddc_phase_shed_control = false;
3793
3794         stay_in_boot = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3795                                        PHM_PlatformCaps_StayInBootState);
3796
3797         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3798                         PHM_PlatformCaps_DynamicPowerManagement);
3799
3800         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3801                         PHM_PlatformCaps_ActivityReporting);
3802
3803         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3804                         PHM_PlatformCaps_GFXClockGatingSupport);
3805
3806         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3807                         PHM_PlatformCaps_MemorySpreadSpectrumSupport);
3808         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3809                         PHM_PlatformCaps_EngineSpreadSpectrumSupport);
3810
3811         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3812                         PHM_PlatformCaps_DynamicPCIEGen2Support);
3813         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3814                         PHM_PlatformCaps_SMC);
3815
3816         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3817                         PHM_PlatformCaps_DisablePowerGating);
3818         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3819                         PHM_PlatformCaps_BACO);
3820
3821         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3822                         PHM_PlatformCaps_ThermalAutoThrottling);
3823         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3824                         PHM_PlatformCaps_DisableLSClockGating);
3825         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3826                         PHM_PlatformCaps_SamuDPM);
3827         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3828                         PHM_PlatformCaps_AcpDPM);
3829         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3830                         PHM_PlatformCaps_OD6inACSupport);
3831         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3832                         PHM_PlatformCaps_EnablePlatformPowerManagement);
3833
3834         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3835                         PHM_PlatformCaps_PauseMMSessions);
3836
3837         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3838                         PHM_PlatformCaps_OD6PlusinACSupport);
3839         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3840                         PHM_PlatformCaps_PauseMMSessions);
3841         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3842                         PHM_PlatformCaps_GFXClockGatingManagedInCAIL);
3843         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3844                         PHM_PlatformCaps_IcelandULPSSWWorkAround);
3845
3846
3847         /* iceland doesn't support UVD and VCE */
3848         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3849                       PHM_PlatformCaps_UVDPowerGating);
3850         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3851                       PHM_PlatformCaps_VCEPowerGating);
3852
3853         sys_info.size = sizeof(struct cgs_system_info);
3854         sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS;
3855         result = cgs_query_system_info(hwmgr->device, &sys_info);
3856         if (!result) {
3857                 if (sys_info.value & AMD_PG_SUPPORT_UVD)
3858                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3859                                       PHM_PlatformCaps_UVDPowerGating);
3860                 if (sys_info.value & AMD_PG_SUPPORT_VCE)
3861                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3862                                       PHM_PlatformCaps_VCEPowerGating);
3863
3864                 data->is_tlu_enabled = false;
3865                 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
3866                         ICELAND_MAX_HARDWARE_POWERLEVELS;
3867                 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
3868                 hwmgr->platform_descriptor.minimumClocksReductionPercentage  = 50;
3869
3870                 sys_info.size = sizeof(struct cgs_system_info);
3871                 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
3872                 result = cgs_query_system_info(hwmgr->device, &sys_info);
3873                 if (result)
3874                         data->pcie_gen_cap = AMDGPU_DEFAULT_PCIE_GEN_MASK;
3875                 else
3876                         data->pcie_gen_cap = (uint32_t)sys_info.value;
3877                 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
3878                         data->pcie_spc_cap = 20;
3879                 sys_info.size = sizeof(struct cgs_system_info);
3880                 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
3881                 result = cgs_query_system_info(hwmgr->device, &sys_info);
3882                 if (result)
3883                         data->pcie_lane_cap = AMDGPU_DEFAULT_PCIE_MLW_MASK;
3884                 else
3885                         data->pcie_lane_cap = (uint32_t)sys_info.value;
3886         } else {
3887                 /* Ignore return value in here, we are cleaning up a mess. */
3888                 iceland_hwmgr_backend_fini(hwmgr);
3889         }
3890
3891         return 0;
3892 failed:
3893         return result;
3894 }
3895
3896 static int iceland_get_num_of_entries(struct pp_hwmgr *hwmgr)
3897 {
3898         int result;
3899         unsigned long ret = 0;
3900
3901         result = pp_tables_get_num_of_entries(hwmgr, &ret);
3902
3903         return result ? 0 : ret;
3904 }
3905
3906 static const unsigned long PhwIceland_Magic = (unsigned long)(PHM_VIslands_Magic);
3907
3908 struct iceland_power_state *cast_phw_iceland_power_state(
3909                                   struct pp_hw_power_state *hw_ps)
3910 {
3911         if (hw_ps == NULL)
3912                 return NULL;
3913
3914         PP_ASSERT_WITH_CODE((PhwIceland_Magic == hw_ps->magic),
3915                                 "Invalid Powerstate Type!",
3916                                  return NULL);
3917
3918         return (struct iceland_power_state *)hw_ps;
3919 }
3920
3921 static int iceland_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
3922                                 struct pp_power_state  *prequest_ps,
3923                         const struct pp_power_state *pcurrent_ps)
3924 {
3925         struct iceland_power_state *iceland_ps =
3926                                 cast_phw_iceland_power_state(&prequest_ps->hardware);
3927
3928         uint32_t sclk;
3929         uint32_t mclk;
3930         struct PP_Clocks minimum_clocks = {0};
3931         bool disable_mclk_switching;
3932         bool disable_mclk_switching_for_frame_lock;
3933         struct cgs_display_info info = {0};
3934         const struct phm_clock_and_voltage_limits *max_limits;
3935         uint32_t i;
3936         iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend);
3937
3938         int32_t count;
3939         int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
3940
3941         data->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label);
3942
3943         PP_ASSERT_WITH_CODE(iceland_ps->performance_level_count == 2,
3944                                  "VI should always have 2 performance levels",
3945                                  );
3946
3947         max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
3948                         &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
3949                         &(hwmgr->dyn_state.max_clock_voltage_on_dc);
3950
3951         if (PP_PowerSource_DC == hwmgr->power_source) {
3952                 for (i = 0; i < iceland_ps->performance_level_count; i++) {
3953                         if (iceland_ps->performance_levels[i].memory_clock > max_limits->mclk)
3954                                 iceland_ps->performance_levels[i].memory_clock = max_limits->mclk;
3955                         if (iceland_ps->performance_levels[i].engine_clock > max_limits->sclk)
3956                                 iceland_ps->performance_levels[i].engine_clock = max_limits->sclk;
3957                 }
3958         }
3959
3960         iceland_ps->vce_clocks.EVCLK = hwmgr->vce_arbiter.evclk;
3961         iceland_ps->vce_clocks.ECCLK = hwmgr->vce_arbiter.ecclk;
3962
3963         cgs_get_active_displays_info(hwmgr->device, &info);
3964
3965         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
3966
3967                 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
3968                 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
3969
3970                 for (count = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1; count >= 0; count--) {
3971                         if (stable_pstate_sclk >= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk) {
3972                                 stable_pstate_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk;
3973                                 break;
3974                         }
3975                 }
3976
3977                 if (count < 0)
3978                         stable_pstate_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].clk;
3979
3980                 stable_pstate_mclk = max_limits->mclk;
3981
3982                 minimum_clocks.engineClock = stable_pstate_sclk;
3983                 minimum_clocks.memoryClock = stable_pstate_mclk;
3984         }
3985
3986         if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
3987                 minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
3988
3989         if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
3990                 minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
3991
3992         iceland_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
3993
3994         if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
3995                 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <= hwmgr->platform_descriptor.overdriveLimit.engineClock),
3996                                         "Overdrive sclk exceeds limit",
3997                                         hwmgr->gfx_arbiter.sclk_over_drive = hwmgr->platform_descriptor.overdriveLimit.engineClock);
3998
3999                 if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
4000                         iceland_ps->performance_levels[1].engine_clock = hwmgr->gfx_arbiter.sclk_over_drive;
4001         }
4002
4003         if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
4004                 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <= hwmgr->platform_descriptor.overdriveLimit.memoryClock),
4005                         "Overdrive mclk exceeds limit",
4006                         hwmgr->gfx_arbiter.mclk_over_drive = hwmgr->platform_descriptor.overdriveLimit.memoryClock);
4007
4008                 if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
4009                         iceland_ps->performance_levels[1].memory_clock = hwmgr->gfx_arbiter.mclk_over_drive;
4010         }
4011
4012         disable_mclk_switching_for_frame_lock = phm_cap_enabled(
4013                                     hwmgr->platform_descriptor.platformCaps,
4014                                     PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
4015
4016         disable_mclk_switching = (1 < info.display_count) ||
4017                                     disable_mclk_switching_for_frame_lock;
4018
4019         sclk  = iceland_ps->performance_levels[0].engine_clock;
4020         mclk  = iceland_ps->performance_levels[0].memory_clock;
4021
4022         if (disable_mclk_switching)
4023                 mclk  = iceland_ps->performance_levels[iceland_ps->performance_level_count - 1].memory_clock;
4024
4025         if (sclk < minimum_clocks.engineClock)
4026                 sclk = (minimum_clocks.engineClock > max_limits->sclk) ? max_limits->sclk : minimum_clocks.engineClock;
4027
4028         if (mclk < minimum_clocks.memoryClock)
4029                 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ? max_limits->mclk : minimum_clocks.memoryClock;
4030
4031         iceland_ps->performance_levels[0].engine_clock = sclk;
4032         iceland_ps->performance_levels[0].memory_clock = mclk;
4033
4034         iceland_ps->performance_levels[1].engine_clock =
4035                 (iceland_ps->performance_levels[1].engine_clock >= iceland_ps->performance_levels[0].engine_clock) ?
4036                               iceland_ps->performance_levels[1].engine_clock :
4037                               iceland_ps->performance_levels[0].engine_clock;
4038
4039         if (disable_mclk_switching) {
4040                 if (mclk < iceland_ps->performance_levels[1].memory_clock)
4041                         mclk = iceland_ps->performance_levels[1].memory_clock;
4042
4043                 iceland_ps->performance_levels[0].memory_clock = mclk;
4044                 iceland_ps->performance_levels[1].memory_clock = mclk;
4045         } else {
4046                 if (iceland_ps->performance_levels[1].memory_clock < iceland_ps->performance_levels[0].memory_clock)
4047                         iceland_ps->performance_levels[1].memory_clock = iceland_ps->performance_levels[0].memory_clock;
4048         }
4049
4050         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
4051                 for (i=0; i < iceland_ps->performance_level_count; i++) {
4052                         iceland_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
4053                         iceland_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
4054                         iceland_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
4055                         iceland_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
4056                 }
4057         }
4058
4059         return 0;
4060 }
4061
4062 static bool iceland_is_dpm_running(struct pp_hwmgr *hwmgr)
4063 {
4064         /*
4065          * We return the status of Voltage Control instead of checking SCLK/MCLK DPM
4066          * because we may have test scenarios that need us intentionly disable SCLK/MCLK DPM,
4067          * whereas voltage control is a fundemental change that will not be disabled
4068          */
4069         return (0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4070                                         FEATURE_STATUS, VOLTAGE_CONTROLLER_ON) ? 1 : 0);
4071 }
4072
4073 /**
4074  * force DPM power State
4075  *
4076  * @param    hwmgr:  the address of the powerplay hardware manager.
4077  * @param    n     :  DPM level
4078  * @return   The response that came from the SMC.
4079  */
4080 int iceland_dpm_force_state(struct pp_hwmgr *hwmgr, uint32_t n)
4081 {
4082         iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
4083
4084         /* Checking if DPM is running.  If we discover hang because of this, we should skip this message. */
4085         PP_ASSERT_WITH_CODE(0 == iceland_is_dpm_running(hwmgr),
4086                         "Trying to force SCLK when DPM is disabled", return -1;);
4087         if (0 == data->sclk_dpm_key_disabled)
4088                 return (0 == smum_send_msg_to_smc_with_parameter(
4089                                                              hwmgr->smumgr,
4090                                                              PPSMC_MSG_DPM_ForceState,
4091                                                              n) ? 0 : 1);
4092
4093         return 0;
4094 }
4095
4096 /**
4097  * force DPM power State
4098  *
4099  * @param    hwmgr:  the address of the powerplay hardware manager.
4100  * @param    n     :  DPM level
4101  * @return   The response that came from the SMC.
4102  */
4103 int iceland_dpm_force_state_mclk(struct pp_hwmgr *hwmgr, uint32_t n)
4104 {
4105         iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
4106
4107         /* Checking if DPM is running.  If we discover hang because of this, we should skip this message. */
4108         PP_ASSERT_WITH_CODE(0 == iceland_is_dpm_running(hwmgr),
4109                         "Trying to Force MCLK when DPM is disabled", return -1;);
4110         if (0 == data->mclk_dpm_key_disabled)
4111                 return (0 == smum_send_msg_to_smc_with_parameter(
4112                                                                 hwmgr->smumgr,
4113                                                                 PPSMC_MSG_MCLKDPM_ForceState,
4114                                                                 n) ? 0 : 1);
4115
4116         return 0;
4117 }
4118
4119 /**
4120  * force DPM power State
4121  *
4122  * @param    hwmgr:  the address of the powerplay hardware manager.
4123  * @param    n     :  DPM level
4124  * @return   The response that came from the SMC.
4125  */
4126 int iceland_dpm_force_state_pcie(struct pp_hwmgr *hwmgr, uint32_t n)
4127 {
4128         iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
4129
4130         /* Checking if DPM is running.  If we discover hang because of this, we should skip this message.*/
4131         PP_ASSERT_WITH_CODE(0 == iceland_is_dpm_running(hwmgr),
4132                         "Trying to Force PCIE level when DPM is disabled", return -1;);
4133         if (0 == data->pcie_dpm_key_disabled)
4134                 return (0 == smum_send_msg_to_smc_with_parameter(
4135                                                              hwmgr->smumgr,
4136                                                              PPSMC_MSG_PCIeDPM_ForceLevel,
4137                                                              n) ? 0 : 1);
4138
4139         return 0;
4140 }
4141
4142 static int iceland_force_dpm_highest(struct pp_hwmgr *hwmgr)
4143 {
4144         uint32_t level, tmp;
4145         iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
4146
4147         if (0 == data->sclk_dpm_key_disabled) {
4148                 /* SCLK */
4149                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask != 0) {
4150                         level = 0;
4151                         tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
4152                         while (tmp >>= 1)
4153                                 level++ ;
4154
4155                         if (0 != level) {
4156                                 PP_ASSERT_WITH_CODE((0 == iceland_dpm_force_state(hwmgr, level)),
4157                                         "force highest sclk dpm state failed!", return -1);
4158                                 PHM_WAIT_INDIRECT_FIELD(hwmgr->device,
4159                                         SMC_IND, TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX, level);
4160                         }
4161                 }
4162         }
4163
4164         if (0 == data->mclk_dpm_key_disabled) {
4165                 /* MCLK */
4166                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask != 0) {
4167                         level = 0;
4168                         tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
4169                         while (tmp >>= 1)
4170                                 level++ ;
4171
4172                         if (0 != level) {
4173                                 PP_ASSERT_WITH_CODE((0 == iceland_dpm_force_state_mclk(hwmgr, level)),
4174                                         "force highest mclk dpm state failed!", return -1);
4175                                 PHM_WAIT_INDIRECT_FIELD(hwmgr->device, SMC_IND,
4176                                         TARGET_AND_CURRENT_PROFILE_INDEX, CURR_MCLK_INDEX, level);
4177                         }
4178                 }
4179         }
4180
4181         if (0 == data->pcie_dpm_key_disabled) {
4182                 /* PCIE */
4183                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask != 0) {
4184                         level = 0;
4185                         tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
4186                         while (tmp >>= 1)
4187                                 level++ ;
4188
4189                         if (0 != level) {
4190                                 PP_ASSERT_WITH_CODE((0 == iceland_dpm_force_state_pcie(hwmgr, level)),
4191                                         "force highest pcie dpm state failed!", return -1);
4192                         }
4193                 }
4194         }
4195
4196         return 0;
4197 }
4198
4199 static uint32_t iceland_get_lowest_enable_level(struct pp_hwmgr *hwmgr,
4200                                                 uint32_t level_mask)
4201 {
4202         uint32_t level = 0;
4203
4204         while (0 == (level_mask & (1 << level)))
4205                 level++;
4206
4207         return level;
4208 }
4209
4210 static int iceland_force_dpm_lowest(struct pp_hwmgr *hwmgr)
4211 {
4212         uint32_t level;
4213         iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
4214
4215         /* for now force only sclk */
4216         if (0 != data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4217                 level = iceland_get_lowest_enable_level(hwmgr,
4218                                                       data->dpm_level_enable_mask.sclk_dpm_enable_mask);
4219
4220                 PP_ASSERT_WITH_CODE((0 == iceland_dpm_force_state(hwmgr, level)),
4221                                     "force sclk dpm state failed!", return -1);
4222
4223                 PHM_WAIT_INDIRECT_FIELD(hwmgr->device, SMC_IND,
4224                                         TARGET_AND_CURRENT_PROFILE_INDEX,
4225                                         CURR_SCLK_INDEX,
4226                                         level);
4227         }
4228
4229         return 0;
4230 }
4231
4232 int iceland_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
4233 {
4234         iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
4235
4236         PP_ASSERT_WITH_CODE (0 == iceland_is_dpm_running(hwmgr),
4237                 "Trying to Unforce DPM when DPM is disabled. Returning without sending SMC message.",
4238                 return -1);
4239
4240         if (0 == data->sclk_dpm_key_disabled) {
4241                 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(
4242                                                              hwmgr->smumgr,
4243                                         PPSMC_MSG_NoForcedLevel)),
4244                                            "unforce sclk dpm state failed!",
4245                                                                 return -1);
4246         }
4247
4248         if (0 == data->mclk_dpm_key_disabled) {
4249                 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(
4250                                                              hwmgr->smumgr,
4251                                         PPSMC_MSG_MCLKDPM_NoForcedLevel)),
4252                                            "unforce mclk dpm state failed!",
4253                                                                 return -1);
4254         }
4255
4256         if (0 == data->pcie_dpm_key_disabled) {
4257                 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(
4258                                                              hwmgr->smumgr,
4259                                         PPSMC_MSG_PCIeDPM_UnForceLevel)),
4260                                            "unforce pcie level failed!",
4261                                                                 return -1);
4262         }
4263
4264         return 0;
4265 }
4266
4267 static int iceland_force_dpm_level(struct pp_hwmgr *hwmgr,
4268                 enum amd_dpm_forced_level level)
4269 {
4270         int ret = 0;
4271
4272         switch (level) {
4273         case AMD_DPM_FORCED_LEVEL_HIGH:
4274                 ret = iceland_force_dpm_highest(hwmgr);
4275                 if (ret)
4276                         return ret;
4277                 break;
4278         case AMD_DPM_FORCED_LEVEL_LOW:
4279                 ret = iceland_force_dpm_lowest(hwmgr);
4280                 if (ret)
4281                         return ret;
4282                 break;
4283         case AMD_DPM_FORCED_LEVEL_AUTO:
4284                 ret = iceland_unforce_dpm_levels(hwmgr);
4285                 if (ret)
4286                         return ret;
4287                 break;
4288         default:
4289                 break;
4290         }
4291
4292         hwmgr->dpm_level = level;
4293         return ret;
4294 }
4295
4296 const struct iceland_power_state *cast_const_phw_iceland_power_state(
4297                                  const struct pp_hw_power_state *hw_ps)
4298 {
4299         if (hw_ps == NULL)
4300                 return NULL;
4301
4302         PP_ASSERT_WITH_CODE((PhwIceland_Magic == hw_ps->magic),
4303                             "Invalid Powerstate Type!",
4304                             return NULL);
4305
4306         return (const struct iceland_power_state *)hw_ps;
4307 }
4308
4309 static int iceland_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
4310 {
4311         const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
4312         const struct iceland_power_state *iceland_ps = cast_const_phw_iceland_power_state(states->pnew_state);
4313         struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend);
4314         struct iceland_single_dpm_table *psclk_table = &(data->dpm_table.sclk_table);
4315         uint32_t sclk = iceland_ps->performance_levels[iceland_ps->performance_level_count-1].engine_clock;
4316         struct iceland_single_dpm_table *pmclk_table = &(data->dpm_table.mclk_table);
4317         uint32_t mclk = iceland_ps->performance_levels[iceland_ps->performance_level_count-1].memory_clock;
4318         struct PP_Clocks min_clocks = {0};
4319         uint32_t i;
4320         struct cgs_display_info info = {0};
4321
4322         data->need_update_smu7_dpm_table = 0;
4323
4324         for (i = 0; i < psclk_table->count; i++) {
4325                 if (sclk == psclk_table->dpm_levels[i].value)
4326                         break;
4327         }
4328
4329         if (i >= psclk_table->count)
4330                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
4331         else {
4332                 /*
4333                  * TODO: Check SCLK in DAL's minimum clocks in case DeepSleep
4334                  * divider update is required.
4335                  */
4336                 if(data->display_timing.min_clock_insr != min_clocks.engineClockInSR)
4337                         data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
4338         }
4339
4340         for (i = 0; i < pmclk_table->count; i++) {
4341                 if (mclk == pmclk_table->dpm_levels[i].value)
4342                         break;
4343         }
4344
4345         if (i >= pmclk_table->count)
4346                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
4347
4348         cgs_get_active_displays_info(hwmgr->device, &info);
4349
4350         if (data->display_timing.num_existing_displays != info.display_count)
4351                 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
4352
4353         return 0;
4354 }
4355
4356 static uint16_t iceland_get_maximum_link_speed(struct pp_hwmgr *hwmgr, const struct iceland_power_state *hw_ps)
4357 {
4358         uint32_t i;
4359         uint32_t pcie_speed, max_speed = 0;
4360
4361         for (i = 0; i < hw_ps->performance_level_count; i++) {
4362                 pcie_speed = hw_ps->performance_levels[i].pcie_gen;
4363                 if (max_speed < pcie_speed)
4364                         max_speed = pcie_speed;
4365         }
4366
4367         return max_speed;
4368 }
4369
4370 static uint16_t iceland_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
4371 {
4372         uint32_t speed_cntl = 0;
4373
4374         speed_cntl = cgs_read_ind_register(hwmgr->device,
4375                                            CGS_IND_REG__PCIE,
4376                                            ixPCIE_LC_SPEED_CNTL);
4377         return((uint16_t)PHM_GET_FIELD(speed_cntl,
4378                         PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
4379 }
4380
4381
4382 static int iceland_request_link_speed_change_before_state_change(struct pp_hwmgr *hwmgr, const void *input)
4383 {
4384         const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
4385         struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend);
4386         const struct iceland_power_state *iceland_nps = cast_const_phw_iceland_power_state(states->pnew_state);
4387         const struct iceland_power_state *iceland_cps = cast_const_phw_iceland_power_state(states->pcurrent_state);
4388
4389         uint16_t target_link_speed = iceland_get_maximum_link_speed(hwmgr, iceland_nps);
4390         uint16_t current_link_speed;
4391
4392         if (data->force_pcie_gen == PP_PCIEGenInvalid)
4393                 current_link_speed = iceland_get_maximum_link_speed(hwmgr, iceland_cps);
4394         else
4395                 current_link_speed = data->force_pcie_gen;
4396
4397         data->force_pcie_gen = PP_PCIEGenInvalid;
4398         data->pspp_notify_required = false;
4399         if (target_link_speed > current_link_speed) {
4400                 switch(target_link_speed) {
4401                 case PP_PCIEGen3:
4402                         if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
4403                                 break;
4404                         data->force_pcie_gen = PP_PCIEGen2;
4405                         if (current_link_speed == PP_PCIEGen2)
4406                                 break;
4407                 case PP_PCIEGen2:
4408                         if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
4409                                 break;
4410                 default:
4411                         data->force_pcie_gen = iceland_get_current_pcie_speed(hwmgr);
4412                         break;
4413                 }
4414         } else {
4415                 if (target_link_speed < current_link_speed)
4416                         data->pspp_notify_required = true;
4417         }
4418
4419         return 0;
4420 }
4421
4422 static int iceland_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4423 {
4424         struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend);
4425
4426         if (0 == data->need_update_smu7_dpm_table)
4427                 return 0;
4428
4429         if ((0 == data->sclk_dpm_key_disabled) &&
4430                 (data->need_update_smu7_dpm_table &
4431                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4432                 PP_ASSERT_WITH_CODE(
4433                         0 == iceland_is_dpm_running(hwmgr),
4434                         "Trying to freeze SCLK DPM when DPM is disabled",
4435                         );
4436                 PP_ASSERT_WITH_CODE(
4437                         0 == smum_send_msg_to_smc(hwmgr->smumgr,
4438                                           PPSMC_MSG_SCLKDPM_FreezeLevel),
4439                         "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
4440                         return -1);
4441         }
4442
4443         if ((0 == data->mclk_dpm_key_disabled) &&
4444                 (data->need_update_smu7_dpm_table &
4445                  DPMTABLE_OD_UPDATE_MCLK)) {
4446                 PP_ASSERT_WITH_CODE(0 == iceland_is_dpm_running(hwmgr),
4447                         "Trying to freeze MCLK DPM when DPM is disabled",
4448                         );
4449                 PP_ASSERT_WITH_CODE(
4450                         0 == smum_send_msg_to_smc(hwmgr->smumgr,
4451                                                         PPSMC_MSG_MCLKDPM_FreezeLevel),
4452                         "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
4453                         return -1);
4454         }
4455
4456         return 0;
4457 }
4458
4459 static int iceland_populate_and_upload_sclk_mclk_dpm_levels(struct pp_hwmgr *hwmgr, const void *input)
4460 {
4461         int result = 0;
4462
4463         const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
4464         const struct iceland_power_state *iceland_ps = cast_const_phw_iceland_power_state(states->pnew_state);
4465         struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend);
4466         uint32_t sclk = iceland_ps->performance_levels[iceland_ps->performance_level_count-1].engine_clock;
4467         uint32_t mclk = iceland_ps->performance_levels[iceland_ps->performance_level_count-1].memory_clock;
4468         struct iceland_dpm_table *pdpm_table = &data->dpm_table;
4469
4470         struct iceland_dpm_table *pgolden_dpm_table = &data->golden_dpm_table;
4471         uint32_t dpm_count, clock_percent;
4472         uint32_t i;
4473
4474         if (0 == data->need_update_smu7_dpm_table)
4475                 return 0;
4476
4477         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
4478                 pdpm_table->sclk_table.dpm_levels[pdpm_table->sclk_table.count-1].value = sclk;
4479
4480                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
4481                     phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
4482                         /*
4483                          * Need to do calculation based on the golden DPM table
4484                          * as the Heatmap GPU Clock axis is also based on the default values
4485                          */
4486                         PP_ASSERT_WITH_CODE(
4487                                 (pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value != 0),
4488                                 "Divide by 0!",
4489                                 return -1);
4490                         dpm_count = pdpm_table->sclk_table.count < 2 ? 0 : pdpm_table->sclk_table.count-2;
4491                         for (i = dpm_count; i > 1; i--) {
4492                                 if (sclk > pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value) {
4493                                         clock_percent = ((sclk - pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value)*100) /
4494                                                         pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value;
4495
4496                                         pdpm_table->sclk_table.dpm_levels[i].value =
4497                                                         pgolden_dpm_table->sclk_table.dpm_levels[i].value +
4498                                                         (pgolden_dpm_table->sclk_table.dpm_levels[i].value * clock_percent)/100;
4499
4500                                 } else if (pgolden_dpm_table->sclk_table.dpm_levels[pdpm_table->sclk_table.count-1].value > sclk) {
4501                                         clock_percent = ((pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value - sclk)*100) /
4502                                                                 pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value;
4503
4504                                         pdpm_table->sclk_table.dpm_levels[i].value =
4505                                                         pgolden_dpm_table->sclk_table.dpm_levels[i].value -
4506                                                         (pgolden_dpm_table->sclk_table.dpm_levels[i].value * clock_percent)/100;
4507                                 } else
4508                                         pdpm_table->sclk_table.dpm_levels[i].value =
4509                                                         pgolden_dpm_table->sclk_table.dpm_levels[i].value;
4510                         }
4511                 }
4512         }
4513
4514         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
4515                 pdpm_table->mclk_table.dpm_levels[pdpm_table->mclk_table.count-1].value = mclk;
4516
4517                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
4518                         phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
4519
4520                         PP_ASSERT_WITH_CODE(
4521                                         (pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value != 0),
4522                                         "Divide by 0!",
4523                                         return -1);
4524                         dpm_count = pdpm_table->mclk_table.count < 2? 0 : pdpm_table->mclk_table.count-2;
4525                         for (i = dpm_count; i > 1; i--) {
4526                                 if (mclk > pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value) {
4527                                                 clock_percent = ((mclk - pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value)*100) /
4528                                                                     pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value;
4529
4530                                                 pdpm_table->mclk_table.dpm_levels[i].value =
4531                                                                                 pgolden_dpm_table->mclk_table.dpm_levels[i].value +
4532                                                                                 (pgolden_dpm_table->mclk_table.dpm_levels[i].value * clock_percent)/100;
4533
4534                                 } else if (pgolden_dpm_table->mclk_table.dpm_levels[pdpm_table->mclk_table.count-1].value > mclk) {
4535                                                 clock_percent = ((pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value - mclk)*100) /
4536                                                                     pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value;
4537
4538                                                 pdpm_table->mclk_table.dpm_levels[i].value =
4539                                                                         pgolden_dpm_table->mclk_table.dpm_levels[i].value -
4540                                                                         (pgolden_dpm_table->mclk_table.dpm_levels[i].value * clock_percent)/100;
4541                                 } else
4542                                         pdpm_table->mclk_table.dpm_levels[i].value = pgolden_dpm_table->mclk_table.dpm_levels[i].value;
4543                         }
4544                 }
4545         }
4546
4547
4548         if (data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
4549                 result = iceland_populate_all_graphic_levels(hwmgr);
4550                 PP_ASSERT_WITH_CODE((0 == result),
4551                         "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
4552                         return result);
4553         }
4554
4555         if (data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
4556                 /*populate MCLK dpm table to SMU7 */
4557                 result = iceland_populate_all_memory_levels(hwmgr);
4558                 PP_ASSERT_WITH_CODE((0 == result),
4559                                 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
4560                                 return result);
4561         }
4562
4563         return result;
4564 }
4565
4566 static int iceland_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
4567                           struct iceland_single_dpm_table *pdpm_table,
4568                              uint32_t low_limit, uint32_t high_limit)
4569 {
4570         uint32_t i;
4571
4572         for (i = 0; i < pdpm_table->count; i++) {
4573                 if ((pdpm_table->dpm_levels[i].value < low_limit) ||
4574                     (pdpm_table->dpm_levels[i].value > high_limit))
4575                         pdpm_table->dpm_levels[i].enabled = false;
4576                 else
4577                         pdpm_table->dpm_levels[i].enabled = true;
4578         }
4579         return 0;
4580 }
4581
4582 static int iceland_trim_dpm_states(struct pp_hwmgr *hwmgr, const struct iceland_power_state *hw_state)
4583 {
4584         int result = 0;
4585         struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend);
4586         uint32_t high_limit_count;
4587
4588         PP_ASSERT_WITH_CODE((hw_state->performance_level_count >= 1),
4589                                 "power state did not have any performance level",
4590                                  return -1);
4591
4592         high_limit_count = (1 == hw_state->performance_level_count) ? 0: 1;
4593
4594         iceland_trim_single_dpm_states(hwmgr, &(data->dpm_table.sclk_table),
4595                                         hw_state->performance_levels[0].engine_clock,
4596                                         hw_state->performance_levels[high_limit_count].engine_clock);
4597
4598         iceland_trim_single_dpm_states(hwmgr, &(data->dpm_table.mclk_table),
4599                                         hw_state->performance_levels[0].memory_clock,
4600                                         hw_state->performance_levels[high_limit_count].memory_clock);
4601
4602         return result;
4603 }
4604
4605 static int iceland_generate_dpm_level_enable_mask(struct pp_hwmgr *hwmgr, const void *input)
4606 {
4607         int result;
4608         const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
4609         struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend);
4610         const struct iceland_power_state *iceland_ps = cast_const_phw_iceland_power_state(states->pnew_state);
4611
4612         result = iceland_trim_dpm_states(hwmgr, iceland_ps);
4613         if (0 != result)
4614                 return result;
4615
4616         data->dpm_level_enable_mask.sclk_dpm_enable_mask = iceland_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
4617         data->dpm_level_enable_mask.mclk_dpm_enable_mask = iceland_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
4618         data->last_mclk_dpm_enable_mask = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
4619         if (data->uvd_enabled && (data->dpm_level_enable_mask.mclk_dpm_enable_mask & 1))
4620                 data->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
4621
4622         data->dpm_level_enable_mask.pcie_dpm_enable_mask = iceland_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
4623
4624         return 0;
4625 }
4626
4627 static int iceland_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
4628 {
4629         return 0;
4630 }
4631
4632 int iceland_update_sclk_threshold(struct pp_hwmgr *hwmgr)
4633 {
4634         iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
4635
4636         int result = 0;
4637         uint32_t low_sclk_interrupt_threshold = 0;
4638
4639         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4640                         PHM_PlatformCaps_SclkThrottleLowNotification)
4641                 && (hwmgr->gfx_arbiter.sclk_threshold != data->low_sclk_interrupt_threshold)) {
4642                 data->low_sclk_interrupt_threshold = hwmgr->gfx_arbiter.sclk_threshold;
4643                 low_sclk_interrupt_threshold = data->low_sclk_interrupt_threshold;
4644
4645                 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
4646
4647                 result = iceland_copy_bytes_to_smc(
4648                                 hwmgr->smumgr,
4649                                 data->dpm_table_start + offsetof(SMU71_Discrete_DpmTable,
4650                                 LowSclkInterruptThreshold),
4651                                 (uint8_t *)&low_sclk_interrupt_threshold,
4652                                 sizeof(uint32_t),
4653                                 data->sram_end
4654                                 );
4655         }
4656
4657         return result;
4658 }
4659
4660 static int iceland_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
4661 {
4662         struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend);
4663
4664         uint32_t address;
4665         int32_t result;
4666
4667         if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
4668                 return 0;
4669
4670
4671         memset(&data->mc_reg_table, 0, sizeof(SMU71_Discrete_MCRegisters));
4672
4673         result = iceland_convert_mc_reg_table_to_smc(hwmgr, &(data->mc_reg_table));
4674
4675         if(result != 0)
4676                 return result;
4677
4678
4679         address = data->mc_reg_table_start + (uint32_t)offsetof(SMU71_Discrete_MCRegisters, data[0]);
4680
4681         return  iceland_copy_bytes_to_smc(hwmgr->smumgr, address,
4682                                  (uint8_t *)&data->mc_reg_table.data[0],
4683                                 sizeof(SMU71_Discrete_MCRegisterSet) * data->dpm_table.mclk_table.count,
4684                                 data->sram_end);
4685 }
4686
4687 static int iceland_program_memory_timing_parameters_conditionally(struct pp_hwmgr *hwmgr)
4688 {
4689         struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend);
4690
4691         if (data->need_update_smu7_dpm_table &
4692                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
4693                 return iceland_program_memory_timing_parameters(hwmgr);
4694
4695         return 0;
4696 }
4697
4698 static int iceland_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4699 {
4700         struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend);
4701
4702         if (0 == data->need_update_smu7_dpm_table)
4703                 return 0;
4704
4705         if ((0 == data->sclk_dpm_key_disabled) &&
4706                 (data->need_update_smu7_dpm_table &
4707                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4708
4709                 PP_ASSERT_WITH_CODE(0 == iceland_is_dpm_running(hwmgr),
4710                         "Trying to Unfreeze SCLK DPM when DPM is disabled",
4711                         );
4712                 PP_ASSERT_WITH_CODE(
4713                          0 == smum_send_msg_to_smc(hwmgr->smumgr,
4714                                          PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4715                         "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
4716                         return -1);
4717         }
4718
4719         if ((0 == data->mclk_dpm_key_disabled) &&
4720                 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
4721
4722                 PP_ASSERT_WITH_CODE(
4723                                 0 == iceland_is_dpm_running(hwmgr),
4724                                 "Trying to Unfreeze MCLK DPM when DPM is disabled",
4725                                 );
4726                 PP_ASSERT_WITH_CODE(
4727                          0 == smum_send_msg_to_smc(hwmgr->smumgr,
4728                                          PPSMC_MSG_MCLKDPM_UnfreezeLevel),
4729                     "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
4730                     return -1);
4731         }
4732
4733         data->need_update_smu7_dpm_table = 0;
4734
4735         return 0;
4736 }
4737
4738 static int iceland_notify_link_speed_change_after_state_change(struct pp_hwmgr *hwmgr, const void *input)
4739 {
4740         const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
4741         struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend);
4742         const struct iceland_power_state *iceland_ps = cast_const_phw_iceland_power_state(states->pnew_state);
4743         uint16_t target_link_speed = iceland_get_maximum_link_speed(hwmgr, iceland_ps);
4744         uint8_t  request;
4745
4746         if (data->pspp_notify_required  ||
4747             data->pcie_performance_request) {
4748                 if (target_link_speed == PP_PCIEGen3)
4749                         request = PCIE_PERF_REQ_GEN3;
4750                 else if (target_link_speed == PP_PCIEGen2)
4751                         request = PCIE_PERF_REQ_GEN2;
4752                 else
4753                         request = PCIE_PERF_REQ_GEN1;
4754
4755                 if(request == PCIE_PERF_REQ_GEN1 && iceland_get_current_pcie_speed(hwmgr) > 0) {
4756                         data->pcie_performance_request = false;
4757                         return 0;
4758                 }
4759
4760                 if (0 != acpi_pcie_perf_request(hwmgr->device, request, false)) {
4761                         if (PP_PCIEGen2 == target_link_speed)
4762                                 printk("PSPP request to switch to Gen2 from Gen3 Failed!");
4763                         else
4764                                 printk("PSPP request to switch to Gen1 from Gen2 Failed!");
4765                 }
4766         }
4767
4768         data->pcie_performance_request = false;
4769         return 0;
4770 }
4771
4772 int iceland_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
4773 {
4774         PPSMC_Result result;
4775         iceland_hwmgr *data = (iceland_hwmgr *)(hwmgr->backend);
4776
4777         if (0 == data->sclk_dpm_key_disabled) {
4778                 /* Checking if DPM is running.  If we discover hang because of this, we should skip this message.*/
4779                 if (0 != iceland_is_dpm_running(hwmgr))
4780                         printk(KERN_ERR "[ powerplay ] Trying to set Enable Sclk Mask when DPM is disabled \n");
4781
4782                 if (0 != data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4783                         result = smum_send_msg_to_smc_with_parameter(
4784                                                                 hwmgr->smumgr,
4785                                 (PPSMC_Msg)PPSMC_MSG_SCLKDPM_SetEnabledMask,
4786                                 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
4787                         PP_ASSERT_WITH_CODE((0 == result),
4788                                 "Set Sclk Dpm enable Mask failed", return -1);
4789                 }
4790         }
4791
4792         if (0 == data->mclk_dpm_key_disabled) {
4793                 /* Checking if DPM is running.  If we discover hang because of this, we should skip this message.*/
4794                 if (0 != iceland_is_dpm_running(hwmgr))
4795                         printk(KERN_ERR "[ powerplay ] Trying to set Enable Mclk Mask when DPM is disabled \n");
4796
4797                 if (0 != data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4798                         result = smum_send_msg_to_smc_with_parameter(
4799                                                                 hwmgr->smumgr,
4800                                 (PPSMC_Msg)PPSMC_MSG_MCLKDPM_SetEnabledMask,
4801                                 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
4802                         PP_ASSERT_WITH_CODE((0 == result),
4803                                 "Set Mclk Dpm enable Mask failed", return -1);
4804                 }
4805         }
4806
4807         return 0;
4808 }
4809
4810 static int iceland_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
4811 {
4812         int tmp_result, result = 0;
4813
4814         tmp_result = iceland_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
4815         PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to find DPM states clocks in DPM table!", result = tmp_result);
4816
4817         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest)) {
4818                 tmp_result = iceland_request_link_speed_change_before_state_change(hwmgr, input);
4819                 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to request link speed change before state change!", result = tmp_result);
4820         }
4821
4822         tmp_result = iceland_freeze_sclk_mclk_dpm(hwmgr);
4823         PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
4824
4825         tmp_result = iceland_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
4826         PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to populate and upload SCLK MCLK DPM levels!", result = tmp_result);
4827
4828         tmp_result = iceland_generate_dpm_level_enable_mask(hwmgr, input);
4829         PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to generate DPM level enabled mask!", result = tmp_result);
4830
4831         tmp_result = iceland_update_vce_dpm(hwmgr, input);
4832         PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to update VCE DPM!", result = tmp_result);
4833
4834         tmp_result = iceland_update_sclk_threshold(hwmgr);
4835         PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to update SCLK threshold!", result = tmp_result);
4836
4837         tmp_result = iceland_update_and_upload_mc_reg_table(hwmgr);
4838         PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to upload MC reg table!", result = tmp_result);
4839
4840         tmp_result = iceland_program_memory_timing_parameters_conditionally(hwmgr);
4841         PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to program memory timing parameters!", result = tmp_result);
4842
4843         tmp_result = iceland_unfreeze_sclk_mclk_dpm(hwmgr);
4844         PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to unfreeze SCLK MCLK DPM!", result = tmp_result);
4845
4846         tmp_result = iceland_upload_dpm_level_enable_mask(hwmgr);
4847         PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to upload DPM level enabled mask!", result = tmp_result);
4848
4849         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest)) {
4850                 tmp_result = iceland_notify_link_speed_change_after_state_change(hwmgr, input);
4851                 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to notify link speed change after state change!", result = tmp_result);
4852         }
4853
4854         return result;
4855 }
4856
4857 static int iceland_get_power_state_size(struct pp_hwmgr *hwmgr)
4858 {
4859         return sizeof(struct iceland_power_state);
4860 }
4861
4862 static int iceland_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
4863 {
4864         struct pp_power_state  *ps;
4865         struct iceland_power_state  *iceland_ps;
4866
4867         if (hwmgr == NULL)
4868                 return -EINVAL;
4869
4870         ps = hwmgr->request_ps;
4871
4872         if (ps == NULL)
4873                 return -EINVAL;
4874
4875         iceland_ps = cast_phw_iceland_power_state(&ps->hardware);
4876
4877         if (low)
4878                 return iceland_ps->performance_levels[0].memory_clock;
4879         else
4880                 return iceland_ps->performance_levels[iceland_ps->performance_level_count-1].memory_clock;
4881 }
4882
4883 static int iceland_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
4884 {
4885         struct pp_power_state  *ps;
4886         struct iceland_power_state  *iceland_ps;
4887
4888         if (hwmgr == NULL)
4889                 return -EINVAL;
4890
4891         ps = hwmgr->request_ps;
4892
4893         if (ps == NULL)
4894                 return -EINVAL;
4895
4896         iceland_ps = cast_phw_iceland_power_state(&ps->hardware);
4897
4898         if (low)
4899                 return iceland_ps->performance_levels[0].engine_clock;
4900         else
4901                 return iceland_ps->performance_levels[iceland_ps->performance_level_count-1].engine_clock;
4902 }
4903
4904 static int iceland_get_current_pcie_lane_number(
4905                                                    struct pp_hwmgr *hwmgr)
4906 {
4907         uint32_t link_width;
4908
4909         link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device,
4910                                                         CGS_IND_REG__PCIE,
4911                                                   PCIE_LC_LINK_WIDTH_CNTL,
4912                                                         LC_LINK_WIDTH_RD);
4913
4914         PP_ASSERT_WITH_CODE((7 >= link_width),
4915                         "Invalid PCIe lane width!", return 0);
4916
4917         return decode_pcie_lane_width(link_width);
4918 }
4919
4920 static int iceland_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
4921                                         struct pp_hw_power_state *hw_ps)
4922 {
4923         struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend);
4924         struct iceland_power_state *ps = (struct iceland_power_state *)hw_ps;
4925         ATOM_FIRMWARE_INFO_V2_2 *fw_info;
4926         uint16_t size;
4927         uint8_t frev, crev;
4928         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
4929
4930         /* First retrieve the Boot clocks and VDDC from the firmware info table.
4931          * We assume here that fw_info is unchanged if this call fails.
4932          */
4933         fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
4934                         hwmgr->device, index,
4935                         &size, &frev, &crev);
4936         if (!fw_info)
4937                 /* During a test, there is no firmware info table. */
4938                 return 0;
4939
4940         /* Patch the state. */
4941         data->vbios_boot_state.sclk_bootup_value  = le32_to_cpu(fw_info->ulDefaultEngineClock);
4942         data->vbios_boot_state.mclk_bootup_value  = le32_to_cpu(fw_info->ulDefaultMemoryClock);
4943         data->vbios_boot_state.mvdd_bootup_value  = le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
4944         data->vbios_boot_state.vddc_bootup_value  = le16_to_cpu(fw_info->usBootUpVDDCVoltage);
4945         data->vbios_boot_state.vddci_bootup_value = le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
4946         data->vbios_boot_state.pcie_gen_bootup_value = iceland_get_current_pcie_speed(hwmgr);
4947         data->vbios_boot_state.pcie_lane_bootup_value =
4948                         (uint16_t)iceland_get_current_pcie_lane_number(hwmgr);
4949
4950         /* set boot power state */
4951         ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
4952         ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
4953         ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
4954         ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
4955
4956         return 0;
4957 }
4958
4959 static int iceland_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
4960                                         struct pp_hw_power_state *power_state,
4961                                         unsigned int index, const void *clock_info)
4962 {
4963         struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend);
4964         struct iceland_power_state  *iceland_power_state = cast_phw_iceland_power_state(power_state);
4965         const ATOM_PPLIB_CI_CLOCK_INFO *visland_clk_info = clock_info;
4966         struct iceland_performance_level *performance_level;
4967         uint32_t engine_clock, memory_clock;
4968         uint16_t pcie_gen_from_bios;
4969
4970         engine_clock = visland_clk_info->ucEngineClockHigh << 16 | visland_clk_info->usEngineClockLow;
4971         memory_clock = visland_clk_info->ucMemoryClockHigh << 16 | visland_clk_info->usMemoryClockLow;
4972
4973         if (!(data->mc_micro_code_feature & DISABLE_MC_LOADMICROCODE) && memory_clock > data->highest_mclk)
4974                 data->highest_mclk = memory_clock;
4975
4976         performance_level = &(iceland_power_state->performance_levels
4977                         [iceland_power_state->performance_level_count++]);
4978
4979         PP_ASSERT_WITH_CODE(
4980                         (iceland_power_state->performance_level_count < SMU71_MAX_LEVELS_GRAPHICS),
4981                         "Performance levels exceeds SMC limit!",
4982                         return -1);
4983
4984         PP_ASSERT_WITH_CODE(
4985                         (iceland_power_state->performance_level_count <=
4986                                         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
4987                         "Performance levels exceeds Driver limit!",
4988                         return -1);
4989
4990         /* Performance levels are arranged from low to high. */
4991         performance_level->memory_clock = memory_clock;
4992         performance_level->engine_clock = engine_clock;
4993
4994         pcie_gen_from_bios = visland_clk_info->ucPCIEGen;
4995
4996         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap, pcie_gen_from_bios);
4997         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap, visland_clk_info->usPCIELane);
4998
4999         return 0;
5000 }
5001
5002 static int iceland_get_pp_table_entry(struct pp_hwmgr *hwmgr,
5003                 unsigned long entry_index, struct pp_power_state *state)
5004 {
5005         int result;
5006         struct iceland_power_state *ps;
5007         struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend);
5008         struct phm_clock_voltage_dependency_table *dep_mclk_table =
5009                         hwmgr->dyn_state.vddci_dependency_on_mclk;
5010
5011         memset(&state->hardware, 0x00, sizeof(struct pp_hw_power_state));
5012
5013         state->hardware.magic = PHM_VIslands_Magic;
5014
5015         ps = (struct iceland_power_state *)(&state->hardware);
5016
5017         result = pp_tables_get_entry(hwmgr, entry_index, state,
5018                         iceland_get_pp_table_entry_callback_func);
5019
5020         /*
5021          * This is the earliest time we have all the dependency table
5022          * and the VBIOS boot state as
5023          * PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot
5024          * state if there is only one VDDCI/MCLK level, check if it's
5025          * the same as VBIOS boot state
5026          */
5027         if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
5028                 if (dep_mclk_table->entries[0].clk !=
5029                                 data->vbios_boot_state.mclk_bootup_value)
5030                         printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
5031                                         "does not match VBIOS boot MCLK level");
5032                 if (dep_mclk_table->entries[0].v !=
5033                                 data->vbios_boot_state.vddci_bootup_value)
5034                         printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
5035                                         "does not match VBIOS boot VDDCI level");
5036         }
5037
5038         /* set DC compatible flag if this state supports DC */
5039         if (!state->validation.disallowOnDC)
5040                 ps->dc_compatible = true;
5041
5042         if (state->classification.flags & PP_StateClassificationFlag_ACPI)
5043                 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
5044         else if (0 != (state->classification.flags & PP_StateClassificationFlag_Boot)) {
5045                 if (data->bacos.best_match == 0xffff) {
5046                         /* For C.I. use boot state as base BACO state */
5047                         data->bacos.best_match = PP_StateClassificationFlag_Boot;
5048                         data->bacos.performance_level = ps->performance_levels[0];
5049                 }
5050         }
5051
5052
5053         ps->uvd_clocks.VCLK = state->uvd_clocks.VCLK;
5054         ps->uvd_clocks.DCLK = state->uvd_clocks.DCLK;
5055
5056         if (!result) {
5057                 uint32_t i;
5058
5059                 switch (state->classification.ui_label) {
5060                 case PP_StateUILabel_Performance:
5061                         data->use_pcie_performance_levels = true;
5062
5063                         for (i = 0; i < ps->performance_level_count; i++) {
5064                                 if (data->pcie_gen_performance.max <
5065                                                 ps->performance_levels[i].pcie_gen)
5066                                         data->pcie_gen_performance.max =
5067                                                         ps->performance_levels[i].pcie_gen;
5068
5069                                 if (data->pcie_gen_performance.min >
5070                                                 ps->performance_levels[i].pcie_gen)
5071                                         data->pcie_gen_performance.min =
5072                                                         ps->performance_levels[i].pcie_gen;
5073
5074                                 if (data->pcie_lane_performance.max <
5075                                                 ps->performance_levels[i].pcie_lane)
5076                                         data->pcie_lane_performance.max =
5077                                                         ps->performance_levels[i].pcie_lane;
5078
5079                                 if (data->pcie_lane_performance.min >
5080                                                 ps->performance_levels[i].pcie_lane)
5081                                         data->pcie_lane_performance.min =
5082                                                         ps->performance_levels[i].pcie_lane;
5083                         }
5084                         break;
5085                 case PP_StateUILabel_Battery:
5086                         data->use_pcie_power_saving_levels = true;
5087
5088                         for (i = 0; i < ps->performance_level_count; i++) {
5089                                 if (data->pcie_gen_power_saving.max <
5090                                                 ps->performance_levels[i].pcie_gen)
5091                                         data->pcie_gen_power_saving.max =
5092                                                         ps->performance_levels[i].pcie_gen;
5093
5094                                 if (data->pcie_gen_power_saving.min >
5095                                                 ps->performance_levels[i].pcie_gen)
5096                                         data->pcie_gen_power_saving.min =
5097                                                         ps->performance_levels[i].pcie_gen;
5098
5099                                 if (data->pcie_lane_power_saving.max <
5100                                                 ps->performance_levels[i].pcie_lane)
5101                                         data->pcie_lane_power_saving.max =
5102                                                         ps->performance_levels[i].pcie_lane;
5103
5104                                 if (data->pcie_lane_power_saving.min >
5105                                                 ps->performance_levels[i].pcie_lane)
5106                                         data->pcie_lane_power_saving.min =
5107                                                         ps->performance_levels[i].pcie_lane;
5108                         }
5109                         break;
5110                 default:
5111                         break;
5112                 }
5113         }
5114         return 0;
5115 }
5116
5117 static void
5118 iceland_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
5119 {
5120         uint32_t sclk, mclk, activity_percent;
5121         uint32_t offset;
5122         struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend);
5123
5124         smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)(PPSMC_MSG_API_GetSclkFrequency));
5125
5126         sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5127
5128         smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)(PPSMC_MSG_API_GetMclkFrequency));
5129
5130         mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5131         seq_printf(m, "\n [  mclk  ]: %u MHz\n\n [  sclk  ]: %u MHz\n", mclk/100, sclk/100);
5132
5133         offset = data->soft_regs_start + offsetof(SMU71_SoftRegisters, AverageGraphicsActivity);
5134         activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
5135         activity_percent += 0x80;
5136         activity_percent >>= 8;
5137
5138         seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);
5139
5140         seq_printf(m, "uvd    %sabled\n", data->uvd_power_gated ? "dis" : "en");
5141
5142         seq_printf(m, "vce    %sabled\n", data->vce_power_gated ? "dis" : "en");
5143 }
5144
5145 int iceland_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
5146 {
5147         uint32_t num_active_displays = 0;
5148         struct cgs_display_info info = {0};
5149         info.mode_info = NULL;
5150
5151         cgs_get_active_displays_info(hwmgr->device, &info);
5152
5153         num_active_displays = info.display_count;
5154
5155         if (num_active_displays > 1)  /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */
5156                 iceland_notify_smc_display_change(hwmgr, false);
5157         else
5158                 iceland_notify_smc_display_change(hwmgr, true);
5159
5160         return 0;
5161 }
5162
5163 /**
5164 * Programs the display gap
5165 *
5166 * @param    hwmgr  the address of the powerplay hardware manager.
5167 * @return   always OK
5168 */
5169 int iceland_program_display_gap(struct pp_hwmgr *hwmgr)
5170 {
5171         uint32_t num_active_displays = 0;
5172         uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
5173         uint32_t display_gap2;
5174         uint32_t pre_vbi_time_in_us;
5175         uint32_t frame_time_in_us;
5176         uint32_t ref_clock;
5177         uint32_t refresh_rate = 0;
5178         struct cgs_display_info info = {0};
5179         struct cgs_mode_info mode_info;
5180
5181         info.mode_info = &mode_info;
5182
5183         cgs_get_active_displays_info(hwmgr->device, &info);
5184         num_active_displays = info.display_count;
5185
5186         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0)? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
5187         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
5188
5189         ref_clock = mode_info.ref_clock;
5190         refresh_rate = mode_info.refresh_rate;
5191
5192         if(0 == refresh_rate)
5193                 refresh_rate = 60;
5194
5195         frame_time_in_us = 1000000 / refresh_rate;
5196
5197         pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
5198         display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
5199
5200         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
5201
5202         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SOFT_REGISTERS_TABLE_4, PreVBlankGap, 0x64);
5203
5204         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SOFT_REGISTERS_TABLE_5, VBlankTimeout, (frame_time_in_us - pre_vbi_time_in_us));
5205
5206         if (num_active_displays == 1)
5207                 iceland_notify_smc_display_change(hwmgr, true);
5208
5209         return 0;
5210 }
5211
5212 int iceland_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
5213 {
5214         iceland_program_display_gap(hwmgr);
5215
5216         return 0;
5217 }
5218
5219 /**
5220 *  Set maximum target operating fan output PWM
5221 *
5222 * @param    pHwMgr:  the address of the powerplay hardware manager.
5223 * @param    usMaxFanPwm:  max operating fan PWM in percents
5224 * @return   The response that came from the SMC.
5225 */
5226 static int iceland_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
5227 {
5228         hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
5229
5230         if (phm_is_hw_access_blocked(hwmgr))
5231                 return 0;
5232
5233         return (0 == smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm) ? 0 : -1);
5234 }
5235
5236 /**
5237 *  Set maximum target operating fan output RPM
5238 *
5239 * @param    pHwMgr:  the address of the powerplay hardware manager.
5240 * @param    usMaxFanRpm:  max operating fan RPM value.
5241 * @return   The response that came from the SMC.
5242 */
5243 static int iceland_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
5244 {
5245         hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM = us_max_fan_pwm;
5246
5247         if (phm_is_hw_access_blocked(hwmgr))
5248                 return 0;
5249
5250         return (0 == smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFanRpmMax, us_max_fan_pwm) ? 0 : -1);
5251 }
5252
5253 static int iceland_dpm_set_interrupt_state(void *private_data,
5254                                          unsigned src_id, unsigned type,
5255                                          int enabled)
5256 {
5257         uint32_t cg_thermal_int;
5258         struct pp_hwmgr *hwmgr = ((struct pp_eventmgr *)private_data)->hwmgr;
5259
5260         if (hwmgr == NULL)
5261                 return -EINVAL;
5262
5263         switch (type) {
5264         case AMD_THERMAL_IRQ_LOW_TO_HIGH:
5265                 if (enabled) {
5266                         cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5267                         cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
5268                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5269                 } else {
5270                         cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5271                         cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
5272                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5273                 }
5274                 break;
5275
5276         case AMD_THERMAL_IRQ_HIGH_TO_LOW:
5277                 if (enabled) {
5278                         cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5279                         cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
5280                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5281                 } else {
5282                         cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5283                         cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
5284                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5285                 }
5286                 break;
5287         default:
5288                 break;
5289         }
5290         return 0;
5291 }
5292
5293 static int iceland_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
5294                                         const void *thermal_interrupt_info)
5295 {
5296         int result;
5297         const struct pp_interrupt_registration_info *info =
5298                         (const struct pp_interrupt_registration_info *)thermal_interrupt_info;
5299
5300         if (info == NULL)
5301                 return -EINVAL;
5302
5303         result = cgs_add_irq_source(hwmgr->device, 230, AMD_THERMAL_IRQ_LAST,
5304                                 iceland_dpm_set_interrupt_state,
5305                                 info->call_back, info->context);
5306
5307         if (result)
5308                 return -EINVAL;
5309
5310         result = cgs_add_irq_source(hwmgr->device, 231, AMD_THERMAL_IRQ_LAST,
5311                                 iceland_dpm_set_interrupt_state,
5312                                 info->call_back, info->context);
5313
5314         if (result)
5315                 return -EINVAL;
5316
5317         return 0;
5318 }
5319
5320
5321 static bool iceland_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
5322 {
5323         struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend);
5324         bool is_update_required = false;
5325         struct cgs_display_info info = {0,0,NULL};
5326
5327         cgs_get_active_displays_info(hwmgr->device, &info);
5328
5329         if (data->display_timing.num_existing_displays != info.display_count)
5330                 is_update_required = true;
5331 /* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
5332         if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
5333                 cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
5334                 if(min_clocks.engineClockInSR != data->display_timing.minClockInSR)
5335                         is_update_required = true;
5336 */
5337         return is_update_required;
5338 }
5339
5340
5341 static inline bool iceland_are_power_levels_equal(const struct iceland_performance_level *pl1,
5342                                                            const struct iceland_performance_level *pl2)
5343 {
5344         return ((pl1->memory_clock == pl2->memory_clock) &&
5345                   (pl1->engine_clock == pl2->engine_clock) &&
5346                   (pl1->pcie_gen == pl2->pcie_gen) &&
5347                   (pl1->pcie_lane == pl2->pcie_lane));
5348 }
5349
5350 int iceland_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1,
5351                 const struct pp_hw_power_state *pstate2, bool *equal)
5352 {
5353         const struct iceland_power_state *psa = cast_const_phw_iceland_power_state(pstate1);
5354         const struct iceland_power_state *psb = cast_const_phw_iceland_power_state(pstate2);
5355         int i;
5356
5357         if (equal == NULL || psa == NULL || psb == NULL)
5358                 return -EINVAL;
5359
5360         /* If the two states don't even have the same number of performance levels they cannot be the same state. */
5361         if (psa->performance_level_count != psb->performance_level_count) {
5362                 *equal = false;
5363                 return 0;
5364         }
5365
5366         for (i = 0; i < psa->performance_level_count; i++) {
5367                 if (!iceland_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
5368                         /* If we have found even one performance level pair that is different the states are different. */
5369                         *equal = false;
5370                         return 0;
5371                 }
5372         }
5373
5374         /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
5375         *equal = ((psa->uvd_clocks.VCLK == psb->uvd_clocks.VCLK) && (psa->uvd_clocks.DCLK == psb->uvd_clocks.DCLK));
5376         *equal &= ((psa->vce_clocks.EVCLK == psb->vce_clocks.EVCLK) && (psa->vce_clocks.ECCLK == psb->vce_clocks.ECCLK));
5377         *equal &= (psa->sclk_threshold == psb->sclk_threshold);
5378         *equal &= (psa->acp_clk == psb->acp_clk);
5379
5380         return 0;
5381 }
5382
5383 static int iceland_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
5384 {
5385         if (mode) {
5386                 /* stop auto-manage */
5387                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
5388                                 PHM_PlatformCaps_MicrocodeFanControl))
5389                         iceland_fan_ctrl_stop_smc_fan_control(hwmgr);
5390                 iceland_fan_ctrl_set_static_mode(hwmgr, mode);
5391         } else
5392                 /* restart auto-manage */
5393                 iceland_fan_ctrl_reset_fan_speed_to_default(hwmgr);
5394
5395         return 0;
5396 }
5397
5398 static int iceland_get_fan_control_mode(struct pp_hwmgr *hwmgr)
5399 {
5400         if (hwmgr->fan_ctrl_is_in_default_mode)
5401                 return hwmgr->fan_ctrl_default_mode;
5402         else
5403                 return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
5404                                 CG_FDO_CTRL2, FDO_PWM_MODE);
5405 }
5406
5407 static int iceland_force_clock_level(struct pp_hwmgr *hwmgr,
5408                 enum pp_clock_type type, uint32_t mask)
5409 {
5410         struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend);
5411
5412         if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
5413                 return -EINVAL;
5414
5415         switch (type) {
5416         case PP_SCLK:
5417                 if (!data->sclk_dpm_key_disabled)
5418                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5419                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
5420                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
5421                 break;
5422         case PP_MCLK:
5423                 if (!data->mclk_dpm_key_disabled)
5424                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5425                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
5426                                         data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
5427                 break;
5428         case PP_PCIE:
5429         {
5430                 uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
5431                 uint32_t level = 0;
5432
5433                 while (tmp >>= 1)
5434                         level++;
5435
5436                 if (!data->pcie_dpm_key_disabled)
5437                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5438                                         PPSMC_MSG_PCIeDPM_ForceLevel,
5439                                         level);
5440                 break;
5441         }
5442         default:
5443                 break;
5444         }
5445
5446         return 0;
5447 }
5448
5449 static int iceland_print_clock_levels(struct pp_hwmgr *hwmgr,
5450                 enum pp_clock_type type, char *buf)
5451 {
5452         struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend);
5453         struct iceland_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
5454         struct iceland_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
5455         struct iceland_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
5456         int i, now, size = 0;
5457         uint32_t clock, pcie_speed;
5458
5459         switch (type) {
5460         case PP_SCLK:
5461                 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
5462                 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5463
5464                 for (i = 0; i < sclk_table->count; i++) {
5465                         if (clock > sclk_table->dpm_levels[i].value)
5466                                 continue;
5467                         break;
5468                 }
5469                 now = i;
5470
5471                 for (i = 0; i < sclk_table->count; i++)
5472                         size += sprintf(buf + size, "%d: %uMhz %s\n",
5473                                         i, sclk_table->dpm_levels[i].value / 100,
5474                                         (i == now) ? "*" : "");
5475                 break;
5476         case PP_MCLK:
5477                 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
5478                 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5479
5480                 for (i = 0; i < mclk_table->count; i++) {
5481                         if (clock > mclk_table->dpm_levels[i].value)
5482                                 continue;
5483                         break;
5484                 }
5485                 now = i;
5486
5487                 for (i = 0; i < mclk_table->count; i++)
5488                         size += sprintf(buf + size, "%d: %uMhz %s\n",
5489                                         i, mclk_table->dpm_levels[i].value / 100,
5490                                         (i == now) ? "*" : "");
5491                 break;
5492         case PP_PCIE:
5493                 pcie_speed = iceland_get_current_pcie_speed(hwmgr);
5494                 for (i = 0; i < pcie_table->count; i++) {
5495                         if (pcie_speed != pcie_table->dpm_levels[i].value)
5496                                 continue;
5497                         break;
5498                 }
5499                 now = i;
5500
5501                 for (i = 0; i < pcie_table->count; i++)
5502                         size += sprintf(buf + size, "%d: %s %s\n", i,
5503                                         (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x8" :
5504                                         (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
5505                                         (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
5506                                         (i == now) ? "*" : "");
5507                 break;
5508         default:
5509                 break;
5510         }
5511         return size;
5512 }
5513
5514 static int iceland_get_sclk_od(struct pp_hwmgr *hwmgr)
5515 {
5516         struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend);
5517         struct iceland_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
5518         struct iceland_single_dpm_table *golden_sclk_table =
5519                         &(data->golden_dpm_table.sclk_table);
5520         int value;
5521
5522         value = (sclk_table->dpm_levels[sclk_table->count - 1].value -
5523                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value) *
5524                         100 /
5525                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
5526
5527         return value;
5528 }
5529
5530 static int iceland_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
5531 {
5532         struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend);
5533         struct iceland_single_dpm_table *golden_sclk_table =
5534                         &(data->golden_dpm_table.sclk_table);
5535         struct pp_power_state  *ps;
5536         struct iceland_power_state  *iceland_ps;
5537
5538         if (value > 20)
5539                 value = 20;
5540
5541         ps = hwmgr->request_ps;
5542
5543         if (ps == NULL)
5544                 return -EINVAL;
5545
5546         iceland_ps = cast_phw_iceland_power_state(&ps->hardware);
5547
5548         iceland_ps->performance_levels[iceland_ps->performance_level_count - 1].engine_clock =
5549                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value *
5550                         value / 100 +
5551                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
5552
5553         return 0;
5554 }
5555
5556 static int iceland_get_mclk_od(struct pp_hwmgr *hwmgr)
5557 {
5558         struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend);
5559         struct iceland_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
5560         struct iceland_single_dpm_table *golden_mclk_table =
5561                         &(data->golden_dpm_table.mclk_table);
5562         int value;
5563
5564         value = (mclk_table->dpm_levels[mclk_table->count - 1].value -
5565                         golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value) *
5566                         100 /
5567                         golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
5568
5569         return value;
5570 }
5571
5572 uint32_t iceland_get_xclk(struct pp_hwmgr *hwmgr)
5573 {
5574         uint32_t reference_clock;
5575         uint32_t tc;
5576         uint32_t divide;
5577
5578         ATOM_FIRMWARE_INFO *fw_info;
5579         uint16_t size;
5580         uint8_t frev, crev;
5581         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
5582
5583         tc = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK);
5584
5585         if (tc)
5586                 return TCLK;
5587
5588         fw_info = (ATOM_FIRMWARE_INFO *)cgs_atom_get_data_table(hwmgr->device, index,
5589                                                   &size, &frev, &crev);
5590
5591         if (!fw_info)
5592                 return 0;
5593
5594         reference_clock = le16_to_cpu(fw_info->usReferenceClock);
5595
5596         divide = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE);
5597
5598         if (0 != divide)
5599                 return reference_clock / 4;
5600
5601         return reference_clock;
5602 }
5603
5604 static int iceland_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
5605 {
5606         struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend);
5607         struct iceland_single_dpm_table *golden_mclk_table =
5608                         &(data->golden_dpm_table.mclk_table);
5609         struct pp_power_state  *ps;
5610         struct iceland_power_state  *iceland_ps;
5611
5612         if (value > 20)
5613                 value = 20;
5614
5615         ps = hwmgr->request_ps;
5616
5617         if (ps == NULL)
5618                 return -EINVAL;
5619
5620         iceland_ps = cast_phw_iceland_power_state(&ps->hardware);
5621
5622         iceland_ps->performance_levels[iceland_ps->performance_level_count - 1].memory_clock =
5623                         golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value *
5624                         value / 100 +
5625                         golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
5626
5627         return 0;
5628 }
5629
5630 static const struct pp_hwmgr_func iceland_hwmgr_funcs = {
5631         .backend_init = &iceland_hwmgr_backend_init,
5632         .backend_fini = &iceland_hwmgr_backend_fini,
5633         .asic_setup = &iceland_setup_asic_task,
5634         .dynamic_state_management_enable = &iceland_enable_dpm_tasks,
5635         .apply_state_adjust_rules = iceland_apply_state_adjust_rules,
5636         .force_dpm_level = &iceland_force_dpm_level,
5637         .power_state_set = iceland_set_power_state_tasks,
5638         .get_power_state_size = iceland_get_power_state_size,
5639         .get_mclk = iceland_dpm_get_mclk,
5640         .get_sclk = iceland_dpm_get_sclk,
5641         .patch_boot_state = iceland_dpm_patch_boot_state,
5642         .get_pp_table_entry = iceland_get_pp_table_entry,
5643         .get_num_of_pp_table_entries = iceland_get_num_of_entries,
5644         .print_current_perforce_level = iceland_print_current_perforce_level,
5645         .powerdown_uvd = iceland_phm_powerdown_uvd,
5646         .powergate_uvd = iceland_phm_powergate_uvd,
5647         .powergate_vce = iceland_phm_powergate_vce,
5648         .disable_clock_power_gating = iceland_phm_disable_clock_power_gating,
5649         .update_clock_gatings = iceland_phm_update_clock_gatings,
5650         .notify_smc_display_config_after_ps_adjustment = iceland_notify_smc_display_config_after_ps_adjustment,
5651         .display_config_changed = iceland_display_configuration_changed_task,
5652         .set_max_fan_pwm_output = iceland_set_max_fan_pwm_output,
5653         .set_max_fan_rpm_output = iceland_set_max_fan_rpm_output,
5654         .get_temperature = iceland_thermal_get_temperature,
5655         .stop_thermal_controller = iceland_thermal_stop_thermal_controller,
5656         .get_fan_speed_info = iceland_fan_ctrl_get_fan_speed_info,
5657         .get_fan_speed_percent = iceland_fan_ctrl_get_fan_speed_percent,
5658         .set_fan_speed_percent = iceland_fan_ctrl_set_fan_speed_percent,
5659         .reset_fan_speed_to_default = iceland_fan_ctrl_reset_fan_speed_to_default,
5660         .get_fan_speed_rpm = iceland_fan_ctrl_get_fan_speed_rpm,
5661         .set_fan_speed_rpm = iceland_fan_ctrl_set_fan_speed_rpm,
5662         .uninitialize_thermal_controller = iceland_thermal_ctrl_uninitialize_thermal_controller,
5663         .register_internal_thermal_interrupt = iceland_register_internal_thermal_interrupt,
5664         .check_smc_update_required_for_display_configuration = iceland_check_smc_update_required_for_display_configuration,
5665         .check_states_equal = iceland_check_states_equal,
5666         .set_fan_control_mode = iceland_set_fan_control_mode,
5667         .get_fan_control_mode = iceland_get_fan_control_mode,
5668         .force_clock_level = iceland_force_clock_level,
5669         .print_clock_levels = iceland_print_clock_levels,
5670         .get_sclk_od = iceland_get_sclk_od,
5671         .set_sclk_od = iceland_set_sclk_od,
5672         .get_mclk_od = iceland_get_mclk_od,
5673         .set_mclk_od = iceland_set_mclk_od,
5674 };
5675
5676 int iceland_hwmgr_init(struct pp_hwmgr *hwmgr)
5677 {
5678         iceland_hwmgr  *data;
5679
5680         data = kzalloc (sizeof(iceland_hwmgr), GFP_KERNEL);
5681         if (data == NULL)
5682                 return -ENOMEM;
5683         memset(data, 0x00, sizeof(iceland_hwmgr));
5684
5685         hwmgr->backend = data;
5686         hwmgr->hwmgr_func = &iceland_hwmgr_funcs;
5687         hwmgr->pptable_func = &pptable_funcs;
5688
5689         /* thermal */
5690         pp_iceland_thermal_initialize(hwmgr);
5691         return 0;
5692 }