2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/module.h>
24 #include <linux/slab.h>
26 #include <asm/div64.h>
27 #include "linux/delay.h"
30 #include "polaris10_hwmgr.h"
31 #include "polaris10_powertune.h"
32 #include "polaris10_dyn_defaults.h"
33 #include "polaris10_smumgr.h"
35 #include "ppatomctrl.h"
37 #include "tonga_pptable.h"
38 #include "pppcielanes.h"
39 #include "amd_pcie_helpers.h"
40 #include "hardwaremanager.h"
41 #include "tonga_processpptables.h"
42 #include "cgs_common.h"
44 #include "smu_ucode_xfer_vi.h"
45 #include "smu74_discrete.h"
46 #include "smu/smu_7_1_3_d.h"
47 #include "smu/smu_7_1_3_sh_mask.h"
48 #include "gmc/gmc_8_1_d.h"
49 #include "gmc/gmc_8_1_sh_mask.h"
50 #include "oss/oss_3_0_d.h"
51 #include "gca/gfx_8_0_d.h"
52 #include "bif/bif_5_0_d.h"
53 #include "bif/bif_5_0_sh_mask.h"
54 #include "gmc/gmc_8_1_d.h"
55 #include "gmc/gmc_8_1_sh_mask.h"
56 #include "bif/bif_5_0_d.h"
57 #include "bif/bif_5_0_sh_mask.h"
58 #include "dce/dce_10_0_d.h"
59 #include "dce/dce_10_0_sh_mask.h"
61 #include "polaris10_thermal.h"
62 #include "polaris10_clockpowergating.h"
64 #define MC_CG_ARB_FREQ_F0 0x0a
65 #define MC_CG_ARB_FREQ_F1 0x0b
66 #define MC_CG_ARB_FREQ_F2 0x0c
67 #define MC_CG_ARB_FREQ_F3 0x0d
69 #define MC_CG_SEQ_DRAMCONF_S0 0x05
70 #define MC_CG_SEQ_DRAMCONF_S1 0x06
71 #define MC_CG_SEQ_YCLK_SUSPEND 0x04
72 #define MC_CG_SEQ_YCLK_RESUME 0x0a
75 #define SMC_RAM_END 0x40000
77 #define SMC_CG_IND_START 0xc0030000
78 #define SMC_CG_IND_END 0xc0040000
80 #define VOLTAGE_SCALE 4
81 #define VOLTAGE_VID_OFFSET_SCALE1 625
82 #define VOLTAGE_VID_OFFSET_SCALE2 100
84 #define VDDC_VDDCI_DELTA 200
86 #define MEM_FREQ_LOW_LATENCY 25000
87 #define MEM_FREQ_HIGH_LATENCY 80000
89 #define MEM_LATENCY_HIGH 45
90 #define MEM_LATENCY_LOW 35
91 #define MEM_LATENCY_ERR 0xFFFF
93 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
94 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
95 #define MC_SEQ_MISC0_GDDR5_VALUE 5
98 #define PCIE_BUS_CLK 10000
99 #define TCLK (PCIE_BUS_CLK / 10)
102 static const uint16_t polaris10_clock_stretcher_lookup_table[2][4] =
103 { {600, 1050, 3, 0}, {600, 1050, 6, 1} };
105 /* [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */
106 static const uint32_t polaris10_clock_stretcher_ddt_table[2][4][4] =
107 { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
108 { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
110 /* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */
111 static const uint8_t polaris10_clock_stretch_amount_conversion[2][6] =
112 { {0, 1, 3, 2, 4, 5}, {0, 2, 4, 5, 6, 5} };
114 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
116 DPM_EVENT_SRC_ANALOG = 0,
117 DPM_EVENT_SRC_EXTERNAL = 1,
118 DPM_EVENT_SRC_DIGITAL = 2,
119 DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
120 DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
123 static const unsigned long PhwPolaris10_Magic = (unsigned long)(PHM_VIslands_Magic);
125 struct polaris10_power_state *cast_phw_polaris10_power_state(
126 struct pp_hw_power_state *hw_ps)
128 PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
129 "Invalid Powerstate Type!",
132 return (struct polaris10_power_state *)hw_ps;
135 const struct polaris10_power_state *cast_const_phw_polaris10_power_state(
136 const struct pp_hw_power_state *hw_ps)
138 PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
139 "Invalid Powerstate Type!",
142 return (const struct polaris10_power_state *)hw_ps;
145 static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr)
147 return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
148 CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
153 * Find the MC microcode version and store it in the HwMgr struct
155 * @param hwmgr the address of the powerplay hardware manager.
158 int phm_get_mc_microcode_version (struct pp_hwmgr *hwmgr)
160 cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
162 hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
167 uint16_t phm_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
169 uint32_t speedCntl = 0;
171 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
172 speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
173 ixPCIE_LC_SPEED_CNTL);
174 return((uint16_t)PHM_GET_FIELD(speedCntl,
175 PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
178 int phm_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
182 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
183 link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
184 PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
186 PP_ASSERT_WITH_CODE((7 >= link_width),
187 "Invalid PCIe lane width!", return 0);
189 return decode_pcie_lane_width(link_width);
193 * Enable voltage control
195 * @param pHwMgr the address of the powerplay hardware manager.
196 * @return always PP_Result_OK
198 int polaris10_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
201 (hwmgr->smumgr->smumgr_funcs->send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable) == 0),
202 "Failed to enable voltage DPM during DPM Start Function!",
210 * Checks if we want to support voltage control
212 * @param hwmgr the address of the powerplay hardware manager.
214 static bool polaris10_voltage_control(const struct pp_hwmgr *hwmgr)
216 const struct polaris10_hwmgr *data =
217 (const struct polaris10_hwmgr *)(hwmgr->backend);
219 return (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control);
223 * Enable voltage control
225 * @param hwmgr the address of the powerplay hardware manager.
228 static int polaris10_enable_voltage_control(struct pp_hwmgr *hwmgr)
230 /* enable voltage control */
231 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
232 GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
238 * Create Voltage Tables.
240 * @param hwmgr the address of the powerplay hardware manager.
243 static int polaris10_construct_voltage_tables(struct pp_hwmgr *hwmgr)
245 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
246 struct phm_ppt_v1_information *table_info =
247 (struct phm_ppt_v1_information *)hwmgr->pptable;
250 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
251 result = atomctrl_get_voltage_table_v3(hwmgr,
252 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT,
253 &(data->mvdd_voltage_table));
254 PP_ASSERT_WITH_CODE((0 == result),
255 "Failed to retrieve MVDD table.",
257 } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
258 result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table),
259 table_info->vdd_dep_on_mclk);
260 PP_ASSERT_WITH_CODE((0 == result),
261 "Failed to retrieve SVI2 MVDD table from dependancy table.",
265 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
266 result = atomctrl_get_voltage_table_v3(hwmgr,
267 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
268 &(data->vddci_voltage_table));
269 PP_ASSERT_WITH_CODE((0 == result),
270 "Failed to retrieve VDDCI table.",
272 } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
273 result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table),
274 table_info->vdd_dep_on_mclk);
275 PP_ASSERT_WITH_CODE((0 == result),
276 "Failed to retrieve SVI2 VDDCI table from dependancy table.",
280 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
281 result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table),
282 table_info->vddc_lookup_table);
283 PP_ASSERT_WITH_CODE((0 == result),
284 "Failed to retrieve SVI2 VDDC table from lookup table.",
289 (data->vddc_voltage_table.count <= (SMU74_MAX_LEVELS_VDDC)),
290 "Too many voltage values for VDDC. Trimming to fit state table.",
291 phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDC,
292 &(data->vddc_voltage_table)));
295 (data->vddci_voltage_table.count <= (SMU74_MAX_LEVELS_VDDCI)),
296 "Too many voltage values for VDDCI. Trimming to fit state table.",
297 phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDCI,
298 &(data->vddci_voltage_table)));
301 (data->mvdd_voltage_table.count <= (SMU74_MAX_LEVELS_MVDD)),
302 "Too many voltage values for MVDD. Trimming to fit state table.",
303 phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_MVDD,
304 &(data->mvdd_voltage_table)));
310 * Programs static screed detection parameters
312 * @param hwmgr the address of the powerplay hardware manager.
315 static int polaris10_program_static_screen_threshold_parameters(
316 struct pp_hwmgr *hwmgr)
318 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
320 /* Set static screen threshold unit */
321 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
322 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
323 data->static_screen_threshold_unit);
324 /* Set static screen threshold */
325 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
326 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
327 data->static_screen_threshold);
333 * Setup display gap for glitch free memory clock switching.
335 * @param hwmgr the address of the powerplay hardware manager.
338 static int polaris10_enable_display_gap(struct pp_hwmgr *hwmgr)
340 uint32_t display_gap =
341 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
342 ixCG_DISPLAY_GAP_CNTL);
344 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
345 DISP_GAP, DISPLAY_GAP_IGNORE);
347 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
348 DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
350 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
351 ixCG_DISPLAY_GAP_CNTL, display_gap);
357 * Programs activity state transition voting clients
359 * @param hwmgr the address of the powerplay hardware manager.
362 static int polaris10_program_voting_clients(struct pp_hwmgr *hwmgr)
364 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
366 /* Clear reset for voting clients before enabling DPM */
367 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
368 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
369 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
370 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
372 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
373 ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
374 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
375 ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
376 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
377 ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
378 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
379 ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
380 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
381 ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
382 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
383 ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
384 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
385 ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
386 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
387 ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
393 * Get the location of various tables inside the FW image.
395 * @param hwmgr the address of the powerplay hardware manager.
398 static int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
400 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
401 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
406 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
407 SMU7_FIRMWARE_HEADER_LOCATION +
408 offsetof(SMU74_Firmware_Header, DpmTable),
409 &tmp, data->sram_end);
412 data->dpm_table_start = tmp;
414 error |= (0 != result);
416 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
417 SMU7_FIRMWARE_HEADER_LOCATION +
418 offsetof(SMU74_Firmware_Header, SoftRegisters),
419 &tmp, data->sram_end);
422 data->soft_regs_start = tmp;
423 smu_data->soft_regs_start = tmp;
426 error |= (0 != result);
428 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
429 SMU7_FIRMWARE_HEADER_LOCATION +
430 offsetof(SMU74_Firmware_Header, mcRegisterTable),
431 &tmp, data->sram_end);
434 data->mc_reg_table_start = tmp;
436 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
437 SMU7_FIRMWARE_HEADER_LOCATION +
438 offsetof(SMU74_Firmware_Header, FanTable),
439 &tmp, data->sram_end);
442 data->fan_table_start = tmp;
444 error |= (0 != result);
446 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
447 SMU7_FIRMWARE_HEADER_LOCATION +
448 offsetof(SMU74_Firmware_Header, mcArbDramTimingTable),
449 &tmp, data->sram_end);
452 data->arb_table_start = tmp;
454 error |= (0 != result);
456 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
457 SMU7_FIRMWARE_HEADER_LOCATION +
458 offsetof(SMU74_Firmware_Header, Version),
459 &tmp, data->sram_end);
462 hwmgr->microcode_version_info.SMC = tmp;
464 error |= (0 != result);
466 return error ? -1 : 0;
469 /* Copy one arb setting to another and then switch the active set.
470 * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
472 static int polaris10_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
473 uint32_t arb_src, uint32_t arb_dest)
475 uint32_t mc_arb_dram_timing;
476 uint32_t mc_arb_dram_timing2;
478 uint32_t mc_cg_config;
481 case MC_CG_ARB_FREQ_F0:
482 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
483 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
484 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
486 case MC_CG_ARB_FREQ_F1:
487 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
488 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
489 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
496 case MC_CG_ARB_FREQ_F0:
497 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
498 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
499 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
501 case MC_CG_ARB_FREQ_F1:
502 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
503 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
504 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
510 mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
511 mc_cg_config |= 0x0000000F;
512 cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
513 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
519 * Initial switch from ARB F0->F1
521 * @param hwmgr the address of the powerplay hardware manager.
523 * This function is to be called from the SetPowerState table.
525 static int polaris10_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
527 return polaris10_copy_and_switch_arb_sets(hwmgr,
528 MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
531 static int polaris10_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
533 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
534 struct phm_ppt_v1_information *table_info =
535 (struct phm_ppt_v1_information *)(hwmgr->pptable);
536 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
537 uint32_t i, max_entry;
539 PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
540 data->use_pcie_power_saving_levels), "No pcie performance levels!",
543 if (data->use_pcie_performance_levels &&
544 !data->use_pcie_power_saving_levels) {
545 data->pcie_gen_power_saving = data->pcie_gen_performance;
546 data->pcie_lane_power_saving = data->pcie_lane_performance;
547 } else if (!data->use_pcie_performance_levels &&
548 data->use_pcie_power_saving_levels) {
549 data->pcie_gen_performance = data->pcie_gen_power_saving;
550 data->pcie_lane_performance = data->pcie_lane_power_saving;
553 phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table,
554 SMU74_MAX_LEVELS_LINK,
555 MAX_REGULAR_DPM_NUMBER);
557 if (pcie_table != NULL) {
558 /* max_entry is used to make sure we reserve one PCIE level
559 * for boot level (fix for A+A PSPP issue).
560 * If PCIE table from PPTable have ULV entry + 8 entries,
561 * then ignore the last entry.*/
562 max_entry = (SMU74_MAX_LEVELS_LINK < pcie_table->count) ?
563 SMU74_MAX_LEVELS_LINK : pcie_table->count;
564 for (i = 1; i < max_entry; i++) {
565 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
566 get_pcie_gen_support(data->pcie_gen_cap,
567 pcie_table->entries[i].gen_speed),
568 get_pcie_lane_support(data->pcie_lane_cap,
569 pcie_table->entries[i].lane_width));
571 data->dpm_table.pcie_speed_table.count = max_entry - 1;
573 /* Setup BIF_SCLK levels */
574 for (i = 0; i < max_entry; i++)
575 data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk;
577 /* Hardcode Pcie Table */
578 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
579 get_pcie_gen_support(data->pcie_gen_cap,
581 get_pcie_lane_support(data->pcie_lane_cap,
583 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
584 get_pcie_gen_support(data->pcie_gen_cap,
586 get_pcie_lane_support(data->pcie_lane_cap,
588 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
589 get_pcie_gen_support(data->pcie_gen_cap,
591 get_pcie_lane_support(data->pcie_lane_cap,
593 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
594 get_pcie_gen_support(data->pcie_gen_cap,
596 get_pcie_lane_support(data->pcie_lane_cap,
598 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
599 get_pcie_gen_support(data->pcie_gen_cap,
601 get_pcie_lane_support(data->pcie_lane_cap,
603 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
604 get_pcie_gen_support(data->pcie_gen_cap,
606 get_pcie_lane_support(data->pcie_lane_cap,
609 data->dpm_table.pcie_speed_table.count = 6;
611 /* Populate last level for boot PCIE level, but do not increment count. */
612 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
613 data->dpm_table.pcie_speed_table.count,
614 get_pcie_gen_support(data->pcie_gen_cap,
616 get_pcie_lane_support(data->pcie_lane_cap,
623 * This function is to initalize all DPM state tables
624 * for SMU7 based on the dependency table.
625 * Dynamic state patching function will then trim these
626 * state tables to the allowed range based
627 * on the power policy or external client requests,
628 * such as UVD request, etc.
630 int polaris10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
632 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
633 struct phm_ppt_v1_information *table_info =
634 (struct phm_ppt_v1_information *)(hwmgr->pptable);
637 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table =
638 table_info->vdd_dep_on_sclk;
639 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
640 table_info->vdd_dep_on_mclk;
642 PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
643 "SCLK dependency table is missing. This table is mandatory",
645 PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
646 "SCLK dependency table has to have is missing."
647 "This table is mandatory",
650 PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
651 "MCLK dependency table is missing. This table is mandatory",
653 PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
654 "MCLK dependency table has to have is missing."
655 "This table is mandatory",
658 /* clear the state table to reset everything to default */
659 phm_reset_single_dpm_table(
660 &data->dpm_table.sclk_table, SMU74_MAX_LEVELS_GRAPHICS, MAX_REGULAR_DPM_NUMBER);
661 phm_reset_single_dpm_table(
662 &data->dpm_table.mclk_table, SMU74_MAX_LEVELS_MEMORY, MAX_REGULAR_DPM_NUMBER);
665 /* Initialize Sclk DPM table based on allow Sclk values */
666 data->dpm_table.sclk_table.count = 0;
667 for (i = 0; i < dep_sclk_table->count; i++) {
668 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value !=
669 dep_sclk_table->entries[i].clk) {
671 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
672 dep_sclk_table->entries[i].clk;
674 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled =
675 (i == 0) ? true : false;
676 data->dpm_table.sclk_table.count++;
680 /* Initialize Mclk DPM table based on allow Mclk values */
681 data->dpm_table.mclk_table.count = 0;
682 for (i = 0; i < dep_mclk_table->count; i++) {
683 if (i == 0 || data->dpm_table.mclk_table.dpm_levels
684 [data->dpm_table.mclk_table.count - 1].value !=
685 dep_mclk_table->entries[i].clk) {
686 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
687 dep_mclk_table->entries[i].clk;
688 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled =
689 (i == 0) ? true : false;
690 data->dpm_table.mclk_table.count++;
694 /* setup PCIE gen speed levels */
695 polaris10_setup_default_pcie_table(hwmgr);
697 /* save a copy of the default DPM table */
698 memcpy(&(data->golden_dpm_table), &(data->dpm_table),
699 sizeof(struct polaris10_dpm_table));
704 uint8_t convert_to_vid(uint16_t vddc)
706 return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
710 * Mvdd table preparation for SMC.
712 * @param *hwmgr The address of the hardware manager.
713 * @param *table The SMC DPM table structure to be populated.
716 static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
717 SMU74_Discrete_DpmTable *table)
719 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
720 uint32_t count, level;
722 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
723 count = data->mvdd_voltage_table.count;
724 if (count > SMU_MAX_SMIO_LEVELS)
725 count = SMU_MAX_SMIO_LEVELS;
726 for (level = 0; level < count; level++) {
727 table->SmioTable2.Pattern[level].Voltage =
728 PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
729 /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
730 table->SmioTable2.Pattern[level].Smio =
732 table->Smio[level] |=
733 data->mvdd_voltage_table.entries[level].smio_low;
735 table->SmioMask2 = data->vddci_voltage_table.mask_low;
737 table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
743 static int polaris10_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
744 struct SMU74_Discrete_DpmTable *table)
746 uint32_t count, level;
747 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
749 count = data->vddci_voltage_table.count;
751 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
752 if (count > SMU_MAX_SMIO_LEVELS)
753 count = SMU_MAX_SMIO_LEVELS;
754 for (level = 0; level < count; ++level) {
755 table->SmioTable1.Pattern[level].Voltage =
756 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE);
757 table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
759 table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
763 table->SmioMask1 = data->vddci_voltage_table.mask_low;
769 * Preparation of vddc and vddgfx CAC tables for SMC.
771 * @param hwmgr the address of the hardware manager
772 * @param table the SMC DPM table structure to be populated
775 static int polaris10_populate_cac_table(struct pp_hwmgr *hwmgr,
776 struct SMU74_Discrete_DpmTable *table)
780 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
781 struct phm_ppt_v1_information *table_info =
782 (struct phm_ppt_v1_information *)(hwmgr->pptable);
783 struct phm_ppt_v1_voltage_lookup_table *lookup_table =
784 table_info->vddc_lookup_table;
785 /* tables is already swapped, so in order to use the value from it,
786 * we need to swap it back.
787 * We are populating vddc CAC data to BapmVddc table
788 * in split and merged mode
790 for (count = 0; count < lookup_table->count; count++) {
791 index = phm_get_voltage_index(lookup_table,
792 data->vddc_voltage_table.entries[count].value);
793 table->BapmVddcVidLoSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_low);
794 table->BapmVddcVidHiSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_mid);
795 table->BapmVddcVidHiSidd2[count] = convert_to_vid(lookup_table->entries[index].us_cac_high);
802 * Preparation of voltage tables for SMC.
804 * @param hwmgr the address of the hardware manager
805 * @param table the SMC DPM table structure to be populated
809 int polaris10_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
810 struct SMU74_Discrete_DpmTable *table)
812 polaris10_populate_smc_vddci_table(hwmgr, table);
813 polaris10_populate_smc_mvdd_table(hwmgr, table);
814 polaris10_populate_cac_table(hwmgr, table);
819 static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
820 struct SMU74_Discrete_Ulv *state)
822 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
823 struct phm_ppt_v1_information *table_info =
824 (struct phm_ppt_v1_information *)(hwmgr->pptable);
826 state->CcPwrDynRm = 0;
827 state->CcPwrDynRm1 = 0;
829 state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
830 state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
831 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
833 state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
835 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
836 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
837 CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
842 static int polaris10_populate_ulv_state(struct pp_hwmgr *hwmgr,
843 struct SMU74_Discrete_DpmTable *table)
845 return polaris10_populate_ulv_level(hwmgr, &table->Ulv);
848 static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr,
849 struct SMU74_Discrete_DpmTable *table)
851 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
852 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
855 /* Index (dpm_table->pcie_speed_table.count)
856 * is reserved for PCIE boot level. */
857 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
858 table->LinkLevel[i].PcieGenSpeed =
859 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
860 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
861 dpm_table->pcie_speed_table.dpm_levels[i].param1);
862 table->LinkLevel[i].EnabledForActivity = 1;
863 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
864 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
865 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
868 data->smc_state_table.LinkLevelCount =
869 (uint8_t)dpm_table->pcie_speed_table.count;
870 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
871 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
876 static uint32_t polaris10_get_xclk(struct pp_hwmgr *hwmgr)
878 uint32_t reference_clock, tmp;
879 struct cgs_display_info info = {0};
880 struct cgs_mode_info mode_info;
882 info.mode_info = &mode_info;
884 tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK);
889 cgs_get_active_displays_info(hwmgr->device, &info);
890 reference_clock = mode_info.ref_clock;
892 tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE);
895 return reference_clock / 4;
897 return reference_clock;
901 * Calculates the SCLK dividers using the provided engine clock
903 * @param hwmgr the address of the hardware manager
904 * @param clock the engine clock to use to populate the structure
905 * @param sclk the SMC SCLK structure to be populated
907 static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
908 uint32_t clock, SMU_SclkSetting *sclk_setting)
910 const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
911 const SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
912 struct pp_atomctrl_clock_dividers_ai dividers;
915 uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq;
920 sclk_setting->SclkFrequency = clock;
921 /* get the engine clock dividers for this clock value */
922 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, ÷rs);
924 sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
925 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
926 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
927 sclk_setting->PllRange = dividers.ucSclkPllRange;
928 sclk_setting->Sclk_slew_rate = 0x400;
929 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
930 sclk_setting->Pcc_down_slew_rate = 0xffff;
931 sclk_setting->SSc_En = dividers.ucSscEnable;
932 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
933 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
934 sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
938 ref_clock = polaris10_get_xclk(hwmgr);
940 for (i = 0; i < NUM_SCLK_RANGE; i++) {
941 if (clock > data->range_table[i].trans_lower_frequency
942 && clock <= data->range_table[i].trans_upper_frequency) {
943 sclk_setting->PllRange = i;
948 sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
949 temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
951 do_div(temp, ref_clock);
952 sclk_setting->Fcw_frac = temp & 0xffff;
954 pcc_target_percent = 10; /* Hardcode 10% for now. */
955 pcc_target_freq = clock - (clock * pcc_target_percent / 100);
956 sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
958 ss_target_percent = 2; /* Hardcode 2% for now. */
959 sclk_setting->SSc_En = 0;
960 if (ss_target_percent) {
961 sclk_setting->SSc_En = 1;
962 ss_target_freq = clock - (clock * ss_target_percent / 100);
963 sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
964 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
966 do_div(temp, ref_clock);
967 sclk_setting->Fcw1_frac = temp & 0xffff;
973 static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
974 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
975 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
979 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
981 *voltage = *mvdd = 0;
983 /* clock - voltage dependency table is empty table */
984 if (dep_table->count == 0)
987 for (i = 0; i < dep_table->count; i++) {
988 /* find first sclk bigger than request */
989 if (dep_table->entries[i].clk >= clock) {
990 *voltage |= (dep_table->entries[i].vddc *
991 VOLTAGE_SCALE) << VDDC_SHIFT;
992 if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
993 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
994 VOLTAGE_SCALE) << VDDCI_SHIFT;
995 else if (dep_table->entries[i].vddci)
996 *voltage |= (dep_table->entries[i].vddci *
997 VOLTAGE_SCALE) << VDDCI_SHIFT;
999 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
1000 (dep_table->entries[i].vddc -
1001 (uint16_t)data->vddc_vddci_delta));
1002 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1005 if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1006 *mvdd = data->vbios_boot_state.mvdd_bootup_value *
1008 else if (dep_table->entries[i].mvdd)
1009 *mvdd = (uint32_t) dep_table->entries[i].mvdd *
1012 *voltage |= 1 << PHASES_SHIFT;
1017 /* sclk is bigger than max sclk in the dependence table */
1018 *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1020 if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
1021 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1022 VOLTAGE_SCALE) << VDDCI_SHIFT;
1023 else if (dep_table->entries[i-1].vddci) {
1024 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
1025 (dep_table->entries[i].vddc -
1026 (uint16_t)data->vddc_vddci_delta));
1027 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1030 if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1031 *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
1032 else if (dep_table->entries[i].mvdd)
1033 *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
1038 static const sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] =
1039 { {VCO_2_4, POSTDIV_DIV_BY_16, 75, 160, 112},
1040 {VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
1041 {VCO_2_4, POSTDIV_DIV_BY_8, 75, 160, 112},
1042 {VCO_3_6, POSTDIV_DIV_BY_8, 112, 224, 160},
1043 {VCO_2_4, POSTDIV_DIV_BY_4, 75, 160, 112},
1044 {VCO_3_6, POSTDIV_DIV_BY_4, 112, 216, 160},
1045 {VCO_2_4, POSTDIV_DIV_BY_2, 75, 160, 108},
1046 {VCO_3_6, POSTDIV_DIV_BY_2, 112, 216, 160} };
1048 static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr)
1050 uint32_t i, ref_clk;
1051 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1052 SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
1053 struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
1055 ref_clk = polaris10_get_xclk(hwmgr);
1057 if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
1058 for (i = 0; i < NUM_SCLK_RANGE; i++) {
1059 table->SclkFcwRangeTable[i].vco_setting = range_table_from_vbios.entry[i].ucVco_setting;
1060 table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv;
1061 table->SclkFcwRangeTable[i].fcw_pcc = range_table_from_vbios.entry[i].usFcw_pcc;
1063 table->SclkFcwRangeTable[i].fcw_trans_upper = range_table_from_vbios.entry[i].usFcw_trans_upper;
1064 table->SclkFcwRangeTable[i].fcw_trans_lower = range_table_from_vbios.entry[i].usRcw_trans_lower;
1066 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
1067 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
1068 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
1073 for (i = 0; i < NUM_SCLK_RANGE; i++) {
1075 data->range_table[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
1076 data->range_table[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
1078 table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;
1079 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
1080 table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;
1082 table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;
1083 table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;
1085 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
1086 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
1087 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
1092 * Populates single SMC SCLK structure using the provided engine clock
1094 * @param hwmgr the address of the hardware manager
1095 * @param clock the engine clock to use to populate the structure
1096 * @param sclk the SMC SCLK structure to be populated
1099 static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
1100 uint32_t clock, uint16_t sclk_al_threshold,
1101 struct SMU74_Discrete_GraphicsLevel *level)
1103 int result, i, temp;
1104 /* PP_Clocks minClocks; */
1106 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1107 struct phm_ppt_v1_information *table_info =
1108 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1109 SMU_SclkSetting curr_sclk_setting = { 0 };
1111 result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
1113 /* populate graphics levels */
1114 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1115 table_info->vdd_dep_on_sclk, clock,
1116 &level->MinVoltage, &mvdd);
1118 PP_ASSERT_WITH_CODE((0 == result),
1119 "can not find VDDC voltage value for "
1120 "VDDC engine clock dependency table",
1122 level->ActivityLevel = sclk_al_threshold;
1124 level->CcPwrDynRm = 0;
1125 level->CcPwrDynRm1 = 0;
1126 level->EnabledForActivity = 0;
1127 level->EnabledForThrottle = 1;
1129 level->DownHyst = 0;
1130 level->VoltageDownHyst = 0;
1131 level->PowerThrottle = 0;
1134 * TODO: get minimum clocks from dal configaration
1135 * PECI_GetMinClockSettings(hwmgr->pPECI, &minClocks);
1137 /* data->DisplayTiming.minClockInSR = minClocks.engineClockInSR; */
1139 /* get level->DeepSleepDivId
1140 if (phm_cap_enabled(hwmgr->platformDescriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
1141 level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR);
1143 PP_ASSERT_WITH_CODE((clock >= POLARIS10_MINIMUM_ENGINE_CLOCK), "Engine clock can't satisfy stutter requirement!", return 0);
1144 for (i = POLARIS10_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
1147 if (temp >= POLARIS10_MINIMUM_ENGINE_CLOCK || i == 0)
1151 level->DeepSleepDivId = i;
1153 /* Default to slow, highest DPM level will be
1154 * set to PPSMC_DISPLAY_WATERMARK_LOW later.
1156 if (data->update_up_hyst)
1157 level->UpHyst = (uint8_t)data->up_hyst;
1158 if (data->update_down_hyst)
1159 level->DownHyst = (uint8_t)data->down_hyst;
1161 level->SclkSetting = curr_sclk_setting;
1163 CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
1164 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
1165 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
1166 CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
1167 CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency);
1168 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int);
1169 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac);
1170 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int);
1171 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate);
1172 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate);
1173 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate);
1174 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
1175 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac);
1176 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate);
1181 * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
1183 * @param hwmgr the address of the hardware manager
1185 static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1187 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1188 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
1189 struct phm_ppt_v1_information *table_info =
1190 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1191 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1192 uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;
1194 uint32_t array = data->dpm_table_start +
1195 offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
1196 uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) *
1197 SMU74_MAX_LEVELS_GRAPHICS;
1198 struct SMU74_Discrete_GraphicsLevel *levels =
1199 data->smc_state_table.GraphicsLevel;
1200 uint32_t i, max_entry;
1201 uint8_t hightest_pcie_level_enabled = 0,
1202 lowest_pcie_level_enabled = 0,
1203 mid_pcie_level_enabled = 0,
1206 polaris10_get_sclk_range_table(hwmgr);
1208 for (i = 0; i < dpm_table->sclk_table.count; i++) {
1210 result = polaris10_populate_single_graphic_level(hwmgr,
1211 dpm_table->sclk_table.dpm_levels[i].value,
1212 (uint16_t)data->activity_target[i],
1213 &(data->smc_state_table.GraphicsLevel[i]));
1217 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
1219 levels[i].DeepSleepDivId = 0;
1221 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1222 PHM_PlatformCaps_SPLLShutdownSupport))
1223 data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
1225 data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
1226 data->smc_state_table.GraphicsDpmLevelCount =
1227 (uint8_t)dpm_table->sclk_table.count;
1228 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1229 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1232 if (pcie_table != NULL) {
1233 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
1234 "There must be 1 or more PCIE levels defined in PPTable.",
1236 max_entry = pcie_entry_cnt - 1;
1237 for (i = 0; i < dpm_table->sclk_table.count; i++)
1238 levels[i].pcieDpmLevel =
1239 (uint8_t) ((i < max_entry) ? i : max_entry);
1241 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1242 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1243 (1 << (hightest_pcie_level_enabled + 1))) != 0))
1244 hightest_pcie_level_enabled++;
1246 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1247 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1248 (1 << lowest_pcie_level_enabled)) == 0))
1249 lowest_pcie_level_enabled++;
1251 while ((count < hightest_pcie_level_enabled) &&
1252 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1253 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
1256 mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
1257 hightest_pcie_level_enabled ?
1258 (lowest_pcie_level_enabled + 1 + count) :
1259 hightest_pcie_level_enabled;
1261 /* set pcieDpmLevel to hightest_pcie_level_enabled */
1262 for (i = 2; i < dpm_table->sclk_table.count; i++)
1263 levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
1265 /* set pcieDpmLevel to lowest_pcie_level_enabled */
1266 levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
1268 /* set pcieDpmLevel to mid_pcie_level_enabled */
1269 levels[1].pcieDpmLevel = mid_pcie_level_enabled;
1271 /* level count will send to smc once at init smc table and never change */
1272 result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
1273 (uint32_t)array_size, data->sram_end);
1278 static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
1279 uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level)
1281 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1282 struct phm_ppt_v1_information *table_info =
1283 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1285 struct cgs_display_info info = {0, 0, NULL};
1287 cgs_get_active_displays_info(hwmgr->device, &info);
1289 if (table_info->vdd_dep_on_mclk) {
1290 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1291 table_info->vdd_dep_on_mclk, clock,
1292 &mem_level->MinVoltage, &mem_level->MinMvdd);
1293 PP_ASSERT_WITH_CODE((0 == result),
1294 "can not find MinVddc voltage value from memory "
1295 "VDDC voltage dependency table", return result);
1298 mem_level->MclkFrequency = clock;
1299 mem_level->EnabledForThrottle = 1;
1300 mem_level->EnabledForActivity = 0;
1301 mem_level->UpHyst = 0;
1302 mem_level->DownHyst = 100;
1303 mem_level->VoltageDownHyst = 0;
1304 mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
1305 mem_level->StutterEnable = false;
1306 mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1308 data->display_timing.num_existing_displays = info.display_count;
1310 if ((data->mclk_stutter_mode_threshold) &&
1311 (clock <= data->mclk_stutter_mode_threshold) &&
1312 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
1313 STUTTER_ENABLE) & 0x1))
1314 mem_level->StutterEnable = true;
1317 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
1318 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
1319 CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
1320 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
1326 * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
1328 * @param hwmgr the address of the hardware manager
1330 static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1332 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1333 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
1335 /* populate MCLK dpm table to SMU7 */
1336 uint32_t array = data->dpm_table_start +
1337 offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
1338 uint32_t array_size = sizeof(SMU74_Discrete_MemoryLevel) *
1339 SMU74_MAX_LEVELS_MEMORY;
1340 struct SMU74_Discrete_MemoryLevel *levels =
1341 data->smc_state_table.MemoryLevel;
1344 for (i = 0; i < dpm_table->mclk_table.count; i++) {
1345 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1346 "can not populate memory level as memory clock is zero",
1348 result = polaris10_populate_single_memory_level(hwmgr,
1349 dpm_table->mclk_table.dpm_levels[i].value,
1351 if (i == dpm_table->mclk_table.count - 1) {
1352 levels[i].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
1353 levels[i].EnabledForActivity = 1;
1359 /* in order to prevent MC activity from stutter mode to push DPM up.
1360 * the UVD change complements this by putting the MCLK in
1361 * a higher state by default such that we are not effected by
1362 * up threshold or and MCLK DPM latency.
1364 levels[0].ActivityLevel = 0x1f;
1365 CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
1367 data->smc_state_table.MemoryDpmLevelCount =
1368 (uint8_t)dpm_table->mclk_table.count;
1369 data->dpm_level_enable_mask.mclk_dpm_enable_mask =
1370 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
1372 /* level count will send to smc once at init smc table and never change */
1373 result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
1374 (uint32_t)array_size, data->sram_end);
1380 * Populates the SMC MVDD structure using the provided memory clock.
1382 * @param hwmgr the address of the hardware manager
1383 * @param mclk the MCLK value to be used in the decision if MVDD should be high or low.
1384 * @param voltage the SMC VOLTAGE structure to be populated
1386 int polaris10_populate_mvdd_value(struct pp_hwmgr *hwmgr,
1387 uint32_t mclk, SMIO_Pattern *smio_pat)
1389 const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1390 struct phm_ppt_v1_information *table_info =
1391 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1394 if (POLARIS10_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
1395 /* find mvdd value which clock is more than request */
1396 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
1397 if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
1398 smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
1402 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
1403 "MVDD Voltage is outside the supported range.",
1411 static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
1412 SMU74_Discrete_DpmTable *table)
1415 uint32_t sclk_frequency;
1416 const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1417 struct phm_ppt_v1_information *table_info =
1418 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1419 SMIO_Pattern vol_level;
1423 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1425 if (!data->sclk_dpm_key_disabled) {
1426 /* Get MinVoltage and Frequency from DPM0,
1427 * already converted to SMC_UL */
1428 sclk_frequency = data->dpm_table.sclk_table.dpm_levels[0].value;
1429 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1430 table_info->vdd_dep_on_sclk,
1431 table->ACPILevel.SclkFrequency,
1432 &table->ACPILevel.MinVoltage, &mvdd);
1433 PP_ASSERT_WITH_CODE((0 == result),
1434 "Cannot find ACPI VDDC voltage value "
1435 "in Clock Dependency Table", );
1437 sclk_frequency = data->vbios_boot_state.sclk_bootup_value;
1438 table->ACPILevel.MinVoltage =
1439 data->vbios_boot_state.vddc_bootup_value * VOLTAGE_SCALE;
1442 result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency, &(table->ACPILevel.SclkSetting));
1443 PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result);
1445 table->ACPILevel.DeepSleepDivId = 0;
1446 table->ACPILevel.CcPwrDynRm = 0;
1447 table->ACPILevel.CcPwrDynRm1 = 0;
1449 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1450 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
1451 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1452 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1454 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);
1455 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
1456 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
1457 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
1458 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
1459 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
1460 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
1461 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
1462 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
1463 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
1465 if (!data->mclk_dpm_key_disabled) {
1466 /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
1467 table->MemoryACPILevel.MclkFrequency =
1468 data->dpm_table.mclk_table.dpm_levels[0].value;
1469 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1470 table_info->vdd_dep_on_mclk,
1471 table->MemoryACPILevel.MclkFrequency,
1472 &table->MemoryACPILevel.MinVoltage, &mvdd);
1473 PP_ASSERT_WITH_CODE((0 == result),
1474 "Cannot find ACPI VDDCI voltage value "
1475 "in Clock Dependency Table",
1478 table->MemoryACPILevel.MclkFrequency =
1479 data->vbios_boot_state.mclk_bootup_value;
1480 table->MemoryACPILevel.MinVoltage =
1481 data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE;
1485 if ((POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
1486 (data->mclk_dpm_key_disabled))
1487 us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
1489 if (!polaris10_populate_mvdd_value(hwmgr,
1490 data->dpm_table.mclk_table.dpm_levels[0].value,
1492 us_mvdd = vol_level.Voltage;
1495 if (0 == polaris10_populate_mvdd_value(hwmgr, 0, &vol_level))
1496 table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
1498 table->MemoryACPILevel.MinMvdd = 0;
1500 table->MemoryACPILevel.StutterEnable = false;
1502 table->MemoryACPILevel.EnabledForThrottle = 0;
1503 table->MemoryACPILevel.EnabledForActivity = 0;
1504 table->MemoryACPILevel.UpHyst = 0;
1505 table->MemoryACPILevel.DownHyst = 100;
1506 table->MemoryACPILevel.VoltageDownHyst = 0;
1507 table->MemoryACPILevel.ActivityLevel =
1508 PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
1510 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
1511 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
1516 static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1517 SMU74_Discrete_DpmTable *table)
1519 int result = -EINVAL;
1521 struct pp_atomctrl_clock_dividers_vi dividers;
1522 struct phm_ppt_v1_information *table_info =
1523 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1524 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1525 table_info->mm_dep_table;
1526 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1528 table->VceLevelCount = (uint8_t)(mm_table->count);
1529 table->VceBootLevel = 0;
1531 for (count = 0; count < table->VceLevelCount; count++) {
1532 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
1533 table->VceLevel[count].MinVoltage = 0;
1534 table->VceLevel[count].MinVoltage |=
1535 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1536 table->VceLevel[count].MinVoltage |=
1537 ((mm_table->entries[count].vddc - data->vddc_vddci_delta) *
1538 VOLTAGE_SCALE) << VDDCI_SHIFT;
1539 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1541 /*retrieve divider value for VBIOS */
1542 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1543 table->VceLevel[count].Frequency, ÷rs);
1544 PP_ASSERT_WITH_CODE((0 == result),
1545 "can not find divide id for VCE engine clock",
1548 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1550 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1551 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
1556 static int polaris10_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
1557 SMU74_Discrete_DpmTable *table)
1559 int result = -EINVAL;
1561 struct pp_atomctrl_clock_dividers_vi dividers;
1562 struct phm_ppt_v1_information *table_info =
1563 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1564 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1565 table_info->mm_dep_table;
1566 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1568 table->SamuBootLevel = 0;
1569 table->SamuLevelCount = (uint8_t)(mm_table->count);
1571 for (count = 0; count < table->SamuLevelCount; count++) {
1572 /* not sure whether we need evclk or not */
1573 table->SamuLevel[count].MinVoltage = 0;
1574 table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
1575 table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1576 VOLTAGE_SCALE) << VDDC_SHIFT;
1577 table->SamuLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
1578 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
1579 table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1581 /* retrieve divider value for VBIOS */
1582 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1583 table->SamuLevel[count].Frequency, ÷rs);
1584 PP_ASSERT_WITH_CODE((0 == result),
1585 "can not find divide id for samu clock", return result);
1587 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1589 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
1590 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
1595 static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
1596 int32_t eng_clock, int32_t mem_clock,
1597 SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs)
1599 uint32_t dram_timing;
1600 uint32_t dram_timing2;
1601 uint32_t burst_time;
1604 result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1605 eng_clock, mem_clock);
1606 PP_ASSERT_WITH_CODE(result == 0,
1607 "Error calling VBIOS to set DRAM_TIMING.", return result);
1609 dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1610 dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1611 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1614 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing);
1615 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
1616 arb_regs->McArbBurstTime = (uint8_t)burst_time;
1621 static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1623 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1624 struct SMU74_Discrete_MCArbDramTimingTable arb_regs;
1628 for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1629 for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
1630 result = polaris10_populate_memory_timing_parameters(hwmgr,
1631 data->dpm_table.sclk_table.dpm_levels[i].value,
1632 data->dpm_table.mclk_table.dpm_levels[j].value,
1633 &arb_regs.entries[i][j]);
1635 result = atomctrl_set_ac_timing_ai(hwmgr, data->dpm_table.mclk_table.dpm_levels[j].value, j);
1641 result = polaris10_copy_bytes_to_smc(
1643 data->arb_table_start,
1644 (uint8_t *)&arb_regs,
1645 sizeof(SMU74_Discrete_MCArbDramTimingTable),
1650 static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1651 struct SMU74_Discrete_DpmTable *table)
1653 int result = -EINVAL;
1655 struct pp_atomctrl_clock_dividers_vi dividers;
1656 struct phm_ppt_v1_information *table_info =
1657 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1658 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1659 table_info->mm_dep_table;
1660 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1662 table->UvdLevelCount = (uint8_t)(mm_table->count);
1663 table->UvdBootLevel = 0;
1665 for (count = 0; count < table->UvdLevelCount; count++) {
1666 table->UvdLevel[count].MinVoltage = 0;
1667 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1668 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1669 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1670 VOLTAGE_SCALE) << VDDC_SHIFT;
1671 table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
1672 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
1673 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1675 /* retrieve divider value for VBIOS */
1676 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1677 table->UvdLevel[count].VclkFrequency, ÷rs);
1678 PP_ASSERT_WITH_CODE((0 == result),
1679 "can not find divide id for Vclk clock", return result);
1681 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1683 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1684 table->UvdLevel[count].DclkFrequency, ÷rs);
1685 PP_ASSERT_WITH_CODE((0 == result),
1686 "can not find divide id for Dclk clock", return result);
1688 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1690 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1691 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1692 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
1698 static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1699 struct SMU74_Discrete_DpmTable *table)
1702 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1704 table->GraphicsBootLevel = 0;
1705 table->MemoryBootLevel = 0;
1707 /* find boot level from dpm table */
1708 result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1709 data->vbios_boot_state.sclk_bootup_value,
1710 (uint32_t *)&(table->GraphicsBootLevel));
1712 result = phm_find_boot_level(&(data->dpm_table.mclk_table),
1713 data->vbios_boot_state.mclk_bootup_value,
1714 (uint32_t *)&(table->MemoryBootLevel));
1716 table->BootVddc = data->vbios_boot_state.vddc_bootup_value *
1718 table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
1720 table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value *
1723 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
1724 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
1725 CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
1731 static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
1733 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1734 struct phm_ppt_v1_information *table_info =
1735 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1736 uint8_t count, level;
1738 count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
1740 for (level = 0; level < count; level++) {
1741 if (table_info->vdd_dep_on_sclk->entries[level].clk >=
1742 data->vbios_boot_state.sclk_bootup_value) {
1743 data->smc_state_table.GraphicsBootLevel = level;
1748 count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
1749 for (level = 0; level < count; level++) {
1750 if (table_info->vdd_dep_on_mclk->entries[level].clk >=
1751 data->vbios_boot_state.mclk_bootup_value) {
1752 data->smc_state_table.MemoryBootLevel = level;
1760 static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1762 uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min;
1763 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1764 uint8_t i, stretch_amount, stretch_amount2, volt_offset = 0;
1765 struct phm_ppt_v1_information *table_info =
1766 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1767 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1768 table_info->vdd_dep_on_sclk;
1770 stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
1772 /* Read SMU_Eefuse to read and calculate RO and determine
1773 * if the part is SS or FF. if RO >= 1660MHz, part is FF.
1775 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1776 ixSMU_EFUSE_0 + (67 * 4));
1777 efuse &= 0xFF000000;
1778 efuse = efuse >> 24;
1780 if (hwmgr->chip_id == CHIP_POLARIS10) {
1788 ro = efuse * (max -min)/255 + min;
1790 /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
1791 for (i = 0; i < sclk_table->count; i++) {
1792 data->smc_state_table.Sclk_CKS_masterEn0_7 |=
1793 sclk_table->entries[i].cks_enable << i;
1795 volt_without_cks = (uint32_t)(((ro - 40) * 1000 - 2753594 - sclk_table->entries[i].clk/100 * 136418 /1000) / \
1796 (sclk_table->entries[i].clk/100 * 1132925 /10000 - 242418)/100);
1798 volt_with_cks = (uint32_t)((ro * 1000 -2396351 - sclk_table->entries[i].clk/100 * 329021/1000) / \
1799 (sclk_table->entries[i].clk/10000 * 649434 /1000 - 18005)/10);
1801 if (volt_without_cks >= volt_with_cks)
1802 volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
1803 sclk_table->entries[i].cks_voffset) * 100 / 625) + 1);
1805 data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1808 /* Populate CKS Lookup Table */
1809 if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
1810 stretch_amount2 = 0;
1811 else if (stretch_amount == 3 || stretch_amount == 4)
1812 stretch_amount2 = 1;
1814 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1815 PHM_PlatformCaps_ClockStretcher);
1816 PP_ASSERT_WITH_CODE(false,
1817 "Stretch Amount in PPTable not supported\n",
1821 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
1822 value &= 0xFFFFFFFE;
1823 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
1829 * Populates the SMC VRConfig field in DPM table.
1831 * @param hwmgr the address of the hardware manager
1832 * @param table the SMC DPM table structure to be populated
1835 static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
1836 struct SMU74_Discrete_DpmTable *table)
1838 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1841 config = VR_MERGED_WITH_VDDC;
1842 table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
1844 /* Set Vddc Voltage Controller */
1845 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1846 config = VR_SVI2_PLANE_1;
1847 table->VRConfig |= config;
1849 PP_ASSERT_WITH_CODE(false,
1850 "VDDC should be on SVI2 control in merged mode!",
1853 /* Set Vddci Voltage Controller */
1854 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
1855 config = VR_SVI2_PLANE_2; /* only in merged mode */
1856 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1857 } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
1858 config = VR_SMIO_PATTERN_1;
1859 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1861 config = VR_STATIC_VOLTAGE;
1862 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1864 /* Set Mvdd Voltage Controller */
1865 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
1866 config = VR_SVI2_PLANE_2;
1867 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1868 } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1869 config = VR_SMIO_PATTERN_2;
1870 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1872 config = VR_STATIC_VOLTAGE;
1873 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1880 int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
1882 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1883 SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
1885 struct pp_atom_ctrl__avfs_parameters avfs_params = {0};
1886 AVFS_meanNsigma_t AVFS_meanNsigma = { {0} };
1887 AVFS_Sclk_Offset_t AVFS_SclkOffset = { {0} };
1889 struct pp_smumgr *smumgr = hwmgr->smumgr;
1890 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
1892 struct phm_ppt_v1_information *table_info =
1893 (struct phm_ppt_v1_information *)hwmgr->pptable;
1894 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1895 table_info->vdd_dep_on_sclk;
1898 if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
1901 result = atomctrl_get_avfs_information(hwmgr, &avfs_params);
1904 table->BTCGB_VDROOP_TABLE[0].a0 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0);
1905 table->BTCGB_VDROOP_TABLE[0].a1 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1);
1906 table->BTCGB_VDROOP_TABLE[0].a2 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2);
1907 table->BTCGB_VDROOP_TABLE[1].a0 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0);
1908 table->BTCGB_VDROOP_TABLE[1].a1 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1);
1909 table->BTCGB_VDROOP_TABLE[1].a2 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2);
1910 table->AVFSGB_VDROOP_TABLE[0].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1);
1911 table->AVFSGB_VDROOP_TABLE[0].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSON_m2);
1912 table->AVFSGB_VDROOP_TABLE[0].b = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b);
1913 table->AVFSGB_VDROOP_TABLE[0].m1_shift = 24;
1914 table->AVFSGB_VDROOP_TABLE[0].m2_shift = 12;
1915 table->AVFSGB_VDROOP_TABLE[1].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1);
1916 table->AVFSGB_VDROOP_TABLE[1].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2);
1917 table->AVFSGB_VDROOP_TABLE[1].b = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b);
1918 table->AVFSGB_VDROOP_TABLE[1].m1_shift = 24;
1919 table->AVFSGB_VDROOP_TABLE[1].m2_shift = 12;
1920 table->MaxVoltage = PP_HOST_TO_SMC_US(avfs_params.usMaxVoltage_0_25mv);
1921 AVFS_meanNsigma.Aconstant[0] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant0);
1922 AVFS_meanNsigma.Aconstant[1] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant1);
1923 AVFS_meanNsigma.Aconstant[2] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant2);
1924 AVFS_meanNsigma.DC_tol_sigma = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_DC_tol_sigma);
1925 AVFS_meanNsigma.Platform_mean = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_mean);
1926 AVFS_meanNsigma.PSM_Age_CompFactor = PP_HOST_TO_SMC_US(avfs_params.usPSM_Age_ComFactor);
1927 AVFS_meanNsigma.Platform_sigma = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_sigma);
1929 for (i = 0; i < NUM_VFT_COLUMNS; i++) {
1930 AVFS_meanNsigma.Static_Voltage_Offset[i] = (uint8_t)(sclk_table->entries[i].cks_voffset * 100 / 625);
1931 AVFS_SclkOffset.Sclk_Offset[i] = PP_HOST_TO_SMC_US((uint16_t)(sclk_table->entries[i].sclk_offset) / 100);
1934 result = polaris10_read_smc_sram_dword(smumgr,
1935 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsMeanNSigma),
1936 &tmp, data->sram_end);
1938 polaris10_copy_bytes_to_smc(smumgr,
1940 (uint8_t *)&AVFS_meanNsigma,
1941 sizeof(AVFS_meanNsigma_t),
1944 result = polaris10_read_smc_sram_dword(smumgr,
1945 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsSclkOffsetTable),
1946 &tmp, data->sram_end);
1947 polaris10_copy_bytes_to_smc(smumgr,
1949 (uint8_t *)&AVFS_SclkOffset,
1950 sizeof(AVFS_Sclk_Offset_t),
1953 data->avfs_vdroop_override_setting = (avfs_params.ucEnableGB_VDROOP_TABLE_CKSON << BTCGB0_Vdroop_Enable_SHIFT) |
1954 (avfs_params.ucEnableGB_VDROOP_TABLE_CKSOFF << BTCGB1_Vdroop_Enable_SHIFT) |
1955 (avfs_params.ucEnableGB_FUSE_TABLE_CKSON << AVFSGB0_Vdroop_Enable_SHIFT) |
1956 (avfs_params.ucEnableGB_FUSE_TABLE_CKSOFF << AVFSGB1_Vdroop_Enable_SHIFT);
1957 data->apply_avfs_cks_off_voltage = (avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage == 1) ? true : false;
1964 * Initializes the SMC table and uploads it
1966 * @param hwmgr the address of the powerplay hardware manager.
1969 static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
1972 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1973 struct phm_ppt_v1_information *table_info =
1974 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1975 struct SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
1976 const struct polaris10_ulv_parm *ulv = &(data->ulv);
1978 struct pp_atomctrl_gpio_pin_assignment gpio_pin;
1979 pp_atomctrl_clock_dividers_vi dividers;
1981 result = polaris10_setup_default_dpm_tables(hwmgr);
1982 PP_ASSERT_WITH_CODE(0 == result,
1983 "Failed to setup default DPM tables!", return result);
1985 if (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control)
1986 polaris10_populate_smc_voltage_tables(hwmgr, table);
1988 table->SystemFlags = 0;
1989 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1990 PHM_PlatformCaps_AutomaticDCTransition))
1991 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
1993 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1994 PHM_PlatformCaps_StepVddc))
1995 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
1997 if (data->is_memory_gddr5)
1998 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
2000 if (ulv->ulv_supported && table_info->us_ulv_voltage_offset) {
2001 result = polaris10_populate_ulv_state(hwmgr, table);
2002 PP_ASSERT_WITH_CODE(0 == result,
2003 "Failed to initialize ULV state!", return result);
2004 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2005 ixCG_ULV_PARAMETER, PPPOLARIS10_CGULVPARAMETER_DFLT);
2008 result = polaris10_populate_smc_link_level(hwmgr, table);
2009 PP_ASSERT_WITH_CODE(0 == result,
2010 "Failed to initialize Link Level!", return result);
2012 result = polaris10_populate_all_graphic_levels(hwmgr);
2013 PP_ASSERT_WITH_CODE(0 == result,
2014 "Failed to initialize Graphics Level!", return result);
2016 result = polaris10_populate_all_memory_levels(hwmgr);
2017 PP_ASSERT_WITH_CODE(0 == result,
2018 "Failed to initialize Memory Level!", return result);
2020 result = polaris10_populate_smc_acpi_level(hwmgr, table);
2021 PP_ASSERT_WITH_CODE(0 == result,
2022 "Failed to initialize ACPI Level!", return result);
2024 result = polaris10_populate_smc_vce_level(hwmgr, table);
2025 PP_ASSERT_WITH_CODE(0 == result,
2026 "Failed to initialize VCE Level!", return result);
2028 result = polaris10_populate_smc_samu_level(hwmgr, table);
2029 PP_ASSERT_WITH_CODE(0 == result,
2030 "Failed to initialize SAMU Level!", return result);
2032 /* Since only the initial state is completely set up at this point
2033 * (the other states are just copies of the boot state) we only
2034 * need to populate the ARB settings for the initial state.
2036 result = polaris10_program_memory_timing_parameters(hwmgr);
2037 PP_ASSERT_WITH_CODE(0 == result,
2038 "Failed to Write ARB settings for the initial state.", return result);
2040 result = polaris10_populate_smc_uvd_level(hwmgr, table);
2041 PP_ASSERT_WITH_CODE(0 == result,
2042 "Failed to initialize UVD Level!", return result);
2044 result = polaris10_populate_smc_boot_level(hwmgr, table);
2045 PP_ASSERT_WITH_CODE(0 == result,
2046 "Failed to initialize Boot Level!", return result);
2048 result = polaris10_populate_smc_initailial_state(hwmgr);
2049 PP_ASSERT_WITH_CODE(0 == result,
2050 "Failed to initialize Boot State!", return result);
2052 result = polaris10_populate_bapm_parameters_in_dpm_table(hwmgr);
2053 PP_ASSERT_WITH_CODE(0 == result,
2054 "Failed to populate BAPM Parameters!", return result);
2056 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2057 PHM_PlatformCaps_ClockStretcher)) {
2058 result = polaris10_populate_clock_stretcher_data_table(hwmgr);
2059 PP_ASSERT_WITH_CODE(0 == result,
2060 "Failed to populate Clock Stretcher Data Table!",
2064 result = polaris10_populate_avfs_parameters(hwmgr);
2065 PP_ASSERT_WITH_CODE(0 == result, "Failed to populate AVFS Parameters!", return result;);
2067 table->CurrSclkPllRange = 0xff;
2068 table->GraphicsVoltageChangeEnable = 1;
2069 table->GraphicsThermThrottleEnable = 1;
2070 table->GraphicsInterval = 1;
2071 table->VoltageInterval = 1;
2072 table->ThermalInterval = 1;
2073 table->TemperatureLimitHigh =
2074 table_info->cac_dtp_table->usTargetOperatingTemp *
2075 POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
2076 table->TemperatureLimitLow =
2077 (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
2078 POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
2079 table->MemoryVoltageChangeEnable = 1;
2080 table->MemoryInterval = 1;
2081 table->VoltageResponseTime = 0;
2082 table->PhaseResponseTime = 0;
2083 table->MemoryThermThrottleEnable = 1;
2084 table->PCIeBootLinkLevel = 0;
2085 table->PCIeGenInterval = 1;
2086 table->VRConfig = 0;
2088 result = polaris10_populate_vr_config(hwmgr, table);
2089 PP_ASSERT_WITH_CODE(0 == result,
2090 "Failed to populate VRConfig setting!", return result);
2092 table->ThermGpio = 17;
2093 table->SclkStepSize = 0x4000;
2095 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
2096 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
2098 table->VRHotGpio = POLARIS10_UNUSED_GPIO_PIN;
2099 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2100 PHM_PlatformCaps_RegulatorHot);
2103 if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
2105 table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
2106 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2107 PHM_PlatformCaps_AutomaticDCTransition);
2109 table->AcDcGpio = POLARIS10_UNUSED_GPIO_PIN;
2110 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2111 PHM_PlatformCaps_AutomaticDCTransition);
2114 /* Thermal Output GPIO */
2115 if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
2117 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2118 PHM_PlatformCaps_ThermalOutGPIO);
2120 table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
2122 /* For porlarity read GPIOPAD_A with assigned Gpio pin
2123 * since VBIOS will program this register to set 'inactive state',
2124 * driver can then determine 'active state' from this and
2125 * program SMU with correct polarity
2127 table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A)
2128 & (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
2129 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
2131 /* if required, combine VRHot/PCC with thermal out GPIO */
2132 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot)
2133 && phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CombinePCCWithThermalSignal))
2134 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
2136 table->ThermOutGpio = 17;
2137 table->ThermOutPolarity = 1;
2138 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
2141 /* Populate BIF_SCLK levels into SMC DPM table */
2142 for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++) {
2143 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, data->bif_sclk_table[i], ÷rs);
2144 PP_ASSERT_WITH_CODE((result == 0), "Can not find DFS divide id for Sclk", return result);
2147 table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2149 table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2152 for (i = 0; i < SMU74_MAX_ENTRIES_SMIO; i++)
2153 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
2155 CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2156 CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
2157 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
2158 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
2159 CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
2160 CONVERT_FROM_HOST_TO_SMC_UL(table->CurrSclkPllRange);
2161 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2162 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2163 CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2164 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2166 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2167 result = polaris10_copy_bytes_to_smc(hwmgr->smumgr,
2168 data->dpm_table_start +
2169 offsetof(SMU74_Discrete_DpmTable, SystemFlags),
2170 (uint8_t *)&(table->SystemFlags),
2171 sizeof(SMU74_Discrete_DpmTable) - 3 * sizeof(SMU74_PIDController),
2173 PP_ASSERT_WITH_CODE(0 == result,
2174 "Failed to upload dpm data to SMC memory!", return result);
2180 * Initialize the ARB DRAM timing table's index field.
2182 * @param hwmgr the address of the powerplay hardware manager.
2185 static int polaris10_init_arb_table_index(struct pp_hwmgr *hwmgr)
2187 const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2191 /* This is a read-modify-write on the first byte of the ARB table.
2192 * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
2193 * is the field 'current'.
2194 * This solution is ugly, but we never write the whole table only
2195 * individual fields in it.
2196 * In reality this field should not be in that structure
2197 * but in a soft register.
2199 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
2200 data->arb_table_start, &tmp, data->sram_end);
2206 tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
2208 return polaris10_write_smc_sram_dword(hwmgr->smumgr,
2209 data->arb_table_start, tmp, data->sram_end);
2212 static int polaris10_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
2214 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2215 PHM_PlatformCaps_RegulatorHot))
2216 return smum_send_msg_to_smc(hwmgr->smumgr,
2217 PPSMC_MSG_EnableVRHotGPIOInterrupt);
2222 static int polaris10_enable_sclk_control(struct pp_hwmgr *hwmgr)
2224 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2225 SCLK_PWRMGT_OFF, 0);
2229 static int polaris10_enable_ulv(struct pp_hwmgr *hwmgr)
2231 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2232 struct polaris10_ulv_parm *ulv = &(data->ulv);
2234 if (ulv->ulv_supported)
2235 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV);
2240 static int polaris10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2242 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2243 PHM_PlatformCaps_SclkDeepSleep)) {
2244 if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON))
2245 PP_ASSERT_WITH_CODE(false,
2246 "Attempt to enable Master Deep Sleep switch failed!",
2249 if (smum_send_msg_to_smc(hwmgr->smumgr,
2250 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
2251 PP_ASSERT_WITH_CODE(false,
2252 "Attempt to disable Master Deep Sleep switch failed!",
2260 static int polaris10_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
2262 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2263 uint32_t soft_register_value = 0;
2264 uint32_t handshake_disables_offset = data->soft_regs_start
2265 + offsetof(SMU74_SoftRegisters, HandshakeDisables);
2267 /* enable SCLK dpm */
2268 if (!data->sclk_dpm_key_disabled)
2269 PP_ASSERT_WITH_CODE(
2270 (0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)),
2271 "Failed to enable SCLK DPM during DPM Start Function!",
2274 /* enable MCLK dpm */
2275 if (0 == data->mclk_dpm_key_disabled) {
2276 /* Disable UVD - SMU handshake for MCLK. */
2277 soft_register_value = cgs_read_ind_register(hwmgr->device,
2278 CGS_IND_REG__SMC, handshake_disables_offset);
2279 soft_register_value |= SMU7_UVD_MCLK_HANDSHAKE_DISABLE;
2280 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2281 handshake_disables_offset, soft_register_value);
2283 PP_ASSERT_WITH_CODE(
2284 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2285 PPSMC_MSG_MCLKDPM_Enable)),
2286 "Failed to enable MCLK DPM during DPM Start Function!",
2289 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
2291 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
2292 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
2293 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005);
2295 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);
2296 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);
2297 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005);
2303 static int polaris10_start_dpm(struct pp_hwmgr *hwmgr)
2305 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2307 /*enable general power management */
2309 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2310 GLOBAL_PWRMGT_EN, 1);
2312 /* enable sclk deep sleep */
2314 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2317 /* prepare for PCIE DPM */
2319 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2320 data->soft_regs_start + offsetof(SMU74_SoftRegisters,
2321 VoltageChangeTimeout), 0x1000);
2322 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
2323 SWRST_COMMAND_1, RESETLC, 0x0);
2325 PP_ASSERT_WITH_CODE(
2326 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2327 PPSMC_MSG_Voltage_Cntl_Enable)),
2328 "Failed to enable voltage DPM during DPM Start Function!",
2332 if (polaris10_enable_sclk_mclk_dpm(hwmgr)) {
2333 printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!");
2337 /* enable PCIE dpm */
2338 if (0 == data->pcie_dpm_key_disabled) {
2339 PP_ASSERT_WITH_CODE(
2340 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2341 PPSMC_MSG_PCIeDPM_Enable)),
2342 "Failed to enable pcie DPM during DPM Start Function!",
2346 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2347 PHM_PlatformCaps_Falcon_QuickTransition)) {
2348 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr->smumgr,
2349 PPSMC_MSG_EnableACDCGPIOInterrupt)),
2350 "Failed to enable AC DC GPIO Interrupt!",
2357 static void polaris10_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources)
2360 enum DPM_EVENT_SRC src;
2364 printk(KERN_ERR "Unknown throttling event sources.");
2370 case (1 << PHM_AutoThrottleSource_Thermal):
2372 src = DPM_EVENT_SRC_DIGITAL;
2374 case (1 << PHM_AutoThrottleSource_External):
2376 src = DPM_EVENT_SRC_EXTERNAL;
2378 case (1 << PHM_AutoThrottleSource_External) |
2379 (1 << PHM_AutoThrottleSource_Thermal):
2381 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
2384 /* Order matters - don't enable thermal protection for the wrong source. */
2386 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
2387 DPM_EVENT_SRC, src);
2388 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2389 THERMAL_PROTECTION_DIS,
2390 !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2391 PHM_PlatformCaps_ThermalController));
2393 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2394 THERMAL_PROTECTION_DIS, 1);
2397 static int polaris10_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
2398 PHM_AutoThrottleSource source)
2400 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2402 if (!(data->active_auto_throttle_sources & (1 << source))) {
2403 data->active_auto_throttle_sources |= 1 << source;
2404 polaris10_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
2409 static int polaris10_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
2411 return polaris10_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
2414 int polaris10_pcie_performance_request(struct pp_hwmgr *hwmgr)
2416 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2417 data->pcie_performance_request = true;
2422 int polaris10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
2424 int tmp_result, result = 0;
2425 tmp_result = (!polaris10_is_dpm_running(hwmgr)) ? 0 : -1;
2426 PP_ASSERT_WITH_CODE(result == 0,
2427 "DPM is already running right now, no need to enable DPM!",
2430 if (polaris10_voltage_control(hwmgr)) {
2431 tmp_result = polaris10_enable_voltage_control(hwmgr);
2432 PP_ASSERT_WITH_CODE(tmp_result == 0,
2433 "Failed to enable voltage control!",
2434 result = tmp_result);
2436 tmp_result = polaris10_construct_voltage_tables(hwmgr);
2437 PP_ASSERT_WITH_CODE((0 == tmp_result),
2438 "Failed to contruct voltage tables!",
2439 result = tmp_result);
2442 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2443 PHM_PlatformCaps_EngineSpreadSpectrumSupport))
2444 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2445 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
2447 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2448 PHM_PlatformCaps_ThermalController))
2449 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2450 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
2452 tmp_result = polaris10_program_static_screen_threshold_parameters(hwmgr);
2453 PP_ASSERT_WITH_CODE((0 == tmp_result),
2454 "Failed to program static screen threshold parameters!",
2455 result = tmp_result);
2457 tmp_result = polaris10_enable_display_gap(hwmgr);
2458 PP_ASSERT_WITH_CODE((0 == tmp_result),
2459 "Failed to enable display gap!", result = tmp_result);
2461 tmp_result = polaris10_program_voting_clients(hwmgr);
2462 PP_ASSERT_WITH_CODE((0 == tmp_result),
2463 "Failed to program voting clients!", result = tmp_result);
2465 tmp_result = polaris10_process_firmware_header(hwmgr);
2466 PP_ASSERT_WITH_CODE((0 == tmp_result),
2467 "Failed to process firmware header!", result = tmp_result);
2469 tmp_result = polaris10_initial_switch_from_arbf0_to_f1(hwmgr);
2470 PP_ASSERT_WITH_CODE((0 == tmp_result),
2471 "Failed to initialize switch from ArbF0 to F1!",
2472 result = tmp_result);
2474 tmp_result = polaris10_init_smc_table(hwmgr);
2475 PP_ASSERT_WITH_CODE((0 == tmp_result),
2476 "Failed to initialize SMC table!", result = tmp_result);
2478 tmp_result = polaris10_init_arb_table_index(hwmgr);
2479 PP_ASSERT_WITH_CODE((0 == tmp_result),
2480 "Failed to initialize ARB table index!", result = tmp_result);
2482 tmp_result = polaris10_populate_pm_fuses(hwmgr);
2483 PP_ASSERT_WITH_CODE((0 == tmp_result),
2484 "Failed to populate PM fuses!", result = tmp_result);
2486 tmp_result = polaris10_enable_vrhot_gpio_interrupt(hwmgr);
2487 PP_ASSERT_WITH_CODE((0 == tmp_result),
2488 "Failed to enable VR hot GPIO interrupt!", result = tmp_result);
2490 tmp_result = polaris10_enable_sclk_control(hwmgr);
2491 PP_ASSERT_WITH_CODE((0 == tmp_result),
2492 "Failed to enable SCLK control!", result = tmp_result);
2494 tmp_result = polaris10_enable_smc_voltage_controller(hwmgr);
2495 PP_ASSERT_WITH_CODE((0 == tmp_result),
2496 "Failed to enable voltage control!", result = tmp_result);
2498 tmp_result = polaris10_enable_ulv(hwmgr);
2499 PP_ASSERT_WITH_CODE((0 == tmp_result),
2500 "Failed to enable ULV!", result = tmp_result);
2502 tmp_result = polaris10_enable_deep_sleep_master_switch(hwmgr);
2503 PP_ASSERT_WITH_CODE((0 == tmp_result),
2504 "Failed to enable deep sleep master switch!", result = tmp_result);
2506 tmp_result = polaris10_start_dpm(hwmgr);
2507 PP_ASSERT_WITH_CODE((0 == tmp_result),
2508 "Failed to start DPM!", result = tmp_result);
2510 tmp_result = polaris10_enable_smc_cac(hwmgr);
2511 PP_ASSERT_WITH_CODE((0 == tmp_result),
2512 "Failed to enable SMC CAC!", result = tmp_result);
2514 tmp_result = polaris10_enable_power_containment(hwmgr);
2515 PP_ASSERT_WITH_CODE((0 == tmp_result),
2516 "Failed to enable power containment!", result = tmp_result);
2518 tmp_result = polaris10_power_control_set_level(hwmgr);
2519 PP_ASSERT_WITH_CODE((0 == tmp_result),
2520 "Failed to power control set level!", result = tmp_result);
2522 tmp_result = polaris10_enable_thermal_auto_throttle(hwmgr);
2523 PP_ASSERT_WITH_CODE((0 == tmp_result),
2524 "Failed to enable thermal auto throttle!", result = tmp_result);
2526 tmp_result = polaris10_pcie_performance_request(hwmgr);
2527 PP_ASSERT_WITH_CODE((0 == tmp_result),
2528 "pcie performance request failed!", result = tmp_result);
2533 int polaris10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
2539 int polaris10_reset_asic_tasks(struct pp_hwmgr *hwmgr)
2545 int polaris10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
2547 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2549 if (data->soft_pp_table) {
2550 kfree(data->soft_pp_table);
2551 data->soft_pp_table = NULL;
2554 return phm_hwmgr_backend_fini(hwmgr);
2557 int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
2559 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2561 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2562 PHM_PlatformCaps_SclkDeepSleep);
2564 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2565 PHM_PlatformCaps_DynamicPatchPowerState);
2567 if (data->mvdd_control == POLARIS10_VOLTAGE_CONTROL_NONE)
2568 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2569 PHM_PlatformCaps_EnableMVDDControl);
2571 if (data->vddci_control == POLARIS10_VOLTAGE_CONTROL_NONE)
2572 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2573 PHM_PlatformCaps_ControlVDDCI);
2575 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2576 PHM_PlatformCaps_TablelessHardwareInterface);
2578 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2579 PHM_PlatformCaps_EnableSMU7ThermalManagement);
2581 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2582 PHM_PlatformCaps_DynamicPowerManagement);
2584 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2585 PHM_PlatformCaps_UnTabledHardwareInterface);
2587 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2588 PHM_PlatformCaps_TablelessHardwareInterface);
2590 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2591 PHM_PlatformCaps_SMC);
2593 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2594 PHM_PlatformCaps_NonABMSupportInPPLib);
2596 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2597 PHM_PlatformCaps_DynamicUVDState);
2599 /* power tune caps Assume disabled */
2600 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2601 PHM_PlatformCaps_SQRamping);
2602 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2603 PHM_PlatformCaps_DBRamping);
2604 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2605 PHM_PlatformCaps_TDRamping);
2606 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2607 PHM_PlatformCaps_TCPRamping);
2609 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2610 PHM_PlatformCaps_PowerContainment);
2611 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2612 PHM_PlatformCaps_CAC);
2614 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2615 PHM_PlatformCaps_RegulatorHot);
2617 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2618 PHM_PlatformCaps_AutomaticDCTransition);
2620 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2621 PHM_PlatformCaps_ODFuzzyFanControlSupport);
2623 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2624 PHM_PlatformCaps_FanSpeedInTableIsRPM);
2626 if (hwmgr->chip_id == CHIP_POLARIS11)
2627 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2628 PHM_PlatformCaps_SPLLShutdownSupport);
2632 static void polaris10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
2634 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2636 polaris10_initialize_power_tune_defaults(hwmgr);
2638 data->pcie_gen_performance.max = PP_PCIEGen1;
2639 data->pcie_gen_performance.min = PP_PCIEGen3;
2640 data->pcie_gen_power_saving.max = PP_PCIEGen1;
2641 data->pcie_gen_power_saving.min = PP_PCIEGen3;
2642 data->pcie_lane_performance.max = 0;
2643 data->pcie_lane_performance.min = 16;
2644 data->pcie_lane_power_saving.max = 0;
2645 data->pcie_lane_power_saving.min = 16;
2649 * Get Leakage VDDC based on leakage ID.
2651 * @param hwmgr the address of the powerplay hardware manager.
2654 static int polaris10_get_evv_voltages(struct pp_hwmgr *hwmgr)
2656 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2661 struct phm_ppt_v1_information *table_info =
2662 (struct phm_ppt_v1_information *)hwmgr->pptable;
2663 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2664 table_info->vdd_dep_on_sclk;
2667 for (i = 0; i < POLARIS10_MAX_LEAKAGE_COUNT; i++) {
2668 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
2669 if (!phm_get_sclk_for_voltage_evv(hwmgr,
2670 table_info->vddc_lookup_table, vv_id, &sclk)) {
2671 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2672 PHM_PlatformCaps_ClockStretcher)) {
2673 for (j = 1; j < sclk_table->count; j++) {
2674 if (sclk_table->entries[j].clk == sclk &&
2675 sclk_table->entries[j].cks_enable == 0) {
2683 PP_ASSERT_WITH_CODE(0 == atomctrl_get_voltage_evv_on_sclk_ai(hwmgr,
2684 VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc),
2685 "Error retrieving EVV voltage value!",
2689 /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
2690 PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0),
2691 "Invalid VDDC value", result = -EINVAL;);
2693 /* the voltage should not be zero nor equal to leakage ID */
2694 if (vddc != 0 && vddc != vv_id) {
2695 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc/100);
2696 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
2697 data->vddc_leakage.count++;
2706 * Change virtual leakage voltage to actual value.
2708 * @param hwmgr the address of the powerplay hardware manager.
2709 * @param pointer to changing voltage
2710 * @param pointer to leakage table
2712 static void polaris10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
2713 uint16_t *voltage, struct polaris10_leakage_voltage *leakage_table)
2717 /* search for leakage voltage ID 0xff01 ~ 0xff08 */
2718 for (index = 0; index < leakage_table->count; index++) {
2719 /* if this voltage matches a leakage voltage ID */
2720 /* patch with actual leakage voltage */
2721 if (leakage_table->leakage_id[index] == *voltage) {
2722 *voltage = leakage_table->actual_voltage[index];
2727 if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
2728 printk(KERN_ERR "Voltage value looks like a Leakage ID but it's not patched \n");
2732 * Patch voltage lookup table by EVV leakages.
2734 * @param hwmgr the address of the powerplay hardware manager.
2735 * @param pointer to voltage lookup table
2736 * @param pointer to leakage table
2739 static int polaris10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
2740 phm_ppt_v1_voltage_lookup_table *lookup_table,
2741 struct polaris10_leakage_voltage *leakage_table)
2745 for (i = 0; i < lookup_table->count; i++)
2746 polaris10_patch_with_vdd_leakage(hwmgr,
2747 &lookup_table->entries[i].us_vdd, leakage_table);
2752 static int polaris10_patch_clock_voltage_limits_with_vddc_leakage(
2753 struct pp_hwmgr *hwmgr, struct polaris10_leakage_voltage *leakage_table,
2756 struct phm_ppt_v1_information *table_info =
2757 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2758 polaris10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
2759 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
2760 table_info->max_clock_voltage_on_dc.vddc;
2764 static int polaris10_patch_voltage_dependency_tables_with_lookup_table(
2765 struct pp_hwmgr *hwmgr)
2769 struct phm_ppt_v1_information *table_info =
2770 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2772 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2773 table_info->vdd_dep_on_sclk;
2774 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
2775 table_info->vdd_dep_on_mclk;
2776 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2777 table_info->mm_dep_table;
2779 for (entryId = 0; entryId < sclk_table->count; ++entryId) {
2780 voltageId = sclk_table->entries[entryId].vddInd;
2781 sclk_table->entries[entryId].vddc =
2782 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2785 for (entryId = 0; entryId < mclk_table->count; ++entryId) {
2786 voltageId = mclk_table->entries[entryId].vddInd;
2787 mclk_table->entries[entryId].vddc =
2788 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2791 for (entryId = 0; entryId < mm_table->count; ++entryId) {
2792 voltageId = mm_table->entries[entryId].vddcInd;
2793 mm_table->entries[entryId].vddc =
2794 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2801 static int polaris10_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
2803 /* Need to determine if we need calculated voltage. */
2807 static int polaris10_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
2809 /* Need to determine if we need calculated voltage from mm table. */
2813 static int polaris10_sort_lookup_table(struct pp_hwmgr *hwmgr,
2814 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
2816 uint32_t table_size, i, j;
2817 struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
2818 table_size = lookup_table->count;
2820 PP_ASSERT_WITH_CODE(0 != lookup_table->count,
2821 "Lookup table is empty", return -EINVAL);
2823 /* Sorting voltages */
2824 for (i = 0; i < table_size - 1; i++) {
2825 for (j = i + 1; j > 0; j--) {
2826 if (lookup_table->entries[j].us_vdd <
2827 lookup_table->entries[j - 1].us_vdd) {
2828 tmp_voltage_lookup_record = lookup_table->entries[j - 1];
2829 lookup_table->entries[j - 1] = lookup_table->entries[j];
2830 lookup_table->entries[j] = tmp_voltage_lookup_record;
2838 static int polaris10_complete_dependency_tables(struct pp_hwmgr *hwmgr)
2842 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2843 struct phm_ppt_v1_information *table_info =
2844 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2846 tmp_result = polaris10_patch_lookup_table_with_leakage(hwmgr,
2847 table_info->vddc_lookup_table, &(data->vddc_leakage));
2849 result = tmp_result;
2851 tmp_result = polaris10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
2852 &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
2854 result = tmp_result;
2856 tmp_result = polaris10_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
2858 result = tmp_result;
2860 tmp_result = polaris10_calc_voltage_dependency_tables(hwmgr);
2862 result = tmp_result;
2864 tmp_result = polaris10_calc_mm_voltage_dependency_table(hwmgr);
2866 result = tmp_result;
2868 tmp_result = polaris10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
2870 result = tmp_result;
2875 static int polaris10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
2877 struct phm_ppt_v1_information *table_info =
2878 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2880 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
2881 table_info->vdd_dep_on_sclk;
2882 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
2883 table_info->vdd_dep_on_mclk;
2885 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
2886 "VDD dependency on SCLK table is missing. \
2887 This table is mandatory", return -EINVAL);
2888 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
2889 "VDD dependency on SCLK table has to have is missing. \
2890 This table is mandatory", return -EINVAL);
2892 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
2893 "VDD dependency on MCLK table is missing. \
2894 This table is mandatory", return -EINVAL);
2895 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
2896 "VDD dependency on MCLK table has to have is missing. \
2897 This table is mandatory", return -EINVAL);
2899 table_info->max_clock_voltage_on_ac.sclk =
2900 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
2901 table_info->max_clock_voltage_on_ac.mclk =
2902 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
2903 table_info->max_clock_voltage_on_ac.vddc =
2904 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
2905 table_info->max_clock_voltage_on_ac.vddci =
2906 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
2908 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk;
2909 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = table_info->max_clock_voltage_on_ac.mclk;
2910 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = table_info->max_clock_voltage_on_ac.vddc;
2911 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =table_info->max_clock_voltage_on_ac.vddci;
2916 int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
2918 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2919 struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
2922 struct phm_ppt_v1_information *table_info =
2923 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2925 data->dll_default_on = false;
2926 data->sram_end = SMC_RAM_END;
2927 data->mclk_dpm0_activity_target = 0xa;
2928 data->disable_dpm_mask = 0xFF;
2929 data->static_screen_threshold = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
2930 data->static_screen_threshold_unit = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
2931 data->activity_target[0] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2932 data->activity_target[1] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2933 data->activity_target[2] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2934 data->activity_target[3] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2935 data->activity_target[4] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2936 data->activity_target[5] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2937 data->activity_target[6] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2938 data->activity_target[7] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2940 data->voting_rights_clients0 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT0;
2941 data->voting_rights_clients1 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT1;
2942 data->voting_rights_clients2 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT2;
2943 data->voting_rights_clients3 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT3;
2944 data->voting_rights_clients4 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT4;
2945 data->voting_rights_clients5 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT5;
2946 data->voting_rights_clients6 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT6;
2947 data->voting_rights_clients7 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT7;
2949 data->vddc_vddci_delta = VDDC_VDDCI_DELTA;
2951 data->mclk_activity_target = PPPOLARIS10_MCLK_TARGETACTIVITY_DFLT;
2953 /* need to set voltage control types before EVV patching */
2954 data->voltage_control = POLARIS10_VOLTAGE_CONTROL_NONE;
2955 data->vddci_control = POLARIS10_VOLTAGE_CONTROL_NONE;
2956 data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_NONE;
2958 data->enable_tdc_limit_feature = true;
2959 data->enable_pkg_pwr_tracking_feature = true;
2960 data->force_pcie_gen = PP_PCIEGenInvalid;
2961 data->mclk_stutter_mode_threshold = 40000;
2963 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2964 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
2965 data->voltage_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
2967 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2968 PHM_PlatformCaps_EnableMVDDControl)) {
2969 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2970 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
2971 data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
2972 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2973 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
2974 data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
2977 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2978 PHM_PlatformCaps_ControlVDDCI)) {
2979 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2980 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
2981 data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
2982 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2983 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
2984 data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
2987 if (table_info->cac_dtp_table->usClockStretchAmount != 0)
2988 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2989 PHM_PlatformCaps_ClockStretcher);
2991 polaris10_set_features_platform_caps(hwmgr);
2993 polaris10_init_dpm_defaults(hwmgr);
2995 /* Get leakage voltage based on leakage ID. */
2996 result = polaris10_get_evv_voltages(hwmgr);
2999 printk("Get EVV Voltage Failed. Abort Driver loading!\n");
3003 polaris10_complete_dependency_tables(hwmgr);
3004 polaris10_set_private_data_based_on_pptable(hwmgr);
3006 /* Initalize Dynamic State Adjustment Rule Settings */
3007 result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
3010 struct cgs_system_info sys_info = {0};
3012 data->is_tlu_enabled = 0;
3014 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
3015 POLARIS10_MAX_HARDWARE_POWERLEVELS;
3016 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
3017 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
3020 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
3021 temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
3022 switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
3024 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
3027 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
3030 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
3033 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
3036 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
3039 PP_ASSERT_WITH_CODE(0,
3040 "Failed to setup PCC HW register! Wrong GPIO assigned for VDDC_PCC_GPIO_PINID!",
3044 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg);
3047 if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp != 0 &&
3048 hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode) {
3049 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit =
3050 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
3052 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMaxLimit =
3053 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
3055 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMStep = 1;
3057 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 100;
3059 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMinLimit =
3060 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
3062 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMStep = 1;
3064 table_info->cac_dtp_table->usDefaultTargetOperatingTemp = (table_info->cac_dtp_table->usDefaultTargetOperatingTemp >= 50) ?
3065 (table_info->cac_dtp_table->usDefaultTargetOperatingTemp -50) : 0;
3067 table_info->cac_dtp_table->usOperatingTempMaxLimit = table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
3068 table_info->cac_dtp_table->usOperatingTempStep = 1;
3069 table_info->cac_dtp_table->usOperatingTempHyst = 1;
3071 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM =
3072 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
3074 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
3075 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM;
3077 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit =
3078 table_info->cac_dtp_table->usOperatingTempMinLimit;
3080 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit =
3081 table_info->cac_dtp_table->usOperatingTempMaxLimit;
3083 hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
3084 table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
3086 hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep =
3087 table_info->cac_dtp_table->usOperatingTempStep;
3089 hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp =
3090 table_info->cac_dtp_table->usTargetOperatingTemp;
3093 sys_info.size = sizeof(struct cgs_system_info);
3094 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
3095 result = cgs_query_system_info(hwmgr->device, &sys_info);
3097 data->pcie_gen_cap = 0x30007;
3099 data->pcie_gen_cap = (uint32_t)sys_info.value;
3100 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
3101 data->pcie_spc_cap = 20;
3102 sys_info.size = sizeof(struct cgs_system_info);
3103 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
3104 result = cgs_query_system_info(hwmgr->device, &sys_info);
3106 data->pcie_lane_cap = 0x2f0000;
3108 data->pcie_lane_cap = (uint32_t)sys_info.value;
3110 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
3111 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
3112 hwmgr->platform_descriptor.clockStep.engineClock = 500;
3113 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
3115 /* Ignore return value in here, we are cleaning up a mess. */
3116 polaris10_hwmgr_backend_fini(hwmgr);
3122 static int polaris10_force_dpm_highest(struct pp_hwmgr *hwmgr)
3124 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3125 uint32_t level, tmp;
3127 if (!data->pcie_dpm_key_disabled) {
3128 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3130 tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
3135 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3136 PPSMC_MSG_PCIeDPM_ForceLevel, level);
3140 if (!data->sclk_dpm_key_disabled) {
3141 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3143 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
3148 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3149 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3154 if (!data->mclk_dpm_key_disabled) {
3155 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3157 tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
3162 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3163 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3171 static int polaris10_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
3173 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3175 phm_apply_dal_min_voltage_request(hwmgr);
3177 if (!data->sclk_dpm_key_disabled) {
3178 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
3179 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3180 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3181 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3184 if (!data->mclk_dpm_key_disabled) {
3185 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask)
3186 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3187 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3188 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3194 static int polaris10_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
3196 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3198 if (!polaris10_is_dpm_running(hwmgr))
3201 if (!data->pcie_dpm_key_disabled) {
3202 smum_send_msg_to_smc(hwmgr->smumgr,
3203 PPSMC_MSG_PCIeDPM_UnForceLevel);
3206 return polaris10_upload_dpm_level_enable_mask(hwmgr);
3209 static int polaris10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
3211 struct polaris10_hwmgr *data =
3212 (struct polaris10_hwmgr *)(hwmgr->backend);
3215 if (!data->sclk_dpm_key_disabled)
3216 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3217 level = phm_get_lowest_enabled_level(hwmgr,
3218 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3219 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3220 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3225 if (!data->mclk_dpm_key_disabled) {
3226 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3227 level = phm_get_lowest_enabled_level(hwmgr,
3228 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3229 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3230 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3235 if (!data->pcie_dpm_key_disabled) {
3236 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3237 level = phm_get_lowest_enabled_level(hwmgr,
3238 data->dpm_level_enable_mask.pcie_dpm_enable_mask);
3239 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3240 PPSMC_MSG_PCIeDPM_ForceLevel,
3248 static int polaris10_force_dpm_level(struct pp_hwmgr *hwmgr,
3249 enum amd_dpm_forced_level level)
3254 case AMD_DPM_FORCED_LEVEL_HIGH:
3255 ret = polaris10_force_dpm_highest(hwmgr);
3259 case AMD_DPM_FORCED_LEVEL_LOW:
3260 ret = polaris10_force_dpm_lowest(hwmgr);
3264 case AMD_DPM_FORCED_LEVEL_AUTO:
3265 ret = polaris10_unforce_dpm_levels(hwmgr);
3273 hwmgr->dpm_level = level;
3278 static int polaris10_get_power_state_size(struct pp_hwmgr *hwmgr)
3280 return sizeof(struct polaris10_power_state);
3284 static int polaris10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
3285 struct pp_power_state *request_ps,
3286 const struct pp_power_state *current_ps)
3289 struct polaris10_power_state *polaris10_ps =
3290 cast_phw_polaris10_power_state(&request_ps->hardware);
3293 struct PP_Clocks minimum_clocks = {0};
3294 bool disable_mclk_switching;
3295 bool disable_mclk_switching_for_frame_lock;
3296 struct cgs_display_info info = {0};
3297 const struct phm_clock_and_voltage_limits *max_limits;
3299 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3300 struct phm_ppt_v1_information *table_info =
3301 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3303 int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
3305 data->battery_state = (PP_StateUILabel_Battery ==
3306 request_ps->classification.ui_label);
3308 PP_ASSERT_WITH_CODE(polaris10_ps->performance_level_count == 2,
3309 "VI should always have 2 performance levels",
3312 max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
3313 &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
3314 &(hwmgr->dyn_state.max_clock_voltage_on_dc);
3316 /* Cap clock DPM tables at DC MAX if it is in DC. */
3317 if (PP_PowerSource_DC == hwmgr->power_source) {
3318 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3319 if (polaris10_ps->performance_levels[i].memory_clock > max_limits->mclk)
3320 polaris10_ps->performance_levels[i].memory_clock = max_limits->mclk;
3321 if (polaris10_ps->performance_levels[i].engine_clock > max_limits->sclk)
3322 polaris10_ps->performance_levels[i].engine_clock = max_limits->sclk;
3326 polaris10_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk;
3327 polaris10_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;
3329 cgs_get_active_displays_info(hwmgr->device, &info);
3331 /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
3333 /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
3335 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3336 PHM_PlatformCaps_StablePState)) {
3337 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
3338 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
3340 for (count = table_info->vdd_dep_on_sclk->count - 1;
3341 count >= 0; count--) {
3342 if (stable_pstate_sclk >=
3343 table_info->vdd_dep_on_sclk->entries[count].clk) {
3344 stable_pstate_sclk =
3345 table_info->vdd_dep_on_sclk->entries[count].clk;
3351 stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3353 stable_pstate_mclk = max_limits->mclk;
3355 minimum_clocks.engineClock = stable_pstate_sclk;
3356 minimum_clocks.memoryClock = stable_pstate_mclk;
3359 if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
3360 minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
3362 if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
3363 minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
3365 polaris10_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
3367 if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
3368 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <=
3369 hwmgr->platform_descriptor.overdriveLimit.engineClock),
3370 "Overdrive sclk exceeds limit",
3371 hwmgr->gfx_arbiter.sclk_over_drive =
3372 hwmgr->platform_descriptor.overdriveLimit.engineClock);
3374 if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
3375 polaris10_ps->performance_levels[1].engine_clock =
3376 hwmgr->gfx_arbiter.sclk_over_drive;
3379 if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
3380 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <=
3381 hwmgr->platform_descriptor.overdriveLimit.memoryClock),
3382 "Overdrive mclk exceeds limit",
3383 hwmgr->gfx_arbiter.mclk_over_drive =
3384 hwmgr->platform_descriptor.overdriveLimit.memoryClock);
3386 if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
3387 polaris10_ps->performance_levels[1].memory_clock =
3388 hwmgr->gfx_arbiter.mclk_over_drive;
3391 disable_mclk_switching_for_frame_lock = phm_cap_enabled(
3392 hwmgr->platform_descriptor.platformCaps,
3393 PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
3395 disable_mclk_switching = (1 < info.display_count) ||
3396 disable_mclk_switching_for_frame_lock;
3398 sclk = polaris10_ps->performance_levels[0].engine_clock;
3399 mclk = polaris10_ps->performance_levels[0].memory_clock;
3401 if (disable_mclk_switching)
3402 mclk = polaris10_ps->performance_levels
3403 [polaris10_ps->performance_level_count - 1].memory_clock;
3405 if (sclk < minimum_clocks.engineClock)
3406 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
3407 max_limits->sclk : minimum_clocks.engineClock;
3409 if (mclk < minimum_clocks.memoryClock)
3410 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
3411 max_limits->mclk : minimum_clocks.memoryClock;
3413 polaris10_ps->performance_levels[0].engine_clock = sclk;
3414 polaris10_ps->performance_levels[0].memory_clock = mclk;
3416 polaris10_ps->performance_levels[1].engine_clock =
3417 (polaris10_ps->performance_levels[1].engine_clock >=
3418 polaris10_ps->performance_levels[0].engine_clock) ?
3419 polaris10_ps->performance_levels[1].engine_clock :
3420 polaris10_ps->performance_levels[0].engine_clock;
3422 if (disable_mclk_switching) {
3423 if (mclk < polaris10_ps->performance_levels[1].memory_clock)
3424 mclk = polaris10_ps->performance_levels[1].memory_clock;
3426 polaris10_ps->performance_levels[0].memory_clock = mclk;
3427 polaris10_ps->performance_levels[1].memory_clock = mclk;
3429 if (polaris10_ps->performance_levels[1].memory_clock <
3430 polaris10_ps->performance_levels[0].memory_clock)
3431 polaris10_ps->performance_levels[1].memory_clock =
3432 polaris10_ps->performance_levels[0].memory_clock;
3435 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3436 PHM_PlatformCaps_StablePState)) {
3437 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3438 polaris10_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
3439 polaris10_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
3440 polaris10_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
3441 polaris10_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
3448 static int polaris10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
3450 struct pp_power_state *ps;
3451 struct polaris10_power_state *polaris10_ps;
3456 ps = hwmgr->request_ps;
3461 polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
3464 return polaris10_ps->performance_levels[0].memory_clock;
3466 return polaris10_ps->performance_levels
3467 [polaris10_ps->performance_level_count-1].memory_clock;
3470 static int polaris10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
3472 struct pp_power_state *ps;
3473 struct polaris10_power_state *polaris10_ps;
3478 ps = hwmgr->request_ps;
3483 polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
3486 return polaris10_ps->performance_levels[0].engine_clock;
3488 return polaris10_ps->performance_levels
3489 [polaris10_ps->performance_level_count-1].engine_clock;
3492 static int polaris10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
3493 struct pp_hw_power_state *hw_ps)
3495 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3496 struct polaris10_power_state *ps = (struct polaris10_power_state *)hw_ps;
3497 ATOM_FIRMWARE_INFO_V2_2 *fw_info;
3500 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
3502 /* First retrieve the Boot clocks and VDDC from the firmware info table.
3503 * We assume here that fw_info is unchanged if this call fails.
3505 fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
3506 hwmgr->device, index,
3507 &size, &frev, &crev);
3509 /* During a test, there is no firmware info table. */
3512 /* Patch the state. */
3513 data->vbios_boot_state.sclk_bootup_value =
3514 le32_to_cpu(fw_info->ulDefaultEngineClock);
3515 data->vbios_boot_state.mclk_bootup_value =
3516 le32_to_cpu(fw_info->ulDefaultMemoryClock);
3517 data->vbios_boot_state.mvdd_bootup_value =
3518 le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
3519 data->vbios_boot_state.vddc_bootup_value =
3520 le16_to_cpu(fw_info->usBootUpVDDCVoltage);
3521 data->vbios_boot_state.vddci_bootup_value =
3522 le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
3523 data->vbios_boot_state.pcie_gen_bootup_value =
3524 phm_get_current_pcie_speed(hwmgr);
3526 data->vbios_boot_state.pcie_lane_bootup_value =
3527 (uint16_t)phm_get_current_pcie_lane_number(hwmgr);
3529 /* set boot power state */
3530 ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
3531 ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
3532 ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
3533 ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
3538 static int polaris10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
3539 void *state, struct pp_power_state *power_state,
3540 void *pp_table, uint32_t classification_flag)
3542 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3543 struct polaris10_power_state *polaris10_power_state =
3544 (struct polaris10_power_state *)(&(power_state->hardware));
3545 struct polaris10_performance_level *performance_level;
3546 ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
3547 ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
3548 (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
3549 PPTable_Generic_SubTable_Header *sclk_dep_table =
3550 (PPTable_Generic_SubTable_Header *)
3551 (((unsigned long)powerplay_table) +
3552 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
3554 ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
3555 (ATOM_Tonga_MCLK_Dependency_Table *)
3556 (((unsigned long)powerplay_table) +
3557 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
3559 /* The following fields are not initialized here: id orderedList allStatesList */
3560 power_state->classification.ui_label =
3561 (le16_to_cpu(state_entry->usClassification) &
3562 ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
3563 ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
3564 power_state->classification.flags = classification_flag;
3565 /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
3567 power_state->classification.temporary_state = false;
3568 power_state->classification.to_be_deleted = false;
3570 power_state->validation.disallowOnDC =
3571 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3572 ATOM_Tonga_DISALLOW_ON_DC));
3574 power_state->pcie.lanes = 0;
3576 power_state->display.disableFrameModulation = false;
3577 power_state->display.limitRefreshrate = false;
3578 power_state->display.enableVariBright =
3579 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3580 ATOM_Tonga_ENABLE_VARIBRIGHT));
3582 power_state->validation.supportedPowerLevels = 0;
3583 power_state->uvd_clocks.VCLK = 0;
3584 power_state->uvd_clocks.DCLK = 0;
3585 power_state->temperatures.min = 0;
3586 power_state->temperatures.max = 0;
3588 performance_level = &(polaris10_power_state->performance_levels
3589 [polaris10_power_state->performance_level_count++]);
3591 PP_ASSERT_WITH_CODE(
3592 (polaris10_power_state->performance_level_count < SMU74_MAX_LEVELS_GRAPHICS),
3593 "Performance levels exceeds SMC limit!",
3596 PP_ASSERT_WITH_CODE(
3597 (polaris10_power_state->performance_level_count <=
3598 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3599 "Performance levels exceeds Driver limit!",
3602 /* Performance levels are arranged from low to high. */
3603 performance_level->memory_clock = mclk_dep_table->entries
3604 [state_entry->ucMemoryClockIndexLow].ulMclk;
3605 if (sclk_dep_table->ucRevId == 0)
3606 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3607 [state_entry->ucEngineClockIndexLow].ulSclk;
3608 else if (sclk_dep_table->ucRevId == 1)
3609 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3610 [state_entry->ucEngineClockIndexLow].ulSclk;
3611 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3612 state_entry->ucPCIEGenLow);
3613 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3614 state_entry->ucPCIELaneHigh);
3616 performance_level = &(polaris10_power_state->performance_levels
3617 [polaris10_power_state->performance_level_count++]);
3618 performance_level->memory_clock = mclk_dep_table->entries
3619 [state_entry->ucMemoryClockIndexHigh].ulMclk;
3621 if (sclk_dep_table->ucRevId == 0)
3622 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3623 [state_entry->ucEngineClockIndexHigh].ulSclk;
3624 else if (sclk_dep_table->ucRevId == 1)
3625 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3626 [state_entry->ucEngineClockIndexHigh].ulSclk;
3628 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3629 state_entry->ucPCIEGenHigh);
3630 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3631 state_entry->ucPCIELaneHigh);
3636 static int polaris10_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3637 unsigned long entry_index, struct pp_power_state *state)
3640 struct polaris10_power_state *ps;
3641 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3642 struct phm_ppt_v1_information *table_info =
3643 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3644 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
3645 table_info->vdd_dep_on_mclk;
3647 state->hardware.magic = PHM_VIslands_Magic;
3649 ps = (struct polaris10_power_state *)(&state->hardware);
3651 result = tonga_get_powerplay_table_entry(hwmgr, entry_index, state,
3652 polaris10_get_pp_table_entry_callback_func);
3654 /* This is the earliest time we have all the dependency table and the VBIOS boot state
3655 * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
3656 * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
3658 if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3659 if (dep_mclk_table->entries[0].clk !=
3660 data->vbios_boot_state.mclk_bootup_value)
3661 printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
3662 "does not match VBIOS boot MCLK level");
3663 if (dep_mclk_table->entries[0].vddci !=
3664 data->vbios_boot_state.vddci_bootup_value)
3665 printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
3666 "does not match VBIOS boot VDDCI level");
3669 /* set DC compatible flag if this state supports DC */
3670 if (!state->validation.disallowOnDC)
3671 ps->dc_compatible = true;
3673 if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3674 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3676 ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3677 ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3682 switch (state->classification.ui_label) {
3683 case PP_StateUILabel_Performance:
3684 data->use_pcie_performance_levels = true;
3685 for (i = 0; i < ps->performance_level_count; i++) {
3686 if (data->pcie_gen_performance.max <
3687 ps->performance_levels[i].pcie_gen)
3688 data->pcie_gen_performance.max =
3689 ps->performance_levels[i].pcie_gen;
3691 if (data->pcie_gen_performance.min >
3692 ps->performance_levels[i].pcie_gen)
3693 data->pcie_gen_performance.min =
3694 ps->performance_levels[i].pcie_gen;
3696 if (data->pcie_lane_performance.max <
3697 ps->performance_levels[i].pcie_lane)
3698 data->pcie_lane_performance.max =
3699 ps->performance_levels[i].pcie_lane;
3700 if (data->pcie_lane_performance.min >
3701 ps->performance_levels[i].pcie_lane)
3702 data->pcie_lane_performance.min =
3703 ps->performance_levels[i].pcie_lane;
3706 case PP_StateUILabel_Battery:
3707 data->use_pcie_power_saving_levels = true;
3709 for (i = 0; i < ps->performance_level_count; i++) {
3710 if (data->pcie_gen_power_saving.max <
3711 ps->performance_levels[i].pcie_gen)
3712 data->pcie_gen_power_saving.max =
3713 ps->performance_levels[i].pcie_gen;
3715 if (data->pcie_gen_power_saving.min >
3716 ps->performance_levels[i].pcie_gen)
3717 data->pcie_gen_power_saving.min =
3718 ps->performance_levels[i].pcie_gen;
3720 if (data->pcie_lane_power_saving.max <
3721 ps->performance_levels[i].pcie_lane)
3722 data->pcie_lane_power_saving.max =
3723 ps->performance_levels[i].pcie_lane;
3725 if (data->pcie_lane_power_saving.min >
3726 ps->performance_levels[i].pcie_lane)
3727 data->pcie_lane_power_saving.min =
3728 ps->performance_levels[i].pcie_lane;
3739 polaris10_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
3741 uint32_t sclk, mclk, activity_percent;
3743 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3745 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
3747 sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3749 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
3751 mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3752 seq_printf(m, "\n [ mclk ]: %u MHz\n\n [ sclk ]: %u MHz\n",
3753 mclk / 100, sclk / 100);
3755 offset = data->soft_regs_start + offsetof(SMU74_SoftRegisters, AverageGraphicsActivity);
3756 activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
3757 activity_percent += 0x80;
3758 activity_percent >>= 8;
3760 seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);
3762 seq_printf(m, "uvd %sabled\n", data->uvd_power_gated ? "dis" : "en");
3764 seq_printf(m, "vce %sabled\n", data->vce_power_gated ? "dis" : "en");
3767 static int polaris10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
3769 const struct phm_set_power_state_input *states =
3770 (const struct phm_set_power_state_input *)input;
3771 const struct polaris10_power_state *polaris10_ps =
3772 cast_const_phw_polaris10_power_state(states->pnew_state);
3773 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3774 struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
3775 uint32_t sclk = polaris10_ps->performance_levels
3776 [polaris10_ps->performance_level_count - 1].engine_clock;
3777 struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
3778 uint32_t mclk = polaris10_ps->performance_levels
3779 [polaris10_ps->performance_level_count - 1].memory_clock;
3780 struct PP_Clocks min_clocks = {0};
3782 struct cgs_display_info info = {0};
3784 data->need_update_smu7_dpm_table = 0;
3786 for (i = 0; i < sclk_table->count; i++) {
3787 if (sclk == sclk_table->dpm_levels[i].value)
3791 if (i >= sclk_table->count)
3792 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3794 /* TODO: Check SCLK in DAL's minimum clocks
3795 * in case DeepSleep divider update is required.
3797 if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR &&
3798 (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
3799 data->display_timing.min_clock_in_sr >= POLARIS10_MINIMUM_ENGINE_CLOCK))
3800 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3803 for (i = 0; i < mclk_table->count; i++) {
3804 if (mclk == mclk_table->dpm_levels[i].value)
3808 if (i >= mclk_table->count)
3809 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3811 cgs_get_active_displays_info(hwmgr->device, &info);
3813 if (data->display_timing.num_existing_displays != info.display_count)
3814 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
3819 static uint16_t polaris10_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
3820 const struct polaris10_power_state *polaris10_ps)
3823 uint32_t sclk, max_sclk = 0;
3824 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3825 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
3827 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3828 sclk = polaris10_ps->performance_levels[i].engine_clock;
3829 if (max_sclk < sclk)
3833 for (i = 0; i < dpm_table->sclk_table.count; i++) {
3834 if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk)
3835 return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ?
3836 dpm_table->pcie_speed_table.dpm_levels
3837 [dpm_table->pcie_speed_table.count - 1].value :
3838 dpm_table->pcie_speed_table.dpm_levels[i].value);
3844 static int polaris10_request_link_speed_change_before_state_change(
3845 struct pp_hwmgr *hwmgr, const void *input)
3847 const struct phm_set_power_state_input *states =
3848 (const struct phm_set_power_state_input *)input;
3849 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3850 const struct polaris10_power_state *polaris10_nps =
3851 cast_const_phw_polaris10_power_state(states->pnew_state);
3852 const struct polaris10_power_state *polaris10_cps =
3853 cast_const_phw_polaris10_power_state(states->pcurrent_state);
3855 uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_nps);
3856 uint16_t current_link_speed;
3858 if (data->force_pcie_gen == PP_PCIEGenInvalid)
3859 current_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_cps);
3861 current_link_speed = data->force_pcie_gen;
3863 data->force_pcie_gen = PP_PCIEGenInvalid;
3864 data->pspp_notify_required = false;
3866 if (target_link_speed > current_link_speed) {
3867 switch (target_link_speed) {
3869 if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
3871 data->force_pcie_gen = PP_PCIEGen2;
3872 if (current_link_speed == PP_PCIEGen2)
3875 if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
3878 data->force_pcie_gen = phm_get_current_pcie_speed(hwmgr);
3882 if (target_link_speed < current_link_speed)
3883 data->pspp_notify_required = true;
3889 static int polaris10_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
3891 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3893 if (0 == data->need_update_smu7_dpm_table)
3896 if ((0 == data->sclk_dpm_key_disabled) &&
3897 (data->need_update_smu7_dpm_table &
3898 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
3899 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
3900 "Trying to freeze SCLK DPM when DPM is disabled",
3902 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
3903 PPSMC_MSG_SCLKDPM_FreezeLevel),
3904 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
3908 if ((0 == data->mclk_dpm_key_disabled) &&
3909 (data->need_update_smu7_dpm_table &
3910 DPMTABLE_OD_UPDATE_MCLK)) {
3911 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
3912 "Trying to freeze MCLK DPM when DPM is disabled",
3914 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
3915 PPSMC_MSG_MCLKDPM_FreezeLevel),
3916 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
3923 static int polaris10_populate_and_upload_sclk_mclk_dpm_levels(
3924 struct pp_hwmgr *hwmgr, const void *input)
3927 const struct phm_set_power_state_input *states =
3928 (const struct phm_set_power_state_input *)input;
3929 const struct polaris10_power_state *polaris10_ps =
3930 cast_const_phw_polaris10_power_state(states->pnew_state);
3931 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3932 uint32_t sclk = polaris10_ps->performance_levels
3933 [polaris10_ps->performance_level_count - 1].engine_clock;
3934 uint32_t mclk = polaris10_ps->performance_levels
3935 [polaris10_ps->performance_level_count - 1].memory_clock;
3936 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
3938 struct polaris10_dpm_table *golden_dpm_table = &data->golden_dpm_table;
3939 uint32_t dpm_count, clock_percent;
3942 if (0 == data->need_update_smu7_dpm_table)
3945 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
3946 dpm_table->sclk_table.dpm_levels
3947 [dpm_table->sclk_table.count - 1].value = sclk;
3949 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
3950 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
3951 /* Need to do calculation based on the golden DPM table
3952 * as the Heatmap GPU Clock axis is also based on the default values
3954 PP_ASSERT_WITH_CODE(
3955 (golden_dpm_table->sclk_table.dpm_levels
3956 [golden_dpm_table->sclk_table.count - 1].value != 0),
3959 dpm_count = dpm_table->sclk_table.count < 2 ? 0 : dpm_table->sclk_table.count - 2;
3961 for (i = dpm_count; i > 1; i--) {
3962 if (sclk > golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value) {
3965 - golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value
3967 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
3969 dpm_table->sclk_table.dpm_levels[i].value =
3970 golden_dpm_table->sclk_table.dpm_levels[i].value +
3971 (golden_dpm_table->sclk_table.dpm_levels[i].value *
3974 } else if (golden_dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value > sclk) {
3976 ((golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value
3978 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
3980 dpm_table->sclk_table.dpm_levels[i].value =
3981 golden_dpm_table->sclk_table.dpm_levels[i].value -
3982 (golden_dpm_table->sclk_table.dpm_levels[i].value *
3983 clock_percent) / 100;
3985 dpm_table->sclk_table.dpm_levels[i].value =
3986 golden_dpm_table->sclk_table.dpm_levels[i].value;
3991 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
3992 dpm_table->mclk_table.dpm_levels
3993 [dpm_table->mclk_table.count - 1].value = mclk;
3995 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
3996 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
3998 PP_ASSERT_WITH_CODE(
3999 (golden_dpm_table->mclk_table.dpm_levels
4000 [golden_dpm_table->mclk_table.count-1].value != 0),
4003 dpm_count = dpm_table->mclk_table.count < 2 ? 0 : dpm_table->mclk_table.count - 2;
4004 for (i = dpm_count; i > 1; i--) {
4005 if (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value < mclk) {
4006 clock_percent = ((mclk -
4007 golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value) * 100)
4008 / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
4010 dpm_table->mclk_table.dpm_levels[i].value =
4011 golden_dpm_table->mclk_table.dpm_levels[i].value +
4012 (golden_dpm_table->mclk_table.dpm_levels[i].value *
4013 clock_percent) / 100;
4015 } else if (golden_dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value > mclk) {
4017 (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value - mclk)
4019 / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
4021 dpm_table->mclk_table.dpm_levels[i].value =
4022 golden_dpm_table->mclk_table.dpm_levels[i].value -
4023 (golden_dpm_table->mclk_table.dpm_levels[i].value *
4024 clock_percent) / 100;
4026 dpm_table->mclk_table.dpm_levels[i].value =
4027 golden_dpm_table->mclk_table.dpm_levels[i].value;
4032 if (data->need_update_smu7_dpm_table &
4033 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
4034 result = polaris10_populate_all_graphic_levels(hwmgr);
4035 PP_ASSERT_WITH_CODE((0 == result),
4036 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
4040 if (data->need_update_smu7_dpm_table &
4041 (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
4042 /*populate MCLK dpm table to SMU7 */
4043 result = polaris10_populate_all_memory_levels(hwmgr);
4044 PP_ASSERT_WITH_CODE((0 == result),
4045 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
4052 static int polaris10_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
4053 struct polaris10_single_dpm_table *dpm_table,
4054 uint32_t low_limit, uint32_t high_limit)
4058 for (i = 0; i < dpm_table->count; i++) {
4059 if ((dpm_table->dpm_levels[i].value < low_limit)
4060 || (dpm_table->dpm_levels[i].value > high_limit))
4061 dpm_table->dpm_levels[i].enabled = false;
4063 dpm_table->dpm_levels[i].enabled = true;
4069 static int polaris10_trim_dpm_states(struct pp_hwmgr *hwmgr,
4070 const struct polaris10_power_state *polaris10_ps)
4073 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4074 uint32_t high_limit_count;
4076 PP_ASSERT_WITH_CODE((polaris10_ps->performance_level_count >= 1),
4077 "power state did not have any performance level",
4080 high_limit_count = (1 == polaris10_ps->performance_level_count) ? 0 : 1;
4082 polaris10_trim_single_dpm_states(hwmgr,
4083 &(data->dpm_table.sclk_table),
4084 polaris10_ps->performance_levels[0].engine_clock,
4085 polaris10_ps->performance_levels[high_limit_count].engine_clock);
4087 polaris10_trim_single_dpm_states(hwmgr,
4088 &(data->dpm_table.mclk_table),
4089 polaris10_ps->performance_levels[0].memory_clock,
4090 polaris10_ps->performance_levels[high_limit_count].memory_clock);
4095 static int polaris10_generate_dpm_level_enable_mask(
4096 struct pp_hwmgr *hwmgr, const void *input)
4099 const struct phm_set_power_state_input *states =
4100 (const struct phm_set_power_state_input *)input;
4101 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4102 const struct polaris10_power_state *polaris10_ps =
4103 cast_const_phw_polaris10_power_state(states->pnew_state);
4105 result = polaris10_trim_dpm_states(hwmgr, polaris10_ps);
4109 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
4110 phm_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
4111 data->dpm_level_enable_mask.mclk_dpm_enable_mask =
4112 phm_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
4113 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
4114 phm_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
4119 int polaris10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
4121 return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
4122 PPSMC_MSG_UVDDPM_Enable :
4123 PPSMC_MSG_UVDDPM_Disable);
4126 int polaris10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
4128 return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4129 PPSMC_MSG_VCEDPM_Enable :
4130 PPSMC_MSG_VCEDPM_Disable);
4133 int polaris10_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
4135 return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4136 PPSMC_MSG_SAMUDPM_Enable :
4137 PPSMC_MSG_SAMUDPM_Disable);
4140 int polaris10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4142 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4143 uint32_t mm_boot_level_offset, mm_boot_level_value;
4144 struct phm_ppt_v1_information *table_info =
4145 (struct phm_ppt_v1_information *)(hwmgr->pptable);
4148 data->smc_state_table.UvdBootLevel = 0;
4149 if (table_info->mm_dep_table->count > 0)
4150 data->smc_state_table.UvdBootLevel =
4151 (uint8_t) (table_info->mm_dep_table->count - 1);
4152 mm_boot_level_offset = data->dpm_table_start +
4153 offsetof(SMU74_Discrete_DpmTable, UvdBootLevel);
4154 mm_boot_level_offset /= 4;
4155 mm_boot_level_offset *= 4;
4156 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4157 CGS_IND_REG__SMC, mm_boot_level_offset);
4158 mm_boot_level_value &= 0x00FFFFFF;
4159 mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24;
4160 cgs_write_ind_register(hwmgr->device,
4161 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4163 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4164 PHM_PlatformCaps_UVDDPM) ||
4165 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4166 PHM_PlatformCaps_StablePState))
4167 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4168 PPSMC_MSG_UVDDPM_SetEnabledMask,
4169 (uint32_t)(1 << data->smc_state_table.UvdBootLevel));
4172 return polaris10_enable_disable_uvd_dpm(hwmgr, !bgate);
4175 static int polaris10_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
4177 const struct phm_set_power_state_input *states =
4178 (const struct phm_set_power_state_input *)input;
4179 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4180 const struct polaris10_power_state *polaris10_nps =
4181 cast_const_phw_polaris10_power_state(states->pnew_state);
4182 const struct polaris10_power_state *polaris10_cps =
4183 cast_const_phw_polaris10_power_state(states->pcurrent_state);
4185 uint32_t mm_boot_level_offset, mm_boot_level_value;
4186 struct phm_ppt_v1_information *table_info =
4187 (struct phm_ppt_v1_information *)(hwmgr->pptable);
4189 if (polaris10_nps->vce_clks.evclk > 0 &&
4190 (polaris10_cps == NULL || polaris10_cps->vce_clks.evclk == 0)) {
4192 data->smc_state_table.VceBootLevel =
4193 (uint8_t) (table_info->mm_dep_table->count - 1);
4195 mm_boot_level_offset = data->dpm_table_start +
4196 offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
4197 mm_boot_level_offset /= 4;
4198 mm_boot_level_offset *= 4;
4199 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4200 CGS_IND_REG__SMC, mm_boot_level_offset);
4201 mm_boot_level_value &= 0xFF00FFFF;
4202 mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16;
4203 cgs_write_ind_register(hwmgr->device,
4204 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4206 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
4207 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4208 PPSMC_MSG_VCEDPM_SetEnabledMask,
4209 (uint32_t)1 << data->smc_state_table.VceBootLevel);
4211 polaris10_enable_disable_vce_dpm(hwmgr, true);
4212 } else if (polaris10_nps->vce_clks.evclk == 0 &&
4213 polaris10_cps != NULL &&
4214 polaris10_cps->vce_clks.evclk > 0)
4215 polaris10_enable_disable_vce_dpm(hwmgr, false);
4221 int polaris10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4223 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4224 uint32_t mm_boot_level_offset, mm_boot_level_value;
4227 data->smc_state_table.SamuBootLevel = 0;
4228 mm_boot_level_offset = data->dpm_table_start +
4229 offsetof(SMU74_Discrete_DpmTable, SamuBootLevel);
4230 mm_boot_level_offset /= 4;
4231 mm_boot_level_offset *= 4;
4232 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4233 CGS_IND_REG__SMC, mm_boot_level_offset);
4234 mm_boot_level_value &= 0xFFFFFF00;
4235 mm_boot_level_value |= data->smc_state_table.SamuBootLevel << 0;
4236 cgs_write_ind_register(hwmgr->device,
4237 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4239 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4240 PHM_PlatformCaps_StablePState))
4241 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4242 PPSMC_MSG_SAMUDPM_SetEnabledMask,
4243 (uint32_t)(1 << data->smc_state_table.SamuBootLevel));
4246 return polaris10_enable_disable_samu_dpm(hwmgr, !bgate);
4249 static int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
4251 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4254 uint32_t low_sclk_interrupt_threshold = 0;
4256 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4257 PHM_PlatformCaps_SclkThrottleLowNotification)
4258 && (hwmgr->gfx_arbiter.sclk_threshold !=
4259 data->low_sclk_interrupt_threshold)) {
4260 data->low_sclk_interrupt_threshold =
4261 hwmgr->gfx_arbiter.sclk_threshold;
4262 low_sclk_interrupt_threshold =
4263 data->low_sclk_interrupt_threshold;
4265 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
4267 result = polaris10_copy_bytes_to_smc(
4269 data->dpm_table_start +
4270 offsetof(SMU74_Discrete_DpmTable,
4271 LowSclkInterruptThreshold),
4272 (uint8_t *)&low_sclk_interrupt_threshold,
4280 static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
4282 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4284 if (data->need_update_smu7_dpm_table &
4285 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
4286 return polaris10_program_memory_timing_parameters(hwmgr);
4291 static int polaris10_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4293 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4295 if (0 == data->need_update_smu7_dpm_table)
4298 if ((0 == data->sclk_dpm_key_disabled) &&
4299 (data->need_update_smu7_dpm_table &
4300 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4302 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
4303 "Trying to Unfreeze SCLK DPM when DPM is disabled",
4305 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4306 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4307 "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
4311 if ((0 == data->mclk_dpm_key_disabled) &&
4312 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
4314 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
4315 "Trying to Unfreeze MCLK DPM when DPM is disabled",
4317 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4318 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4319 "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
4323 data->need_update_smu7_dpm_table = 0;
4328 static int polaris10_notify_link_speed_change_after_state_change(
4329 struct pp_hwmgr *hwmgr, const void *input)
4331 const struct phm_set_power_state_input *states =
4332 (const struct phm_set_power_state_input *)input;
4333 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4334 const struct polaris10_power_state *polaris10_ps =
4335 cast_const_phw_polaris10_power_state(states->pnew_state);
4336 uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_ps);
4339 if (data->pspp_notify_required) {
4340 if (target_link_speed == PP_PCIEGen3)
4341 request = PCIE_PERF_REQ_GEN3;
4342 else if (target_link_speed == PP_PCIEGen2)
4343 request = PCIE_PERF_REQ_GEN2;
4345 request = PCIE_PERF_REQ_GEN1;
4347 if (request == PCIE_PERF_REQ_GEN1 &&
4348 phm_get_current_pcie_speed(hwmgr) > 0)
4351 if (acpi_pcie_perf_request(hwmgr->device, request, false)) {
4352 if (PP_PCIEGen2 == target_link_speed)
4353 printk("PSPP request to switch to Gen2 from Gen3 Failed!");
4355 printk("PSPP request to switch to Gen1 from Gen2 Failed!");
4362 static int polaris10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
4364 int tmp_result, result = 0;
4365 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4367 tmp_result = polaris10_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
4368 PP_ASSERT_WITH_CODE((0 == tmp_result),
4369 "Failed to find DPM states clocks in DPM table!",
4370 result = tmp_result);
4372 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4373 PHM_PlatformCaps_PCIEPerformanceRequest)) {
4375 polaris10_request_link_speed_change_before_state_change(hwmgr, input);
4376 PP_ASSERT_WITH_CODE((0 == tmp_result),
4377 "Failed to request link speed change before state change!",
4378 result = tmp_result);
4381 tmp_result = polaris10_freeze_sclk_mclk_dpm(hwmgr);
4382 PP_ASSERT_WITH_CODE((0 == tmp_result),
4383 "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
4385 tmp_result = polaris10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
4386 PP_ASSERT_WITH_CODE((0 == tmp_result),
4387 "Failed to populate and upload SCLK MCLK DPM levels!",
4388 result = tmp_result);
4390 tmp_result = polaris10_generate_dpm_level_enable_mask(hwmgr, input);
4391 PP_ASSERT_WITH_CODE((0 == tmp_result),
4392 "Failed to generate DPM level enabled mask!",
4393 result = tmp_result);
4395 tmp_result = polaris10_update_vce_dpm(hwmgr, input);
4396 PP_ASSERT_WITH_CODE((0 == tmp_result),
4397 "Failed to update VCE DPM!",
4398 result = tmp_result);
4400 tmp_result = polaris10_update_sclk_threshold(hwmgr);
4401 PP_ASSERT_WITH_CODE((0 == tmp_result),
4402 "Failed to update SCLK threshold!",
4403 result = tmp_result);
4405 tmp_result = polaris10_program_mem_timing_parameters(hwmgr);
4406 PP_ASSERT_WITH_CODE((0 == tmp_result),
4407 "Failed to program memory timing parameters!",
4408 result = tmp_result);
4410 tmp_result = polaris10_unfreeze_sclk_mclk_dpm(hwmgr);
4411 PP_ASSERT_WITH_CODE((0 == tmp_result),
4412 "Failed to unfreeze SCLK MCLK DPM!",
4413 result = tmp_result);
4415 tmp_result = polaris10_upload_dpm_level_enable_mask(hwmgr);
4416 PP_ASSERT_WITH_CODE((0 == tmp_result),
4417 "Failed to upload DPM level enabled mask!",
4418 result = tmp_result);
4420 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4421 PHM_PlatformCaps_PCIEPerformanceRequest)) {
4423 polaris10_notify_link_speed_change_after_state_change(hwmgr, input);
4424 PP_ASSERT_WITH_CODE((0 == tmp_result),
4425 "Failed to notify link speed change after state change!",
4426 result = tmp_result);
4428 data->apply_optimized_settings = false;
4432 static int polaris10_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
4434 hwmgr->thermal_controller.
4435 advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
4437 if (phm_is_hw_access_blocked(hwmgr))
4440 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4441 PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
4444 int polaris10_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
4446 PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
4448 return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ? 0 : -1;
4451 int polaris10_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
4453 uint32_t num_active_displays = 0;
4454 struct cgs_display_info info = {0};
4455 info.mode_info = NULL;
4457 cgs_get_active_displays_info(hwmgr->device, &info);
4459 num_active_displays = info.display_count;
4461 if (num_active_displays > 1) /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */
4462 polaris10_notify_smc_display_change(hwmgr, false);
4464 polaris10_notify_smc_display_change(hwmgr, true);
4470 * Programs the display gap
4472 * @param hwmgr the address of the powerplay hardware manager.
4475 int polaris10_program_display_gap(struct pp_hwmgr *hwmgr)
4477 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4478 uint32_t num_active_displays = 0;
4479 uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
4480 uint32_t display_gap2;
4481 uint32_t pre_vbi_time_in_us;
4482 uint32_t frame_time_in_us;
4484 uint32_t refresh_rate = 0;
4485 struct cgs_display_info info = {0};
4486 struct cgs_mode_info mode_info;
4488 info.mode_info = &mode_info;
4490 cgs_get_active_displays_info(hwmgr->device, &info);
4491 num_active_displays = info.display_count;
4493 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
4494 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
4496 ref_clock = mode_info.ref_clock;
4497 refresh_rate = mode_info.refresh_rate;
4499 if (0 == refresh_rate)
4502 frame_time_in_us = 1000000 / refresh_rate;
4504 pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
4505 display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
4507 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
4509 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, PreVBlankGap), 0x64);
4511 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
4513 polaris10_notify_smc_display_change(hwmgr, num_active_displays != 0);
4519 int polaris10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
4521 return polaris10_program_display_gap(hwmgr);
4525 * Set maximum target operating fan output RPM
4527 * @param hwmgr: the address of the powerplay hardware manager.
4528 * @param usMaxFanRpm: max operating fan RPM value.
4529 * @return The response that came from the SMC.
4531 static int polaris10_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm)
4533 hwmgr->thermal_controller.
4534 advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
4536 if (phm_is_hw_access_blocked(hwmgr))
4539 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4540 PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
4543 int polaris10_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
4544 const void *thermal_interrupt_info)
4549 bool polaris10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
4551 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4552 bool is_update_required = false;
4553 struct cgs_display_info info = {0, 0, NULL};
4555 cgs_get_active_displays_info(hwmgr->device, &info);
4557 if (data->display_timing.num_existing_displays != info.display_count)
4558 is_update_required = true;
4559 /* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
4560 if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
4561 cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
4562 if (min_clocks.engineClockInSR != data->display_timing.minClockInSR &&
4563 (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
4564 data->display_timing.minClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK))
4565 is_update_required = true;
4567 return is_update_required;
4570 static inline bool polaris10_are_power_levels_equal(const struct polaris10_performance_level *pl1,
4571 const struct polaris10_performance_level *pl2)
4573 return ((pl1->memory_clock == pl2->memory_clock) &&
4574 (pl1->engine_clock == pl2->engine_clock) &&
4575 (pl1->pcie_gen == pl2->pcie_gen) &&
4576 (pl1->pcie_lane == pl2->pcie_lane));
4579 int polaris10_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
4581 const struct polaris10_power_state *psa = cast_const_phw_polaris10_power_state(pstate1);
4582 const struct polaris10_power_state *psb = cast_const_phw_polaris10_power_state(pstate2);
4585 if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
4588 /* If the two states don't even have the same number of performance levels they cannot be the same state. */
4589 if (psa->performance_level_count != psb->performance_level_count) {
4594 for (i = 0; i < psa->performance_level_count; i++) {
4595 if (!polaris10_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
4596 /* If we have found even one performance level pair that is different the states are different. */
4602 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
4603 *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
4604 *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
4605 *equal &= (psa->sclk_threshold == psb->sclk_threshold);
4610 int polaris10_upload_mc_firmware(struct pp_hwmgr *hwmgr)
4612 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4614 uint32_t vbios_version;
4616 /* Read MC indirect register offset 0x9F bits [3:0] to see if VBIOS has already loaded a full version of MC ucode or not.*/
4618 phm_get_mc_microcode_version(hwmgr);
4619 vbios_version = hwmgr->microcode_version_info.MC & 0xf;
4620 /* Full version of MC ucode has already been loaded. */
4621 if (vbios_version == 0) {
4622 data->need_long_memory_training = false;
4626 data->need_long_memory_training = true;
4629 * PPMCME_FirmwareDescriptorEntry *pfd = NULL;
4630 pfd = &tonga_mcmeFirmware;
4631 if (0 == PHM_READ_FIELD(hwmgr->device, MC_SEQ_SUP_CNTL, RUN))
4632 polaris10_load_mc_microcode(hwmgr, pfd->dpmThreshold,
4633 pfd->cfgArray, pfd->cfgSize, pfd->ioDebugArray,
4634 pfd->ioDebugSize, pfd->ucodeArray, pfd->ucodeSize);
4640 * Read clock related registers.
4642 * @param hwmgr the address of the powerplay hardware manager.
4645 static int polaris10_read_clock_registers(struct pp_hwmgr *hwmgr)
4647 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4649 data->clock_registers.vCG_SPLL_FUNC_CNTL = cgs_read_ind_register(hwmgr->device,
4650 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL)
4651 & CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK;
4653 data->clock_registers.vCG_SPLL_FUNC_CNTL_2 = cgs_read_ind_register(hwmgr->device,
4654 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2)
4655 & CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
4657 data->clock_registers.vCG_SPLL_FUNC_CNTL_4 = cgs_read_ind_register(hwmgr->device,
4658 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4)
4659 & CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK;
4665 * Find out if memory is GDDR5.
4667 * @param hwmgr the address of the powerplay hardware manager.
4670 static int polaris10_get_memory_type(struct pp_hwmgr *hwmgr)
4672 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4675 temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
4677 data->is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
4678 ((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
4679 MC_SEQ_MISC0_GDDR5_SHIFT));
4685 * Enables Dynamic Power Management by SMC
4687 * @param hwmgr the address of the powerplay hardware manager.
4690 static int polaris10_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
4692 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4693 GENERAL_PWRMGT, STATIC_PM_EN, 1);
4699 * Initialize PowerGating States for different engines
4701 * @param hwmgr the address of the powerplay hardware manager.
4704 static int polaris10_init_power_gate_state(struct pp_hwmgr *hwmgr)
4706 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4708 data->uvd_power_gated = false;
4709 data->vce_power_gated = false;
4710 data->samu_power_gated = false;
4715 static int polaris10_init_sclk_threshold(struct pp_hwmgr *hwmgr)
4717 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4718 data->low_sclk_interrupt_threshold = 0;
4723 int polaris10_setup_asic_task(struct pp_hwmgr *hwmgr)
4725 int tmp_result, result = 0;
4727 polaris10_upload_mc_firmware(hwmgr);
4729 tmp_result = polaris10_read_clock_registers(hwmgr);
4730 PP_ASSERT_WITH_CODE((0 == tmp_result),
4731 "Failed to read clock registers!", result = tmp_result);
4733 tmp_result = polaris10_get_memory_type(hwmgr);
4734 PP_ASSERT_WITH_CODE((0 == tmp_result),
4735 "Failed to get memory type!", result = tmp_result);
4737 tmp_result = polaris10_enable_acpi_power_management(hwmgr);
4738 PP_ASSERT_WITH_CODE((0 == tmp_result),
4739 "Failed to enable ACPI power management!", result = tmp_result);
4741 tmp_result = polaris10_init_power_gate_state(hwmgr);
4742 PP_ASSERT_WITH_CODE((0 == tmp_result),
4743 "Failed to init power gate state!", result = tmp_result);
4745 tmp_result = phm_get_mc_microcode_version(hwmgr);
4746 PP_ASSERT_WITH_CODE((0 == tmp_result),
4747 "Failed to get MC microcode version!", result = tmp_result);
4749 tmp_result = polaris10_init_sclk_threshold(hwmgr);
4750 PP_ASSERT_WITH_CODE((0 == tmp_result),
4751 "Failed to init sclk threshold!", result = tmp_result);
4756 static int polaris10_get_pp_table(struct pp_hwmgr *hwmgr, char **table)
4758 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4760 if (!data->soft_pp_table) {
4761 data->soft_pp_table = kmemdup(hwmgr->soft_pp_table,
4762 hwmgr->soft_pp_table_size,
4764 if (!data->soft_pp_table)
4768 *table = (char *)&data->soft_pp_table;
4770 return hwmgr->soft_pp_table_size;
4773 static int polaris10_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t size)
4775 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4777 if (!data->soft_pp_table) {
4778 data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL);
4779 if (!data->soft_pp_table)
4783 memcpy(data->soft_pp_table, buf, size);
4785 hwmgr->soft_pp_table = data->soft_pp_table;
4787 /* TODO: re-init powerplay to implement modified pptable */
4792 static int polaris10_force_clock_level(struct pp_hwmgr *hwmgr,
4793 enum pp_clock_type type, uint32_t mask)
4795 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4797 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
4802 if (!data->sclk_dpm_key_disabled)
4803 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4804 PPSMC_MSG_SCLKDPM_SetEnabledMask,
4805 data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
4808 if (!data->mclk_dpm_key_disabled)
4809 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4810 PPSMC_MSG_MCLKDPM_SetEnabledMask,
4811 data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
4815 uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
4821 if (!data->pcie_dpm_key_disabled)
4822 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4823 PPSMC_MSG_PCIeDPM_ForceLevel,
4834 static uint16_t polaris10_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
4836 uint32_t speedCntl = 0;
4838 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
4839 speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
4840 ixPCIE_LC_SPEED_CNTL);
4841 return((uint16_t)PHM_GET_FIELD(speedCntl,
4842 PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
4845 static int polaris10_print_clock_levels(struct pp_hwmgr *hwmgr,
4846 enum pp_clock_type type, char *buf)
4848 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4849 struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4850 struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4851 struct polaris10_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
4852 int i, now, size = 0;
4853 uint32_t clock, pcie_speed;
4857 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
4858 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4860 for (i = 0; i < sclk_table->count; i++) {
4861 if (clock > sclk_table->dpm_levels[i].value)
4867 for (i = 0; i < sclk_table->count; i++)
4868 size += sprintf(buf + size, "%d: %uMhz %s\n",
4869 i, sclk_table->dpm_levels[i].value / 100,
4870 (i == now) ? "*" : "");
4873 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
4874 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4876 for (i = 0; i < mclk_table->count; i++) {
4877 if (clock > mclk_table->dpm_levels[i].value)
4883 for (i = 0; i < mclk_table->count; i++)
4884 size += sprintf(buf + size, "%d: %uMhz %s\n",
4885 i, mclk_table->dpm_levels[i].value / 100,
4886 (i == now) ? "*" : "");
4889 pcie_speed = polaris10_get_current_pcie_speed(hwmgr);
4890 for (i = 0; i < pcie_table->count; i++) {
4891 if (pcie_speed != pcie_table->dpm_levels[i].value)
4897 for (i = 0; i < pcie_table->count; i++)
4898 size += sprintf(buf + size, "%d: %s %s\n", i,
4899 (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x8" :
4900 (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
4901 (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
4902 (i == now) ? "*" : "");
4910 static int polaris10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
4913 /* stop auto-manage */
4914 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4915 PHM_PlatformCaps_MicrocodeFanControl))
4916 polaris10_fan_ctrl_stop_smc_fan_control(hwmgr);
4917 polaris10_fan_ctrl_set_static_mode(hwmgr, mode);
4919 /* restart auto-manage */
4920 polaris10_fan_ctrl_reset_fan_speed_to_default(hwmgr);
4925 static int polaris10_get_fan_control_mode(struct pp_hwmgr *hwmgr)
4927 if (hwmgr->fan_ctrl_is_in_default_mode)
4928 return hwmgr->fan_ctrl_default_mode;
4930 return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4931 CG_FDO_CTRL2, FDO_PWM_MODE);
4934 static const struct pp_hwmgr_func polaris10_hwmgr_funcs = {
4935 .backend_init = &polaris10_hwmgr_backend_init,
4936 .backend_fini = &polaris10_hwmgr_backend_fini,
4937 .asic_setup = &polaris10_setup_asic_task,
4938 .dynamic_state_management_enable = &polaris10_enable_dpm_tasks,
4939 .apply_state_adjust_rules = polaris10_apply_state_adjust_rules,
4940 .force_dpm_level = &polaris10_force_dpm_level,
4941 .power_state_set = polaris10_set_power_state_tasks,
4942 .get_power_state_size = polaris10_get_power_state_size,
4943 .get_mclk = polaris10_dpm_get_mclk,
4944 .get_sclk = polaris10_dpm_get_sclk,
4945 .patch_boot_state = polaris10_dpm_patch_boot_state,
4946 .get_pp_table_entry = polaris10_get_pp_table_entry,
4947 .get_num_of_pp_table_entries = tonga_get_number_of_powerplay_table_entries,
4948 .print_current_perforce_level = polaris10_print_current_perforce_level,
4949 .powerdown_uvd = polaris10_phm_powerdown_uvd,
4950 .powergate_uvd = polaris10_phm_powergate_uvd,
4951 .powergate_vce = polaris10_phm_powergate_vce,
4952 .disable_clock_power_gating = polaris10_phm_disable_clock_power_gating,
4953 .update_clock_gatings = polaris10_phm_update_clock_gatings,
4954 .notify_smc_display_config_after_ps_adjustment = polaris10_notify_smc_display_config_after_ps_adjustment,
4955 .display_config_changed = polaris10_display_configuration_changed_task,
4956 .set_max_fan_pwm_output = polaris10_set_max_fan_pwm_output,
4957 .set_max_fan_rpm_output = polaris10_set_max_fan_rpm_output,
4958 .get_temperature = polaris10_thermal_get_temperature,
4959 .stop_thermal_controller = polaris10_thermal_stop_thermal_controller,
4960 .get_fan_speed_info = polaris10_fan_ctrl_get_fan_speed_info,
4961 .get_fan_speed_percent = polaris10_fan_ctrl_get_fan_speed_percent,
4962 .set_fan_speed_percent = polaris10_fan_ctrl_set_fan_speed_percent,
4963 .reset_fan_speed_to_default = polaris10_fan_ctrl_reset_fan_speed_to_default,
4964 .get_fan_speed_rpm = polaris10_fan_ctrl_get_fan_speed_rpm,
4965 .set_fan_speed_rpm = polaris10_fan_ctrl_set_fan_speed_rpm,
4966 .uninitialize_thermal_controller = polaris10_thermal_ctrl_uninitialize_thermal_controller,
4967 .register_internal_thermal_interrupt = polaris10_register_internal_thermal_interrupt,
4968 .check_smc_update_required_for_display_configuration = polaris10_check_smc_update_required_for_display_configuration,
4969 .check_states_equal = polaris10_check_states_equal,
4970 .set_fan_control_mode = polaris10_set_fan_control_mode,
4971 .get_fan_control_mode = polaris10_get_fan_control_mode,
4972 .get_pp_table = polaris10_get_pp_table,
4973 .set_pp_table = polaris10_set_pp_table,
4974 .force_clock_level = polaris10_force_clock_level,
4975 .print_clock_levels = polaris10_print_clock_levels,
4976 .enable_per_cu_power_gating = polaris10_phm_enable_per_cu_power_gating,
4979 int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr)
4981 struct polaris10_hwmgr *data;
4983 data = kzalloc (sizeof(struct polaris10_hwmgr), GFP_KERNEL);
4987 hwmgr->backend = data;
4988 hwmgr->hwmgr_func = &polaris10_hwmgr_funcs;
4989 hwmgr->pptable_func = &tonga_pptable_funcs;
4990 pp_polaris10_thermal_initialize(hwmgr);