drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef PP_ATOMVOLTAGECTRL_H
  25 #define PP_ATOMVOLTAGECTRL_H
  26
  27 #include "hwmgr.h"
  28
  29 #define MEM_TYPE_GDDR5  0x50
  30 #define MEM_TYPE_GDDR4  0x40
  31 #define MEM_TYPE_GDDR3  0x30
  32 #define MEM_TYPE_DDR2   0x20
  33 #define MEM_TYPE_GDDR1  0x10
  34 #define MEM_TYPE_DDR3   0xb0
  35 #define MEM_TYPE_MASK   0xF0
  36
  37
  38 /* As returned from PowerConnectorDetectionTable. */
  39 #define PP_ATOM_POWER_BUDGET_DISABLE_OVERDRIVE  0x80
  40 #define PP_ATOM_POWER_BUDGET_SHOW_WARNING       0x40
  41 #define PP_ATOM_POWER_BUDGET_SHOW_WAIVER        0x20
  42 #define PP_ATOM_POWER_POWER_BUDGET_BEHAVIOUR    0x0F
  43
  44 /* New functions for Evergreen and beyond. */
  45 #define PP_ATOMCTRL_MAX_VOLTAGE_ENTRIES 32
  46
  47 struct pp_atomctrl_clock_dividers {
  48         uint32_t pll_post_divider;
  49         uint32_t pll_feedback_divider;
  50         uint32_t pll_ref_divider;
  51         bool  enable_post_divider;
  52 };
  53
  54 typedef struct pp_atomctrl_clock_dividers pp_atomctrl_clock_dividers;
  55
  56 union pp_atomctrl_tcipll_fb_divider {
  57         struct {
  58                 uint32_t ul_fb_div_frac : 14;
  59                 uint32_t ul_fb_div : 12;
  60                 uint32_t un_used : 6;
  61         };
  62         uint32_t ul_fb_divider;
  63 };
  64
  65 typedef union pp_atomctrl_tcipll_fb_divider pp_atomctrl_tcipll_fb_divider;
  66
  67 struct pp_atomctrl_clock_dividers_rv730 {
  68         uint32_t pll_post_divider;
  69         pp_atomctrl_tcipll_fb_divider mpll_feedback_divider;
  70         uint32_t pll_ref_divider;
  71         bool  enable_post_divider;
  72         bool  enable_dithen;
  73         uint32_t vco_mode;
  74 };
  75 typedef struct pp_atomctrl_clock_dividers_rv730 pp_atomctrl_clock_dividers_rv730;
  76
  77
  78 struct pp_atomctrl_clock_dividers_kong {
  79         uint32_t    pll_post_divider;
  80         uint32_t    real_clock;
  81 };
  82 typedef struct pp_atomctrl_clock_dividers_kong pp_atomctrl_clock_dividers_kong;
  83
  84 struct pp_atomctrl_clock_dividers_ci {
  85         uint32_t    pll_post_divider;               /* post divider value */
  86         uint32_t    real_clock;
  87         pp_atomctrl_tcipll_fb_divider   ul_fb_div;         /* Output Parameter: PLL FB divider */
  88         uint8_t   uc_pll_ref_div;                      /* Output Parameter: PLL ref divider */
  89         uint8_t   uc_pll_post_div;                      /* Output Parameter: PLL post divider */
  90         uint8_t   uc_pll_cntl_flag;                    /*Output Flags: control flag */
  91 };
  92 typedef struct pp_atomctrl_clock_dividers_ci pp_atomctrl_clock_dividers_ci;
  93
  94 struct pp_atomctrl_clock_dividers_vi {
  95         uint32_t    pll_post_divider;               /* post divider value */
  96         uint32_t    real_clock;
  97         pp_atomctrl_tcipll_fb_divider   ul_fb_div;         /*Output Parameter: PLL FB divider */
  98         uint8_t   uc_pll_ref_div;                      /*Output Parameter: PLL ref divider */
  99         uint8_t   uc_pll_post_div;                     /*Output Parameter: PLL post divider */
 100         uint8_t   uc_pll_cntl_flag;                    /*Output Flags: control flag */
 101 };
 102 typedef struct pp_atomctrl_clock_dividers_vi pp_atomctrl_clock_dividers_vi;
 103
 104 union pp_atomctrl_s_mpll_fb_divider {
 105         struct {
 106                 uint32_t cl_kf : 12;
 107                 uint32_t clk_frac : 12;
 108                 uint32_t un_used : 8;
 109         };
 110         uint32_t ul_fb_divider;
 111 };
 112 typedef union pp_atomctrl_s_mpll_fb_divider pp_atomctrl_s_mpll_fb_divider;
 113
 114 enum pp_atomctrl_spread_spectrum_mode {
 115         pp_atomctrl_spread_spectrum_mode_down = 0,
 116         pp_atomctrl_spread_spectrum_mode_center
 117 };
 118 typedef enum pp_atomctrl_spread_spectrum_mode pp_atomctrl_spread_spectrum_mode;
 119
 120 struct pp_atomctrl_memory_clock_param {
 121         pp_atomctrl_s_mpll_fb_divider mpll_fb_divider;
 122         uint32_t mpll_post_divider;
 123         uint32_t bw_ctrl;
 124         uint32_t dll_speed;
 125         uint32_t vco_mode;
 126         uint32_t yclk_sel;
 127         uint32_t qdr;
 128         uint32_t half_rate;
 129 };
 130 typedef struct pp_atomctrl_memory_clock_param pp_atomctrl_memory_clock_param;
 131
 132 struct pp_atomctrl_internal_ss_info {
 133         uint32_t speed_spectrum_percentage;                      /* in 1/100 percentage */
 134         uint32_t speed_spectrum_rate;                            /* in KHz */
 135         pp_atomctrl_spread_spectrum_mode speed_spectrum_mode;
 136 };
 137 typedef struct pp_atomctrl_internal_ss_info pp_atomctrl_internal_ss_info;
 138
 139 #ifndef NUMBER_OF_M3ARB_PARAMS
 140 #define NUMBER_OF_M3ARB_PARAMS 3
 141 #endif
 142
 143 #ifndef NUMBER_OF_M3ARB_PARAM_SETS
 144 #define NUMBER_OF_M3ARB_PARAM_SETS 10
 145 #endif
 146
 147 struct pp_atomctrl_kong_system_info {
 148         uint32_t                        ul_bootup_uma_clock;          /* in 10kHz unit */
 149         uint16_t                        us_max_nb_voltage;            /* high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; */
 150         uint16_t                        us_min_nb_voltage;            /* low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; */
 151         uint16_t                        us_bootup_nb_voltage;         /* boot up NB voltage */
 152         uint8_t                 uc_htc_tmp_lmt;               /* bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD */
 153         uint8_t                 uc_tj_offset;                /* bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD */
 154         /* 0: default 1: uvd 2: fs-3d */
 155         uint32_t          ul_csr_m3_srb_cntl[NUMBER_OF_M3ARB_PARAM_SETS][NUMBER_OF_M3ARB_PARAMS];/* arrays with values for CSR M3 arbiter for default */
 156 };
 157 typedef struct pp_atomctrl_kong_system_info pp_atomctrl_kong_system_info;
 158
 159 struct pp_atomctrl_memory_info {
 160         uint8_t memory_vendor;
 161         uint8_t memory_type;
 162 };
 163 typedef struct pp_atomctrl_memory_info pp_atomctrl_memory_info;
 164
 165 #define MAX_AC_TIMING_ENTRIES 16
 166
 167 struct pp_atomctrl_memory_clock_range_table {
 168         uint8_t   num_entries;
 169         uint8_t   rsv[3];
 170
 171         uint32_t mclk[MAX_AC_TIMING_ENTRIES];
 172 };
 173 typedef struct pp_atomctrl_memory_clock_range_table pp_atomctrl_memory_clock_range_table;
 174
 175 struct pp_atomctrl_voltage_table_entry {
 176         uint16_t value;
 177         uint32_t smio_low;
 178 };
 179
 180 typedef struct pp_atomctrl_voltage_table_entry pp_atomctrl_voltage_table_entry;
 181
 182 struct pp_atomctrl_voltage_table {
 183         uint32_t count;
 184         uint32_t mask_low;
 185         uint32_t phase_delay;   /* Used for ATOM_GPIO_VOLTAGE_OBJECT_V3 and later */
 186         pp_atomctrl_voltage_table_entry entries[PP_ATOMCTRL_MAX_VOLTAGE_ENTRIES];
 187 };
 188
 189 typedef struct pp_atomctrl_voltage_table pp_atomctrl_voltage_table;
 190
 191 #define VBIOS_MC_REGISTER_ARRAY_SIZE           32
 192 #define VBIOS_MAX_AC_TIMING_ENTRIES            20
 193
 194 struct pp_atomctrl_mc_reg_entry {
 195         uint32_t           mclk_max;
 196         uint32_t mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];
 197 };
 198 typedef struct pp_atomctrl_mc_reg_entry pp_atomctrl_mc_reg_entry;
 199
 200 struct pp_atomctrl_mc_register_address {
 201         uint16_t s1;
 202         uint8_t  uc_pre_reg_data;
 203 };
 204
 205 typedef struct pp_atomctrl_mc_register_address pp_atomctrl_mc_register_address;
 206
 207 struct pp_atomctrl_mc_reg_table {
 208         uint8_t                         last;                    /* number of registers */
 209         uint8_t                         num_entries;             /* number of AC timing entries */
 210         pp_atomctrl_mc_reg_entry        mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES];
 211         pp_atomctrl_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE];
 212 };
 213 typedef struct pp_atomctrl_mc_reg_table pp_atomctrl_mc_reg_table;
 214
 215 struct pp_atomctrl_gpio_pin_assignment {
 216         uint16_t                   us_gpio_pin_aindex;
 217         uint8_t                    uc_gpio_pin_bit_shift;
 218 };
 219 typedef struct pp_atomctrl_gpio_pin_assignment pp_atomctrl_gpio_pin_assignment;
 220
 221 extern bool atomctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr, const uint32_t pinId, pp_atomctrl_gpio_pin_assignment *gpio_pin_assignment);
 222 extern int atomctrl_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage);
 223 extern uint32_t atomctrl_get_mpll_reference_clock(struct pp_hwmgr *hwmgr);
 224 extern int atomctrl_get_memory_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t memory_clock, pp_atomctrl_internal_ss_info *ssInfo);
 225 extern int atomctrl_get_engine_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t engine_clock, pp_atomctrl_internal_ss_info *ssInfo);
 226 extern int atomctrl_initialize_mc_reg_table(struct pp_hwmgr *hwmgr, uint8_t module_index, pp_atomctrl_mc_reg_table *table);
 227 extern int atomctrl_set_engine_dram_timings_rv770(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock);
 228 extern uint32_t atomctrl_get_reference_clock(struct pp_hwmgr *hwmgr);
 229 extern int atomctrl_get_memory_pll_dividers_si(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param, bool strobe_mode);
 230 extern int atomctrl_get_engine_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
 231 extern int atomctrl_get_dfs_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
 232 extern bool atomctrl_is_voltage_controled_by_gpio_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode);
 233 extern int atomctrl_get_voltage_table_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode, pp_atomctrl_voltage_table *voltage_table);
 234 extern int atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr,
 235                 uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param);
 236 extern int atomctrl_get_engine_pll_dividers_kong(struct pp_hwmgr *hwmgr,
 237                                                  uint32_t clock_value,
 238                                                  pp_atomctrl_clock_dividers_kong *dividers);
 239 extern int atomctrl_read_efuse(void *device, uint16_t start_index,
 240                 uint16_t end_index, uint32_t mask, uint32_t *efuse);
 241 extern int atomctrl_calculate_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
 242                 uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage, uint16_t dpm_level, bool debug);
 243
 244
 245 #endif
 246