drivers/gpu/drm/amd/powerplay/inc/hwmgr.h

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #ifndef _HWMGR_H_
  24 #define _HWMGR_H_
  25
  26 #include <linux/seq_file.h>
  27 #include "amd_powerplay.h"
  28 #include "pp_instance.h"
  29 #include "hardwaremanager.h"
  30 #include "pp_power_source.h"
  31 #include "hwmgr_ppt.h"
  32 #include "ppatomctrl.h"
  33 #include "hwmgr_ppt.h"
  34 #include "power_state.h"
  35
  36 struct pp_instance;
  37 struct pp_hwmgr;
  38 struct phm_fan_speed_info;
  39 struct pp_atomctrl_voltage_table;
  40
  41 extern int amdgpu_powercontainment;
  42 extern int amdgpu_sclk_deep_sleep_en;
  43 extern unsigned amdgpu_pp_feature_mask;
  44
  45 enum DISPLAY_GAP {
  46         DISPLAY_GAP_VBLANK_OR_WM = 0,   /* Wait for vblank or MCHG watermark. */
  47         DISPLAY_GAP_VBLANK       = 1,   /* Wait for vblank. */
  48         DISPLAY_GAP_WATERMARK    = 2,   /* Wait for MCHG watermark. (Note that HW may deassert WM in VBI depending on DC_STUTTER_CNTL.) */
  49         DISPLAY_GAP_IGNORE       = 3    /* Do not wait. */
  50 };
  51 typedef enum DISPLAY_GAP DISPLAY_GAP;
  52
  53 struct vi_dpm_level {
  54         bool enabled;
  55         uint32_t value;
  56         uint32_t param1;
  57 };
  58
  59 struct vi_dpm_table {
  60         uint32_t count;
  61         struct vi_dpm_level dpm_level[1];
  62 };
  63
  64 enum PP_Result {
  65         PP_Result_TableImmediateExit = 0x13,
  66 };
  67
  68 #define PCIE_PERF_REQ_REMOVE_REGISTRY   0
  69 #define PCIE_PERF_REQ_FORCE_LOWPOWER    1
  70 #define PCIE_PERF_REQ_GEN1         2
  71 #define PCIE_PERF_REQ_GEN2         3
  72 #define PCIE_PERF_REQ_GEN3         4
  73
  74 enum PP_FEATURE_MASK {
  75         PP_SCLK_DPM_MASK = 0x1,
  76         PP_MCLK_DPM_MASK = 0x2,
  77         PP_PCIE_DPM_MASK = 0x4,
  78         PP_SCLK_DEEP_SLEEP_MASK = 0x8,
  79         PP_POWER_CONTAINMENT_MASK = 0x10,
  80         PP_UVD_HANDSHAKE_MASK = 0x20,
  81         PP_SMC_VOLTAGE_CONTROL_MASK = 0x40,
  82         PP_VBI_TIME_SUPPORT_MASK = 0x80,
  83         PP_ULV_MASK = 0x100,
  84         PP_ENABLE_GFX_CG_THRU_SMU = 0x200
  85 };
  86
  87 enum PHM_BackEnd_Magic {
  88         PHM_Dummy_Magic       = 0xAA5555AA,
  89         PHM_RV770_Magic       = 0xDCBAABCD,
  90         PHM_Kong_Magic        = 0x239478DF,
  91         PHM_NIslands_Magic    = 0x736C494E,
  92         PHM_Sumo_Magic        = 0x8339FA11,
  93         PHM_SIslands_Magic    = 0x369431AC,
  94         PHM_Trinity_Magic     = 0x96751873,
  95         PHM_CIslands_Magic    = 0x38AC78B0,
  96         PHM_Kv_Magic          = 0xDCBBABC0,
  97         PHM_VIslands_Magic    = 0x20130307,
  98         PHM_Cz_Magic          = 0x67DCBA25
  99 };
 100
 101
 102 #define PHM_PCIE_POWERGATING_TARGET_GFX            0
 103 #define PHM_PCIE_POWERGATING_TARGET_DDI            1
 104 #define PHM_PCIE_POWERGATING_TARGET_PLLCASCADE     2
 105 #define PHM_PCIE_POWERGATING_TARGET_PHY            3
 106
 107 typedef int (*phm_table_function)(struct pp_hwmgr *hwmgr, void *input,
 108                                   void *output, void *storage, int result);
 109
 110 typedef bool (*phm_check_function)(struct pp_hwmgr *hwmgr);
 111
 112 struct phm_set_power_state_input {
 113         const struct pp_hw_power_state *pcurrent_state;
 114         const struct pp_hw_power_state *pnew_state;
 115 };
 116
 117 struct phm_acp_arbiter {
 118         uint32_t acpclk;
 119 };
 120
 121 struct phm_uvd_arbiter {
 122         uint32_t vclk;
 123         uint32_t dclk;
 124         uint32_t vclk_ceiling;
 125         uint32_t dclk_ceiling;
 126 };
 127
 128 struct phm_vce_arbiter {
 129         uint32_t   evclk;
 130         uint32_t   ecclk;
 131 };
 132
 133 struct phm_gfx_arbiter {
 134         uint32_t sclk;
 135         uint32_t mclk;
 136         uint32_t sclk_over_drive;
 137         uint32_t mclk_over_drive;
 138         uint32_t sclk_threshold;
 139         uint32_t num_cus;
 140 };
 141
 142 /* Entries in the master tables */
 143 struct phm_master_table_item {
 144         phm_check_function isFunctionNeededInRuntimeTable;
 145         phm_table_function tableFunction;
 146 };
 147
 148 enum phm_master_table_flag {
 149         PHM_MasterTableFlag_None         = 0,
 150         PHM_MasterTableFlag_ExitOnError  = 1,
 151 };
 152
 153 /* The header of the master tables */
 154 struct phm_master_table_header {
 155         uint32_t storage_size;
 156         uint32_t flags;
 157         const struct phm_master_table_item *master_list;
 158 };
 159
 160 struct phm_runtime_table_header {
 161         uint32_t storage_size;
 162         bool exit_error;
 163         phm_table_function *function_list;
 164 };
 165
 166 struct phm_clock_array {
 167         uint32_t count;
 168         uint32_t values[1];
 169 };
 170
 171 struct phm_clock_voltage_dependency_record {
 172         uint32_t clk;
 173         uint32_t v;
 174 };
 175
 176 struct phm_vceclock_voltage_dependency_record {
 177         uint32_t ecclk;
 178         uint32_t evclk;
 179         uint32_t v;
 180 };
 181
 182 struct phm_uvdclock_voltage_dependency_record {
 183         uint32_t vclk;
 184         uint32_t dclk;
 185         uint32_t v;
 186 };
 187
 188 struct phm_samuclock_voltage_dependency_record {
 189         uint32_t samclk;
 190         uint32_t v;
 191 };
 192
 193 struct phm_acpclock_voltage_dependency_record {
 194         uint32_t acpclk;
 195         uint32_t v;
 196 };
 197
 198 struct phm_clock_voltage_dependency_table {
 199         uint32_t count;                                                                         /* Number of entries. */
 200         struct phm_clock_voltage_dependency_record entries[1];          /* Dynamically allocate count entries. */
 201 };
 202
 203 struct phm_phase_shedding_limits_record {
 204         uint32_t  Voltage;
 205         uint32_t    Sclk;
 206         uint32_t    Mclk;
 207 };
 208
 209
 210 extern int phm_dispatch_table(struct pp_hwmgr *hwmgr,
 211                               struct phm_runtime_table_header *rt_table,
 212                               void *input, void *output);
 213
 214 extern int phm_construct_table(struct pp_hwmgr *hwmgr,
 215                                const struct phm_master_table_header *master_table,
 216                                struct phm_runtime_table_header *rt_table);
 217
 218 extern int phm_destroy_table(struct pp_hwmgr *hwmgr,
 219                              struct phm_runtime_table_header *rt_table);
 220
 221
 222 struct phm_uvd_clock_voltage_dependency_record {
 223         uint32_t vclk;
 224         uint32_t dclk;
 225         uint32_t v;
 226 };
 227
 228 struct phm_uvd_clock_voltage_dependency_table {
 229         uint8_t count;
 230         struct phm_uvd_clock_voltage_dependency_record entries[1];
 231 };
 232
 233 struct phm_acp_clock_voltage_dependency_record {
 234         uint32_t acpclk;
 235         uint32_t v;
 236 };
 237
 238 struct phm_acp_clock_voltage_dependency_table {
 239         uint32_t count;
 240         struct phm_acp_clock_voltage_dependency_record entries[1];
 241 };
 242
 243 struct phm_vce_clock_voltage_dependency_record {
 244         uint32_t ecclk;
 245         uint32_t evclk;
 246         uint32_t v;
 247 };
 248
 249 struct phm_phase_shedding_limits_table {
 250         uint32_t                           count;
 251         struct phm_phase_shedding_limits_record  entries[1];
 252 };
 253
 254 struct phm_vceclock_voltage_dependency_table {
 255         uint8_t count;                                    /* Number of entries. */
 256         struct phm_vceclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
 257 };
 258
 259 struct phm_uvdclock_voltage_dependency_table {
 260         uint8_t count;                                    /* Number of entries. */
 261         struct phm_uvdclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
 262 };
 263
 264 struct phm_samuclock_voltage_dependency_table {
 265         uint8_t count;                                    /* Number of entries. */
 266         struct phm_samuclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
 267 };
 268
 269 struct phm_acpclock_voltage_dependency_table {
 270         uint32_t count;                                    /* Number of entries. */
 271         struct phm_acpclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
 272 };
 273
 274 struct phm_vce_clock_voltage_dependency_table {
 275         uint8_t count;
 276         struct phm_vce_clock_voltage_dependency_record entries[1];
 277 };
 278
 279 struct pp_hwmgr_func {
 280         int (*backend_init)(struct pp_hwmgr *hw_mgr);
 281         int (*backend_fini)(struct pp_hwmgr *hw_mgr);
 282         int (*asic_setup)(struct pp_hwmgr *hw_mgr);
 283         int (*get_power_state_size)(struct pp_hwmgr *hw_mgr);
 284
 285         int (*apply_state_adjust_rules)(struct pp_hwmgr *hwmgr,
 286                                 struct pp_power_state  *prequest_ps,
 287                         const struct pp_power_state *pcurrent_ps);
 288
 289         int (*force_dpm_level)(struct pp_hwmgr *hw_mgr,
 290                                         enum amd_dpm_forced_level level);
 291
 292         int (*dynamic_state_management_enable)(
 293                                                 struct pp_hwmgr *hw_mgr);
 294         int (*dynamic_state_management_disable)(
 295                                                 struct pp_hwmgr *hw_mgr);
 296
 297         int (*patch_boot_state)(struct pp_hwmgr *hwmgr,
 298                                      struct pp_hw_power_state *hw_ps);
 299
 300         int (*get_pp_table_entry)(struct pp_hwmgr *hwmgr,
 301                             unsigned long, struct pp_power_state *);
 302         int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr);
 303         int (*powerdown_uvd)(struct pp_hwmgr *hwmgr);
 304         int (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate);
 305         int (*powergate_uvd)(struct pp_hwmgr *hwmgr, bool bgate);
 306         int (*get_mclk)(struct pp_hwmgr *hwmgr, bool low);
 307         int (*get_sclk)(struct pp_hwmgr *hwmgr, bool low);
 308         int (*power_state_set)(struct pp_hwmgr *hwmgr,
 309                                                 const void *state);
 310         void (*print_current_perforce_level)(struct pp_hwmgr *hwmgr,
 311                                                         struct seq_file *m);
 312         int (*enable_clock_power_gating)(struct pp_hwmgr *hwmgr);
 313         int (*notify_smc_display_config_after_ps_adjustment)(struct pp_hwmgr *hwmgr);
 314         int (*display_config_changed)(struct pp_hwmgr *hwmgr);
 315         int (*disable_clock_power_gating)(struct pp_hwmgr *hwmgr);
 316         int (*update_clock_gatings)(struct pp_hwmgr *hwmgr,
 317                                                 const uint32_t *msg_id);
 318         int (*set_max_fan_rpm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
 319         int (*set_max_fan_pwm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
 320         int (*get_temperature)(struct pp_hwmgr *hwmgr);
 321         int (*stop_thermal_controller)(struct pp_hwmgr *hwmgr);
 322         int (*get_fan_speed_info)(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info);
 323         int (*set_fan_control_mode)(struct pp_hwmgr *hwmgr, uint32_t mode);
 324         int (*get_fan_control_mode)(struct pp_hwmgr *hwmgr);
 325         int (*set_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t percent);
 326         int (*get_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t *speed);
 327         int (*set_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t percent);
 328         int (*get_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t *speed);
 329         int (*reset_fan_speed_to_default)(struct pp_hwmgr *hwmgr);
 330         int (*uninitialize_thermal_controller)(struct pp_hwmgr *hwmgr);
 331         int (*register_internal_thermal_interrupt)(struct pp_hwmgr *hwmgr,
 332                                         const void *thermal_interrupt_info);
 333         bool (*check_smc_update_required_for_display_configuration)(struct pp_hwmgr *hwmgr);
 334         int (*check_states_equal)(struct pp_hwmgr *hwmgr,
 335                                         const struct pp_hw_power_state *pstate1,
 336                                         const struct pp_hw_power_state *pstate2,
 337                                         bool *equal);
 338         int (*set_cpu_power_state)(struct pp_hwmgr *hwmgr);
 339         int (*store_cc6_data)(struct pp_hwmgr *hwmgr, uint32_t separation_time,
 340                                 bool cc6_disable, bool pstate_disable,
 341                                 bool pstate_switch_disable);
 342         int (*get_dal_power_level)(struct pp_hwmgr *hwmgr,
 343                         struct amd_pp_simple_clock_info *info);
 344         int (*get_performance_level)(struct pp_hwmgr *, const struct pp_hw_power_state *,
 345                         PHM_PerformanceLevelDesignation, uint32_t, PHM_PerformanceLevel *);
 346         int (*get_current_shallow_sleep_clocks)(struct pp_hwmgr *hwmgr,
 347                                 const struct pp_hw_power_state *state, struct pp_clock_info *clock_info);
 348         int (*get_clock_by_type)(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks);
 349         int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
 350         int (*power_off_asic)(struct pp_hwmgr *hwmgr);
 351         int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask);
 352         int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf);
 353         int (*enable_per_cu_power_gating)(struct pp_hwmgr *hwmgr, bool enable);
 354         int (*get_sclk_od)(struct pp_hwmgr *hwmgr);
 355         int (*set_sclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
 356         int (*get_mclk_od)(struct pp_hwmgr *hwmgr);
 357         int (*set_mclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
 358 };
 359
 360 struct pp_table_func {
 361         int (*pptable_init)(struct pp_hwmgr *hw_mgr);
 362         int (*pptable_fini)(struct pp_hwmgr *hw_mgr);
 363         int (*pptable_get_number_of_vce_state_table_entries)(struct pp_hwmgr *hw_mgr);
 364         int (*pptable_get_vce_state_table_entry)(
 365                                                 struct pp_hwmgr *hwmgr,
 366                                                 unsigned long i,
 367                                                 struct pp_vce_state *vce_state,
 368                                                 void **clock_info,
 369                                                 unsigned long *flag);
 370 };
 371
 372 union phm_cac_leakage_record {
 373         struct {
 374                 uint16_t Vddc;          /* in CI, we use it for StdVoltageHiSidd */
 375                 uint32_t Leakage;       /* in CI, we use it for StdVoltageLoSidd */
 376         };
 377         struct {
 378                 uint16_t Vddc1;
 379                 uint16_t Vddc2;
 380                 uint16_t Vddc3;
 381         };
 382 };
 383
 384 struct phm_cac_leakage_table {
 385         uint32_t count;
 386         union phm_cac_leakage_record entries[1];
 387 };
 388
 389 struct phm_samu_clock_voltage_dependency_record {
 390         uint32_t samclk;
 391         uint32_t v;
 392 };
 393
 394
 395 struct phm_samu_clock_voltage_dependency_table {
 396         uint8_t count;
 397         struct phm_samu_clock_voltage_dependency_record entries[1];
 398 };
 399
 400 struct phm_cac_tdp_table {
 401         uint16_t usTDP;
 402         uint16_t usConfigurableTDP;
 403         uint16_t usTDC;
 404         uint16_t usBatteryPowerLimit;
 405         uint16_t usSmallPowerLimit;
 406         uint16_t usLowCACLeakage;
 407         uint16_t usHighCACLeakage;
 408         uint16_t usMaximumPowerDeliveryLimit;
 409         uint16_t usOperatingTempMinLimit;
 410         uint16_t usOperatingTempMaxLimit;
 411         uint16_t usOperatingTempStep;
 412         uint16_t usOperatingTempHyst;
 413         uint16_t usDefaultTargetOperatingTemp;
 414         uint16_t usTargetOperatingTemp;
 415         uint16_t usPowerTuneDataSetID;
 416         uint16_t usSoftwareShutdownTemp;
 417         uint16_t usClockStretchAmount;
 418         uint16_t usTemperatureLimitHotspot;
 419         uint16_t usTemperatureLimitLiquid1;
 420         uint16_t usTemperatureLimitLiquid2;
 421         uint16_t usTemperatureLimitVrVddc;
 422         uint16_t usTemperatureLimitVrMvdd;
 423         uint16_t usTemperatureLimitPlx;
 424         uint8_t  ucLiquid1_I2C_address;
 425         uint8_t  ucLiquid2_I2C_address;
 426         uint8_t  ucLiquid_I2C_Line;
 427         uint8_t  ucVr_I2C_address;
 428         uint8_t  ucVr_I2C_Line;
 429         uint8_t  ucPlx_I2C_address;
 430         uint8_t  ucPlx_I2C_Line;
 431         uint32_t usBoostPowerLimit;
 432         uint8_t  ucCKS_LDO_REFSEL;
 433 };
 434
 435 struct phm_ppm_table {
 436         uint8_t   ppm_design;
 437         uint16_t  cpu_core_number;
 438         uint32_t  platform_tdp;
 439         uint32_t  small_ac_platform_tdp;
 440         uint32_t  platform_tdc;
 441         uint32_t  small_ac_platform_tdc;
 442         uint32_t  apu_tdp;
 443         uint32_t  dgpu_tdp;
 444         uint32_t  dgpu_ulv_power;
 445         uint32_t  tj_max;
 446 };
 447
 448 struct phm_vq_budgeting_record {
 449         uint32_t ulCUs;
 450         uint32_t ulSustainableSOCPowerLimitLow;
 451         uint32_t ulSustainableSOCPowerLimitHigh;
 452         uint32_t ulMinSclkLow;
 453         uint32_t ulMinSclkHigh;
 454         uint8_t  ucDispConfig;
 455         uint32_t ulDClk;
 456         uint32_t ulEClk;
 457         uint32_t ulSustainableSclk;
 458         uint32_t ulSustainableCUs;
 459 };
 460
 461 struct phm_vq_budgeting_table {
 462         uint8_t numEntries;
 463         struct phm_vq_budgeting_record entries[1];
 464 };
 465
 466 struct phm_clock_and_voltage_limits {
 467         uint32_t sclk;
 468         uint32_t mclk;
 469         uint16_t vddc;
 470         uint16_t vddci;
 471         uint16_t vddgfx;
 472 };
 473
 474 /* Structure to hold PPTable information */
 475
 476 struct phm_ppt_v1_information {
 477         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
 478         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
 479         struct phm_clock_array *valid_sclk_values;
 480         struct phm_clock_array *valid_mclk_values;
 481         struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
 482         struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
 483         struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
 484         struct phm_ppm_table *ppm_parameter_table;
 485         struct phm_cac_tdp_table *cac_dtp_table;
 486         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
 487         struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
 488         struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
 489         struct phm_ppt_v1_pcie_table *pcie_table;
 490         uint16_t us_ulv_voltage_offset;
 491 };
 492
 493 struct phm_dynamic_state_info {
 494         struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk;
 495         struct phm_clock_voltage_dependency_table *vddci_dependency_on_mclk;
 496         struct phm_clock_voltage_dependency_table *vddc_dependency_on_mclk;
 497         struct phm_clock_voltage_dependency_table *mvdd_dependency_on_mclk;
 498         struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
 499         struct phm_clock_array                    *valid_sclk_values;
 500         struct phm_clock_array                    *valid_mclk_values;
 501         struct phm_clock_and_voltage_limits       max_clock_voltage_on_dc;
 502         struct phm_clock_and_voltage_limits       max_clock_voltage_on_ac;
 503         uint32_t                                  mclk_sclk_ratio;
 504         uint32_t                                  sclk_mclk_delta;
 505         uint32_t                                  vddc_vddci_delta;
 506         uint32_t                                  min_vddc_for_pcie_gen2;
 507         struct phm_cac_leakage_table              *cac_leakage_table;
 508         struct phm_phase_shedding_limits_table    *vddc_phase_shed_limits_table;
 509
 510         struct phm_vce_clock_voltage_dependency_table
 511                                             *vce_clock_voltage_dependency_table;
 512         struct phm_uvd_clock_voltage_dependency_table
 513                                             *uvd_clock_voltage_dependency_table;
 514         struct phm_acp_clock_voltage_dependency_table
 515                                             *acp_clock_voltage_dependency_table;
 516         struct phm_samu_clock_voltage_dependency_table
 517                                            *samu_clock_voltage_dependency_table;
 518
 519         struct phm_ppm_table                          *ppm_parameter_table;
 520         struct phm_cac_tdp_table                      *cac_dtp_table;
 521         struct phm_clock_voltage_dependency_table         *vdd_gfx_dependency_on_sclk;
 522         struct phm_vq_budgeting_table                             *vq_budgeting_table;
 523 };
 524
 525 struct pp_fan_info {
 526         bool bNoFan;
 527         uint8_t   ucTachometerPulsesPerRevolution;
 528         uint32_t   ulMinRPM;
 529         uint32_t   ulMaxRPM;
 530 };
 531
 532 struct pp_advance_fan_control_parameters {
 533         uint16_t  usTMin;                          /* The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. */
 534         uint16_t  usTMed;                          /* The middle temperature where we change slopes. */
 535         uint16_t  usTHigh;                         /* The high temperature for setting the second slope. */
 536         uint16_t  usPWMMin;                        /* The minimum PWM value in percent (0.01% increments). */
 537         uint16_t  usPWMMed;                        /* The PWM value (in percent) at TMed. */
 538         uint16_t  usPWMHigh;                       /* The PWM value at THigh. */
 539         uint8_t   ucTHyst;                         /* Temperature hysteresis. Integer. */
 540         uint32_t   ulCycleDelay;                   /* The time between two invocations of the fan control routine in microseconds. */
 541         uint16_t  usTMax;                          /* The max temperature */
 542         uint8_t   ucFanControlMode;
 543         uint16_t  usFanPWMMinLimit;
 544         uint16_t  usFanPWMMaxLimit;
 545         uint16_t  usFanPWMStep;
 546         uint16_t  usDefaultMaxFanPWM;
 547         uint16_t  usFanOutputSensitivity;
 548         uint16_t  usDefaultFanOutputSensitivity;
 549         uint16_t  usMaxFanPWM;                     /* The max Fan PWM value for Fuzzy Fan Control feature */
 550         uint16_t  usFanRPMMinLimit;                /* Minimum limit range in percentage, need to calculate based on minRPM/MaxRpm */
 551         uint16_t  usFanRPMMaxLimit;                /* Maximum limit range in percentage, usually set to 100% by default */
 552         uint16_t  usFanRPMStep;                    /* Step increments/decerements, in percent */
 553         uint16_t  usDefaultMaxFanRPM;              /* The max Fan RPM value for Fuzzy Fan Control feature, default from PPTable */
 554         uint16_t  usMaxFanRPM;                     /* The max Fan RPM value for Fuzzy Fan Control feature, user defined */
 555         uint16_t  usFanCurrentLow;                 /* Low current */
 556         uint16_t  usFanCurrentHigh;                /* High current */
 557         uint16_t  usFanRPMLow;                     /* Low RPM */
 558         uint16_t  usFanRPMHigh;                    /* High RPM */
 559         uint32_t   ulMinFanSCLKAcousticLimit;      /* Minimum Fan Controller SCLK Frequency Acoustic Limit. */
 560         uint8_t   ucTargetTemperature;             /* Advanced fan controller target temperature. */
 561         uint8_t   ucMinimumPWMLimit;               /* The minimum PWM that the advanced fan controller can set.  This should be set to the highest PWM that will run the fan at its lowest RPM. */
 562         uint16_t  usFanGainEdge;                   /* The following is added for Fiji */
 563         uint16_t  usFanGainHotspot;
 564         uint16_t  usFanGainLiquid;
 565         uint16_t  usFanGainVrVddc;
 566         uint16_t  usFanGainVrMvdd;
 567         uint16_t  usFanGainPlx;
 568         uint16_t  usFanGainHbm;
 569 };
 570
 571 struct pp_thermal_controller_info {
 572         uint8_t ucType;
 573         uint8_t ucI2cLine;
 574         uint8_t ucI2cAddress;
 575         struct pp_fan_info fanInfo;
 576         struct pp_advance_fan_control_parameters advanceFanControlParameters;
 577 };
 578
 579 struct phm_microcode_version_info {
 580         uint32_t SMC;
 581         uint32_t DMCU;
 582         uint32_t MC;
 583         uint32_t NB;
 584 };
 585
 586 #define PP_MAX_VCE_LEVELS 6
 587
 588 enum PP_VCE_LEVEL {
 589         PP_VCE_LEVEL_AC_ALL = 0,     /* AC, All cases */
 590         PP_VCE_LEVEL_DC_EE = 1,      /* DC, entropy encoding */
 591         PP_VCE_LEVEL_DC_LL_LOW = 2,  /* DC, low latency queue, res <= 720 */
 592         PP_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
 593         PP_VCE_LEVEL_DC_GP_LOW = 4,  /* DC, general purpose queue, res <= 720 */
 594         PP_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
 595 };
 596
 597
 598 /**
 599  * The main hardware manager structure.
 600  */
 601 struct pp_hwmgr {
 602         uint32_t chip_family;
 603         uint32_t chip_id;
 604
 605         void *device;
 606         struct pp_smumgr *smumgr;
 607         const void *soft_pp_table;
 608         uint32_t soft_pp_table_size;
 609         void *hardcode_pp_table;
 610         bool need_pp_table_upload;
 611
 612         struct pp_vce_state vce_states[PP_MAX_VCE_LEVELS];
 613         uint32_t num_vce_state_tables;
 614
 615         enum amd_dpm_forced_level dpm_level;
 616         bool block_hw_access;
 617         struct phm_gfx_arbiter gfx_arbiter;
 618         struct phm_acp_arbiter acp_arbiter;
 619         struct phm_uvd_arbiter uvd_arbiter;
 620         struct phm_vce_arbiter vce_arbiter;
 621         uint32_t usec_timeout;
 622         void *pptable;
 623         struct phm_platform_descriptor platform_descriptor;
 624         void *backend;
 625         enum PP_DAL_POWERLEVEL dal_power_level;
 626         struct phm_dynamic_state_info dyn_state;
 627         struct phm_runtime_table_header setup_asic;
 628         struct phm_runtime_table_header power_down_asic;
 629         struct phm_runtime_table_header disable_dynamic_state_management;
 630         struct phm_runtime_table_header enable_dynamic_state_management;
 631         struct phm_runtime_table_header set_power_state;
 632         struct phm_runtime_table_header enable_clock_power_gatings;
 633         struct phm_runtime_table_header display_configuration_changed;
 634         struct phm_runtime_table_header start_thermal_controller;
 635         struct phm_runtime_table_header set_temperature_range;
 636         const struct pp_hwmgr_func *hwmgr_func;
 637         const struct pp_table_func *pptable_func;
 638         struct pp_power_state    *ps;
 639         enum pp_power_source  power_source;
 640         uint32_t num_ps;
 641         struct pp_thermal_controller_info thermal_controller;
 642         bool fan_ctrl_is_in_default_mode;
 643         uint32_t fan_ctrl_default_mode;
 644         uint32_t tmin;
 645         struct phm_microcode_version_info microcode_version_info;
 646         uint32_t ps_size;
 647         struct pp_power_state    *current_ps;
 648         struct pp_power_state    *request_ps;
 649         struct pp_power_state    *boot_ps;
 650         struct pp_power_state    *uvd_ps;
 651         struct amd_pp_display_configuration display_config;
 652         uint32_t feature_mask;
 653 };
 654
 655
 656 extern int hwmgr_init(struct amd_pp_init *pp_init,
 657                       struct pp_instance *handle);
 658
 659 extern int hwmgr_fini(struct pp_hwmgr *hwmgr);
 660
 661 extern int hw_init_power_state_table(struct pp_hwmgr *hwmgr);
 662
 663 extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
 664                                 uint32_t value, uint32_t mask);
 665
 666
 667
 668 extern void phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
 669                                 uint32_t indirect_port,
 670                                 uint32_t index,
 671                                 uint32_t value,
 672                                 uint32_t mask);
 673
 674
 675
 676 extern bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr);
 677 extern bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr);
 678 extern bool phm_cf_want_microcode_fan_ctrl(struct pp_hwmgr *hwmgr);
 679
 680 extern int phm_trim_voltage_table(struct pp_atomctrl_voltage_table *vol_table);
 681 extern int phm_get_svi2_mvdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table);
 682 extern int phm_get_svi2_vddci_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table);
 683 extern int phm_get_svi2_vdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_voltage_lookup_table *lookup_table);
 684 extern void phm_trim_voltage_table_to_fit_state_table(uint32_t max_vol_steps, struct pp_atomctrl_voltage_table *vol_table);
 685 extern int phm_reset_single_dpm_table(void *table, uint32_t count, int max);
 686 extern void phm_setup_pcie_table_entry(void *table, uint32_t index, uint32_t pcie_gen, uint32_t pcie_lanes);
 687 extern int32_t phm_get_dpm_level_enable_mask_value(void *table);
 688 extern uint8_t phm_get_voltage_id(struct pp_atomctrl_voltage_table *voltage_table,
 689                 uint32_t voltage);
 690 extern uint8_t phm_get_voltage_index(struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage);
 691 extern uint16_t phm_find_closest_vddci(struct pp_atomctrl_voltage_table *vddci_table, uint16_t vddci);
 692 extern int phm_find_boot_level(void *table, uint32_t value, uint32_t *boot_level);
 693 extern int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr, phm_ppt_v1_voltage_lookup_table *lookup_table,
 694                                                                 uint16_t virtual_voltage_id, int32_t *sclk);
 695 extern int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr);
 696 extern int phm_hwmgr_backend_fini(struct pp_hwmgr *hwmgr);
 697 extern uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask);
 698 extern void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr);
 699
 700 extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
 701                                 uint32_t sclk, uint16_t id, uint16_t *voltage);
 702
 703 #define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU
 704
 705 #define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
 706 #define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK
 707
 708 #define PHM_SET_FIELD(origval, reg, field, fieldval)    \
 709         (((origval) & ~PHM_FIELD_MASK(reg, field)) |    \
 710          (PHM_FIELD_MASK(reg, field) & ((fieldval) << PHM_FIELD_SHIFT(reg, field))))
 711
 712 #define PHM_GET_FIELD(value, reg, field)        \
 713         (((value) & PHM_FIELD_MASK(reg, field)) >>      \
 714          PHM_FIELD_SHIFT(reg, field))
 715
 716
 717 /* Operations on named fields. */
 718
 719 #define PHM_READ_FIELD(device, reg, field)      \
 720         PHM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field)
 721
 722 #define PHM_READ_INDIRECT_FIELD(device, port, reg, field)       \
 723         PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg),     \
 724                         reg, field)
 725
 726 #define PHM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field)  \
 727         PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg),     \
 728                         reg, field)
 729
 730 #define PHM_WRITE_FIELD(device, reg, field, fieldval)   \
 731         cgs_write_register(device, mm##reg, PHM_SET_FIELD(      \
 732                                 cgs_read_register(device, mm##reg), reg, field, fieldval))
 733
 734 #define PHM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval)    \
 735         cgs_write_ind_register(device, port, ix##reg,   \
 736                         PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg),     \
 737                                 reg, field, fieldval))
 738
 739 #define PHM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval)       \
 740         cgs_write_ind_register(device, port, ix##reg,   \
 741                         PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg),     \
 742                                 reg, field, fieldval))
 743
 744 #define PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask)        \
 745        phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX, index, value, mask)
 746
 747
 748 #define PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask)      \
 749        PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
 750
 751 #define PHM_WAIT_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval)      \
 752         PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \
 753                         << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
 754
 755
 756 #endif /* _HWMGR_H_ */