drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef SMU74_DISCRETE_H
  25 #define SMU74_DISCRETE_H
  26
  27 #include "smu74.h"
  28
  29 #pragma pack(push, 1)
  30
  31
  32 #define NUM_SCLK_RANGE 8
  33
  34 #define VCO_3_6 1
  35 #define VCO_2_4 3
  36
  37 #define POSTDIV_DIV_BY_1  0
  38 #define POSTDIV_DIV_BY_2  1
  39 #define POSTDIV_DIV_BY_4  2
  40 #define POSTDIV_DIV_BY_8  3
  41 #define POSTDIV_DIV_BY_16 4
  42
  43 struct sclkFcwRange_t {
  44         uint8_t  vco_setting;
  45         uint8_t  postdiv;
  46         uint16_t fcw_pcc;
  47
  48         uint16_t fcw_trans_upper;
  49         uint16_t fcw_trans_lower;
  50 };
  51 typedef struct sclkFcwRange_t sclkFcwRange_t;
  52
  53 struct SMIO_Pattern {
  54         uint16_t Voltage;
  55         uint8_t  Smio;
  56         uint8_t  padding;
  57 };
  58
  59 typedef struct SMIO_Pattern SMIO_Pattern;
  60
  61 struct SMIO_Table {
  62         SMIO_Pattern Pattern[SMU_MAX_SMIO_LEVELS];
  63 };
  64
  65 typedef struct SMIO_Table SMIO_Table;
  66
  67 struct SMU_SclkSetting {
  68         uint32_t    SclkFrequency;
  69         uint16_t    Fcw_int;
  70         uint16_t    Fcw_frac;
  71         uint16_t    Pcc_fcw_int;
  72         uint8_t     PllRange;
  73         uint8_t     SSc_En;
  74         uint16_t    Sclk_slew_rate;
  75         uint16_t    Pcc_up_slew_rate;
  76         uint16_t    Pcc_down_slew_rate;
  77         uint16_t    Fcw1_int;
  78         uint16_t    Fcw1_frac;
  79         uint16_t    Sclk_ss_slew_rate;
  80 };
  81 typedef struct SMU_SclkSetting SMU_SclkSetting;
  82
  83 struct SMU74_Discrete_GraphicsLevel {
  84         SMU_VoltageLevel MinVoltage;
  85         uint8_t     pcieDpmLevel;
  86         uint8_t     DeepSleepDivId;
  87         uint16_t    ActivityLevel;
  88         uint32_t    CgSpllFuncCntl3;
  89         uint32_t    CgSpllFuncCntl4;
  90         uint32_t    CcPwrDynRm;
  91         uint32_t    CcPwrDynRm1;
  92         uint8_t     SclkDid;
  93         uint8_t     padding;
  94         uint8_t     EnabledForActivity;
  95         uint8_t     EnabledForThrottle;
  96         uint8_t     UpHyst;
  97         uint8_t     DownHyst;
  98         uint8_t     VoltageDownHyst;
  99         uint8_t     PowerThrottle;
 100         SMU_SclkSetting SclkSetting;
 101 };
 102
 103 typedef struct SMU74_Discrete_GraphicsLevel SMU74_Discrete_GraphicsLevel;
 104
 105 struct SMU74_Discrete_ACPILevel {
 106         uint32_t    Flags;
 107         SMU_VoltageLevel MinVoltage;
 108         uint32_t    SclkFrequency;
 109         uint8_t     SclkDid;
 110         uint8_t     DisplayWatermark;
 111         uint8_t     DeepSleepDivId;
 112         uint8_t     padding;
 113         uint32_t    CcPwrDynRm;
 114         uint32_t    CcPwrDynRm1;
 115
 116         SMU_SclkSetting SclkSetting;
 117 };
 118
 119 typedef struct SMU74_Discrete_ACPILevel SMU74_Discrete_ACPILevel;
 120
 121 struct SMU74_Discrete_Ulv {
 122         uint32_t    CcPwrDynRm;
 123         uint32_t    CcPwrDynRm1;
 124         uint16_t    VddcOffset;
 125         uint8_t     VddcOffsetVid;
 126         uint8_t     VddcPhase;
 127         uint16_t    BifSclkDfs;
 128         uint16_t    Reserved;
 129 };
 130
 131 typedef struct SMU74_Discrete_Ulv SMU74_Discrete_Ulv;
 132
 133 struct SMU74_Discrete_MemoryLevel {
 134         SMU_VoltageLevel MinVoltage;
 135         uint32_t    MinMvdd;
 136
 137         uint32_t    MclkFrequency;
 138
 139         uint8_t     StutterEnable;
 140         uint8_t     EnabledForThrottle;
 141         uint8_t     EnabledForActivity;
 142         uint8_t     padding_0;
 143
 144         uint8_t     UpHyst;
 145         uint8_t     DownHyst;
 146         uint8_t     VoltageDownHyst;
 147         uint8_t     padding_1;
 148
 149         uint16_t    ActivityLevel;
 150         uint8_t     DisplayWatermark;
 151         uint8_t     Reserved;
 152 };
 153
 154 typedef struct SMU74_Discrete_MemoryLevel SMU74_Discrete_MemoryLevel;
 155
 156 struct SMU74_Discrete_LinkLevel {
 157         uint8_t     PcieGenSpeed;
 158         uint8_t     PcieLaneCount;
 159         uint8_t     EnabledForActivity;
 160         uint8_t     SPC;
 161         uint32_t    DownThreshold;
 162         uint32_t    UpThreshold;
 163         uint16_t    BifSclkDfs;
 164         uint16_t    Reserved;
 165 };
 166
 167 typedef struct SMU74_Discrete_LinkLevel SMU74_Discrete_LinkLevel;
 168
 169 struct SMU74_Discrete_MCArbDramTimingTableEntry {
 170         uint32_t McArbDramTiming;
 171         uint32_t McArbDramTiming2;
 172         uint8_t  McArbBurstTime;
 173         uint8_t  padding[3];
 174 };
 175
 176 typedef struct SMU74_Discrete_MCArbDramTimingTableEntry SMU74_Discrete_MCArbDramTimingTableEntry;
 177
 178 struct SMU74_Discrete_MCArbDramTimingTable {
 179         SMU74_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
 180 };
 181
 182 typedef struct SMU74_Discrete_MCArbDramTimingTable SMU74_Discrete_MCArbDramTimingTable;
 183
 184 struct SMU74_Discrete_UvdLevel {
 185         uint32_t VclkFrequency;
 186         uint32_t DclkFrequency;
 187         SMU_VoltageLevel MinVoltage;
 188         uint8_t  VclkDivider;
 189         uint8_t  DclkDivider;
 190         uint8_t  padding[2];
 191 };
 192
 193 typedef struct SMU74_Discrete_UvdLevel SMU74_Discrete_UvdLevel;
 194
 195 struct SMU74_Discrete_ExtClkLevel {
 196         uint32_t Frequency;
 197         SMU_VoltageLevel MinVoltage;
 198         uint8_t  Divider;
 199         uint8_t  padding[3];
 200 };
 201
 202 typedef struct SMU74_Discrete_ExtClkLevel SMU74_Discrete_ExtClkLevel;
 203
 204 struct SMU74_Discrete_StateInfo {
 205         uint32_t SclkFrequency;
 206         uint32_t MclkFrequency;
 207         uint32_t VclkFrequency;
 208         uint32_t DclkFrequency;
 209         uint32_t SamclkFrequency;
 210         uint32_t AclkFrequency;
 211         uint32_t EclkFrequency;
 212         uint16_t MvddVoltage;
 213         uint16_t padding16;
 214         uint8_t  DisplayWatermark;
 215         uint8_t  McArbIndex;
 216         uint8_t  McRegIndex;
 217         uint8_t  SeqIndex;
 218         uint8_t  SclkDid;
 219         int8_t   SclkIndex;
 220         int8_t   MclkIndex;
 221         uint8_t  PCIeGen;
 222 };
 223
 224 typedef struct SMU74_Discrete_StateInfo SMU74_Discrete_StateInfo;
 225
 226 struct SMU74_Discrete_DpmTable {
 227
 228         SMU74_PIDController                  GraphicsPIDController;
 229         SMU74_PIDController                  MemoryPIDController;
 230         SMU74_PIDController                  LinkPIDController;
 231
 232         uint32_t                            SystemFlags;
 233
 234         uint32_t                            VRConfig;
 235         uint32_t                            SmioMask1;
 236         uint32_t                            SmioMask2;
 237         SMIO_Table                          SmioTable1;
 238         SMIO_Table                          SmioTable2;
 239
 240         uint32_t                            MvddLevelCount;
 241
 242
 243         uint8_t                             BapmVddcVidHiSidd[SMU74_MAX_LEVELS_VDDC];
 244         uint8_t                             BapmVddcVidLoSidd[SMU74_MAX_LEVELS_VDDC];
 245         uint8_t                             BapmVddcVidHiSidd2[SMU74_MAX_LEVELS_VDDC];
 246
 247         uint8_t                             GraphicsDpmLevelCount;
 248         uint8_t                             MemoryDpmLevelCount;
 249         uint8_t                             LinkLevelCount;
 250         uint8_t                             MasterDeepSleepControl;
 251
 252         uint8_t                             UvdLevelCount;
 253         uint8_t                             VceLevelCount;
 254         uint8_t                             AcpLevelCount;
 255         uint8_t                             SamuLevelCount;
 256
 257         uint8_t                             ThermOutGpio;
 258         uint8_t                             ThermOutPolarity;
 259         uint8_t                             ThermOutMode;
 260         uint8_t                             BootPhases;
 261         uint32_t                            Reserved[4];
 262
 263         SMU74_Discrete_GraphicsLevel        GraphicsLevel[SMU74_MAX_LEVELS_GRAPHICS];
 264         SMU74_Discrete_MemoryLevel          MemoryACPILevel;
 265         SMU74_Discrete_MemoryLevel          MemoryLevel[SMU74_MAX_LEVELS_MEMORY];
 266         SMU74_Discrete_LinkLevel            LinkLevel[SMU74_MAX_LEVELS_LINK];
 267         SMU74_Discrete_ACPILevel            ACPILevel;
 268         SMU74_Discrete_UvdLevel             UvdLevel[SMU74_MAX_LEVELS_UVD];
 269         SMU74_Discrete_ExtClkLevel          VceLevel[SMU74_MAX_LEVELS_VCE];
 270         SMU74_Discrete_ExtClkLevel          AcpLevel[SMU74_MAX_LEVELS_ACP];
 271         SMU74_Discrete_ExtClkLevel          SamuLevel[SMU74_MAX_LEVELS_SAMU];
 272         SMU74_Discrete_Ulv                  Ulv;
 273
 274         uint8_t                             DisplayWatermark[SMU74_MAX_LEVELS_MEMORY][SMU74_MAX_LEVELS_GRAPHICS];
 275
 276         uint32_t                            SclkStepSize;
 277         uint32_t                            Smio[SMU74_MAX_ENTRIES_SMIO];
 278
 279         uint8_t                             UvdBootLevel;
 280         uint8_t                             VceBootLevel;
 281         uint8_t                             AcpBootLevel;
 282         uint8_t                             SamuBootLevel;
 283
 284         uint8_t                             GraphicsBootLevel;
 285         uint8_t                             GraphicsVoltageChangeEnable;
 286         uint8_t                             GraphicsThermThrottleEnable;
 287         uint8_t                             GraphicsInterval;
 288
 289         uint8_t                             VoltageInterval;
 290         uint8_t                             ThermalInterval;
 291         uint16_t                            TemperatureLimitHigh;
 292
 293         uint16_t                            TemperatureLimitLow;
 294         uint8_t                             MemoryBootLevel;
 295         uint8_t                             MemoryVoltageChangeEnable;
 296
 297         uint16_t                            BootMVdd;
 298         uint8_t                             MemoryInterval;
 299         uint8_t                             MemoryThermThrottleEnable;
 300
 301         uint16_t                            VoltageResponseTime;
 302         uint16_t                            PhaseResponseTime;
 303
 304         uint8_t                             PCIeBootLinkLevel;
 305         uint8_t                             PCIeGenInterval;
 306         uint8_t                             DTEInterval;
 307         uint8_t                             DTEMode;
 308
 309         uint8_t                             SVI2Enable;
 310         uint8_t                             VRHotGpio;
 311         uint8_t                             AcDcGpio;
 312         uint8_t                             ThermGpio;
 313
 314         uint16_t                            PPM_PkgPwrLimit;
 315         uint16_t                            PPM_TemperatureLimit;
 316
 317         uint16_t                            DefaultTdp;
 318         uint16_t                            TargetTdp;
 319
 320         uint16_t                            FpsHighThreshold;
 321         uint16_t                            FpsLowThreshold;
 322
 323         uint16_t                            BAPMTI_R[SMU74_DTE_ITERATIONS][SMU74_DTE_SOURCES][SMU74_DTE_SINKS];
 324         uint16_t                            BAPMTI_RC[SMU74_DTE_ITERATIONS][SMU74_DTE_SOURCES][SMU74_DTE_SINKS];
 325
 326         uint16_t                            TemperatureLimitEdge;
 327         uint16_t                            TemperatureLimitHotspot;
 328
 329         uint16_t                            BootVddc;
 330         uint16_t                            BootVddci;
 331
 332         uint16_t                            FanGainEdge;
 333         uint16_t                            FanGainHotspot;
 334
 335         uint32_t                            LowSclkInterruptThreshold;
 336         uint32_t                            VddGfxReChkWait;
 337
 338         uint8_t                             ClockStretcherAmount;
 339         uint8_t                             Sclk_CKS_masterEn0_7;
 340         uint8_t                             Sclk_CKS_masterEn8_15;
 341         uint8_t                             DPMFreezeAndForced;
 342
 343         uint8_t                             Sclk_voltageOffset[8];
 344
 345         SMU_ClockStretcherDataTable         ClockStretcherDataTable;
 346         SMU_CKS_LOOKUPTable                 CKS_LOOKUPTable;
 347
 348         uint32_t                            CurrSclkPllRange;
 349         sclkFcwRange_t                      SclkFcwRangeTable[NUM_SCLK_RANGE];
 350 };
 351
 352 typedef struct SMU74_Discrete_DpmTable SMU74_Discrete_DpmTable;
 353
 354
 355 struct SMU74_Discrete_FanTable {
 356         uint16_t FdoMode;
 357         int16_t  TempMin;
 358         int16_t  TempMed;
 359         int16_t  TempMax;
 360         int16_t  Slope1;
 361         int16_t  Slope2;
 362         int16_t  FdoMin;
 363         int16_t  HystUp;
 364         int16_t  HystDown;
 365         int16_t  HystSlope;
 366         int16_t  TempRespLim;
 367         int16_t  TempCurr;
 368         int16_t  SlopeCurr;
 369         int16_t  PwmCurr;
 370         uint32_t RefreshPeriod;
 371         int16_t  FdoMax;
 372         uint8_t  TempSrc;
 373         int8_t   Padding;
 374 };
 375
 376 typedef struct SMU74_Discrete_FanTable SMU74_Discrete_FanTable;
 377
 378 #define SMU7_DISCRETE_GPIO_SCLK_DEBUG             4
 379 #define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT         (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG)
 380
 381
 382 struct SMU7_MclkDpmScoreboard {
 383         uint32_t PercentageBusy;
 384
 385         int32_t  PIDError;
 386         int32_t  PIDIntegral;
 387         int32_t  PIDOutput;
 388
 389         uint32_t SigmaDeltaAccum;
 390         uint32_t SigmaDeltaOutput;
 391         uint32_t SigmaDeltaLevel;
 392
 393         uint32_t UtilizationSetpoint;
 394
 395         uint8_t  TdpClampMode;
 396         uint8_t  TdcClampMode;
 397         uint8_t  ThermClampMode;
 398         uint8_t  VoltageBusy;
 399
 400         int8_t   CurrLevel;
 401         int8_t   TargLevel;
 402         uint8_t  LevelChangeInProgress;
 403         uint8_t  UpHyst;
 404
 405         uint8_t  DownHyst;
 406         uint8_t  VoltageDownHyst;
 407         uint8_t  DpmEnable;
 408         uint8_t  DpmRunning;
 409
 410         uint8_t  DpmForce;
 411         uint8_t  DpmForceLevel;
 412         uint8_t  padding2;
 413         uint8_t  McArbIndex;
 414
 415         uint32_t MinimumPerfMclk;
 416
 417         uint8_t  AcpiReq;
 418         uint8_t  AcpiAck;
 419         uint8_t  MclkSwitchInProgress;
 420         uint8_t  MclkSwitchCritical;
 421
 422         uint8_t  IgnoreVBlank;
 423         uint8_t  TargetMclkIndex;
 424         uint16_t VbiFailureCount;
 425         uint8_t  VbiWaitCounter;
 426         uint8_t  EnabledLevelsChange;
 427
 428         uint16_t LevelResidencyCounters[SMU74_MAX_LEVELS_MEMORY];
 429         uint16_t LevelSwitchCounters[SMU74_MAX_LEVELS_MEMORY];
 430
 431         void     (*TargetStateCalculator)(uint8_t);
 432         void     (*SavedTargetStateCalculator)(uint8_t);
 433
 434         uint16_t AutoDpmInterval;
 435         uint16_t AutoDpmRange;
 436
 437         uint16_t VbiTimeoutCount;
 438         uint16_t MclkSwitchingTime;
 439
 440         uint8_t  fastSwitch;
 441         uint8_t  Save_PIC_VDDGFX_EXIT;
 442         uint8_t  Save_PIC_VDDGFX_ENTER;
 443         uint8_t  padding;
 444 };
 445
 446 typedef struct SMU7_MclkDpmScoreboard SMU7_MclkDpmScoreboard;
 447
 448 struct SMU7_UlvScoreboard {
 449         uint8_t     EnterUlv;
 450         uint8_t     ExitUlv;
 451         uint8_t     UlvActive;
 452         uint8_t     WaitingForUlv;
 453         uint8_t     UlvEnable;
 454         uint8_t     UlvRunning;
 455         uint8_t     UlvMasterEnable;
 456         uint8_t     padding;
 457         uint32_t    UlvAbortedCount;
 458         uint32_t    UlvTimeStamp;
 459 };
 460
 461 typedef struct SMU7_UlvScoreboard SMU7_UlvScoreboard;
 462
 463 struct VddgfxSavedRegisters {
 464         uint32_t GPU_DBG[3];
 465         uint32_t MEC_BaseAddress_Hi;
 466         uint32_t MEC_BaseAddress_Lo;
 467         uint32_t THM_TMON0_CTRL2__RDIR_PRESENT;
 468         uint32_t THM_TMON1_CTRL2__RDIR_PRESENT;
 469         uint32_t CP_INT_CNTL;
 470 };
 471
 472 typedef struct VddgfxSavedRegisters VddgfxSavedRegisters;
 473
 474 struct SMU7_VddGfxScoreboard {
 475         uint8_t     VddGfxEnable;
 476         uint8_t     VddGfxActive;
 477         uint8_t     VPUResetOccured;
 478         uint8_t     padding;
 479
 480         uint32_t    VddGfxEnteredCount;
 481         uint32_t    VddGfxAbortedCount;
 482
 483         uint32_t    VddGfxVid;
 484
 485         VddgfxSavedRegisters SavedRegisters;
 486 };
 487
 488 typedef struct SMU7_VddGfxScoreboard SMU7_VddGfxScoreboard;
 489
 490 struct SMU7_TdcLimitScoreboard {
 491         uint8_t  Enable;
 492         uint8_t  Running;
 493         uint16_t Alpha;
 494         uint32_t FilteredIddc;
 495         uint32_t IddcLimit;
 496         uint32_t IddcHyst;
 497         SMU7_HystController_Data HystControllerData;
 498 };
 499
 500 typedef struct SMU7_TdcLimitScoreboard SMU7_TdcLimitScoreboard;
 501
 502 struct SMU7_PkgPwrLimitScoreboard {
 503         uint8_t  Enable;
 504         uint8_t  Running;
 505         uint16_t Alpha;
 506         uint32_t FilteredPkgPwr;
 507         uint32_t Limit;
 508         uint32_t Hyst;
 509         uint32_t LimitFromDriver;
 510         SMU7_HystController_Data HystControllerData;
 511 };
 512
 513 typedef struct SMU7_PkgPwrLimitScoreboard SMU7_PkgPwrLimitScoreboard;
 514
 515 struct SMU7_BapmScoreboard {
 516         uint32_t source_powers[SMU74_DTE_SOURCES];
 517         uint32_t source_powers_last[SMU74_DTE_SOURCES];
 518         int32_t entity_temperatures[SMU74_NUM_GPU_TES];
 519         int32_t initial_entity_temperatures[SMU74_NUM_GPU_TES];
 520         int32_t Limit;
 521         int32_t Hyst;
 522         int32_t therm_influence_coeff_table[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS * 2];
 523         int32_t therm_node_table[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS];
 524         uint16_t ConfigTDPPowerScalar;
 525         uint16_t FanSpeedPowerScalar;
 526         uint16_t OverDrivePowerScalar;
 527         uint16_t OverDriveLimitScalar;
 528         uint16_t FinalPowerScalar;
 529         uint8_t VariantID;
 530         uint8_t spare997;
 531
 532         SMU7_HystController_Data HystControllerData;
 533
 534         int32_t temperature_gradient_slope;
 535         int32_t temperature_gradient;
 536         uint32_t measured_temperature;
 537 };
 538
 539
 540 typedef struct SMU7_BapmScoreboard SMU7_BapmScoreboard;
 541
 542 struct SMU7_AcpiScoreboard {
 543         uint32_t SavedInterruptMask[2];
 544         uint8_t LastACPIRequest;
 545         uint8_t CgBifResp;
 546         uint8_t RequestType;
 547         uint8_t Padding;
 548         SMU74_Discrete_ACPILevel D0Level;
 549 };
 550
 551 typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard;
 552
 553 struct SMU_QuadraticCoeffs {
 554         int32_t m1;
 555         uint32_t b;
 556
 557         int16_t m2;
 558         uint8_t m1_shift;
 559         uint8_t m2_shift;
 560 };
 561 typedef struct SMU_QuadraticCoeffs SMU_QuadraticCoeffs;
 562
 563 struct SMU74_Discrete_PmFuses {
 564         uint8_t BapmVddCVidHiSidd[8];
 565         uint8_t BapmVddCVidLoSidd[8];
 566         uint8_t VddCVid[8];
 567         uint8_t SviLoadLineEn;
 568         uint8_t SviLoadLineVddC;
 569         uint8_t SviLoadLineTrimVddC;
 570         uint8_t SviLoadLineOffsetVddC;
 571         uint16_t TDC_VDDC_PkgLimit;
 572         uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
 573         uint8_t TDC_MAWt;
 574         uint8_t TdcWaterfallCtl;
 575         uint8_t LPMLTemperatureMin;
 576         uint8_t LPMLTemperatureMax;
 577         uint8_t Reserved;
 578
 579         uint8_t LPMLTemperatureScaler[16];
 580
 581         int16_t FuzzyFan_ErrorSetDelta;
 582         int16_t FuzzyFan_ErrorRateSetDelta;
 583         int16_t FuzzyFan_PwmSetDelta;
 584         uint16_t Reserved6;
 585
 586         uint8_t GnbLPML[16];
 587
 588         uint8_t GnbLPMLMaxVid;
 589         uint8_t GnbLPMLMinVid;
 590         uint8_t Reserved1[2];
 591
 592         uint16_t BapmVddCBaseLeakageHiSidd;
 593         uint16_t BapmVddCBaseLeakageLoSidd;
 594
 595         uint16_t  VFT_Temp[3];
 596         uint16_t  padding;
 597
 598         SMU_QuadraticCoeffs VFT_ATE[3];
 599
 600         SMU_QuadraticCoeffs AVFS_GB;
 601         SMU_QuadraticCoeffs ATE_ACBTC_GB;
 602
 603         SMU_QuadraticCoeffs P2V;
 604
 605         uint32_t PsmCharzFreq;
 606
 607         uint16_t InversionVoltage;
 608         uint16_t PsmCharzTemp;
 609
 610         uint32_t EnabledAvfsModules;
 611 };
 612
 613 typedef struct SMU74_Discrete_PmFuses SMU74_Discrete_PmFuses;
 614
 615 struct SMU7_Discrete_Log_Header_Table {
 616         uint32_t    version;
 617         uint32_t    asic_id;
 618         uint16_t    flags;
 619         uint16_t    entry_size;
 620         uint32_t    total_size;
 621         uint32_t    num_of_entries;
 622         uint8_t     type;
 623         uint8_t     mode;
 624         uint8_t     filler_0[2];
 625         uint32_t    filler_1[2];
 626 };
 627
 628 typedef struct SMU7_Discrete_Log_Header_Table SMU7_Discrete_Log_Header_Table;
 629
 630 struct SMU7_Discrete_Log_Cntl {
 631         uint8_t             Enabled;
 632         uint8_t             Type;
 633         uint8_t             padding[2];
 634         uint32_t            BufferSize;
 635         uint32_t            SamplesLogged;
 636         uint32_t            SampleSize;
 637         uint32_t            AddrL;
 638         uint32_t            AddrH;
 639 };
 640
 641 typedef struct SMU7_Discrete_Log_Cntl SMU7_Discrete_Log_Cntl;
 642
 643 #if defined SMU__DGPU_ONLY
 644 #define CAC_ACC_NW_NUM_OF_SIGNALS 87
 645 #endif
 646
 647
 648 struct SMU7_Discrete_Cac_Collection_Table {
 649         uint32_t temperature;
 650         uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS];
 651 };
 652
 653 typedef struct SMU7_Discrete_Cac_Collection_Table SMU7_Discrete_Cac_Collection_Table;
 654
 655 struct SMU7_Discrete_Cac_Verification_Table {
 656         uint32_t VddcTotalPower;
 657         uint32_t VddcLeakagePower;
 658         uint32_t VddcConstantPower;
 659         uint32_t VddcGfxDynamicPower;
 660         uint32_t VddcUvdDynamicPower;
 661         uint32_t VddcVceDynamicPower;
 662         uint32_t VddcAcpDynamicPower;
 663         uint32_t VddcPcieDynamicPower;
 664         uint32_t VddcDceDynamicPower;
 665         uint32_t VddcCurrent;
 666         uint32_t VddcVoltage;
 667         uint32_t VddciTotalPower;
 668         uint32_t VddciLeakagePower;
 669         uint32_t VddciConstantPower;
 670         uint32_t VddciDynamicPower;
 671         uint32_t Vddr1TotalPower;
 672         uint32_t Vddr1LeakagePower;
 673         uint32_t Vddr1ConstantPower;
 674         uint32_t Vddr1DynamicPower;
 675         uint32_t spare[4];
 676         uint32_t temperature;
 677 };
 678
 679 typedef struct SMU7_Discrete_Cac_Verification_Table SMU7_Discrete_Cac_Verification_Table;
 680
 681 struct SMU7_Discrete_Pm_Status_Table {
 682         int32_t T_meas_max;
 683         int32_t T_meas_acc;
 684         int32_t T_calc_max;
 685         int32_t T_calc_acc;
 686         uint32_t P_scalar_acc;
 687         uint32_t P_calc_max;
 688         uint32_t P_calc_acc;
 689
 690         uint32_t I_calc_max;
 691         uint32_t I_calc_acc;
 692         uint32_t I_calc_acc_vddci;
 693         uint32_t V_calc_noload_acc;
 694         uint32_t V_calc_load_acc;
 695         uint32_t V_calc_noload_acc_vddci;
 696         uint32_t P_meas_acc;
 697         uint32_t V_meas_noload_acc;
 698         uint32_t V_meas_load_acc;
 699         uint32_t I_meas_acc;
 700         uint32_t P_meas_acc_vddci;
 701         uint32_t V_meas_noload_acc_vddci;
 702         uint32_t V_meas_load_acc_vddci;
 703         uint32_t I_meas_acc_vddci;
 704
 705         uint16_t Sclk_dpm_residency[8];
 706         uint16_t Uvd_dpm_residency[8];
 707         uint16_t Vce_dpm_residency[8];
 708         uint16_t Mclk_dpm_residency[4];
 709
 710         uint32_t P_vddci_acc;
 711         uint32_t P_vddr1_acc;
 712         uint32_t P_nte1_acc;
 713         uint32_t PkgPwr_max;
 714         uint32_t PkgPwr_acc;
 715         uint32_t MclkSwitchingTime_max;
 716         uint32_t MclkSwitchingTime_acc;
 717         uint32_t FanPwm_acc;
 718         uint32_t FanRpm_acc;
 719
 720         uint32_t AccCnt;
 721 };
 722
 723 typedef struct SMU7_Discrete_Pm_Status_Table SMU7_Discrete_Pm_Status_Table;
 724
 725 #define SMU7_MAX_GFX_CU_COUNT 16
 726
 727 struct SMU7_GfxCuPgScoreboard {
 728         uint8_t Enabled;
 729         uint8_t WaterfallUp;
 730         uint8_t WaterfallDown;
 731         uint8_t WaterfallLimit;
 732         uint8_t CurrMaxCu;
 733         uint8_t TargMaxCu;
 734         uint8_t ClampMode;
 735         uint8_t Active;
 736         uint8_t MaxSupportedCu;
 737         uint8_t MinSupportedCu;
 738         uint8_t PendingGfxCuHostInterrupt;
 739         uint8_t LastFilteredMaxCuInteger;
 740         uint16_t FilteredMaxCu;
 741         uint16_t FilteredMaxCuAlpha;
 742         uint16_t FilterResetCount;
 743         uint16_t FilterResetCountLimit;
 744         uint8_t ForceCu;
 745         uint8_t ForceCuCount;
 746         uint8_t spare[2];
 747 };
 748
 749 typedef struct SMU7_GfxCuPgScoreboard SMU7_GfxCuPgScoreboard;
 750
 751 #define SMU7_SCLK_CAC 0x561
 752 #define SMU7_MCLK_CAC 0xF9
 753 #define SMU7_VCLK_CAC 0x2DE
 754 #define SMU7_DCLK_CAC 0x2DE
 755 #define SMU7_ECLK_CAC 0x25E
 756 #define SMU7_ACLK_CAC 0x25E
 757 #define SMU7_SAMCLK_CAC 0x25E
 758 #define SMU7_DISPCLK_CAC 0x100
 759 #define SMU7_CAC_CONSTANT 0x2EE3430
 760 #define SMU7_CAC_CONSTANT_SHIFT 18
 761
 762 #define SMU7_VDDCI_MCLK_CONST        1765
 763 #define SMU7_VDDCI_MCLK_CONST_SHIFT  16
 764 #define SMU7_VDDCI_VDDCI_CONST       50958
 765 #define SMU7_VDDCI_VDDCI_CONST_SHIFT 14
 766 #define SMU7_VDDCI_CONST             11781
 767 #define SMU7_VDDCI_STROBE_PWR        1331
 768
 769 #define SMU7_VDDR1_CONST            693
 770 #define SMU7_VDDR1_CAC_WEIGHT       20
 771 #define SMU7_VDDR1_CAC_WEIGHT_SHIFT 19
 772 #define SMU7_VDDR1_STROBE_PWR       512
 773
 774 #define SMU7_AREA_COEFF_UVD 0xA78
 775 #define SMU7_AREA_COEFF_VCE 0x190A
 776 #define SMU7_AREA_COEFF_ACP 0x22D1
 777 #define SMU7_AREA_COEFF_SAMU 0x534
 778
 779 #define SMU7_THERM_OUT_MODE_DISABLE       0x0
 780 #define SMU7_THERM_OUT_MODE_THERM_ONLY    0x1
 781 #define SMU7_THERM_OUT_MODE_THERM_VRHOT   0x2
 782
 783 // DIDT Defines
 784 #define SQ_Enable_MASK 0x1
 785 #define SQ_IR_MASK 0x2
 786 #define SQ_PCC_MASK 0x4
 787 #define SQ_EDC_MASK 0x8
 788
 789 #define TCP_Enable_MASK 0x100
 790 #define TCP_IR_MASK 0x200
 791 #define TCP_PCC_MASK 0x400
 792 #define TCP_EDC_MASK 0x800
 793
 794 #define TD_Enable_MASK 0x10000
 795 #define TD_IR_MASK 0x20000
 796 #define TD_PCC_MASK 0x40000
 797 #define TD_EDC_MASK 0x80000
 798
 799 #define DB_Enable_MASK 0x1000000
 800 #define DB_IR_MASK 0x2000000
 801 #define DB_PCC_MASK 0x4000000
 802 #define DB_EDC_MASK 0x8000000
 803
 804 #define SQ_Enable_SHIFT 0
 805 #define SQ_IR_SHIFT 1
 806 #define SQ_PCC_SHIFT 2
 807 #define SQ_EDC_SHIFT 3
 808
 809 #define TCP_Enable_SHIFT 8
 810 #define TCP_IR_SHIFT 9
 811 #define TCP_PCC_SHIFT 10
 812 #define TCP_EDC_SHIFT 11
 813
 814 #define TD_Enable_SHIFT 16
 815 #define TD_IR_SHIFT 17
 816 #define TD_PCC_SHIFT 18
 817 #define TD_EDC_SHIFT 19
 818
 819 #define DB_Enable_SHIFT 24
 820 #define DB_IR_SHIFT 25
 821 #define DB_PCC_SHIFT 26
 822 #define DB_EDC_SHIFT 27
 823
 824 #pragma pack(pop)
 825
 826
 827 #endif
 828