2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/types.h>
24 #include <linux/kernel.h>
25 #include <linux/slab.h>
26 #include <linux/gfp.h>
27 #include "linux/delay.h"
28 #include "cgs_common.h"
29 #include "smu/smu_8_0_d.h"
30 #include "smu/smu_8_0_sh_mask.h"
32 #include "smu8_fusion.h"
33 #include "cz_smumgr.h"
35 #include "smu_ucode_xfer_cz.h"
36 #include "gca/gfx_8_0_d.h"
37 #include "gca/gfx_8_0_sh_mask.h"
40 #define SIZE_ALIGN_32(x) (((x) + 31) / 32 * 32)
42 static const enum cz_scratch_entry firmware_list[] = {
43 CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0,
44 CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1,
45 CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE,
46 CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP,
47 CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME,
48 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1,
49 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2,
50 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G,
53 static int cz_smum_get_argument(struct pp_smumgr *smumgr)
55 if (smumgr == NULL || smumgr->device == NULL)
58 return cgs_read_register(smumgr->device,
59 mmSMU_MP1_SRBM2P_ARG_0);
62 static int cz_send_msg_to_smc_async(struct pp_smumgr *smumgr,
67 if (smumgr == NULL || smumgr->device == NULL)
70 result = SMUM_WAIT_FIELD_UNEQUAL(smumgr,
71 SMU_MP1_SRBM2P_RESP_0, CONTENT, 0);
73 printk(KERN_ERR "[ powerplay ] cz_send_msg_to_smc_async failed\n");
77 cgs_write_register(smumgr->device, mmSMU_MP1_SRBM2P_RESP_0, 0);
78 cgs_write_register(smumgr->device, mmSMU_MP1_SRBM2P_MSG_0, msg);
83 /* Send a message to the SMC, and wait for its response.*/
84 static int cz_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
88 result = cz_send_msg_to_smc_async(smumgr, msg);
92 return SMUM_WAIT_FIELD_UNEQUAL(smumgr,
93 SMU_MP1_SRBM2P_RESP_0, CONTENT, 0);
96 static int cz_set_smc_sram_address(struct pp_smumgr *smumgr,
97 uint32_t smc_address, uint32_t limit)
99 if (smumgr == NULL || smumgr->device == NULL)
102 if (0 != (3 & smc_address)) {
103 printk(KERN_ERR "[ powerplay ] SMC address must be 4 byte aligned\n");
107 if (limit <= (smc_address + 3)) {
108 printk(KERN_ERR "[ powerplay ] SMC address beyond the SMC RAM area\n");
112 cgs_write_register(smumgr->device, mmMP0PUB_IND_INDEX_0,
113 SMN_MP1_SRAM_START_ADDR + smc_address);
118 static int cz_write_smc_sram_dword(struct pp_smumgr *smumgr,
119 uint32_t smc_address, uint32_t value, uint32_t limit)
123 if (smumgr == NULL || smumgr->device == NULL)
126 result = cz_set_smc_sram_address(smumgr, smc_address, limit);
128 cgs_write_register(smumgr->device, mmMP0PUB_IND_DATA_0, value);
133 static int cz_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
134 uint16_t msg, uint32_t parameter)
136 if (smumgr == NULL || smumgr->device == NULL)
139 cgs_write_register(smumgr->device, mmSMU_MP1_SRBM2P_ARG_0, parameter);
141 return cz_send_msg_to_smc(smumgr, msg);
144 static int cz_request_smu_load_fw(struct pp_smumgr *smumgr)
146 struct cz_smumgr *cz_smu = (struct cz_smumgr *)(smumgr->backend);
147 uint32_t smc_address;
149 if (!smumgr->reload_fw) {
150 printk(KERN_INFO "[ powerplay ] skip reloading...\n");
154 smc_address = SMU8_FIRMWARE_HEADER_LOCATION +
155 offsetof(struct SMU8_Firmware_Header, UcodeLoadStatus);
157 cz_write_smc_sram_dword(smumgr, smc_address, 0, smc_address+4);
159 cz_send_msg_to_smc_with_parameter(smumgr,
160 PPSMC_MSG_DriverDramAddrHi,
161 cz_smu->toc_buffer.mc_addr_high);
163 cz_send_msg_to_smc_with_parameter(smumgr,
164 PPSMC_MSG_DriverDramAddrLo,
165 cz_smu->toc_buffer.mc_addr_low);
167 cz_send_msg_to_smc(smumgr, PPSMC_MSG_InitJobs);
169 cz_send_msg_to_smc_with_parameter(smumgr,
170 PPSMC_MSG_ExecuteJob,
171 cz_smu->toc_entry_aram);
172 cz_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_ExecuteJob,
173 cz_smu->toc_entry_power_profiling_index);
175 return cz_send_msg_to_smc_with_parameter(smumgr,
176 PPSMC_MSG_ExecuteJob,
177 cz_smu->toc_entry_initialize_index);
180 static int cz_check_fw_load_finish(struct pp_smumgr *smumgr,
184 uint32_t index = SMN_MP1_SRAM_START_ADDR +
185 SMU8_FIRMWARE_HEADER_LOCATION +
186 offsetof(struct SMU8_Firmware_Header, UcodeLoadStatus);
188 if (smumgr == NULL || smumgr->device == NULL)
191 cgs_write_register(smumgr->device, mmMP0PUB_IND_INDEX, index);
193 for (i = 0; i < smumgr->usec_timeout; i++) {
195 (cgs_read_register(smumgr->device, mmMP0PUB_IND_DATA) & firmware))
200 if (i >= smumgr->usec_timeout) {
201 printk(KERN_ERR "[ powerplay ] SMU check loaded firmware failed.\n");
208 static int cz_load_mec_firmware(struct pp_smumgr *smumgr)
213 struct cgs_firmware_info info = {0};
214 struct cz_smumgr *cz_smu;
216 if (smumgr == NULL || smumgr->device == NULL)
219 cz_smu = (struct cz_smumgr *)smumgr->backend;
220 ret = cgs_get_firmware_info(smumgr->device,
221 CGS_UCODE_ID_CP_MEC, &info);
226 /* Disable MEC parsing/prefetching */
227 tmp = cgs_read_register(smumgr->device,
229 tmp = SMUM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1);
230 tmp = SMUM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1);
231 cgs_write_register(smumgr->device, mmCP_MEC_CNTL, tmp);
233 tmp = cgs_read_register(smumgr->device,
234 mmCP_CPC_IC_BASE_CNTL);
236 tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
237 tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ATC, 0);
238 tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
239 tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, MTYPE, 1);
240 cgs_write_register(smumgr->device, mmCP_CPC_IC_BASE_CNTL, tmp);
242 reg_data = smu_lower_32_bits(info.mc_addr) &
243 SMUM_FIELD_MASK(CP_CPC_IC_BASE_LO, IC_BASE_LO);
244 cgs_write_register(smumgr->device, mmCP_CPC_IC_BASE_LO, reg_data);
246 reg_data = smu_upper_32_bits(info.mc_addr) &
247 SMUM_FIELD_MASK(CP_CPC_IC_BASE_HI, IC_BASE_HI);
248 cgs_write_register(smumgr->device, mmCP_CPC_IC_BASE_HI, reg_data);
253 static int cz_start_smu(struct pp_smumgr *smumgr)
256 uint32_t fw_to_check = UCODE_ID_RLC_G_MASK |
257 UCODE_ID_SDMA0_MASK |
258 UCODE_ID_SDMA1_MASK |
259 UCODE_ID_CP_CE_MASK |
260 UCODE_ID_CP_ME_MASK |
261 UCODE_ID_CP_PFP_MASK |
262 UCODE_ID_CP_MEC_JT1_MASK |
263 UCODE_ID_CP_MEC_JT2_MASK;
265 if (smumgr->chip_id == CHIP_STONEY)
266 fw_to_check &= ~(UCODE_ID_SDMA1_MASK | UCODE_ID_CP_MEC_JT2_MASK);
268 ret = cz_request_smu_load_fw(smumgr);
270 printk(KERN_ERR "[ powerplay] SMU firmware load failed\n");
272 cz_check_fw_load_finish(smumgr, fw_to_check);
274 ret = cz_load_mec_firmware(smumgr);
276 printk(KERN_ERR "[ powerplay ] Mec Firmware load failed\n");
281 static uint8_t cz_translate_firmware_enum_to_arg(struct pp_smumgr *smumgr,
282 enum cz_scratch_entry firmware_enum)
286 switch (firmware_enum) {
287 case CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0:
288 ret = UCODE_ID_SDMA0;
290 case CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1:
291 if (smumgr->chip_id == CHIP_STONEY)
292 ret = UCODE_ID_SDMA0;
294 ret = UCODE_ID_SDMA1;
296 case CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE:
297 ret = UCODE_ID_CP_CE;
299 case CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP:
300 ret = UCODE_ID_CP_PFP;
302 case CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME:
303 ret = UCODE_ID_CP_ME;
305 case CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1:
306 ret = UCODE_ID_CP_MEC_JT1;
308 case CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2:
309 if (smumgr->chip_id == CHIP_STONEY)
310 ret = UCODE_ID_CP_MEC_JT1;
312 ret = UCODE_ID_CP_MEC_JT2;
314 case CZ_SCRATCH_ENTRY_UCODE_ID_GMCON_RENG:
315 ret = UCODE_ID_GMCON_RENG;
317 case CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G:
318 ret = UCODE_ID_RLC_G;
320 case CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH:
321 ret = UCODE_ID_RLC_SCRATCH;
323 case CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM:
324 ret = UCODE_ID_RLC_SRM_ARAM;
326 case CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM:
327 ret = UCODE_ID_RLC_SRM_DRAM;
329 case CZ_SCRATCH_ENTRY_UCODE_ID_DMCU_ERAM:
330 ret = UCODE_ID_DMCU_ERAM;
332 case CZ_SCRATCH_ENTRY_UCODE_ID_DMCU_IRAM:
333 ret = UCODE_ID_DMCU_IRAM;
335 case CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING:
336 ret = TASK_ARG_INIT_MM_PWR_LOG;
338 case CZ_SCRATCH_ENTRY_DATA_ID_SDMA_HALT:
339 case CZ_SCRATCH_ENTRY_DATA_ID_SYS_CLOCKGATING:
340 case CZ_SCRATCH_ENTRY_DATA_ID_SDMA_RING_REGS:
341 case CZ_SCRATCH_ENTRY_DATA_ID_NONGFX_REINIT:
342 case CZ_SCRATCH_ENTRY_DATA_ID_SDMA_START:
343 case CZ_SCRATCH_ENTRY_DATA_ID_IH_REGISTERS:
344 ret = TASK_ARG_REG_MMIO;
346 case CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE:
347 ret = TASK_ARG_INIT_CLK_TABLE;
354 static enum cgs_ucode_id cz_convert_fw_type_to_cgs(uint32_t fw_type)
356 enum cgs_ucode_id result = CGS_UCODE_ID_MAXIMUM;
360 result = CGS_UCODE_ID_SDMA0;
363 result = CGS_UCODE_ID_SDMA1;
366 result = CGS_UCODE_ID_CP_CE;
368 case UCODE_ID_CP_PFP:
369 result = CGS_UCODE_ID_CP_PFP;
372 result = CGS_UCODE_ID_CP_ME;
374 case UCODE_ID_CP_MEC_JT1:
375 result = CGS_UCODE_ID_CP_MEC_JT1;
377 case UCODE_ID_CP_MEC_JT2:
378 result = CGS_UCODE_ID_CP_MEC_JT2;
381 result = CGS_UCODE_ID_RLC_G;
390 static int cz_smu_populate_single_scratch_task(
391 struct pp_smumgr *smumgr,
392 enum cz_scratch_entry fw_enum,
393 uint8_t type, bool is_last)
396 struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
397 struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
398 struct SMU_Task *task = &toc->tasks[cz_smu->toc_entry_used_count++];
401 task->arg = cz_translate_firmware_enum_to_arg(smumgr, fw_enum);
402 task->next = is_last ? END_OF_TASK_LIST : cz_smu->toc_entry_used_count;
404 for (i = 0; i < cz_smu->scratch_buffer_length; i++)
405 if (cz_smu->scratch_buffer[i].firmware_ID == fw_enum)
408 if (i >= cz_smu->scratch_buffer_length) {
409 printk(KERN_ERR "[ powerplay ] Invalid Firmware Type\n");
413 task->addr.low = cz_smu->scratch_buffer[i].mc_addr_low;
414 task->addr.high = cz_smu->scratch_buffer[i].mc_addr_high;
415 task->size_bytes = cz_smu->scratch_buffer[i].data_size;
417 if (CZ_SCRATCH_ENTRY_DATA_ID_IH_REGISTERS == fw_enum) {
418 struct cz_ih_meta_data *pIHReg_restore =
419 (struct cz_ih_meta_data *)cz_smu->scratch_buffer[i].kaddr;
420 pIHReg_restore->command =
421 METADATA_CMD_MODE0 | METADATA_PERFORM_ON_LOAD;
427 static int cz_smu_populate_single_ucode_load_task(
428 struct pp_smumgr *smumgr,
429 enum cz_scratch_entry fw_enum,
433 struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
434 struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
435 struct SMU_Task *task = &toc->tasks[cz_smu->toc_entry_used_count++];
437 task->type = TASK_TYPE_UCODE_LOAD;
438 task->arg = cz_translate_firmware_enum_to_arg(smumgr, fw_enum);
439 task->next = is_last ? END_OF_TASK_LIST : cz_smu->toc_entry_used_count;
441 for (i = 0; i < cz_smu->driver_buffer_length; i++)
442 if (cz_smu->driver_buffer[i].firmware_ID == fw_enum)
445 if (i >= cz_smu->driver_buffer_length) {
446 printk(KERN_ERR "[ powerplay ] Invalid Firmware Type\n");
450 task->addr.low = cz_smu->driver_buffer[i].mc_addr_low;
451 task->addr.high = cz_smu->driver_buffer[i].mc_addr_high;
452 task->size_bytes = cz_smu->driver_buffer[i].data_size;
457 static int cz_smu_construct_toc_for_rlc_aram_save(struct pp_smumgr *smumgr)
459 struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
461 cz_smu->toc_entry_aram = cz_smu->toc_entry_used_count;
462 cz_smu_populate_single_scratch_task(smumgr,
463 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
464 TASK_TYPE_UCODE_SAVE, true);
469 static int cz_smu_initialize_toc_empty_job_list(struct pp_smumgr *smumgr)
472 struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
473 struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
475 for (i = 0; i < NUM_JOBLIST_ENTRIES; i++)
476 toc->JobList[i] = (uint8_t)IGNORE_JOB;
481 static int cz_smu_construct_toc_for_vddgfx_enter(struct pp_smumgr *smumgr)
483 struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
484 struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
486 toc->JobList[JOB_GFX_SAVE] = (uint8_t)cz_smu->toc_entry_used_count;
487 cz_smu_populate_single_scratch_task(smumgr,
488 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
489 TASK_TYPE_UCODE_SAVE, false);
491 cz_smu_populate_single_scratch_task(smumgr,
492 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
493 TASK_TYPE_UCODE_SAVE, true);
499 static int cz_smu_construct_toc_for_vddgfx_exit(struct pp_smumgr *smumgr)
501 struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
502 struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
504 toc->JobList[JOB_GFX_RESTORE] = (uint8_t)cz_smu->toc_entry_used_count;
506 cz_smu_populate_single_ucode_load_task(smumgr,
507 CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE, false);
508 cz_smu_populate_single_ucode_load_task(smumgr,
509 CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP, false);
510 cz_smu_populate_single_ucode_load_task(smumgr,
511 CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false);
512 cz_smu_populate_single_ucode_load_task(smumgr,
513 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
515 if (smumgr->chip_id == CHIP_STONEY)
516 cz_smu_populate_single_ucode_load_task(smumgr,
517 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
519 cz_smu_populate_single_ucode_load_task(smumgr,
520 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false);
522 cz_smu_populate_single_ucode_load_task(smumgr,
523 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, false);
525 /* populate scratch */
526 cz_smu_populate_single_scratch_task(smumgr,
527 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
528 TASK_TYPE_UCODE_LOAD, false);
530 cz_smu_populate_single_scratch_task(smumgr,
531 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
532 TASK_TYPE_UCODE_LOAD, false);
534 cz_smu_populate_single_scratch_task(smumgr,
535 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
536 TASK_TYPE_UCODE_LOAD, true);
541 static int cz_smu_construct_toc_for_power_profiling(
542 struct pp_smumgr *smumgr)
544 struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
546 cz_smu->toc_entry_power_profiling_index = cz_smu->toc_entry_used_count;
548 cz_smu_populate_single_scratch_task(smumgr,
549 CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING,
550 TASK_TYPE_INITIALIZE, true);
554 static int cz_smu_construct_toc_for_bootup(struct pp_smumgr *smumgr)
556 struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
558 cz_smu->toc_entry_initialize_index = cz_smu->toc_entry_used_count;
560 cz_smu_populate_single_ucode_load_task(smumgr,
561 CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0, false);
562 if (smumgr->chip_id != CHIP_STONEY)
563 cz_smu_populate_single_ucode_load_task(smumgr,
564 CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1, false);
565 cz_smu_populate_single_ucode_load_task(smumgr,
566 CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE, false);
567 cz_smu_populate_single_ucode_load_task(smumgr,
568 CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP, false);
569 cz_smu_populate_single_ucode_load_task(smumgr,
570 CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false);
571 cz_smu_populate_single_ucode_load_task(smumgr,
572 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
573 if (smumgr->chip_id != CHIP_STONEY)
574 cz_smu_populate_single_ucode_load_task(smumgr,
575 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false);
576 cz_smu_populate_single_ucode_load_task(smumgr,
577 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, true);
582 static int cz_smu_construct_toc_for_clock_table(struct pp_smumgr *smumgr)
584 struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
586 cz_smu->toc_entry_clock_table = cz_smu->toc_entry_used_count;
588 cz_smu_populate_single_scratch_task(smumgr,
589 CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE,
590 TASK_TYPE_INITIALIZE, true);
595 static int cz_smu_construct_toc(struct pp_smumgr *smumgr)
597 struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
599 cz_smu->toc_entry_used_count = 0;
600 cz_smu_initialize_toc_empty_job_list(smumgr);
601 cz_smu_construct_toc_for_rlc_aram_save(smumgr);
602 cz_smu_construct_toc_for_vddgfx_enter(smumgr);
603 cz_smu_construct_toc_for_vddgfx_exit(smumgr);
604 cz_smu_construct_toc_for_power_profiling(smumgr);
605 cz_smu_construct_toc_for_bootup(smumgr);
606 cz_smu_construct_toc_for_clock_table(smumgr);
611 static int cz_smu_populate_firmware_entries(struct pp_smumgr *smumgr)
613 struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
614 uint32_t firmware_type;
617 enum cgs_ucode_id ucode_id;
618 struct cgs_firmware_info info = {0};
620 cz_smu->driver_buffer_length = 0;
622 for (i = 0; i < ARRAY_SIZE(firmware_list); i++) {
624 firmware_type = cz_translate_firmware_enum_to_arg(smumgr,
627 ucode_id = cz_convert_fw_type_to_cgs(firmware_type);
629 ret = cgs_get_firmware_info(smumgr->device,
633 cz_smu->driver_buffer[i].mc_addr_high =
634 smu_upper_32_bits(info.mc_addr);
636 cz_smu->driver_buffer[i].mc_addr_low =
637 smu_lower_32_bits(info.mc_addr);
639 cz_smu->driver_buffer[i].data_size = info.image_size;
641 cz_smu->driver_buffer[i].firmware_ID = firmware_list[i];
642 cz_smu->driver_buffer_length++;
649 static int cz_smu_populate_single_scratch_entry(
650 struct pp_smumgr *smumgr,
651 enum cz_scratch_entry scratch_type,
652 uint32_t ulsize_byte,
653 struct cz_buffer_entry *entry)
655 struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
657 ((long long)(cz_smu->smu_buffer.mc_addr_high) << 32)
658 | cz_smu->smu_buffer.mc_addr_low;
660 uint32_t ulsize_aligned = SIZE_ALIGN_32(ulsize_byte);
662 mc_addr += cz_smu->smu_buffer_used_bytes;
664 entry->data_size = ulsize_byte;
665 entry->kaddr = (char *) cz_smu->smu_buffer.kaddr +
666 cz_smu->smu_buffer_used_bytes;
667 entry->mc_addr_low = smu_lower_32_bits(mc_addr);
668 entry->mc_addr_high = smu_upper_32_bits(mc_addr);
669 entry->firmware_ID = scratch_type;
671 cz_smu->smu_buffer_used_bytes += ulsize_aligned;
676 static int cz_download_pptable_settings(struct pp_smumgr *smumgr, void **table)
678 struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
681 for (i = 0; i < cz_smu->scratch_buffer_length; i++) {
682 if (cz_smu->scratch_buffer[i].firmware_ID
683 == CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE)
687 *table = (struct SMU8_Fusion_ClkTable *)cz_smu->scratch_buffer[i].kaddr;
689 cz_send_msg_to_smc_with_parameter(smumgr,
690 PPSMC_MSG_SetClkTableAddrHi,
691 cz_smu->scratch_buffer[i].mc_addr_high);
693 cz_send_msg_to_smc_with_parameter(smumgr,
694 PPSMC_MSG_SetClkTableAddrLo,
695 cz_smu->scratch_buffer[i].mc_addr_low);
697 cz_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_ExecuteJob,
698 cz_smu->toc_entry_clock_table);
700 cz_send_msg_to_smc(smumgr, PPSMC_MSG_ClkTableXferToDram);
705 static int cz_upload_pptable_settings(struct pp_smumgr *smumgr)
707 struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
710 for (i = 0; i < cz_smu->scratch_buffer_length; i++) {
711 if (cz_smu->scratch_buffer[i].firmware_ID
712 == CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE)
716 cz_send_msg_to_smc_with_parameter(smumgr,
717 PPSMC_MSG_SetClkTableAddrHi,
718 cz_smu->scratch_buffer[i].mc_addr_high);
720 cz_send_msg_to_smc_with_parameter(smumgr,
721 PPSMC_MSG_SetClkTableAddrLo,
722 cz_smu->scratch_buffer[i].mc_addr_low);
724 cz_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_ExecuteJob,
725 cz_smu->toc_entry_clock_table);
727 cz_send_msg_to_smc(smumgr, PPSMC_MSG_ClkTableXferToSmu);
732 static int cz_smu_init(struct pp_smumgr *smumgr)
734 struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
735 uint64_t mc_addr = 0;
738 cz_smu->toc_buffer.data_size = 4096;
739 cz_smu->smu_buffer.data_size =
740 ALIGN(UCODE_ID_RLC_SCRATCH_SIZE_BYTE, 32) +
741 ALIGN(UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE, 32) +
742 ALIGN(UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE, 32) +
743 ALIGN(sizeof(struct SMU8_MultimediaPowerLogData), 32) +
744 ALIGN(sizeof(struct SMU8_Fusion_ClkTable), 32);
746 ret = smu_allocate_memory(smumgr->device,
747 cz_smu->toc_buffer.data_size,
748 CGS_GPU_MEM_TYPE__GART_CACHEABLE,
751 &cz_smu->toc_buffer.kaddr,
752 &cz_smu->toc_buffer.handle);
756 cz_smu->toc_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);
757 cz_smu->toc_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);
759 ret = smu_allocate_memory(smumgr->device,
760 cz_smu->smu_buffer.data_size,
761 CGS_GPU_MEM_TYPE__GART_CACHEABLE,
764 &cz_smu->smu_buffer.kaddr,
765 &cz_smu->smu_buffer.handle);
769 cz_smu->smu_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);
770 cz_smu->smu_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);
772 cz_smu_populate_firmware_entries(smumgr);
773 if (0 != cz_smu_populate_single_scratch_entry(smumgr,
774 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
775 UCODE_ID_RLC_SCRATCH_SIZE_BYTE,
776 &cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
777 printk(KERN_ERR "[ powerplay ] Error when Populate Firmware Entry.\n");
781 if (0 != cz_smu_populate_single_scratch_entry(smumgr,
782 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
783 UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE,
784 &cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
785 printk(KERN_ERR "[ powerplay ] Error when Populate Firmware Entry.\n");
788 if (0 != cz_smu_populate_single_scratch_entry(smumgr,
789 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
790 UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE,
791 &cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
792 printk(KERN_ERR "[ powerplay ] Error when Populate Firmware Entry.\n");
796 if (0 != cz_smu_populate_single_scratch_entry(smumgr,
797 CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING,
798 sizeof(struct SMU8_MultimediaPowerLogData),
799 &cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
800 printk(KERN_ERR "[ powerplay ] Error when Populate Firmware Entry.\n");
804 if (0 != cz_smu_populate_single_scratch_entry(smumgr,
805 CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE,
806 sizeof(struct SMU8_Fusion_ClkTable),
807 &cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
808 printk(KERN_ERR "[ powerplay ] Error when Populate Firmware Entry.\n");
811 cz_smu_construct_toc(smumgr);
816 static int cz_smu_fini(struct pp_smumgr *smumgr)
818 struct cz_smumgr *cz_smu;
820 if (smumgr == NULL || smumgr->device == NULL)
823 cz_smu = (struct cz_smumgr *)smumgr->backend;
825 cgs_free_gpu_mem(smumgr->device,
826 cz_smu->toc_buffer.handle);
827 cgs_free_gpu_mem(smumgr->device,
828 cz_smu->smu_buffer.handle);
836 static const struct pp_smumgr_func cz_smu_funcs = {
837 .smu_init = cz_smu_init,
838 .smu_fini = cz_smu_fini,
839 .start_smu = cz_start_smu,
840 .check_fw_load_finish = cz_check_fw_load_finish,
841 .request_smu_load_fw = NULL,
842 .request_smu_load_specific_fw = NULL,
843 .get_argument = cz_smum_get_argument,
844 .send_msg_to_smc = cz_send_msg_to_smc,
845 .send_msg_to_smc_with_parameter = cz_send_msg_to_smc_with_parameter,
846 .download_pptable_settings = cz_download_pptable_settings,
847 .upload_pptable_settings = cz_upload_pptable_settings,
850 int cz_smum_init(struct pp_smumgr *smumgr)
852 struct cz_smumgr *cz_smu;
854 cz_smu = kzalloc(sizeof(struct cz_smumgr), GFP_KERNEL);
858 smumgr->backend = cz_smu;
859 smumgr->smumgr_funcs = &cz_smu_funcs;