drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24
  25 #include "smumgr.h"
  26 #include "smu_ucode_xfer_vi.h"
  27 #include "smu/smu_7_1_3_d.h"
  28 #include "smu/smu_7_1_3_sh_mask.h"
  29 #include "ppatomctrl.h"
  30 #include "pp_debug.h"
  31 #include "cgs_common.h"
  32 #include "smu7_ppsmc.h"
  33 #include "smu7_smumgr.h"
  34
  35 #define SMU7_SMC_SIZE 0x20000
  36
  37 static int smu7_set_smc_sram_address(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t limit)
  38 {
  39         PP_ASSERT_WITH_CODE((0 == (3 & smc_addr)), "SMC address must be 4 byte aligned.", return -EINVAL);
  40         PP_ASSERT_WITH_CODE((limit > (smc_addr + 3)), "SMC addr is beyond the SMC RAM area.", return -EINVAL);
  41
  42         cgs_write_register(smumgr->device, mmSMC_IND_INDEX_11, smc_addr);
  43         SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0); /* on ci, SMC_IND_ACCESS_CNTL is different */
  44         return 0;
  45 }
  46
  47
  48 int smu7_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, uint32_t *dest, uint32_t byte_count, uint32_t limit)
  49 {
  50         uint32_t data;
  51         uint32_t addr;
  52         uint8_t *dest_byte;
  53         uint8_t i, data_byte[4] = {0};
  54         uint32_t *pdata = (uint32_t *)&data_byte;
  55
  56         PP_ASSERT_WITH_CODE((0 == (3 & smc_start_address)), "SMC address must be 4 byte aligned.", return -EINVAL);
  57         PP_ASSERT_WITH_CODE((limit > (smc_start_address + byte_count)), "SMC address is beyond the SMC RAM area.", return -EINVAL);
  58
  59         addr = smc_start_address;
  60
  61         while (byte_count >= 4) {
  62                 smu7_read_smc_sram_dword(smumgr, addr, &data, limit);
  63
  64                 *dest = PP_SMC_TO_HOST_UL(data);
  65
  66                 dest += 1;
  67                 byte_count -= 4;
  68                 addr += 4;
  69         }
  70
  71         if (byte_count) {
  72                 smu7_read_smc_sram_dword(smumgr, addr, &data, limit);
  73                 *pdata = PP_SMC_TO_HOST_UL(data);
  74         /* Cast dest into byte type in dest_byte.  This way, we don't overflow if the allocated memory is not 4-byte aligned. */
  75                 dest_byte = (uint8_t *)dest;
  76                 for (i = 0; i < byte_count; i++)
  77                         dest_byte[i] = data_byte[i];
  78         }
  79
  80         return 0;
  81 }
  82
  83
  84 int smu7_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address,
  85                                 const uint8_t *src, uint32_t byte_count, uint32_t limit)
  86 {
  87         int result;
  88         uint32_t data = 0;
  89         uint32_t original_data;
  90         uint32_t addr = 0;
  91         uint32_t extra_shift;
  92
  93         PP_ASSERT_WITH_CODE((0 == (3 & smc_start_address)), "SMC address must be 4 byte aligned.", return -EINVAL);
  94         PP_ASSERT_WITH_CODE((limit > (smc_start_address + byte_count)), "SMC address is beyond the SMC RAM area.", return -EINVAL);
  95
  96         addr = smc_start_address;
  97
  98         while (byte_count >= 4) {
  99         /* Bytes are written into the SMC addres space with the MSB first. */
 100                 data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3];
 101
 102                 result = smu7_set_smc_sram_address(smumgr, addr, limit);
 103
 104                 if (0 != result)
 105                         return result;
 106
 107                 cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, data);
 108
 109                 src += 4;
 110                 byte_count -= 4;
 111                 addr += 4;
 112         }
 113
 114         if (0 != byte_count) {
 115
 116                 data = 0;
 117
 118                 result = smu7_set_smc_sram_address(smumgr, addr, limit);
 119
 120                 if (0 != result)
 121                         return result;
 122
 123
 124                 original_data = cgs_read_register(smumgr->device, mmSMC_IND_DATA_11);
 125
 126                 extra_shift = 8 * (4 - byte_count);
 127
 128                 while (byte_count > 0) {
 129                         /* Bytes are written into the SMC addres space with the MSB first. */
 130                         data = (0x100 * data) + *src++;
 131                         byte_count--;
 132                 }
 133
 134                 data <<= extra_shift;
 135
 136                 data |= (original_data & ~((~0UL) << extra_shift));
 137
 138                 result = smu7_set_smc_sram_address(smumgr, addr, limit);
 139
 140                 if (0 != result)
 141                         return result;
 142
 143                 cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, data);
 144         }
 145
 146         return 0;
 147 }
 148
 149
 150 int smu7_program_jump_on_start(struct pp_smumgr *smumgr)
 151 {
 152         static const unsigned char data[4] = { 0xE0, 0x00, 0x80, 0x40 };
 153
 154         smu7_copy_bytes_to_smc(smumgr, 0x0, data, 4, sizeof(data)+1);
 155
 156         return 0;
 157 }
 158
 159 bool smu7_is_smc_ram_running(struct pp_smumgr *smumgr)
 160 {
 161         return ((0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable))
 162         && (0x20100 <= cgs_read_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMC_PC_C)));
 163 }
 164
 165 int smu7_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
 166 {
 167         int ret;
 168
 169         if (!smu7_is_smc_ram_running(smumgr))
 170                 return -EINVAL;
 171
 172
 173         SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
 174
 175         ret = SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP);
 176
 177         if (ret != 1)
 178                 printk("\n failed to send pre message %x ret is %d \n",  msg, ret);
 179
 180         cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
 181
 182         SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
 183
 184         ret = SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP);
 185
 186         if (ret != 1)
 187                 printk("\n failed to send message %x ret is %d \n",  msg, ret);
 188
 189         return 0;
 190 }
 191
 192 int smu7_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr, uint16_t msg)
 193 {
 194         cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
 195
 196         return 0;
 197 }
 198
 199 int smu7_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter)
 200 {
 201         if (!smu7_is_smc_ram_running(smumgr)) {
 202                 return -EINVAL;
 203         }
 204
 205         SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
 206
 207         cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter);
 208
 209         return smu7_send_msg_to_smc(smumgr, msg);
 210 }
 211
 212 int smu7_send_msg_to_smc_with_parameter_without_waiting(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter)
 213 {
 214         cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter);
 215
 216         return smu7_send_msg_to_smc_without_waiting(smumgr, msg);
 217 }
 218
 219 int smu7_send_msg_to_smc_offset(struct pp_smumgr *smumgr)
 220 {
 221         cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, 0x20000);
 222
 223         cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test);
 224
 225         SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
 226
 227         if (1 != SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP))
 228                 printk("Failed to send Message.\n");
 229
 230         return 0;
 231 }
 232
 233 int smu7_wait_for_smc_inactive(struct pp_smumgr *smumgr)
 234 {
 235         if (!smu7_is_smc_ram_running(smumgr))
 236                 return -EINVAL;
 237
 238         SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, SMC_SYSCON_CLOCK_CNTL_0, cken, 0);
 239         return 0;
 240 }
 241
 242
 243 enum cgs_ucode_id smu7_convert_fw_type_to_cgs(uint32_t fw_type)
 244 {
 245         enum cgs_ucode_id result = CGS_UCODE_ID_MAXIMUM;
 246
 247         switch (fw_type) {
 248         case UCODE_ID_SMU:
 249                 result = CGS_UCODE_ID_SMU;
 250                 break;
 251         case UCODE_ID_SMU_SK:
 252                 result = CGS_UCODE_ID_SMU_SK;
 253                 break;
 254         case UCODE_ID_SDMA0:
 255                 result = CGS_UCODE_ID_SDMA0;
 256                 break;
 257         case UCODE_ID_SDMA1:
 258                 result = CGS_UCODE_ID_SDMA1;
 259                 break;
 260         case UCODE_ID_CP_CE:
 261                 result = CGS_UCODE_ID_CP_CE;
 262                 break;
 263         case UCODE_ID_CP_PFP:
 264                 result = CGS_UCODE_ID_CP_PFP;
 265                 break;
 266         case UCODE_ID_CP_ME:
 267                 result = CGS_UCODE_ID_CP_ME;
 268                 break;
 269         case UCODE_ID_CP_MEC:
 270                 result = CGS_UCODE_ID_CP_MEC;
 271                 break;
 272         case UCODE_ID_CP_MEC_JT1:
 273                 result = CGS_UCODE_ID_CP_MEC_JT1;
 274                 break;
 275         case UCODE_ID_CP_MEC_JT2:
 276                 result = CGS_UCODE_ID_CP_MEC_JT2;
 277                 break;
 278         case UCODE_ID_RLC_G:
 279                 result = CGS_UCODE_ID_RLC_G;
 280                 break;
 281         default:
 282                 break;
 283         }
 284
 285         return result;
 286 }
 287
 288
 289 int smu7_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t *value, uint32_t limit)
 290 {
 291         int result;
 292
 293         result = smu7_set_smc_sram_address(smumgr, smc_addr, limit);
 294
 295         if (result)
 296                 return result;
 297
 298         *value = cgs_read_register(smumgr->device, mmSMC_IND_DATA_11);
 299         return 0;
 300 }
 301
 302 int smu7_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t value, uint32_t limit)
 303 {
 304         int result;
 305
 306         result = smu7_set_smc_sram_address(smumgr, smc_addr, limit);
 307
 308         if (result)
 309                 return result;
 310
 311         cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, value);
 312
 313         return 0;
 314 }
 315
 316 /* Convert the firmware type to SMU type mask. For MEC, we need to check all MEC related type */
 317
 318 static uint32_t smu7_get_mask_for_firmware_type(uint32_t fw_type)
 319 {
 320         uint32_t result = 0;
 321
 322         switch (fw_type) {
 323         case UCODE_ID_SDMA0:
 324                 result = UCODE_ID_SDMA0_MASK;
 325                 break;
 326         case UCODE_ID_SDMA1:
 327                 result = UCODE_ID_SDMA1_MASK;
 328                 break;
 329         case UCODE_ID_CP_CE:
 330                 result = UCODE_ID_CP_CE_MASK;
 331                 break;
 332         case UCODE_ID_CP_PFP:
 333                 result = UCODE_ID_CP_PFP_MASK;
 334                 break;
 335         case UCODE_ID_CP_ME:
 336                 result = UCODE_ID_CP_ME_MASK;
 337                 break;
 338         case UCODE_ID_CP_MEC:
 339         case UCODE_ID_CP_MEC_JT1:
 340         case UCODE_ID_CP_MEC_JT2:
 341                 result = UCODE_ID_CP_MEC_MASK;
 342                 break;
 343         case UCODE_ID_RLC_G:
 344                 result = UCODE_ID_RLC_G_MASK;
 345                 break;
 346         default:
 347                 printk("UCode type is out of range! \n");
 348                 result = 0;
 349         }
 350
 351         return result;
 352 }
 353
 354 static int smu7_populate_single_firmware_entry(struct pp_smumgr *smumgr,
 355                                                 uint32_t fw_type,
 356                                                 struct SMU_Entry *entry)
 357 {
 358         int result = 0;
 359         struct cgs_firmware_info info = {0};
 360
 361         result = cgs_get_firmware_info(smumgr->device,
 362                                 smu7_convert_fw_type_to_cgs(fw_type),
 363                                 &info);
 364
 365         if (!result) {
 366                 entry->version = info.version;
 367                 entry->id = (uint16_t)fw_type;
 368                 entry->image_addr_high = smu_upper_32_bits(info.mc_addr);
 369                 entry->image_addr_low = smu_lower_32_bits(info.mc_addr);
 370                 entry->meta_data_addr_high = 0;
 371                 entry->meta_data_addr_low = 0;
 372                 entry->data_size_byte = info.image_size;
 373                 entry->num_register_entries = 0;
 374         }
 375
 376         if (fw_type == UCODE_ID_RLC_G)
 377                 entry->flags = 1;
 378         else
 379                 entry->flags = 0;
 380
 381         return 0;
 382 }
 383
 384 int smu7_request_smu_load_fw(struct pp_smumgr *smumgr)
 385 {
 386         struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
 387         uint32_t fw_to_load;
 388         int result = 0;
 389         struct SMU_DRAMData_TOC *toc;
 390
 391         if (!smumgr->reload_fw) {
 392                 printk(KERN_INFO "[ powerplay ] skip reloading...\n");
 393                 return 0;
 394         }
 395
 396         if (smu_data->soft_regs_start)
 397                 cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
 398                                         smu_data->soft_regs_start + smum_get_offsetof(smumgr,
 399                                         SMU_SoftRegisters, UcodeLoadStatus),
 400                                         0x0);
 401
 402         if (smumgr->chip_id > CHIP_TOPAZ) { /* add support for Topaz */
 403                 smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_SMU_DRAM_ADDR_HI, smu_data->smu_buffer.mc_addr_high);
 404                 smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_SMU_DRAM_ADDR_LO, smu_data->smu_buffer.mc_addr_low);
 405                 fw_to_load = UCODE_ID_RLC_G_MASK
 406                            + UCODE_ID_SDMA0_MASK
 407                            + UCODE_ID_SDMA1_MASK
 408                            + UCODE_ID_CP_CE_MASK
 409                            + UCODE_ID_CP_ME_MASK
 410                            + UCODE_ID_CP_PFP_MASK
 411                            + UCODE_ID_CP_MEC_MASK;
 412         } else {
 413                 fw_to_load = UCODE_ID_RLC_G_MASK
 414                            + UCODE_ID_SDMA0_MASK
 415                            + UCODE_ID_SDMA1_MASK
 416                            + UCODE_ID_CP_CE_MASK
 417                            + UCODE_ID_CP_ME_MASK
 418                            + UCODE_ID_CP_PFP_MASK
 419                            + UCODE_ID_CP_MEC_MASK
 420                            + UCODE_ID_CP_MEC_JT1_MASK
 421                            + UCODE_ID_CP_MEC_JT2_MASK;
 422         }
 423
 424         toc = (struct SMU_DRAMData_TOC *)smu_data->header;
 425         toc->num_entries = 0;
 426         toc->structure_version = 1;
 427
 428         PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr,
 429                                 UCODE_ID_RLC_G, &toc->entry[toc->num_entries++]),
 430                                 "Failed to Get Firmware Entry.", return -EINVAL);
 431         PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr,
 432                                 UCODE_ID_CP_CE, &toc->entry[toc->num_entries++]),
 433                                 "Failed to Get Firmware Entry.", return -EINVAL);
 434         PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr,
 435                                 UCODE_ID_CP_PFP, &toc->entry[toc->num_entries++]),
 436                                 "Failed to Get Firmware Entry.", return -EINVAL);
 437         PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr,
 438                                 UCODE_ID_CP_ME, &toc->entry[toc->num_entries++]),
 439                                 "Failed to Get Firmware Entry.", return -EINVAL);
 440         PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr,
 441                                 UCODE_ID_CP_MEC, &toc->entry[toc->num_entries++]),
 442                                 "Failed to Get Firmware Entry.", return -EINVAL);
 443         PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr,
 444                                 UCODE_ID_CP_MEC_JT1, &toc->entry[toc->num_entries++]),
 445                                 "Failed to Get Firmware Entry.", return -EINVAL);
 446         PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr,
 447                                 UCODE_ID_CP_MEC_JT2, &toc->entry[toc->num_entries++]),
 448                                 "Failed to Get Firmware Entry.", return -EINVAL);
 449         PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr,
 450                                 UCODE_ID_SDMA0, &toc->entry[toc->num_entries++]),
 451                                 "Failed to Get Firmware Entry.", return -EINVAL);
 452         PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr,
 453                                 UCODE_ID_SDMA1, &toc->entry[toc->num_entries++]),
 454                                 "Failed to Get Firmware Entry.", return -EINVAL);
 455
 456         smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, smu_data->header_buffer.mc_addr_high);
 457         smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, smu_data->header_buffer.mc_addr_low);
 458
 459         if (smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_LoadUcodes, fw_to_load))
 460                 printk(KERN_ERR "Fail to Request SMU Load uCode");
 461
 462         return result;
 463 }
 464
 465 /* Check if the FW has been loaded, SMU will not return if loading has not finished. */
 466 int smu7_check_fw_load_finish(struct pp_smumgr *smumgr, uint32_t fw_type)
 467 {
 468         struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
 469         uint32_t fw_mask = smu7_get_mask_for_firmware_type(fw_type);
 470         uint32_t ret;
 471
 472         ret = smum_wait_on_indirect_register(smumgr, mmSMC_IND_INDEX_11,
 473                                         smu_data->soft_regs_start + smum_get_offsetof(smumgr,
 474                                         SMU_SoftRegisters, UcodeLoadStatus),
 475                                         fw_mask, fw_mask);
 476
 477         return ret;
 478 }
 479
 480 int smu7_reload_firmware(struct pp_smumgr *smumgr)
 481 {
 482         return smumgr->smumgr_funcs->start_smu(smumgr);
 483 }
 484
 485 static int smu7_upload_smc_firmware_data(struct pp_smumgr *smumgr, uint32_t length, uint32_t *src, uint32_t limit)
 486 {
 487         uint32_t byte_count = length;
 488
 489         PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -EINVAL);
 490
 491         cgs_write_register(smumgr->device, mmSMC_IND_INDEX_11, 0x20000);
 492         SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 1);
 493
 494         for (; byte_count >= 4; byte_count -= 4)
 495                 cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, *src++);
 496
 497         SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0);
 498
 499         PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be dividable by 4.", return -EINVAL);
 500
 501         return 0;
 502 }
 503
 504
 505 int smu7_upload_smu_firmware_image(struct pp_smumgr *smumgr)
 506 {
 507         int result = 0;
 508         struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
 509
 510         struct cgs_firmware_info info = {0};
 511
 512         if (smu_data->security_hard_key == 1)
 513                 cgs_get_firmware_info(smumgr->device,
 514                         smu7_convert_fw_type_to_cgs(UCODE_ID_SMU), &info);
 515         else
 516                 cgs_get_firmware_info(smumgr->device,
 517                         smu7_convert_fw_type_to_cgs(UCODE_ID_SMU_SK), &info);
 518
 519         result = smu7_upload_smc_firmware_data(smumgr, info.image_size, (uint32_t *)info.kptr, SMU7_SMC_SIZE);
 520
 521         return result;
 522 }
 523
 524
 525 int smu7_init(struct pp_smumgr *smumgr)
 526 {
 527         struct smu7_smumgr *smu_data;
 528         uint8_t *internal_buf;
 529         uint64_t mc_addr = 0;
 530
 531         /* Allocate memory for backend private data */
 532         smu_data = (struct smu7_smumgr *)(smumgr->backend);
 533         smu_data->header_buffer.data_size =
 534                         ((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096;
 535         smu_data->smu_buffer.data_size = 200*4096;
 536
 537 /* Allocate FW image data structure and header buffer and
 538  * send the header buffer address to SMU */
 539         smu_allocate_memory(smumgr->device,
 540                 smu_data->header_buffer.data_size,
 541                 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
 542                 PAGE_SIZE,
 543                 &mc_addr,
 544                 &smu_data->header_buffer.kaddr,
 545                 &smu_data->header_buffer.handle);
 546
 547         smu_data->header = smu_data->header_buffer.kaddr;
 548         smu_data->header_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);
 549         smu_data->header_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);
 550
 551         PP_ASSERT_WITH_CODE((NULL != smu_data->header),
 552                 "Out of memory.",
 553                 kfree(smumgr->backend);
 554                 cgs_free_gpu_mem(smumgr->device,
 555                 (cgs_handle_t)smu_data->header_buffer.handle);
 556                 return -EINVAL);
 557
 558         smu_allocate_memory(smumgr->device,
 559                 smu_data->smu_buffer.data_size,
 560                 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
 561                 PAGE_SIZE,
 562                 &mc_addr,
 563                 &smu_data->smu_buffer.kaddr,
 564                 &smu_data->smu_buffer.handle);
 565
 566         internal_buf = smu_data->smu_buffer.kaddr;
 567         smu_data->smu_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);
 568         smu_data->smu_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);
 569
 570         PP_ASSERT_WITH_CODE((NULL != internal_buf),
 571                 "Out of memory.",
 572                 kfree(smumgr->backend);
 573                 cgs_free_gpu_mem(smumgr->device,
 574                 (cgs_handle_t)smu_data->smu_buffer.handle);
 575                 return -EINVAL);
 576
 577         return 0;
 578 }
 579
 580
 581 int smu7_smu_fini(struct pp_smumgr *smumgr)
 582 {
 583         if (smumgr->backend) {
 584                 kfree(smumgr->backend);
 585                 smumgr->backend = NULL;
 586         }
 587         cgs_rel_firmware(smumgr->device, CGS_UCODE_ID_SMU);
 588         return 0;
 589 }