drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/types.h>
  24 #include <linux/kernel.h>
  25 #include <linux/slab.h>
  26 #include "pp_instance.h"
  27 #include "smumgr.h"
  28 #include "cgs_common.h"
  29 #include "linux/delay.h"
  30 #include "cz_smumgr.h"
  31 #include "tonga_smumgr.h"
  32 #include "fiji_smumgr.h"
  33 #include "polaris10_smumgr.h"
  34
  35 int smum_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
  36 {
  37         struct pp_smumgr *smumgr;
  38
  39         if ((handle == NULL) || (pp_init == NULL))
  40                 return -EINVAL;
  41
  42         smumgr = kzalloc(sizeof(struct pp_smumgr), GFP_KERNEL);
  43         if (smumgr == NULL)
  44                 return -ENOMEM;
  45
  46         smumgr->device = pp_init->device;
  47         smumgr->chip_family = pp_init->chip_family;
  48         smumgr->chip_id = pp_init->chip_id;
  49         smumgr->hw_revision = pp_init->rev_id;
  50         smumgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;
  51         smumgr->reload_fw = 1;
  52         handle->smu_mgr = smumgr;
  53
  54         switch (smumgr->chip_family) {
  55         case AMD_FAMILY_CZ:
  56                 cz_smum_init(smumgr);
  57                 break;
  58         case AMD_FAMILY_VI:
  59                 switch (smumgr->chip_id) {
  60                 case CHIP_TONGA:
  61                         tonga_smum_init(smumgr);
  62                         break;
  63                 case CHIP_FIJI:
  64                         fiji_smum_init(smumgr);
  65                         break;
  66                 case CHIP_POLARIS11:
  67                 case CHIP_POLARIS10:
  68                         polaris10_smum_init(smumgr);
  69                         break;
  70                 default:
  71                         return -EINVAL;
  72                 }
  73                 break;
  74         default:
  75                 kfree(smumgr);
  76                 return -EINVAL;
  77         }
  78
  79         return 0;
  80 }
  81
  82 int smum_fini(struct pp_smumgr *smumgr)
  83 {
  84         kfree(smumgr);
  85         return 0;
  86 }
  87
  88 int smum_get_argument(struct pp_smumgr *smumgr)
  89 {
  90         if (NULL != smumgr->smumgr_funcs->get_argument)
  91                 return smumgr->smumgr_funcs->get_argument(smumgr);
  92
  93         return 0;
  94 }
  95
  96 int smum_download_powerplay_table(struct pp_smumgr *smumgr,
  97                                                                 void **table)
  98 {
  99         if (NULL != smumgr->smumgr_funcs->download_pptable_settings)
 100                 return smumgr->smumgr_funcs->download_pptable_settings(smumgr,
 101                                                                         table);
 102
 103         return 0;
 104 }
 105
 106 int smum_upload_powerplay_table(struct pp_smumgr *smumgr)
 107 {
 108         if (NULL != smumgr->smumgr_funcs->upload_pptable_settings)
 109                 return smumgr->smumgr_funcs->upload_pptable_settings(smumgr);
 110
 111         return 0;
 112 }
 113
 114 int smum_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
 115 {
 116         if (smumgr == NULL || smumgr->smumgr_funcs->send_msg_to_smc == NULL)
 117                 return -EINVAL;
 118
 119         return smumgr->smumgr_funcs->send_msg_to_smc(smumgr, msg);
 120 }
 121
 122 int smum_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
 123                                         uint16_t msg, uint32_t parameter)
 124 {
 125         if (smumgr == NULL ||
 126                 smumgr->smumgr_funcs->send_msg_to_smc_with_parameter == NULL)
 127                 return -EINVAL;
 128         return smumgr->smumgr_funcs->send_msg_to_smc_with_parameter(
 129                                                 smumgr, msg, parameter);
 130 }
 131
 132 /*
 133  * Returns once the part of the register indicated by the mask has
 134  * reached the given value.
 135  */
 136 int smum_wait_on_register(struct pp_smumgr *smumgr,
 137                                 uint32_t index,
 138                                 uint32_t value, uint32_t mask)
 139 {
 140         uint32_t i;
 141         uint32_t cur_value;
 142
 143         if (smumgr == NULL || smumgr->device == NULL)
 144                 return -EINVAL;
 145
 146         for (i = 0; i < smumgr->usec_timeout; i++) {
 147                 cur_value = cgs_read_register(smumgr->device, index);
 148                 if ((cur_value & mask) == (value & mask))
 149                         break;
 150                 udelay(1);
 151         }
 152
 153         /* timeout means wrong logic*/
 154         if (i == smumgr->usec_timeout)
 155                 return -1;
 156
 157         return 0;
 158 }
 159
 160 int smum_wait_for_register_unequal(struct pp_smumgr *smumgr,
 161                                         uint32_t index,
 162                                         uint32_t value, uint32_t mask)
 163 {
 164         uint32_t i;
 165         uint32_t cur_value;
 166
 167         if (smumgr == NULL)
 168                 return -EINVAL;
 169
 170         for (i = 0; i < smumgr->usec_timeout; i++) {
 171                 cur_value = cgs_read_register(smumgr->device,
 172                                                                         index);
 173                 if ((cur_value & mask) != (value & mask))
 174                         break;
 175                 udelay(1);
 176         }
 177
 178         /* timeout means wrong logic */
 179         if (i == smumgr->usec_timeout)
 180                 return -1;
 181
 182         return 0;
 183 }
 184
 185
 186 /*
 187  * Returns once the part of the register indicated by the mask
 188  * has reached the given value.The indirect space is described by
 189  * giving the memory-mapped index of the indirect index register.
 190  */
 191 int smum_wait_on_indirect_register(struct pp_smumgr *smumgr,
 192                                         uint32_t indirect_port,
 193                                         uint32_t index,
 194                                         uint32_t value,
 195                                         uint32_t mask)
 196 {
 197         if (smumgr == NULL || smumgr->device == NULL)
 198                 return -EINVAL;
 199
 200         cgs_write_register(smumgr->device, indirect_port, index);
 201         return smum_wait_on_register(smumgr, indirect_port + 1,
 202                                                 mask, value);
 203 }
 204
 205 void smum_wait_for_indirect_register_unequal(
 206                                                 struct pp_smumgr *smumgr,
 207                                                 uint32_t indirect_port,
 208                                                 uint32_t index,
 209                                                 uint32_t value,
 210                                                 uint32_t mask)
 211 {
 212         if (smumgr == NULL || smumgr->device == NULL)
 213                 return;
 214         cgs_write_register(smumgr->device, indirect_port, index);
 215         smum_wait_for_register_unequal(smumgr, indirect_port + 1,
 216                                                 value, mask);
 217 }
 218
 219 int smu_allocate_memory(void *device, uint32_t size,
 220                          enum cgs_gpu_mem_type type,
 221                          uint32_t byte_align, uint64_t *mc_addr,
 222                          void **kptr, void *handle)
 223 {
 224         int ret = 0;
 225         cgs_handle_t cgs_handle;
 226
 227         if (device == NULL || handle == NULL ||
 228             mc_addr == NULL || kptr == NULL)
 229                 return -EINVAL;
 230
 231         ret = cgs_alloc_gpu_mem(device, type, size, byte_align,
 232                                 0, 0, (cgs_handle_t *)handle);
 233         if (ret)
 234                 return -ENOMEM;
 235
 236         cgs_handle = *(cgs_handle_t *)handle;
 237
 238         ret = cgs_gmap_gpu_mem(device, cgs_handle, mc_addr);
 239         if (ret)
 240                 goto error_gmap;
 241
 242         ret = cgs_kmap_gpu_mem(device, cgs_handle, kptr);
 243         if (ret)
 244                 goto error_kmap;
 245
 246         return 0;
 247
 248 error_kmap:
 249         cgs_gunmap_gpu_mem(device, cgs_handle);
 250
 251 error_gmap:
 252         cgs_free_gpu_mem(device, cgs_handle);
 253         return ret;
 254 }
 255
 256 int smu_free_memory(void *device, void *handle)
 257 {
 258         cgs_handle_t cgs_handle = (cgs_handle_t)handle;
 259
 260         if (device == NULL || handle == NULL)
 261                 return -EINVAL;
 262
 263         cgs_kunmap_gpu_mem(device, cgs_handle);
 264         cgs_gunmap_gpu_mem(device, cgs_handle);
 265         cgs_free_gpu_mem(device, cgs_handle);
 266
 267         return 0;
 268 }