2 * Copyright (C) 2013-2015 ARM Limited
3 * Author: Liviu Dudau <Liviu.Dudau@arm.com>
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file COPYING in the main directory of this archive
12 #include <linux/module.h>
13 #include <linux/spinlock.h>
14 #include <linux/clk.h>
15 #include <linux/component.h>
16 #include <linux/list.h>
17 #include <linux/of_graph.h>
18 #include <linux/of_reserved_mem.h>
19 #include <linux/pm_runtime.h>
22 #include <drm/drm_atomic_helper.h>
23 #include <drm/drm_crtc.h>
24 #include <drm/drm_crtc_helper.h>
25 #include <drm/drm_fb_helper.h>
26 #include <drm/drm_fb_cma_helper.h>
27 #include <drm/drm_gem_cma_helper.h>
28 #include <drm/drm_of.h>
30 #include "hdlcd_drv.h"
31 #include "hdlcd_regs.h"
33 static int hdlcd_load(struct drm_device *drm, unsigned long flags)
35 struct hdlcd_drm_private *hdlcd = drm->dev_private;
36 struct platform_device *pdev = to_platform_device(drm->dev);
41 hdlcd->clk = devm_clk_get(drm->dev, "pxlclk");
42 if (IS_ERR(hdlcd->clk))
43 return PTR_ERR(hdlcd->clk);
45 #ifdef CONFIG_DEBUG_FS
46 atomic_set(&hdlcd->buffer_underrun_count, 0);
47 atomic_set(&hdlcd->bus_error_count, 0);
48 atomic_set(&hdlcd->vsync_count, 0);
49 atomic_set(&hdlcd->dma_end_count, 0);
52 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
53 hdlcd->mmio = devm_ioremap_resource(drm->dev, res);
54 if (IS_ERR(hdlcd->mmio)) {
55 DRM_ERROR("failed to map control registers area\n");
56 ret = PTR_ERR(hdlcd->mmio);
61 version = hdlcd_read(hdlcd, HDLCD_REG_VERSION);
62 if ((version & HDLCD_PRODUCT_MASK) != HDLCD_PRODUCT_ID) {
63 DRM_ERROR("unknown product id: 0x%x\n", version);
66 DRM_INFO("found ARM HDLCD version r%dp%d\n",
67 (version & HDLCD_VERSION_MAJOR_MASK) >> 8,
68 version & HDLCD_VERSION_MINOR_MASK);
70 /* Get the optional framebuffer memory resource */
71 ret = of_reserved_mem_device_init(drm->dev);
72 if (ret && ret != -ENODEV)
75 ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32));
79 ret = hdlcd_setup_crtc(drm);
81 DRM_ERROR("failed to create crtc\n");
85 ret = drm_irq_install(drm, platform_get_irq(pdev, 0));
87 DRM_ERROR("failed to install IRQ handler\n");
94 drm_crtc_cleanup(&hdlcd->crtc);
96 of_reserved_mem_device_release(drm->dev);
101 static void hdlcd_fb_output_poll_changed(struct drm_device *drm)
103 struct hdlcd_drm_private *hdlcd = drm->dev_private;
106 drm_fbdev_cma_hotplug_event(hdlcd->fbdev);
109 static int hdlcd_atomic_commit(struct drm_device *dev,
110 struct drm_atomic_state *state, bool nonblock)
112 return drm_atomic_helper_commit(dev, state, false);
115 static const struct drm_mode_config_funcs hdlcd_mode_config_funcs = {
116 .fb_create = drm_fb_cma_create,
117 .output_poll_changed = hdlcd_fb_output_poll_changed,
118 .atomic_check = drm_atomic_helper_check,
119 .atomic_commit = hdlcd_atomic_commit,
122 static void hdlcd_setup_mode_config(struct drm_device *drm)
124 drm_mode_config_init(drm);
125 drm->mode_config.min_width = 0;
126 drm->mode_config.min_height = 0;
127 drm->mode_config.max_width = HDLCD_MAX_XRES;
128 drm->mode_config.max_height = HDLCD_MAX_YRES;
129 drm->mode_config.funcs = &hdlcd_mode_config_funcs;
132 static void hdlcd_lastclose(struct drm_device *drm)
134 struct hdlcd_drm_private *hdlcd = drm->dev_private;
136 drm_fbdev_cma_restore_mode(hdlcd->fbdev);
139 static irqreturn_t hdlcd_irq(int irq, void *arg)
141 struct drm_device *drm = arg;
142 struct hdlcd_drm_private *hdlcd = drm->dev_private;
143 unsigned long irq_status;
145 irq_status = hdlcd_read(hdlcd, HDLCD_REG_INT_STATUS);
147 #ifdef CONFIG_DEBUG_FS
148 if (irq_status & HDLCD_INTERRUPT_UNDERRUN)
149 atomic_inc(&hdlcd->buffer_underrun_count);
151 if (irq_status & HDLCD_INTERRUPT_DMA_END)
152 atomic_inc(&hdlcd->dma_end_count);
154 if (irq_status & HDLCD_INTERRUPT_BUS_ERROR)
155 atomic_inc(&hdlcd->bus_error_count);
157 if (irq_status & HDLCD_INTERRUPT_VSYNC)
158 atomic_inc(&hdlcd->vsync_count);
161 if (irq_status & HDLCD_INTERRUPT_VSYNC)
162 drm_crtc_handle_vblank(&hdlcd->crtc);
164 /* acknowledge interrupt(s) */
165 hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, irq_status);
170 static void hdlcd_irq_preinstall(struct drm_device *drm)
172 struct hdlcd_drm_private *hdlcd = drm->dev_private;
173 /* Ensure interrupts are disabled */
174 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, 0);
175 hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, ~0);
178 static int hdlcd_irq_postinstall(struct drm_device *drm)
180 #ifdef CONFIG_DEBUG_FS
181 struct hdlcd_drm_private *hdlcd = drm->dev_private;
182 unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
184 /* enable debug interrupts */
185 irq_mask |= HDLCD_DEBUG_INT_MASK;
187 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask);
192 static void hdlcd_irq_uninstall(struct drm_device *drm)
194 struct hdlcd_drm_private *hdlcd = drm->dev_private;
195 /* disable all the interrupts that we might have enabled */
196 unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
198 #ifdef CONFIG_DEBUG_FS
199 /* disable debug interrupts */
200 irq_mask &= ~HDLCD_DEBUG_INT_MASK;
203 /* disable vsync interrupts */
204 irq_mask &= ~HDLCD_INTERRUPT_VSYNC;
206 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask);
209 static int hdlcd_enable_vblank(struct drm_device *drm, unsigned int crtc)
211 struct hdlcd_drm_private *hdlcd = drm->dev_private;
212 unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
214 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask | HDLCD_INTERRUPT_VSYNC);
219 static void hdlcd_disable_vblank(struct drm_device *drm, unsigned int crtc)
221 struct hdlcd_drm_private *hdlcd = drm->dev_private;
222 unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
224 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask & ~HDLCD_INTERRUPT_VSYNC);
227 #ifdef CONFIG_DEBUG_FS
228 static int hdlcd_show_underrun_count(struct seq_file *m, void *arg)
230 struct drm_info_node *node = (struct drm_info_node *)m->private;
231 struct drm_device *drm = node->minor->dev;
232 struct hdlcd_drm_private *hdlcd = drm->dev_private;
234 seq_printf(m, "underrun : %d\n", atomic_read(&hdlcd->buffer_underrun_count));
235 seq_printf(m, "dma_end : %d\n", atomic_read(&hdlcd->dma_end_count));
236 seq_printf(m, "bus_error: %d\n", atomic_read(&hdlcd->bus_error_count));
237 seq_printf(m, "vsync : %d\n", atomic_read(&hdlcd->vsync_count));
241 static int hdlcd_show_pxlclock(struct seq_file *m, void *arg)
243 struct drm_info_node *node = (struct drm_info_node *)m->private;
244 struct drm_device *drm = node->minor->dev;
245 struct hdlcd_drm_private *hdlcd = drm->dev_private;
246 unsigned long clkrate = clk_get_rate(hdlcd->clk);
247 unsigned long mode_clock = hdlcd->crtc.mode.crtc_clock * 1000;
249 seq_printf(m, "hw : %lu\n", clkrate);
250 seq_printf(m, "mode: %lu\n", mode_clock);
254 static struct drm_info_list hdlcd_debugfs_list[] = {
255 { "interrupt_count", hdlcd_show_underrun_count, 0 },
256 { "clocks", hdlcd_show_pxlclock, 0 },
259 static int hdlcd_debugfs_init(struct drm_minor *minor)
261 return drm_debugfs_create_files(hdlcd_debugfs_list,
262 ARRAY_SIZE(hdlcd_debugfs_list), minor->debugfs_root, minor);
265 static void hdlcd_debugfs_cleanup(struct drm_minor *minor)
267 drm_debugfs_remove_files(hdlcd_debugfs_list,
268 ARRAY_SIZE(hdlcd_debugfs_list), minor);
272 static const struct file_operations fops = {
273 .owner = THIS_MODULE,
275 .release = drm_release,
276 .unlocked_ioctl = drm_ioctl,
278 .compat_ioctl = drm_compat_ioctl,
282 .llseek = noop_llseek,
283 .mmap = drm_gem_cma_mmap,
286 static struct drm_driver hdlcd_driver = {
287 .driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM |
288 DRIVER_MODESET | DRIVER_PRIME |
290 .lastclose = hdlcd_lastclose,
291 .irq_handler = hdlcd_irq,
292 .irq_preinstall = hdlcd_irq_preinstall,
293 .irq_postinstall = hdlcd_irq_postinstall,
294 .irq_uninstall = hdlcd_irq_uninstall,
295 .get_vblank_counter = drm_vblank_no_hw_counter,
296 .enable_vblank = hdlcd_enable_vblank,
297 .disable_vblank = hdlcd_disable_vblank,
298 .gem_free_object = drm_gem_cma_free_object,
299 .gem_vm_ops = &drm_gem_cma_vm_ops,
300 .dumb_create = drm_gem_cma_dumb_create,
301 .dumb_map_offset = drm_gem_cma_dumb_map_offset,
302 .dumb_destroy = drm_gem_dumb_destroy,
303 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
304 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
305 .gem_prime_export = drm_gem_prime_export,
306 .gem_prime_import = drm_gem_prime_import,
307 .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
308 .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
309 .gem_prime_vmap = drm_gem_cma_prime_vmap,
310 .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
311 .gem_prime_mmap = drm_gem_cma_prime_mmap,
312 #ifdef CONFIG_DEBUG_FS
313 .debugfs_init = hdlcd_debugfs_init,
314 .debugfs_cleanup = hdlcd_debugfs_cleanup,
318 .desc = "ARM HDLCD Controller DRM",
324 static int hdlcd_drm_bind(struct device *dev)
326 struct drm_device *drm;
327 struct hdlcd_drm_private *hdlcd;
330 hdlcd = devm_kzalloc(dev, sizeof(*hdlcd), GFP_KERNEL);
334 drm = drm_dev_alloc(&hdlcd_driver, dev);
338 drm->dev_private = hdlcd;
339 dev_set_drvdata(dev, drm);
341 hdlcd_setup_mode_config(drm);
342 ret = hdlcd_load(drm, 0);
346 ret = drm_dev_register(drm, 0);
350 ret = component_bind_all(dev, drm);
352 DRM_ERROR("Failed to bind all components\n");
356 ret = pm_runtime_set_active(dev);
360 pm_runtime_enable(dev);
362 ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
364 DRM_ERROR("failed to initialise vblank\n");
368 drm_mode_config_reset(drm);
369 drm_kms_helper_poll_init(drm);
371 hdlcd->fbdev = drm_fbdev_cma_init(drm, 32, drm->mode_config.num_crtc,
372 drm->mode_config.num_connector);
374 if (IS_ERR(hdlcd->fbdev)) {
375 ret = PTR_ERR(hdlcd->fbdev);
383 drm_kms_helper_poll_fini(drm);
384 drm_mode_config_cleanup(drm);
385 drm_vblank_cleanup(drm);
387 pm_runtime_disable(drm->dev);
389 component_unbind_all(dev, drm);
391 drm_dev_unregister(drm);
393 drm_irq_uninstall(drm);
394 of_reserved_mem_device_release(drm->dev);
396 dev_set_drvdata(dev, NULL);
402 static void hdlcd_drm_unbind(struct device *dev)
404 struct drm_device *drm = dev_get_drvdata(dev);
405 struct hdlcd_drm_private *hdlcd = drm->dev_private;
408 drm_fbdev_cma_fini(hdlcd->fbdev);
411 drm_kms_helper_poll_fini(drm);
412 component_unbind_all(dev, drm);
413 drm_vblank_cleanup(drm);
414 pm_runtime_get_sync(drm->dev);
415 drm_irq_uninstall(drm);
416 pm_runtime_put_sync(drm->dev);
417 pm_runtime_disable(drm->dev);
418 of_reserved_mem_device_release(drm->dev);
419 drm_mode_config_cleanup(drm);
420 drm_dev_unregister(drm);
422 drm->dev_private = NULL;
423 dev_set_drvdata(dev, NULL);
426 static const struct component_master_ops hdlcd_master_ops = {
427 .bind = hdlcd_drm_bind,
428 .unbind = hdlcd_drm_unbind,
431 static int compare_dev(struct device *dev, void *data)
433 return dev->of_node == data;
436 static int hdlcd_probe(struct platform_device *pdev)
438 struct device_node *port, *ep;
439 struct component_match *match = NULL;
441 if (!pdev->dev.of_node)
444 /* there is only one output port inside each device, find it */
445 ep = of_graph_get_next_endpoint(pdev->dev.of_node, NULL);
449 if (!of_device_is_available(ep)) {
454 /* add the remote encoder port as component */
455 port = of_graph_get_remote_port_parent(ep);
457 if (!port || !of_device_is_available(port)) {
462 component_match_add(&pdev->dev, &match, compare_dev, port);
464 return component_master_add_with_match(&pdev->dev, &hdlcd_master_ops,
468 static int hdlcd_remove(struct platform_device *pdev)
470 component_master_del(&pdev->dev, &hdlcd_master_ops);
474 static const struct of_device_id hdlcd_of_match[] = {
475 { .compatible = "arm,hdlcd" },
478 MODULE_DEVICE_TABLE(of, hdlcd_of_match);
480 static int __maybe_unused hdlcd_pm_suspend(struct device *dev)
482 struct drm_device *drm = dev_get_drvdata(dev);
483 struct hdlcd_drm_private *hdlcd = drm ? drm->dev_private : NULL;
488 drm_kms_helper_poll_disable(drm);
490 hdlcd->state = drm_atomic_helper_suspend(drm);
491 if (IS_ERR(hdlcd->state)) {
492 drm_kms_helper_poll_enable(drm);
493 return PTR_ERR(hdlcd->state);
499 static int __maybe_unused hdlcd_pm_resume(struct device *dev)
501 struct drm_device *drm = dev_get_drvdata(dev);
502 struct hdlcd_drm_private *hdlcd = drm ? drm->dev_private : NULL;
507 drm_atomic_helper_resume(drm, hdlcd->state);
508 drm_kms_helper_poll_enable(drm);
509 pm_runtime_set_active(dev);
514 static SIMPLE_DEV_PM_OPS(hdlcd_pm_ops, hdlcd_pm_suspend, hdlcd_pm_resume);
516 static struct platform_driver hdlcd_platform_driver = {
517 .probe = hdlcd_probe,
518 .remove = hdlcd_remove,
522 .of_match_table = hdlcd_of_match,
526 module_platform_driver(hdlcd_platform_driver);
528 MODULE_AUTHOR("Liviu Dudau");
529 MODULE_DESCRIPTION("ARM HDLCD DRM driver");
530 MODULE_LICENSE("GPL v2");