drivers/gpu/drm/armada/armada_crtc.c

   1 /*
   2  * Copyright (C) 2012 Russell King
   3  *  Rewritten from the dovefb driver, and Armada510 manuals.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9 #include <linux/clk.h>
  10 #include <drm/drmP.h>
  11 #include <drm/drm_crtc_helper.h>
  12 #include "armada_crtc.h"
  13 #include "armada_drm.h"
  14 #include "armada_fb.h"
  15 #include "armada_gem.h"
  16 #include "armada_hw.h"
  17
  18 struct armada_frame_work {
  19         struct drm_pending_vblank_event *event;
  20         struct armada_regs regs[4];
  21         struct drm_framebuffer *old_fb;
  22 };
  23
  24 enum csc_mode {
  25         CSC_AUTO = 0,
  26         CSC_YUV_CCIR601 = 1,
  27         CSC_YUV_CCIR709 = 2,
  28         CSC_RGB_COMPUTER = 1,
  29         CSC_RGB_STUDIO = 2,
  30 };
  31
  32 /*
  33  * A note about interlacing.  Let's consider HDMI 1920x1080i.
  34  * The timing parameters we have from X are:
  35  *  Hact HsyA HsyI Htot  Vact VsyA VsyI Vtot
  36  *  1920 2448 2492 2640  1080 1084 1094 1125
  37  * Which get translated to:
  38  *  Hact HsyA HsyI Htot  Vact VsyA VsyI Vtot
  39  *  1920 2448 2492 2640   540  542  547  562
  40  *
  41  * This is how it is defined by CEA-861-D - line and pixel numbers are
  42  * referenced to the rising edge of VSYNC and HSYNC.  Total clocks per
  43  * line: 2640.  The odd frame, the first active line is at line 21, and
  44  * the even frame, the first active line is 584.
  45  *
  46  * LN:    560     561     562     563             567     568    569
  47  * DE:    ~~~|____________________________//__________________________
  48  * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
  49  * VSYNC: _________________________|~~~~~~//~~~~~~~~~~~~~~~|__________
  50  *  22 blanking lines.  VSYNC at 1320 (referenced to the HSYNC rising edge).
  51  *
  52  * LN:    1123   1124    1125      1               5       6      7
  53  * DE:    ~~~|____________________________//__________________________
  54  * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
  55  * VSYNC: ____________________|~~~~~~~~~~~//~~~~~~~~~~|_______________
  56  *  23 blanking lines
  57  *
  58  * The Armada LCD Controller line and pixel numbers are, like X timings,
  59  * referenced to the top left of the active frame.
  60  *
  61  * So, translating these to our LCD controller:
  62  *  Odd frame, 563 total lines, VSYNC at line 543-548, pixel 1128.
  63  *  Even frame, 562 total lines, VSYNC at line 542-547, pixel 2448.
  64  * Note: Vsync front porch remains constant!
  65  *
  66  * if (odd_frame) {
  67  *   vtotal = mode->crtc_vtotal + 1;
  68  *   vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay + 1;
  69  *   vhorizpos = mode->crtc_hsync_start - mode->crtc_htotal / 2
  70  * } else {
  71  *   vtotal = mode->crtc_vtotal;
  72  *   vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay;
  73  *   vhorizpos = mode->crtc_hsync_start;
  74  * }
  75  * vfrontporch = mode->crtc_vtotal - mode->crtc_vsync_end;
  76  *
  77  * So, we need to reprogram these registers on each vsync event:
  78  *  LCD_SPU_V_PORCH, LCD_SPU_ADV_REG, LCD_SPUT_V_H_TOTAL
  79  *
  80  * Note: we do not use the frame done interrupts because these appear
  81  * to happen too early, and lead to jitter on the display (presumably
  82  * they occur at the end of the last active line, before the vsync back
  83  * porch, which we're reprogramming.)
  84  */
  85
  86 void
  87 armada_drm_crtc_update_regs(struct armada_crtc *dcrtc, struct armada_regs *regs)
  88 {
  89         while (regs->offset != ~0) {
  90                 void __iomem *reg = dcrtc->base + regs->offset;
  91                 uint32_t val;
  92
  93                 val = regs->mask;
  94                 if (val != 0)
  95                         val &= readl_relaxed(reg);
  96                 writel_relaxed(val | regs->val, reg);
  97                 ++regs;
  98         }
  99 }
 100
 101 #define dpms_blanked(dpms)      ((dpms) != DRM_MODE_DPMS_ON)
 102
 103 static void armada_drm_crtc_update(struct armada_crtc *dcrtc)
 104 {
 105         uint32_t dumb_ctrl;
 106
 107         dumb_ctrl = dcrtc->cfg_dumb_ctrl;
 108
 109         if (!dpms_blanked(dcrtc->dpms))
 110                 dumb_ctrl |= CFG_DUMB_ENA;
 111
 112         /*
 113          * When the dumb interface isn't in DUMB24_RGB888_0 mode, it might
 114          * be using SPI or GPIO.  If we set this to DUMB_BLANK, we will
 115          * force LCD_D[23:0] to output blank color, overriding the GPIO or
 116          * SPI usage.  So leave it as-is unless in DUMB24_RGB888_0 mode.
 117          */
 118         if (dpms_blanked(dcrtc->dpms) &&
 119             (dumb_ctrl & DUMB_MASK) == DUMB24_RGB888_0) {
 120                 dumb_ctrl &= ~DUMB_MASK;
 121                 dumb_ctrl |= DUMB_BLANK;
 122         }
 123
 124         /*
 125          * The documentation doesn't indicate what the normal state of
 126          * the sync signals are.  Sebastian Hesselbart kindly probed
 127          * these signals on his board to determine their state.
 128          *
 129          * The non-inverted state of the sync signals is active high.
 130          * Setting these bits makes the appropriate signal active low.
 131          */
 132         if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NCSYNC)
 133                 dumb_ctrl |= CFG_INV_CSYNC;
 134         if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NHSYNC)
 135                 dumb_ctrl |= CFG_INV_HSYNC;
 136         if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NVSYNC)
 137                 dumb_ctrl |= CFG_INV_VSYNC;
 138
 139         if (dcrtc->dumb_ctrl != dumb_ctrl) {
 140                 dcrtc->dumb_ctrl = dumb_ctrl;
 141                 writel_relaxed(dumb_ctrl, dcrtc->base + LCD_SPU_DUMB_CTRL);
 142         }
 143 }
 144
 145 static unsigned armada_drm_crtc_calc_fb(struct drm_framebuffer *fb,
 146         int x, int y, struct armada_regs *regs, bool interlaced)
 147 {
 148         struct armada_gem_object *obj = drm_fb_obj(fb);
 149         unsigned pitch = fb->pitches[0];
 150         unsigned offset = y * pitch + x * fb->bits_per_pixel / 8;
 151         uint32_t addr_odd, addr_even;
 152         unsigned i = 0;
 153
 154         DRM_DEBUG_DRIVER("pitch %u x %d y %d bpp %d\n",
 155                 pitch, x, y, fb->bits_per_pixel);
 156
 157         addr_odd = addr_even = obj->dev_addr + offset;
 158
 159         if (interlaced) {
 160                 addr_even += pitch;
 161                 pitch *= 2;
 162         }
 163
 164         /* write offset, base, and pitch */
 165         armada_reg_queue_set(regs, i, addr_odd, LCD_CFG_GRA_START_ADDR0);
 166         armada_reg_queue_set(regs, i, addr_even, LCD_CFG_GRA_START_ADDR1);
 167         armada_reg_queue_mod(regs, i, pitch, 0xffff, LCD_CFG_GRA_PITCH);
 168
 169         return i;
 170 }
 171
 172 static int armada_drm_crtc_queue_frame_work(struct armada_crtc *dcrtc,
 173         struct armada_frame_work *work)
 174 {
 175         struct drm_device *dev = dcrtc->crtc.dev;
 176         unsigned long flags;
 177         int ret;
 178
 179         ret = drm_vblank_get(dev, dcrtc->num);
 180         if (ret) {
 181                 DRM_ERROR("failed to acquire vblank counter\n");
 182                 return ret;
 183         }
 184
 185         spin_lock_irqsave(&dev->event_lock, flags);
 186         if (!dcrtc->frame_work)
 187                 dcrtc->frame_work = work;
 188         else
 189                 ret = -EBUSY;
 190         spin_unlock_irqrestore(&dev->event_lock, flags);
 191
 192         if (ret)
 193                 drm_vblank_put(dev, dcrtc->num);
 194
 195         return ret;
 196 }
 197
 198 static void armada_drm_crtc_complete_frame_work(struct armada_crtc *dcrtc)
 199 {
 200         struct drm_device *dev = dcrtc->crtc.dev;
 201         struct armada_frame_work *work = dcrtc->frame_work;
 202
 203         dcrtc->frame_work = NULL;
 204
 205         armada_drm_crtc_update_regs(dcrtc, work->regs);
 206
 207         if (work->event)
 208                 drm_send_vblank_event(dev, dcrtc->num, work->event);
 209
 210         drm_vblank_put(dev, dcrtc->num);
 211
 212         /* Finally, queue the process-half of the cleanup. */
 213         __armada_drm_queue_unref_work(dcrtc->crtc.dev, work->old_fb);
 214         kfree(work);
 215 }
 216
 217 static void armada_drm_crtc_finish_fb(struct armada_crtc *dcrtc,
 218         struct drm_framebuffer *fb, bool force)
 219 {
 220         struct armada_frame_work *work;
 221
 222         if (!fb)
 223                 return;
 224
 225         if (force) {
 226                 /* Display is disabled, so just drop the old fb */
 227                 drm_framebuffer_unreference(fb);
 228                 return;
 229         }
 230
 231         work = kmalloc(sizeof(*work), GFP_KERNEL);
 232         if (work) {
 233                 int i = 0;
 234                 work->event = NULL;
 235                 work->old_fb = fb;
 236                 armada_reg_queue_end(work->regs, i);
 237
 238                 if (armada_drm_crtc_queue_frame_work(dcrtc, work) == 0)
 239                         return;
 240
 241                 kfree(work);
 242         }
 243
 244         /*
 245          * Oops - just drop the reference immediately and hope for
 246          * the best.  The worst that will happen is the buffer gets
 247          * reused before it has finished being displayed.
 248          */
 249         drm_framebuffer_unreference(fb);
 250 }
 251
 252 static void armada_drm_vblank_off(struct armada_crtc *dcrtc)
 253 {
 254         struct drm_device *dev = dcrtc->crtc.dev;
 255
 256         /*
 257          * Tell the DRM core that vblank IRQs aren't going to happen for
 258          * a while.  This cleans up any pending vblank events for us.
 259          */
 260         drm_vblank_off(dev, dcrtc->num);
 261
 262         /* Handle any pending flip event. */
 263         spin_lock_irq(&dev->event_lock);
 264         if (dcrtc->frame_work)
 265                 armada_drm_crtc_complete_frame_work(dcrtc);
 266         spin_unlock_irq(&dev->event_lock);
 267 }
 268
 269 void armada_drm_crtc_gamma_set(struct drm_crtc *crtc, u16 r, u16 g, u16 b,
 270         int idx)
 271 {
 272 }
 273
 274 void armada_drm_crtc_gamma_get(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
 275         int idx)
 276 {
 277 }
 278
 279 /* The mode_config.mutex will be held for this call */
 280 static void armada_drm_crtc_dpms(struct drm_crtc *crtc, int dpms)
 281 {
 282         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 283
 284         if (dcrtc->dpms != dpms) {
 285                 dcrtc->dpms = dpms;
 286                 armada_drm_crtc_update(dcrtc);
 287                 if (dpms_blanked(dpms))
 288                         armada_drm_vblank_off(dcrtc);
 289         }
 290 }
 291
 292 /*
 293  * Prepare for a mode set.  Turn off overlay to ensure that we don't end
 294  * up with the overlay size being bigger than the active screen size.
 295  * We rely upon X refreshing this state after the mode set has completed.
 296  *
 297  * The mode_config.mutex will be held for this call
 298  */
 299 static void armada_drm_crtc_prepare(struct drm_crtc *crtc)
 300 {
 301         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 302         struct drm_plane *plane;
 303
 304         /*
 305          * If we have an overlay plane associated with this CRTC, disable
 306          * it before the modeset to avoid its coordinates being outside
 307          * the new mode parameters.  DRM doesn't provide help with this.
 308          */
 309         plane = dcrtc->plane;
 310         if (plane) {
 311                 struct drm_framebuffer *fb = plane->fb;
 312
 313                 plane->funcs->disable_plane(plane);
 314                 plane->fb = NULL;
 315                 plane->crtc = NULL;
 316                 drm_framebuffer_unreference(fb);
 317         }
 318 }
 319
 320 /* The mode_config.mutex will be held for this call */
 321 static void armada_drm_crtc_commit(struct drm_crtc *crtc)
 322 {
 323         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 324
 325         if (dcrtc->dpms != DRM_MODE_DPMS_ON) {
 326                 dcrtc->dpms = DRM_MODE_DPMS_ON;
 327                 armada_drm_crtc_update(dcrtc);
 328         }
 329 }
 330
 331 /* The mode_config.mutex will be held for this call */
 332 static bool armada_drm_crtc_mode_fixup(struct drm_crtc *crtc,
 333         const struct drm_display_mode *mode, struct drm_display_mode *adj)
 334 {
 335         struct armada_private *priv = crtc->dev->dev_private;
 336         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 337         int ret;
 338
 339         /* We can't do interlaced modes if we don't have the SPU_ADV_REG */
 340         if (!priv->variant->has_spu_adv_reg &&
 341             adj->flags & DRM_MODE_FLAG_INTERLACE)
 342                 return false;
 343
 344         /* Check whether the display mode is possible */
 345         ret = priv->variant->crtc_compute_clock(dcrtc, adj, NULL);
 346         if (ret)
 347                 return false;
 348
 349         return true;
 350 }
 351
 352 void armada_drm_crtc_irq(struct armada_crtc *dcrtc, u32 stat)
 353 {
 354         struct armada_vbl_event *e, *n;
 355         void __iomem *base = dcrtc->base;
 356
 357         if (stat & DMA_FF_UNDERFLOW)
 358                 DRM_ERROR("video underflow on crtc %u\n", dcrtc->num);
 359         if (stat & GRA_FF_UNDERFLOW)
 360                 DRM_ERROR("graphics underflow on crtc %u\n", dcrtc->num);
 361
 362         if (stat & VSYNC_IRQ)
 363                 drm_handle_vblank(dcrtc->crtc.dev, dcrtc->num);
 364
 365         spin_lock(&dcrtc->irq_lock);
 366
 367         list_for_each_entry_safe(e, n, &dcrtc->vbl_list, node) {
 368                 list_del_init(&e->node);
 369                 drm_vblank_put(dcrtc->crtc.dev, dcrtc->num);
 370                 e->fn(dcrtc, e->data);
 371         }
 372
 373         if (stat & GRA_FRAME_IRQ && dcrtc->interlaced) {
 374                 int i = stat & GRA_FRAME_IRQ0 ? 0 : 1;
 375                 uint32_t val;
 376
 377                 writel_relaxed(dcrtc->v[i].spu_v_porch, base + LCD_SPU_V_PORCH);
 378                 writel_relaxed(dcrtc->v[i].spu_v_h_total,
 379                                base + LCD_SPUT_V_H_TOTAL);
 380
 381                 val = readl_relaxed(base + LCD_SPU_ADV_REG);
 382                 val &= ~(ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF | ADV_VSYNCOFFEN);
 383                 val |= dcrtc->v[i].spu_adv_reg;
 384                 writel_relaxed(val, dcrtc->base + LCD_SPU_ADV_REG);
 385         }
 386         spin_unlock(&dcrtc->irq_lock);
 387
 388         if (stat & GRA_FRAME_IRQ) {
 389                 struct drm_device *dev = dcrtc->crtc.dev;
 390
 391                 spin_lock(&dev->event_lock);
 392                 if (dcrtc->frame_work)
 393                         armada_drm_crtc_complete_frame_work(dcrtc);
 394                 spin_unlock(&dev->event_lock);
 395
 396                 wake_up(&dcrtc->frame_wait);
 397         }
 398 }
 399
 400 /* These are locked by dev->vbl_lock */
 401 void armada_drm_crtc_disable_irq(struct armada_crtc *dcrtc, u32 mask)
 402 {
 403         if (dcrtc->irq_ena & mask) {
 404                 dcrtc->irq_ena &= ~mask;
 405                 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
 406         }
 407 }
 408
 409 void armada_drm_crtc_enable_irq(struct armada_crtc *dcrtc, u32 mask)
 410 {
 411         if ((dcrtc->irq_ena & mask) != mask) {
 412                 dcrtc->irq_ena |= mask;
 413                 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
 414                 if (readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR) & mask)
 415                         writel(0, dcrtc->base + LCD_SPU_IRQ_ISR);
 416         }
 417 }
 418
 419 static uint32_t armada_drm_crtc_calculate_csc(struct armada_crtc *dcrtc)
 420 {
 421         struct drm_display_mode *adj = &dcrtc->crtc.mode;
 422         uint32_t val = 0;
 423
 424         if (dcrtc->csc_yuv_mode == CSC_YUV_CCIR709)
 425                 val |= CFG_CSC_YUV_CCIR709;
 426         if (dcrtc->csc_rgb_mode == CSC_RGB_STUDIO)
 427                 val |= CFG_CSC_RGB_STUDIO;
 428
 429         /*
 430          * In auto mode, set the colorimetry, based upon the HDMI spec.
 431          * 1280x720p, 1920x1080p and 1920x1080i use ITU709, others use
 432          * ITU601.  It may be more appropriate to set this depending on
 433          * the source - but what if the graphic frame is YUV and the
 434          * video frame is RGB?
 435          */
 436         if ((adj->hdisplay == 1280 && adj->vdisplay == 720 &&
 437              !(adj->flags & DRM_MODE_FLAG_INTERLACE)) ||
 438             (adj->hdisplay == 1920 && adj->vdisplay == 1080)) {
 439                 if (dcrtc->csc_yuv_mode == CSC_AUTO)
 440                         val |= CFG_CSC_YUV_CCIR709;
 441         }
 442
 443         /*
 444          * We assume we're connected to a TV-like device, so the YUV->RGB
 445          * conversion should produce a limited range.  We should set this
 446          * depending on the connectors attached to this CRTC, and what
 447          * kind of device they report being connected.
 448          */
 449         if (dcrtc->csc_rgb_mode == CSC_AUTO)
 450                 val |= CFG_CSC_RGB_STUDIO;
 451
 452         return val;
 453 }
 454
 455 /* The mode_config.mutex will be held for this call */
 456 static int armada_drm_crtc_mode_set(struct drm_crtc *crtc,
 457         struct drm_display_mode *mode, struct drm_display_mode *adj,
 458         int x, int y, struct drm_framebuffer *old_fb)
 459 {
 460         struct armada_private *priv = crtc->dev->dev_private;
 461         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 462         struct armada_regs regs[17];
 463         uint32_t lm, rm, tm, bm, val, sclk;
 464         unsigned long flags;
 465         unsigned i;
 466         bool interlaced;
 467
 468         drm_framebuffer_reference(crtc->fb);
 469
 470         interlaced = !!(adj->flags & DRM_MODE_FLAG_INTERLACE);
 471
 472         i = armada_drm_crtc_calc_fb(dcrtc->crtc.fb, x, y, regs, interlaced);
 473
 474         rm = adj->crtc_hsync_start - adj->crtc_hdisplay;
 475         lm = adj->crtc_htotal - adj->crtc_hsync_end;
 476         bm = adj->crtc_vsync_start - adj->crtc_vdisplay;
 477         tm = adj->crtc_vtotal - adj->crtc_vsync_end;
 478
 479         DRM_DEBUG_DRIVER("H: %d %d %d %d lm %d rm %d\n",
 480                 adj->crtc_hdisplay,
 481                 adj->crtc_hsync_start,
 482                 adj->crtc_hsync_end,
 483                 adj->crtc_htotal, lm, rm);
 484         DRM_DEBUG_DRIVER("V: %d %d %d %d tm %d bm %d\n",
 485                 adj->crtc_vdisplay,
 486                 adj->crtc_vsync_start,
 487                 adj->crtc_vsync_end,
 488                 adj->crtc_vtotal, tm, bm);
 489
 490         /* Wait for pending flips to complete */
 491         wait_event(dcrtc->frame_wait, !dcrtc->frame_work);
 492
 493         drm_vblank_pre_modeset(crtc->dev, dcrtc->num);
 494
 495         crtc->mode = *adj;
 496
 497         val = dcrtc->dumb_ctrl & ~CFG_DUMB_ENA;
 498         if (val != dcrtc->dumb_ctrl) {
 499                 dcrtc->dumb_ctrl = val;
 500                 writel_relaxed(val, dcrtc->base + LCD_SPU_DUMB_CTRL);
 501         }
 502
 503         /* Now compute the divider for real */
 504         priv->variant->crtc_compute_clock(dcrtc, adj, &sclk);
 505
 506         /* Ensure graphic fifo is enabled */
 507         armada_reg_queue_mod(regs, i, 0, CFG_PDWN64x66, LCD_SPU_SRAM_PARA1);
 508         armada_reg_queue_set(regs, i, sclk, LCD_CFG_SCLK_DIV);
 509
 510         if (interlaced ^ dcrtc->interlaced) {
 511                 if (adj->flags & DRM_MODE_FLAG_INTERLACE)
 512                         drm_vblank_get(dcrtc->crtc.dev, dcrtc->num);
 513                 else
 514                         drm_vblank_put(dcrtc->crtc.dev, dcrtc->num);
 515                 dcrtc->interlaced = interlaced;
 516         }
 517
 518         spin_lock_irqsave(&dcrtc->irq_lock, flags);
 519
 520         /* Even interlaced/progressive frame */
 521         dcrtc->v[1].spu_v_h_total = adj->crtc_vtotal << 16 |
 522                                     adj->crtc_htotal;
 523         dcrtc->v[1].spu_v_porch = tm << 16 | bm;
 524         val = adj->crtc_hsync_start;
 525         dcrtc->v[1].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN;
 526
 527         if (interlaced) {
 528                 /* Odd interlaced frame */
 529                 dcrtc->v[0].spu_v_h_total = dcrtc->v[1].spu_v_h_total +
 530                                                 (1 << 16);
 531                 dcrtc->v[0].spu_v_porch = dcrtc->v[1].spu_v_porch + 1;
 532                 val = adj->crtc_hsync_start - adj->crtc_htotal / 2;
 533                 dcrtc->v[0].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN;
 534         } else {
 535                 dcrtc->v[0] = dcrtc->v[1];
 536         }
 537
 538         val = adj->crtc_vdisplay << 16 | adj->crtc_hdisplay;
 539
 540         armada_reg_queue_set(regs, i, val, LCD_SPU_V_H_ACTIVE);
 541         armada_reg_queue_set(regs, i, val, LCD_SPU_GRA_HPXL_VLN);
 542         armada_reg_queue_set(regs, i, val, LCD_SPU_GZM_HPXL_VLN);
 543         armada_reg_queue_set(regs, i, (lm << 16) | rm, LCD_SPU_H_PORCH);
 544         armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH);
 545         armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total,
 546                            LCD_SPUT_V_H_TOTAL);
 547
 548         if (priv->variant->has_spu_adv_reg)
 549                 armada_reg_queue_mod(regs, i, dcrtc->v[0].spu_adv_reg,
 550                                      ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF |
 551                                      ADV_VSYNCOFFEN, LCD_SPU_ADV_REG);
 552
 553         val = CFG_GRA_ENA | CFG_GRA_HSMOOTH;
 554         val |= CFG_GRA_FMT(drm_fb_to_armada_fb(dcrtc->crtc.fb)->fmt);
 555         val |= CFG_GRA_MOD(drm_fb_to_armada_fb(dcrtc->crtc.fb)->mod);
 556
 557         if (drm_fb_to_armada_fb(dcrtc->crtc.fb)->fmt > CFG_420)
 558                 val |= CFG_PALETTE_ENA;
 559
 560         if (interlaced)
 561                 val |= CFG_GRA_FTOGGLE;
 562
 563         armada_reg_queue_mod(regs, i, val, CFG_GRAFORMAT |
 564                              CFG_GRA_MOD(CFG_SWAPRB | CFG_SWAPUV |
 565                                          CFG_SWAPYU | CFG_YUV2RGB) |
 566                              CFG_PALETTE_ENA | CFG_GRA_FTOGGLE,
 567                              LCD_SPU_DMA_CTRL0);
 568
 569         val = adj->flags & DRM_MODE_FLAG_NVSYNC ? CFG_VSYNC_INV : 0;
 570         armada_reg_queue_mod(regs, i, val, CFG_VSYNC_INV, LCD_SPU_DMA_CTRL1);
 571
 572         val = dcrtc->spu_iopad_ctrl | armada_drm_crtc_calculate_csc(dcrtc);
 573         armada_reg_queue_set(regs, i, val, LCD_SPU_IOPAD_CONTROL);
 574         armada_reg_queue_end(regs, i);
 575
 576         armada_drm_crtc_update_regs(dcrtc, regs);
 577         spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
 578
 579         armada_drm_crtc_update(dcrtc);
 580
 581         drm_vblank_post_modeset(crtc->dev, dcrtc->num);
 582         armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms));
 583
 584         return 0;
 585 }
 586
 587 /* The mode_config.mutex will be held for this call */
 588 static int armada_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
 589         struct drm_framebuffer *old_fb)
 590 {
 591         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 592         struct armada_regs regs[4];
 593         unsigned i;
 594
 595         i = armada_drm_crtc_calc_fb(crtc->fb, crtc->x, crtc->y, regs,
 596                                     dcrtc->interlaced);
 597         armada_reg_queue_end(regs, i);
 598
 599         /* Wait for pending flips to complete */
 600         wait_event(dcrtc->frame_wait, !dcrtc->frame_work);
 601
 602         /* Take a reference to the new fb as we're using it */
 603         drm_framebuffer_reference(crtc->fb);
 604
 605         /* Update the base in the CRTC */
 606         armada_drm_crtc_update_regs(dcrtc, regs);
 607
 608         /* Drop our previously held reference */
 609         armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms));
 610
 611         return 0;
 612 }
 613
 614 static void armada_drm_crtc_load_lut(struct drm_crtc *crtc)
 615 {
 616 }
 617
 618 /* The mode_config.mutex will be held for this call */
 619 static void armada_drm_crtc_disable(struct drm_crtc *crtc)
 620 {
 621         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 622
 623         armada_drm_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 624         armada_drm_crtc_finish_fb(dcrtc, crtc->fb, true);
 625
 626         /* Power down most RAMs and FIFOs */
 627         writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
 628                        CFG_PDWN32x32 | CFG_PDWN16x66 | CFG_PDWN32x66 |
 629                        CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1);
 630 }
 631
 632 static const struct drm_crtc_helper_funcs armada_crtc_helper_funcs = {
 633         .dpms           = armada_drm_crtc_dpms,
 634         .prepare        = armada_drm_crtc_prepare,
 635         .commit         = armada_drm_crtc_commit,
 636         .mode_fixup     = armada_drm_crtc_mode_fixup,
 637         .mode_set       = armada_drm_crtc_mode_set,
 638         .mode_set_base  = armada_drm_crtc_mode_set_base,
 639         .load_lut       = armada_drm_crtc_load_lut,
 640         .disable        = armada_drm_crtc_disable,
 641 };
 642
 643 static void armada_drm_crtc_destroy(struct drm_crtc *crtc)
 644 {
 645         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 646         struct armada_private *priv = crtc->dev->dev_private;
 647
 648         priv->dcrtc[dcrtc->num] = NULL;
 649         drm_crtc_cleanup(&dcrtc->crtc);
 650
 651         if (!IS_ERR(dcrtc->clk))
 652                 clk_disable_unprepare(dcrtc->clk);
 653
 654         kfree(dcrtc);
 655 }
 656
 657 /*
 658  * The mode_config lock is held here, to prevent races between this
 659  * and a mode_set.
 660  */
 661 static int armada_drm_crtc_page_flip(struct drm_crtc *crtc,
 662         struct drm_framebuffer *fb, struct drm_pending_vblank_event *event)
 663 {
 664         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 665         struct armada_frame_work *work;
 666         struct drm_device *dev = crtc->dev;
 667         unsigned long flags;
 668         unsigned i;
 669         int ret;
 670
 671         /* We don't support changing the pixel format */
 672         if (fb->pixel_format != crtc->fb->pixel_format)
 673                 return -EINVAL;
 674
 675         work = kmalloc(sizeof(*work), GFP_KERNEL);
 676         if (!work)
 677                 return -ENOMEM;
 678
 679         work->event = event;
 680         work->old_fb = dcrtc->crtc.fb;
 681
 682         i = armada_drm_crtc_calc_fb(fb, crtc->x, crtc->y, work->regs,
 683                                     dcrtc->interlaced);
 684         armada_reg_queue_end(work->regs, i);
 685
 686         /*
 687          * Hold the old framebuffer for the work - DRM appears to drop our
 688          * reference to the old framebuffer in drm_mode_page_flip_ioctl().
 689          */
 690         drm_framebuffer_reference(work->old_fb);
 691
 692         ret = armada_drm_crtc_queue_frame_work(dcrtc, work);
 693         if (ret) {
 694                 /*
 695                  * Undo our reference above; DRM does not drop the reference
 696                  * to this object on error, so that's okay.
 697                  */
 698                 drm_framebuffer_unreference(work->old_fb);
 699                 kfree(work);
 700                 return ret;
 701         }
 702
 703         /*
 704          * Don't take a reference on the new framebuffer;
 705          * drm_mode_page_flip_ioctl() has already grabbed a reference and
 706          * will _not_ drop that reference on successful return from this
 707          * function.  Simply mark this new framebuffer as the current one.
 708          */
 709         dcrtc->crtc.fb = fb;
 710
 711         /*
 712          * Finally, if the display is blanked, we won't receive an
 713          * interrupt, so complete it now.
 714          */
 715         if (dpms_blanked(dcrtc->dpms)) {
 716                 spin_lock_irqsave(&dev->event_lock, flags);
 717                 if (dcrtc->frame_work)
 718                         armada_drm_crtc_complete_frame_work(dcrtc);
 719                 spin_unlock_irqrestore(&dev->event_lock, flags);
 720         }
 721
 722         return 0;
 723 }
 724
 725 static int
 726 armada_drm_crtc_set_property(struct drm_crtc *crtc,
 727         struct drm_property *property, uint64_t val)
 728 {
 729         struct armada_private *priv = crtc->dev->dev_private;
 730         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 731         bool update_csc = false;
 732
 733         if (property == priv->csc_yuv_prop) {
 734                 dcrtc->csc_yuv_mode = val;
 735                 update_csc = true;
 736         } else if (property == priv->csc_rgb_prop) {
 737                 dcrtc->csc_rgb_mode = val;
 738                 update_csc = true;
 739         }
 740
 741         if (update_csc) {
 742                 uint32_t val;
 743
 744                 val = dcrtc->spu_iopad_ctrl |
 745                       armada_drm_crtc_calculate_csc(dcrtc);
 746                 writel_relaxed(val, dcrtc->base + LCD_SPU_IOPAD_CONTROL);
 747         }
 748
 749         return 0;
 750 }
 751
 752 static struct drm_crtc_funcs armada_crtc_funcs = {
 753         .destroy        = armada_drm_crtc_destroy,
 754         .set_config     = drm_crtc_helper_set_config,
 755         .page_flip      = armada_drm_crtc_page_flip,
 756         .set_property   = armada_drm_crtc_set_property,
 757 };
 758
 759 static struct drm_prop_enum_list armada_drm_csc_yuv_enum_list[] = {
 760         { CSC_AUTO,        "Auto" },
 761         { CSC_YUV_CCIR601, "CCIR601" },
 762         { CSC_YUV_CCIR709, "CCIR709" },
 763 };
 764
 765 static struct drm_prop_enum_list armada_drm_csc_rgb_enum_list[] = {
 766         { CSC_AUTO,         "Auto" },
 767         { CSC_RGB_COMPUTER, "Computer system" },
 768         { CSC_RGB_STUDIO,   "Studio" },
 769 };
 770
 771 static int armada_drm_crtc_create_properties(struct drm_device *dev)
 772 {
 773         struct armada_private *priv = dev->dev_private;
 774
 775         if (priv->csc_yuv_prop)
 776                 return 0;
 777
 778         priv->csc_yuv_prop = drm_property_create_enum(dev, 0,
 779                                 "CSC_YUV", armada_drm_csc_yuv_enum_list,
 780                                 ARRAY_SIZE(armada_drm_csc_yuv_enum_list));
 781         priv->csc_rgb_prop = drm_property_create_enum(dev, 0,
 782                                 "CSC_RGB", armada_drm_csc_rgb_enum_list,
 783                                 ARRAY_SIZE(armada_drm_csc_rgb_enum_list));
 784
 785         if (!priv->csc_yuv_prop || !priv->csc_rgb_prop)
 786                 return -ENOMEM;
 787
 788         return 0;
 789 }
 790
 791 int armada_drm_crtc_create(struct drm_device *dev, unsigned num,
 792         struct resource *res)
 793 {
 794         struct armada_private *priv = dev->dev_private;
 795         struct armada_crtc *dcrtc;
 796         void __iomem *base;
 797         int ret;
 798
 799         ret = armada_drm_crtc_create_properties(dev);
 800         if (ret)
 801                 return ret;
 802
 803         base = devm_request_and_ioremap(dev->dev, res);
 804         if (!base) {
 805                 DRM_ERROR("failed to ioremap register\n");
 806                 return -ENOMEM;
 807         }
 808
 809         dcrtc = kzalloc(sizeof(*dcrtc), GFP_KERNEL);
 810         if (!dcrtc) {
 811                 DRM_ERROR("failed to allocate Armada crtc\n");
 812                 return -ENOMEM;
 813         }
 814
 815         dcrtc->base = base;
 816         dcrtc->num = num;
 817         dcrtc->clk = ERR_PTR(-EINVAL);
 818         dcrtc->csc_yuv_mode = CSC_AUTO;
 819         dcrtc->csc_rgb_mode = CSC_AUTO;
 820         dcrtc->cfg_dumb_ctrl = DUMB24_RGB888_0;
 821         dcrtc->spu_iopad_ctrl = CFG_VSCALE_LN_EN | CFG_IOPAD_DUMB24;
 822         spin_lock_init(&dcrtc->irq_lock);
 823         dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR;
 824         INIT_LIST_HEAD(&dcrtc->vbl_list);
 825         init_waitqueue_head(&dcrtc->frame_wait);
 826
 827         /* Initialize some registers which we don't otherwise set */
 828         writel_relaxed(0x00000001, dcrtc->base + LCD_CFG_SCLK_DIV);
 829         writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_BLANKCOLOR);
 830         writel_relaxed(dcrtc->spu_iopad_ctrl,
 831                        dcrtc->base + LCD_SPU_IOPAD_CONTROL);
 832         writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_SRAM_PARA0);
 833         writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
 834                        CFG_PDWN32x32 | CFG_PDWN16x66 | CFG_PDWN32x66 |
 835                        CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1);
 836         writel_relaxed(0x2032ff81, dcrtc->base + LCD_SPU_DMA_CTRL1);
 837         writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_GRA_OVSA_HPXL_VLN);
 838
 839         if (priv->variant->crtc_init) {
 840                 ret = priv->variant->crtc_init(dcrtc);
 841                 if (ret) {
 842                         kfree(dcrtc);
 843                         return ret;
 844                 }
 845         }
 846
 847         /* Ensure AXI pipeline is enabled */
 848         armada_updatel(CFG_ARBFAST_ENA, 0, dcrtc->base + LCD_SPU_DMA_CTRL0);
 849
 850         priv->dcrtc[dcrtc->num] = dcrtc;
 851
 852         drm_crtc_init(dev, &dcrtc->crtc, &armada_crtc_funcs);
 853         drm_crtc_helper_add(&dcrtc->crtc, &armada_crtc_helper_funcs);
 854
 855         drm_object_attach_property(&dcrtc->crtc.base, priv->csc_yuv_prop,
 856                                    dcrtc->csc_yuv_mode);
 857         drm_object_attach_property(&dcrtc->crtc.base, priv->csc_rgb_prop,
 858                                    dcrtc->csc_rgb_mode);
 859
 860         return armada_overlay_plane_create(dev, 1 << dcrtc->num);
 861 }