drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

   1 /*
   2  * Copyright (C) 2014 Traphandler
   3  * Copyright (C) 2014 Free Electrons
   4  * Copyright (C) 2014 Atmel
   5  *
   6  * Author: Jean-Jacques Hiblot <jjhiblot@traphandler.com>
   7  * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms of the GNU General Public License version 2 as published by
  11  * the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but WITHOUT
  14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  16  * more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along with
  19  * this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <linux/clk.h>
  23 #include <linux/irq.h>
  24 #include <linux/irqchip.h>
  25 #include <linux/module.h>
  26 #include <linux/pm_runtime.h>
  27
  28 #include "atmel_hlcdc_dc.h"
  29
  30 #define ATMEL_HLCDC_LAYER_IRQS_OFFSET           8
  31
  32 static const struct atmel_hlcdc_layer_desc atmel_hlcdc_at91sam9n12_layers[] = {
  33         {
  34                 .name = "base",
  35                 .formats = &atmel_hlcdc_plane_rgb_formats,
  36                 .regs_offset = 0x40,
  37                 .id = 0,
  38                 .type = ATMEL_HLCDC_BASE_LAYER,
  39                 .nconfigs = 5,
  40                 .layout = {
  41                         .xstride = { 2 },
  42                         .default_color = 3,
  43                         .general_config = 4,
  44                 },
  45         },
  46 };
  47
  48 static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_at91sam9n12 = {
  49         .min_width = 0,
  50         .min_height = 0,
  51         .max_width = 1280,
  52         .max_height = 860,
  53         .nlayers = ARRAY_SIZE(atmel_hlcdc_at91sam9n12_layers),
  54         .layers = atmel_hlcdc_at91sam9n12_layers,
  55 };
  56
  57 static const struct atmel_hlcdc_layer_desc atmel_hlcdc_at91sam9x5_layers[] = {
  58         {
  59                 .name = "base",
  60                 .formats = &atmel_hlcdc_plane_rgb_formats,
  61                 .regs_offset = 0x40,
  62                 .id = 0,
  63                 .type = ATMEL_HLCDC_BASE_LAYER,
  64                 .nconfigs = 5,
  65                 .layout = {
  66                         .xstride = { 2 },
  67                         .default_color = 3,
  68                         .general_config = 4,
  69                         .disc_pos = 5,
  70                         .disc_size = 6,
  71                 },
  72         },
  73         {
  74                 .name = "overlay1",
  75                 .formats = &atmel_hlcdc_plane_rgb_formats,
  76                 .regs_offset = 0x100,
  77                 .id = 1,
  78                 .type = ATMEL_HLCDC_OVERLAY_LAYER,
  79                 .nconfigs = 10,
  80                 .layout = {
  81                         .pos = 2,
  82                         .size = 3,
  83                         .xstride = { 4 },
  84                         .pstride = { 5 },
  85                         .default_color = 6,
  86                         .chroma_key = 7,
  87                         .chroma_key_mask = 8,
  88                         .general_config = 9,
  89                 },
  90         },
  91         {
  92                 .name = "high-end-overlay",
  93                 .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
  94                 .regs_offset = 0x280,
  95                 .id = 2,
  96                 .type = ATMEL_HLCDC_OVERLAY_LAYER,
  97                 .nconfigs = 17,
  98                 .layout = {
  99                         .pos = 2,
 100                         .size = 3,
 101                         .memsize = 4,
 102                         .xstride = { 5, 7 },
 103                         .pstride = { 6, 8 },
 104                         .default_color = 9,
 105                         .chroma_key = 10,
 106                         .chroma_key_mask = 11,
 107                         .general_config = 12,
 108                         .csc = 14,
 109                 },
 110         },
 111         {
 112                 .name = "cursor",
 113                 .formats = &atmel_hlcdc_plane_rgb_formats,
 114                 .regs_offset = 0x340,
 115                 .id = 3,
 116                 .type = ATMEL_HLCDC_CURSOR_LAYER,
 117                 .nconfigs = 10,
 118                 .max_width = 128,
 119                 .max_height = 128,
 120                 .layout = {
 121                         .pos = 2,
 122                         .size = 3,
 123                         .xstride = { 4 },
 124                         .default_color = 6,
 125                         .chroma_key = 7,
 126                         .chroma_key_mask = 8,
 127                         .general_config = 9,
 128                 },
 129         },
 130 };
 131
 132 static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_at91sam9x5 = {
 133         .min_width = 0,
 134         .min_height = 0,
 135         .max_width = 800,
 136         .max_height = 600,
 137         .nlayers = ARRAY_SIZE(atmel_hlcdc_at91sam9x5_layers),
 138         .layers = atmel_hlcdc_at91sam9x5_layers,
 139 };
 140
 141 static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d3_layers[] = {
 142         {
 143                 .name = "base",
 144                 .formats = &atmel_hlcdc_plane_rgb_formats,
 145                 .regs_offset = 0x40,
 146                 .id = 0,
 147                 .type = ATMEL_HLCDC_BASE_LAYER,
 148                 .nconfigs = 7,
 149                 .layout = {
 150                         .xstride = { 2 },
 151                         .default_color = 3,
 152                         .general_config = 4,
 153                         .disc_pos = 5,
 154                         .disc_size = 6,
 155                 },
 156         },
 157         {
 158                 .name = "overlay1",
 159                 .formats = &atmel_hlcdc_plane_rgb_formats,
 160                 .regs_offset = 0x140,
 161                 .id = 1,
 162                 .type = ATMEL_HLCDC_OVERLAY_LAYER,
 163                 .nconfigs = 10,
 164                 .layout = {
 165                         .pos = 2,
 166                         .size = 3,
 167                         .xstride = { 4 },
 168                         .pstride = { 5 },
 169                         .default_color = 6,
 170                         .chroma_key = 7,
 171                         .chroma_key_mask = 8,
 172                         .general_config = 9,
 173                 },
 174         },
 175         {
 176                 .name = "overlay2",
 177                 .formats = &atmel_hlcdc_plane_rgb_formats,
 178                 .regs_offset = 0x240,
 179                 .id = 2,
 180                 .type = ATMEL_HLCDC_OVERLAY_LAYER,
 181                 .nconfigs = 10,
 182                 .layout = {
 183                         .pos = 2,
 184                         .size = 3,
 185                         .xstride = { 4 },
 186                         .pstride = { 5 },
 187                         .default_color = 6,
 188                         .chroma_key = 7,
 189                         .chroma_key_mask = 8,
 190                         .general_config = 9,
 191                 },
 192         },
 193         {
 194                 .name = "high-end-overlay",
 195                 .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
 196                 .regs_offset = 0x340,
 197                 .id = 3,
 198                 .type = ATMEL_HLCDC_OVERLAY_LAYER,
 199                 .nconfigs = 42,
 200                 .layout = {
 201                         .pos = 2,
 202                         .size = 3,
 203                         .memsize = 4,
 204                         .xstride = { 5, 7 },
 205                         .pstride = { 6, 8 },
 206                         .default_color = 9,
 207                         .chroma_key = 10,
 208                         .chroma_key_mask = 11,
 209                         .general_config = 12,
 210                         .csc = 14,
 211                 },
 212         },
 213         {
 214                 .name = "cursor",
 215                 .formats = &atmel_hlcdc_plane_rgb_formats,
 216                 .regs_offset = 0x440,
 217                 .id = 4,
 218                 .type = ATMEL_HLCDC_CURSOR_LAYER,
 219                 .nconfigs = 10,
 220                 .max_width = 128,
 221                 .max_height = 128,
 222                 .layout = {
 223                         .pos = 2,
 224                         .size = 3,
 225                         .xstride = { 4 },
 226                         .pstride = { 5 },
 227                         .default_color = 6,
 228                         .chroma_key = 7,
 229                         .chroma_key_mask = 8,
 230                         .general_config = 9,
 231                 },
 232         },
 233 };
 234
 235 static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sama5d3 = {
 236         .min_width = 0,
 237         .min_height = 0,
 238         .max_width = 2048,
 239         .max_height = 2048,
 240         .nlayers = ARRAY_SIZE(atmel_hlcdc_sama5d3_layers),
 241         .layers = atmel_hlcdc_sama5d3_layers,
 242 };
 243
 244 static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d4_layers[] = {
 245         {
 246                 .name = "base",
 247                 .formats = &atmel_hlcdc_plane_rgb_formats,
 248                 .regs_offset = 0x40,
 249                 .id = 0,
 250                 .type = ATMEL_HLCDC_BASE_LAYER,
 251                 .nconfigs = 7,
 252                 .layout = {
 253                         .xstride = { 2 },
 254                         .default_color = 3,
 255                         .general_config = 4,
 256                         .disc_pos = 5,
 257                         .disc_size = 6,
 258                 },
 259         },
 260         {
 261                 .name = "overlay1",
 262                 .formats = &atmel_hlcdc_plane_rgb_formats,
 263                 .regs_offset = 0x140,
 264                 .id = 1,
 265                 .type = ATMEL_HLCDC_OVERLAY_LAYER,
 266                 .nconfigs = 10,
 267                 .layout = {
 268                         .pos = 2,
 269                         .size = 3,
 270                         .xstride = { 4 },
 271                         .pstride = { 5 },
 272                         .default_color = 6,
 273                         .chroma_key = 7,
 274                         .chroma_key_mask = 8,
 275                         .general_config = 9,
 276                 },
 277         },
 278         {
 279                 .name = "overlay2",
 280                 .formats = &atmel_hlcdc_plane_rgb_formats,
 281                 .regs_offset = 0x240,
 282                 .id = 2,
 283                 .type = ATMEL_HLCDC_OVERLAY_LAYER,
 284                 .nconfigs = 10,
 285                 .layout = {
 286                         .pos = 2,
 287                         .size = 3,
 288                         .xstride = { 4 },
 289                         .pstride = { 5 },
 290                         .default_color = 6,
 291                         .chroma_key = 7,
 292                         .chroma_key_mask = 8,
 293                         .general_config = 9,
 294                 },
 295         },
 296         {
 297                 .name = "high-end-overlay",
 298                 .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
 299                 .regs_offset = 0x340,
 300                 .id = 3,
 301                 .type = ATMEL_HLCDC_OVERLAY_LAYER,
 302                 .nconfigs = 42,
 303                 .layout = {
 304                         .pos = 2,
 305                         .size = 3,
 306                         .memsize = 4,
 307                         .xstride = { 5, 7 },
 308                         .pstride = { 6, 8 },
 309                         .default_color = 9,
 310                         .chroma_key = 10,
 311                         .chroma_key_mask = 11,
 312                         .general_config = 12,
 313                         .csc = 14,
 314                 },
 315         },
 316 };
 317
 318 static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sama5d4 = {
 319         .min_width = 0,
 320         .min_height = 0,
 321         .max_width = 2048,
 322         .max_height = 2048,
 323         .nlayers = ARRAY_SIZE(atmel_hlcdc_sama5d4_layers),
 324         .layers = atmel_hlcdc_sama5d4_layers,
 325 };
 326 static const struct of_device_id atmel_hlcdc_of_match[] = {
 327         {
 328                 .compatible = "atmel,at91sam9n12-hlcdc",
 329                 .data = &atmel_hlcdc_dc_at91sam9n12,
 330         },
 331         {
 332                 .compatible = "atmel,at91sam9x5-hlcdc",
 333                 .data = &atmel_hlcdc_dc_at91sam9x5,
 334         },
 335         {
 336                 .compatible = "atmel,sama5d2-hlcdc",
 337                 .data = &atmel_hlcdc_dc_sama5d4,
 338         },
 339         {
 340                 .compatible = "atmel,sama5d3-hlcdc",
 341                 .data = &atmel_hlcdc_dc_sama5d3,
 342         },
 343         {
 344                 .compatible = "atmel,sama5d4-hlcdc",
 345                 .data = &atmel_hlcdc_dc_sama5d4,
 346         },
 347         { /* sentinel */ },
 348 };
 349
 350 int atmel_hlcdc_dc_mode_valid(struct atmel_hlcdc_dc *dc,
 351                               struct drm_display_mode *mode)
 352 {
 353         int vfront_porch = mode->vsync_start - mode->vdisplay;
 354         int vback_porch = mode->vtotal - mode->vsync_end;
 355         int vsync_len = mode->vsync_end - mode->vsync_start;
 356         int hfront_porch = mode->hsync_start - mode->hdisplay;
 357         int hback_porch = mode->htotal - mode->hsync_end;
 358         int hsync_len = mode->hsync_end - mode->hsync_start;
 359
 360         if (hsync_len > 0x40 || hsync_len < 1)
 361                 return MODE_HSYNC;
 362
 363         if (vsync_len > 0x40 || vsync_len < 1)
 364                 return MODE_VSYNC;
 365
 366         if (hfront_porch > 0x200 || hfront_porch < 1 ||
 367             hback_porch > 0x200 || hback_porch < 1 ||
 368             mode->hdisplay < 1)
 369                 return MODE_H_ILLEGAL;
 370
 371         if (vfront_porch > 0x40 || vfront_porch < 1 ||
 372             vback_porch > 0x40 || vback_porch < 0 ||
 373             mode->vdisplay < 1)
 374                 return MODE_V_ILLEGAL;
 375
 376         return MODE_OK;
 377 }
 378
 379 static irqreturn_t atmel_hlcdc_dc_irq_handler(int irq, void *data)
 380 {
 381         struct drm_device *dev = data;
 382         struct atmel_hlcdc_dc *dc = dev->dev_private;
 383         unsigned long status;
 384         unsigned int imr, isr;
 385         int i;
 386
 387         regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_IMR, &imr);
 388         regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_ISR, &isr);
 389         status = imr & isr;
 390         if (!status)
 391                 return IRQ_NONE;
 392
 393         if (status & ATMEL_HLCDC_SOF)
 394                 atmel_hlcdc_crtc_irq(dc->crtc);
 395
 396         for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) {
 397                 struct atmel_hlcdc_layer *layer = dc->layers[i];
 398
 399                 if (!(ATMEL_HLCDC_LAYER_STATUS(i) & status) || !layer)
 400                         continue;
 401
 402                 atmel_hlcdc_layer_irq(layer);
 403         }
 404
 405         return IRQ_HANDLED;
 406 }
 407
 408 static struct drm_framebuffer *atmel_hlcdc_fb_create(struct drm_device *dev,
 409                 struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd)
 410 {
 411         return drm_fb_cma_create(dev, file_priv, mode_cmd);
 412 }
 413
 414 static void atmel_hlcdc_fb_output_poll_changed(struct drm_device *dev)
 415 {
 416         struct atmel_hlcdc_dc *dc = dev->dev_private;
 417
 418         if (dc->fbdev) {
 419                 drm_fbdev_cma_hotplug_event(dc->fbdev);
 420         } else {
 421                 dc->fbdev = drm_fbdev_cma_init(dev, 24,
 422                                 dev->mode_config.num_crtc,
 423                                 dev->mode_config.num_connector);
 424                 if (IS_ERR(dc->fbdev))
 425                         dc->fbdev = NULL;
 426         }
 427 }
 428
 429 static const struct drm_mode_config_funcs mode_config_funcs = {
 430         .fb_create = atmel_hlcdc_fb_create,
 431         .output_poll_changed = atmel_hlcdc_fb_output_poll_changed,
 432         .atomic_check = drm_atomic_helper_check,
 433         .atomic_commit = drm_atomic_helper_commit,
 434 };
 435
 436 static int atmel_hlcdc_dc_modeset_init(struct drm_device *dev)
 437 {
 438         struct atmel_hlcdc_dc *dc = dev->dev_private;
 439         struct atmel_hlcdc_planes *planes;
 440         int ret;
 441         int i;
 442
 443         drm_mode_config_init(dev);
 444
 445         ret = atmel_hlcdc_create_outputs(dev);
 446         if (ret) {
 447                 dev_err(dev->dev, "failed to create panel: %d\n", ret);
 448                 return ret;
 449         }
 450
 451         planes = atmel_hlcdc_create_planes(dev);
 452         if (IS_ERR(planes)) {
 453                 dev_err(dev->dev, "failed to create planes\n");
 454                 return PTR_ERR(planes);
 455         }
 456
 457         dc->planes = planes;
 458
 459         dc->layers[planes->primary->layer.desc->id] =
 460                                                 &planes->primary->layer;
 461
 462         if (planes->cursor)
 463                 dc->layers[planes->cursor->layer.desc->id] =
 464                                                         &planes->cursor->layer;
 465
 466         for (i = 0; i < planes->noverlays; i++)
 467                 dc->layers[planes->overlays[i]->layer.desc->id] =
 468                                                 &planes->overlays[i]->layer;
 469
 470         ret = atmel_hlcdc_crtc_create(dev);
 471         if (ret) {
 472                 dev_err(dev->dev, "failed to create crtc\n");
 473                 return ret;
 474         }
 475
 476         dev->mode_config.min_width = dc->desc->min_width;
 477         dev->mode_config.min_height = dc->desc->min_height;
 478         dev->mode_config.max_width = dc->desc->max_width;
 479         dev->mode_config.max_height = dc->desc->max_height;
 480         dev->mode_config.funcs = &mode_config_funcs;
 481
 482         return 0;
 483 }
 484
 485 static int atmel_hlcdc_dc_load(struct drm_device *dev)
 486 {
 487         struct platform_device *pdev = to_platform_device(dev->dev);
 488         const struct of_device_id *match;
 489         struct atmel_hlcdc_dc *dc;
 490         int ret;
 491
 492         match = of_match_node(atmel_hlcdc_of_match, dev->dev->parent->of_node);
 493         if (!match) {
 494                 dev_err(&pdev->dev, "invalid compatible string\n");
 495                 return -ENODEV;
 496         }
 497
 498         if (!match->data) {
 499                 dev_err(&pdev->dev, "invalid hlcdc description\n");
 500                 return -EINVAL;
 501         }
 502
 503         dc = devm_kzalloc(dev->dev, sizeof(*dc), GFP_KERNEL);
 504         if (!dc)
 505                 return -ENOMEM;
 506
 507         dc->wq = alloc_ordered_workqueue("atmel-hlcdc-dc", 0);
 508         if (!dc->wq)
 509                 return -ENOMEM;
 510
 511         dc->desc = match->data;
 512         dc->hlcdc = dev_get_drvdata(dev->dev->parent);
 513         dev->dev_private = dc;
 514
 515         ret = clk_prepare_enable(dc->hlcdc->periph_clk);
 516         if (ret) {
 517                 dev_err(dev->dev, "failed to enable periph_clk\n");
 518                 goto err_destroy_wq;
 519         }
 520
 521         pm_runtime_enable(dev->dev);
 522
 523         ret = drm_vblank_init(dev, 1);
 524         if (ret < 0) {
 525                 dev_err(dev->dev, "failed to initialize vblank\n");
 526                 goto err_periph_clk_disable;
 527         }
 528
 529         ret = atmel_hlcdc_dc_modeset_init(dev);
 530         if (ret < 0) {
 531                 dev_err(dev->dev, "failed to initialize mode setting\n");
 532                 goto err_periph_clk_disable;
 533         }
 534
 535         drm_mode_config_reset(dev);
 536
 537         pm_runtime_get_sync(dev->dev);
 538         ret = drm_irq_install(dev, dc->hlcdc->irq);
 539         pm_runtime_put_sync(dev->dev);
 540         if (ret < 0) {
 541                 dev_err(dev->dev, "failed to install IRQ handler\n");
 542                 goto err_periph_clk_disable;
 543         }
 544
 545         platform_set_drvdata(pdev, dev);
 546
 547         drm_kms_helper_poll_init(dev);
 548
 549         /* force connectors detection */
 550         drm_helper_hpd_irq_event(dev);
 551
 552         return 0;
 553
 554 err_periph_clk_disable:
 555         pm_runtime_disable(dev->dev);
 556         clk_disable_unprepare(dc->hlcdc->periph_clk);
 557
 558 err_destroy_wq:
 559         destroy_workqueue(dc->wq);
 560
 561         return ret;
 562 }
 563
 564 static void atmel_hlcdc_dc_unload(struct drm_device *dev)
 565 {
 566         struct atmel_hlcdc_dc *dc = dev->dev_private;
 567
 568         if (dc->fbdev)
 569                 drm_fbdev_cma_fini(dc->fbdev);
 570         flush_workqueue(dc->wq);
 571         drm_kms_helper_poll_fini(dev);
 572         drm_mode_config_cleanup(dev);
 573         drm_vblank_cleanup(dev);
 574
 575         pm_runtime_get_sync(dev->dev);
 576         drm_irq_uninstall(dev);
 577         pm_runtime_put_sync(dev->dev);
 578
 579         dev->dev_private = NULL;
 580
 581         pm_runtime_disable(dev->dev);
 582         clk_disable_unprepare(dc->hlcdc->periph_clk);
 583         destroy_workqueue(dc->wq);
 584 }
 585
 586 static int atmel_hlcdc_dc_connector_plug_all(struct drm_device *dev)
 587 {
 588         struct drm_connector *connector, *failed;
 589         int ret;
 590
 591         mutex_lock(&dev->mode_config.mutex);
 592         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 593                 ret = drm_connector_register(connector);
 594                 if (ret) {
 595                         failed = connector;
 596                         goto err;
 597                 }
 598         }
 599         mutex_unlock(&dev->mode_config.mutex);
 600         return 0;
 601
 602 err:
 603         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 604                 if (failed == connector)
 605                         break;
 606
 607                 drm_connector_unregister(connector);
 608         }
 609         mutex_unlock(&dev->mode_config.mutex);
 610
 611         return ret;
 612 }
 613
 614 static void atmel_hlcdc_dc_connector_unplug_all(struct drm_device *dev)
 615 {
 616         mutex_lock(&dev->mode_config.mutex);
 617         drm_connector_unplug_all(dev);
 618         mutex_unlock(&dev->mode_config.mutex);
 619 }
 620
 621 static void atmel_hlcdc_dc_preclose(struct drm_device *dev,
 622                                     struct drm_file *file)
 623 {
 624         struct drm_crtc *crtc;
 625
 626         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 627                 atmel_hlcdc_crtc_cancel_page_flip(crtc, file);
 628 }
 629
 630 static void atmel_hlcdc_dc_lastclose(struct drm_device *dev)
 631 {
 632         struct atmel_hlcdc_dc *dc = dev->dev_private;
 633
 634         drm_fbdev_cma_restore_mode(dc->fbdev);
 635 }
 636
 637 static int atmel_hlcdc_dc_irq_postinstall(struct drm_device *dev)
 638 {
 639         struct atmel_hlcdc_dc *dc = dev->dev_private;
 640         unsigned int cfg = 0;
 641         int i;
 642
 643         /* Enable interrupts on activated layers */
 644         for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) {
 645                 if (dc->layers[i])
 646                         cfg |= ATMEL_HLCDC_LAYER_STATUS(i);
 647         }
 648
 649         regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IER, cfg);
 650
 651         return 0;
 652 }
 653
 654 static void atmel_hlcdc_dc_irq_uninstall(struct drm_device *dev)
 655 {
 656         struct atmel_hlcdc_dc *dc = dev->dev_private;
 657         unsigned int isr;
 658
 659         regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IDR, 0xffffffff);
 660         regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_ISR, &isr);
 661 }
 662
 663 static int atmel_hlcdc_dc_enable_vblank(struct drm_device *dev,
 664                                         unsigned int pipe)
 665 {
 666         struct atmel_hlcdc_dc *dc = dev->dev_private;
 667
 668         /* Enable SOF (Start Of Frame) interrupt for vblank counting */
 669         regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IER, ATMEL_HLCDC_SOF);
 670
 671         return 0;
 672 }
 673
 674 static void atmel_hlcdc_dc_disable_vblank(struct drm_device *dev,
 675                                           unsigned int pipe)
 676 {
 677         struct atmel_hlcdc_dc *dc = dev->dev_private;
 678
 679         regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IDR, ATMEL_HLCDC_SOF);
 680 }
 681
 682 static const struct file_operations fops = {
 683         .owner              = THIS_MODULE,
 684         .open               = drm_open,
 685         .release            = drm_release,
 686         .unlocked_ioctl     = drm_ioctl,
 687 #ifdef CONFIG_COMPAT
 688         .compat_ioctl       = drm_compat_ioctl,
 689 #endif
 690         .poll               = drm_poll,
 691         .read               = drm_read,
 692         .llseek             = no_llseek,
 693         .mmap               = drm_gem_cma_mmap,
 694 };
 695
 696 static struct drm_driver atmel_hlcdc_dc_driver = {
 697         .driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM |
 698                            DRIVER_MODESET | DRIVER_PRIME |
 699                            DRIVER_ATOMIC,
 700         .preclose = atmel_hlcdc_dc_preclose,
 701         .lastclose = atmel_hlcdc_dc_lastclose,
 702         .irq_handler = atmel_hlcdc_dc_irq_handler,
 703         .irq_preinstall = atmel_hlcdc_dc_irq_uninstall,
 704         .irq_postinstall = atmel_hlcdc_dc_irq_postinstall,
 705         .irq_uninstall = atmel_hlcdc_dc_irq_uninstall,
 706         .get_vblank_counter = drm_vblank_no_hw_counter,
 707         .enable_vblank = atmel_hlcdc_dc_enable_vblank,
 708         .disable_vblank = atmel_hlcdc_dc_disable_vblank,
 709         .gem_free_object = drm_gem_cma_free_object,
 710         .gem_vm_ops = &drm_gem_cma_vm_ops,
 711         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
 712         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
 713         .gem_prime_import = drm_gem_prime_import,
 714         .gem_prime_export = drm_gem_prime_export,
 715         .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
 716         .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
 717         .gem_prime_vmap = drm_gem_cma_prime_vmap,
 718         .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
 719         .gem_prime_mmap = drm_gem_cma_prime_mmap,
 720         .dumb_create = drm_gem_cma_dumb_create,
 721         .dumb_map_offset = drm_gem_cma_dumb_map_offset,
 722         .dumb_destroy = drm_gem_dumb_destroy,
 723         .fops = &fops,
 724         .name = "atmel-hlcdc",
 725         .desc = "Atmel HLCD Controller DRM",
 726         .date = "20141504",
 727         .major = 1,
 728         .minor = 0,
 729 };
 730
 731 static int atmel_hlcdc_dc_drm_probe(struct platform_device *pdev)
 732 {
 733         struct drm_device *ddev;
 734         int ret;
 735
 736         ddev = drm_dev_alloc(&atmel_hlcdc_dc_driver, &pdev->dev);
 737         if (!ddev)
 738                 return -ENOMEM;
 739
 740         ret = drm_dev_set_unique(ddev, dev_name(ddev->dev));
 741         if (ret)
 742                 goto err_unref;
 743
 744         ret = atmel_hlcdc_dc_load(ddev);
 745         if (ret)
 746                 goto err_unref;
 747
 748         ret = drm_dev_register(ddev, 0);
 749         if (ret)
 750                 goto err_unload;
 751
 752         ret = atmel_hlcdc_dc_connector_plug_all(ddev);
 753         if (ret)
 754                 goto err_unregister;
 755
 756         return 0;
 757
 758 err_unregister:
 759         drm_dev_unregister(ddev);
 760
 761 err_unload:
 762         atmel_hlcdc_dc_unload(ddev);
 763
 764 err_unref:
 765         drm_dev_unref(ddev);
 766
 767         return ret;
 768 }
 769
 770 static int atmel_hlcdc_dc_drm_remove(struct platform_device *pdev)
 771 {
 772         struct drm_device *ddev = platform_get_drvdata(pdev);
 773
 774         atmel_hlcdc_dc_connector_unplug_all(ddev);
 775         drm_dev_unregister(ddev);
 776         atmel_hlcdc_dc_unload(ddev);
 777         drm_dev_unref(ddev);
 778
 779         return 0;
 780 }
 781
 782 #ifdef CONFIG_PM_SLEEP
 783 static int atmel_hlcdc_dc_drm_suspend(struct device *dev)
 784 {
 785         struct drm_device *drm_dev = dev_get_drvdata(dev);
 786         struct drm_crtc *crtc;
 787
 788         if (pm_runtime_suspended(dev))
 789                 return 0;
 790
 791         drm_modeset_lock_all(drm_dev);
 792         list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head)
 793                 atmel_hlcdc_crtc_suspend(crtc);
 794         drm_modeset_unlock_all(drm_dev);
 795         return 0;
 796 }
 797
 798 static int atmel_hlcdc_dc_drm_resume(struct device *dev)
 799 {
 800         struct drm_device *drm_dev = dev_get_drvdata(dev);
 801         struct drm_crtc *crtc;
 802
 803         if (pm_runtime_suspended(dev))
 804                 return 0;
 805
 806         drm_modeset_lock_all(drm_dev);
 807         list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head)
 808                 atmel_hlcdc_crtc_resume(crtc);
 809         drm_modeset_unlock_all(drm_dev);
 810         return 0;
 811 }
 812 #endif
 813
 814 static SIMPLE_DEV_PM_OPS(atmel_hlcdc_dc_drm_pm_ops,
 815                 atmel_hlcdc_dc_drm_suspend, atmel_hlcdc_dc_drm_resume);
 816
 817 static const struct of_device_id atmel_hlcdc_dc_of_match[] = {
 818         { .compatible = "atmel,hlcdc-display-controller" },
 819         { },
 820 };
 821
 822 static struct platform_driver atmel_hlcdc_dc_platform_driver = {
 823         .probe  = atmel_hlcdc_dc_drm_probe,
 824         .remove = atmel_hlcdc_dc_drm_remove,
 825         .driver = {
 826                 .name   = "atmel-hlcdc-display-controller",
 827                 .pm     = &atmel_hlcdc_dc_drm_pm_ops,
 828                 .of_match_table = atmel_hlcdc_dc_of_match,
 829         },
 830 };
 831 module_platform_driver(atmel_hlcdc_dc_platform_driver);
 832
 833 MODULE_AUTHOR("Jean-Jacques Hiblot <jjhiblot@traphandler.com>");
 834 MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
 835 MODULE_DESCRIPTION("Atmel HLCDC Display Controller DRM Driver");
 836 MODULE_LICENSE("GPL");
 837 MODULE_ALIAS("platform:atmel-hlcdc-dc");